Patch set updated for coreboot: soc/intel/quark: Prepare for FSP2.0 support
Lee Leahy (leroy.p.leahy@intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15862 -gerrit commit 88b0a856dcf5a32cf7c6adf8bcbd7c9185a0a882 Author: Lee Leahy <leroy.p.leahy@intel.com> Date: Wed Jul 20 08:58:58 2016 -0700 soc/intel/quark: Prepare for FSP2.0 support Split the original contents of romstage.c into car.c, romstage.c and fsp1_1.c. TEST=Build and run on Galileo Gen2 Change-Id: I6392d7382e383ea2087afa6bf45b1f087ba78d79 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> --- src/soc/intel/quark/Makefile.inc | 1 + src/soc/intel/quark/chip.c | 14 +- src/soc/intel/quark/fsp1_1.c | 35 +++++ src/soc/intel/quark/include/soc/pm.h | 1 + src/soc/intel/quark/include/soc/ramstage.h | 1 + src/soc/intel/quark/include/soc/romstage.h | 2 + src/soc/intel/quark/romstage/Makefile.inc | 2 + src/soc/intel/quark/romstage/car.c | 67 +++++++++ src/soc/intel/quark/romstage/fsp1_1.c | 204 ++++++++++++++++++++++++++ src/soc/intel/quark/romstage/mtrr.c | 2 +- src/soc/intel/quark/romstage/romstage.c | 227 +---------------------------- 11 files changed, 323 insertions(+), 233 deletions(-) diff --git a/src/soc/intel/quark/Makefile.inc b/src/soc/intel/quark/Makefile.inc index f5b9746..4740ec7 100644 --- a/src/soc/intel/quark/Makefile.inc +++ b/src/soc/intel/quark/Makefile.inc @@ -34,6 +34,7 @@ romstage-$(CONFIG_ENABLE_BUILTIN_HSUART1) += uart_common.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c ramstage-y += chip.c ramstage-y += ehci.c +ramstage-$(CONFIG_PLATFORM_USES_FSP1_1) += fsp1_1.c ramstage-y += gpio_i2c.c ramstage-y += i2c.c ramstage-y += lpc.c diff --git a/src/soc/intel/quark/chip.c b/src/soc/intel/quark/chip.c index 07eca13..c8c6b39 100644 --- a/src/soc/intel/quark/chip.c +++ b/src/soc/intel/quark/chip.c @@ -119,10 +119,7 @@ static void chip_init(void *chip_info) die("(reg_rmu_temp_read(QUARK_NC_RMU_REG_CONFIG) & (TS_LOCK_THRM_CTRL_REGS_ENABLE | TS_LOCK_AUX_TRIP_PT_REGS_ENABLE)) != (TS_LOCK_THRM_CTRL_REGS_ENABLE | TS_LOCK_AUX_TRIP_PT_REGS_ENABLE)\n"); /* Perform silicon specific init. */ - if (IS_ENABLED(CONFIG_RELOCATE_FSP_INTO_DRAM)) - intel_silicon_init(); - else - fsp_run_silicon_init(find_fsp(CONFIG_FSP_ESRAM_LOC), 0); + fsp_silicon_init(); } static void pci_domain_set_resources(device_t dev) @@ -152,12 +149,3 @@ struct chip_operations soc_intel_quark_ops = { .init = &chip_init, .enable_dev = chip_enable_dev, }; - -void soc_silicon_init_params(SILICON_INIT_UPD *upd) -{ -} - -void soc_display_silicon_init_params(const SILICON_INIT_UPD *old, - SILICON_INIT_UPD *new) -{ -} diff --git a/src/soc/intel/quark/fsp1_1.c b/src/soc/intel/quark/fsp1_1.c new file mode 100644 index 0000000..ee10e38 --- /dev/null +++ b/src/soc/intel/quark/fsp1_1.c @@ -0,0 +1,35 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015-2016 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include <console/console.h> +#include <fsp/util.h> +#include <soc/ramstage.h> + +void fsp_silicon_init(void) +{ + if (IS_ENABLED(CONFIG_RELOCATE_FSP_INTO_DRAM)) + intel_silicon_init(); + else + fsp_run_silicon_init(find_fsp(CONFIG_FSP_ESRAM_LOC), 0); +} + +void soc_silicon_init_params(SILICON_INIT_UPD *upd) +{ +} + +void soc_display_silicon_init_params(const SILICON_INIT_UPD *old, + SILICON_INIT_UPD *new) +{ +} diff --git a/src/soc/intel/quark/include/soc/pm.h b/src/soc/intel/quark/include/soc/pm.h index 30d8841..7547a53 100644 --- a/src/soc/intel/quark/include/soc/pm.h +++ b/src/soc/intel/quark/include/soc/pm.h @@ -24,6 +24,7 @@ struct chipset_power_state { uint32_t prev_sleep_state; } __attribute__ ((packed)); +struct chipset_power_state *get_power_state(void); struct chipset_power_state *fill_power_state(void); #endif diff --git a/src/soc/intel/quark/include/soc/ramstage.h b/src/soc/intel/quark/include/soc/ramstage.h index 80e2f00..9f201a0 100644 --- a/src/soc/intel/quark/include/soc/ramstage.h +++ b/src/soc/intel/quark/include/soc/ramstage.h @@ -23,5 +23,6 @@ #include <soc/QuarkNcSocId.h> void mainboard_gpio_i2c_init(device_t dev); +void fsp_silicon_init(void); #endif /* _SOC_RAMSTAGE_H_ */ diff --git a/src/soc/intel/quark/include/soc/romstage.h b/src/soc/intel/quark/include/soc/romstage.h index 7e761ab..fcac3e2 100644 --- a/src/soc/intel/quark/include/soc/romstage.h +++ b/src/soc/intel/quark/include/soc/romstage.h @@ -26,6 +26,8 @@ #include <soc/reg_access.h> asmlinkage void *car_stage_c_entry(void); +void clear_smi_and_wake_events(void); +void disable_rom_shadow(void); void report_platform_info(void); int set_base_address_and_enable_uart(u8 bus, u8 dev, u8 func, u32 mmio_base); void pcie_init(void); diff --git a/src/soc/intel/quark/romstage/Makefile.inc b/src/soc/intel/quark/romstage/Makefile.inc index 16fc5ac..635da83 100644 --- a/src/soc/intel/quark/romstage/Makefile.inc +++ b/src/soc/intel/quark/romstage/Makefile.inc @@ -13,7 +13,9 @@ # GNU General Public License for more details. # +romstage-y += car.c romstage-y += car_stage_entry.S +romstage-$(CONFIG_PLATFORM_USES_FSP1_1) += fsp1_1.c romstage-y += mtrr.c romstage-y += pcie.c romstage-y += report_platform.c diff --git a/src/soc/intel/quark/romstage/car.c b/src/soc/intel/quark/romstage/car.c new file mode 100644 index 0000000..781349c --- /dev/null +++ b/src/soc/intel/quark/romstage/car.c @@ -0,0 +1,67 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015-2016 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#define __SIMPLE_DEVICE__ + +#include <console/console.h> +#include <fsp/util.h> +#include <soc/iomap.h> +#include <soc/pci_devs.h> +#include <soc/romstage.h> +#include <soc/reg_access.h> + +static const struct reg_script legacy_gpio_init[] = { + /* Temporarily enable the legacy GPIO controller */ + REG_PCI_WRITE32(R_QNC_LPC_GBA_BASE, IO_ADDRESS_VALID + | LEGACY_GPIO_BASE_ADDRESS), + /* Temporarily enable the GPE controller */ + REG_PCI_WRITE32(R_QNC_LPC_GPE0BLK, IO_ADDRESS_VALID + | GPE0_BASE_ADDRESS), + REG_PCI_OR8(PCI_COMMAND, PCI_COMMAND_IO), + REG_SCRIPT_END +}; + +static const struct reg_script i2c_gpio_controller_init[] = { + /* Temporarily enable the GPIO controller */ + REG_PCI_WRITE32(PCI_BASE_ADDRESS_0, I2C_BASE_ADDRESS), + REG_PCI_WRITE32(PCI_BASE_ADDRESS_1, GPIO_BASE_ADDRESS), + REG_PCI_OR8(PCI_COMMAND, PCI_COMMAND_MEMORY), + REG_SCRIPT_END +}; + +static const struct reg_script hsuart_init[] = { + /* Enable the HSUART */ + REG_PCI_WRITE32(PCI_BASE_ADDRESS_0, UART_BASE_ADDRESS), + REG_PCI_OR8(PCI_COMMAND, PCI_COMMAND_MEMORY), + REG_SCRIPT_END +}; + +void car_soc_pre_console_init(void) +{ + /* Initialize the controllers */ + reg_script_run_on_dev(I2CGPIO_BDF, i2c_gpio_controller_init); + reg_script_run_on_dev(LPC_BDF, legacy_gpio_init); + + /* Enable the HSUART */ + if (IS_ENABLED(CONFIG_ENABLE_BUILTIN_HSUART0)) + reg_script_run_on_dev(HSUART0_BDF, hsuart_init); + if (IS_ENABLED(CONFIG_ENABLE_BUILTIN_HSUART1)) + reg_script_run_on_dev(HSUART1_BDF, hsuart_init); +} + +void car_soc_post_console_init(void) +{ + report_platform_info(); +}; diff --git a/src/soc/intel/quark/romstage/fsp1_1.c b/src/soc/intel/quark/romstage/fsp1_1.c new file mode 100644 index 0000000..a0fb009 --- /dev/null +++ b/src/soc/intel/quark/romstage/fsp1_1.c @@ -0,0 +1,204 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015-2016 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#define __SIMPLE_DEVICE__ + +#include <arch/early_variables.h> +#include <console/console.h> +#include <cbfs.h> +#include "../chip.h" +#include <fsp/util.h> +#include <lib.h> +#include <soc/iomap.h> +#include <soc/pci_devs.h> +#include <soc/romstage.h> +#include <string.h> + +asmlinkage void *car_stage_c_entry(void) +{ + FSP_INFO_HEADER *fih; + struct cache_as_ram_params car_params = {0}; + void *top_of_stack; + + post_code(0x20); + + /* Copy the FSP binary into ESRAM */ + memcpy((void *)CONFIG_FSP_ESRAM_LOC, (void *)CONFIG_FSP_LOC, + 0x00040000); + + /* Locate the FSP header in ESRAM */ + fih = find_fsp(CONFIG_FSP_ESRAM_LOC); + + /* Start the early verstage/romstage code */ + post_code(0x2A); + car_params.fih = fih; + top_of_stack = cache_as_ram_main(&car_params); + + /* Initialize MTRRs and switch stacks after RAM initialized */ + return top_of_stack; +} + +static struct chipset_power_state power_state CAR_GLOBAL; + +struct chipset_power_state *get_power_state(void) +{ + return (struct chipset_power_state *)car_get_var_ptr(&power_state); +} + +struct chipset_power_state *fill_power_state(void) +{ + struct chipset_power_state *ps = get_power_state(); + + ps->prev_sleep_state = 0; + printk(BIOS_DEBUG, "prev_sleep_state %d\n", ps->prev_sleep_state); + return ps; +} + +/* Initialize the UPD parameters for MemoryInit */ +void soc_memory_init_params(struct romstage_params *params, + MEMORY_INIT_UPD *upd) +{ + const struct device *dev; + const struct soc_intel_quark_config *config; + char *rmu_file; + size_t rmu_file_len; + + /* Locate the configuration data from devicetree.cb */ + dev = dev_find_slot(0, LPC_DEV_FUNC); + if (!dev) { + printk(BIOS_ERR, + "Error! Device (PCI:0:%02x.%01x) not found, " + "soc_memory_init_params!\n", PCI_DEVICE_NUMBER_QNC_LPC, + PCI_FUNCTION_NUMBER_QNC_LPC); + return; + } + config = dev->chip_info; + + /* Display the ROM shadow data */ + hexdump((void *)0x000ffff0, 0x10); + + /* Clear SMI and wake events */ + clear_smi_and_wake_events(); + + /* Locate the RMU data file in flash */ + rmu_file = cbfs_boot_map_with_leak("rmu.bin", CBFS_TYPE_RAW, + &rmu_file_len); + if (!rmu_file) + die("Microcode file (rmu.bin) not found."); + + /* Update the UPD data for MemoryInit */ + printk(BIOS_DEBUG, "Updating UPD values for MemoryInit: 0x%p\n", upd); + upd->AddrMode = config->AddrMode; + upd->ChanMask = config->ChanMask; + upd->ChanWidth = config->ChanWidth; + upd->DramDensity = config->DramDensity; + upd->DramRonVal = config->DramRonVal; + upd->DramRttNomVal = config->DramRttNomVal; + upd->DramRttWrVal = config->DramRttWrVal; + upd->DramSpeed = config->DramSpeed; + upd->DramType = config->DramType; + upd->DramWidth = config->DramWidth; + upd->EccScrubBlkSize = config->EccScrubBlkSize; + upd->EccScrubInterval = config->EccScrubInterval; + upd->Flags = config->Flags; + upd->FspReservedMemoryLength = config->FspReservedMemoryLength; + upd->RankMask = config->RankMask; + upd->RmuBaseAddress = (uintptr_t)rmu_file; + upd->RmuLength = rmu_file_len; + upd->SerialPortBaseAddress = UART_BASE_ADDRESS; + upd->SmmTsegSize = IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) ? + config->SmmTsegSize : 0; + upd->SocRdOdtVal = config->SocRdOdtVal; + upd->SocWrRonVal = config->SocWrRonVal; + upd->SocWrSlewRate = config->SocWrSlewRate; + upd->SrInt = config->SrInt; + upd->SrTemp = config->SrTemp; + upd->tCL = config->tCL; + upd->tFAW = config->tFAW; + upd->tRAS = config->tRAS; + upd->tRRD = config->tRRD; + upd->tWTR = config->tWTR; +} + +void soc_display_memory_init_params(const MEMORY_INIT_UPD *old, + MEMORY_INIT_UPD *new) +{ + /* Display the parameters for MemoryInit */ + printk(BIOS_SPEW, "UPD values for MemoryInit at: 0x%p\n", new); + fsp_display_upd_value("AddrMode", sizeof(old->AddrMode), + old->AddrMode, new->AddrMode); + fsp_display_upd_value("ChanMask", sizeof(old->ChanMask), + old->ChanMask, new->ChanMask); + fsp_display_upd_value("ChanWidth", sizeof(old->ChanWidth), + old->ChanWidth, new->ChanWidth); + fsp_display_upd_value("DramDensity", sizeof(old->DramDensity), + old->DramDensity, new->DramDensity); + fsp_display_upd_value("DramRonVal", sizeof(old->DramRonVal), + old->DramRonVal, new->DramRonVal); + fsp_display_upd_value("DramRttNomVal", sizeof(old->DramRttNomVal), + old->DramRttNomVal, new->DramRttNomVal); + fsp_display_upd_value("DramRttWrVal", sizeof(old->DramRttWrVal), + old->DramRttWrVal, new->DramRttWrVal); + fsp_display_upd_value("DramSpeed", sizeof(old->DramSpeed), + old->DramSpeed, new->DramSpeed); + fsp_display_upd_value("DramType", sizeof(old->DramType), + old->DramType, new->DramType); + fsp_display_upd_value("DramWidth", sizeof(old->DramWidth), + old->DramWidth, new->DramWidth); + fsp_display_upd_value("EccScrubBlkSize", sizeof(old->EccScrubBlkSize), + old->EccScrubBlkSize, new->EccScrubBlkSize); + fsp_display_upd_value("EccScrubInterval", sizeof(old->EccScrubInterval), + old->EccScrubInterval, new->EccScrubInterval); + fsp_display_upd_value("Flags", sizeof(old->Flags), old->Flags, + new->Flags); + fsp_display_upd_value("FspReservedMemoryLength", + sizeof(old->FspReservedMemoryLength), + old->FspReservedMemoryLength, new->FspReservedMemoryLength); + fsp_display_upd_value("RankMask", sizeof(old->RankMask), old->RankMask, + new->RankMask); + fsp_display_upd_value("RmuBaseAddress", sizeof(old->RmuBaseAddress), + old->RmuBaseAddress, new->RmuBaseAddress); + fsp_display_upd_value("RmuLength", sizeof(old->RmuLength), + old->RmuLength, new->RmuLength); + fsp_display_upd_value("SerialPortBaseAddress", + sizeof(old->SerialPortBaseAddress), + old->SerialPortBaseAddress, new->SerialPortBaseAddress); + fsp_display_upd_value("SmmTsegSize", sizeof(old->SmmTsegSize), + old->SmmTsegSize, new->SmmTsegSize); + fsp_display_upd_value("SocRdOdtVal", sizeof(old->SocRdOdtVal), + old->SocRdOdtVal, new->SocRdOdtVal); + fsp_display_upd_value("SocWrRonVal", sizeof(old->SocWrRonVal), + old->SocWrRonVal, new->SocWrRonVal); + fsp_display_upd_value("SocWrSlewRate", sizeof(old->SocWrSlewRate), + old->SocWrSlewRate, new->SocWrSlewRate); + fsp_display_upd_value("SrInt", sizeof(old->SrInt), old->SrInt, + new->SrInt); + fsp_display_upd_value("SrTemp", sizeof(old->SrTemp), old->SrTemp, + new->SrTemp); + fsp_display_upd_value("tCL", sizeof(old->tCL), old->tCL, new->tCL); + fsp_display_upd_value("tFAW", sizeof(old->tFAW), old->tFAW, new->tFAW); + fsp_display_upd_value("tRAS", sizeof(old->tRAS), old->tRAS, new->tRAS); + fsp_display_upd_value("tRRD", sizeof(old->tRRD), old->tRRD, new->tRRD); + fsp_display_upd_value("tWTR", sizeof(old->tWTR), old->tWTR, new->tWTR); +} + +void soc_after_ram_init(struct romstage_params *params) +{ + /* Disable the ROM shadow 0x000e0000 - 0x000fffff */ + disable_rom_shadow(); + + /* Initialize the PCIe bridges */ + pcie_init(); +} diff --git a/src/soc/intel/quark/romstage/mtrr.c b/src/soc/intel/quark/romstage/mtrr.c index ce5bd4a..e6bb51f 100644 --- a/src/soc/intel/quark/romstage/mtrr.c +++ b/src/soc/intel/quark/romstage/mtrr.c @@ -19,7 +19,7 @@ #include <cpu/x86/mtrr.h> #include <soc/intel/common/util.h> #include <soc/pci_devs.h> -#include <soc/romstage.h> +#include <soc/reg_access.h> asmlinkage void *soc_set_mtrrs(void *top_of_stack) { diff --git a/src/soc/intel/quark/romstage/romstage.c b/src/soc/intel/quark/romstage/romstage.c index 4f9b698..9ee4135 100644 --- a/src/soc/intel/quark/romstage/romstage.c +++ b/src/soc/intel/quark/romstage/romstage.c @@ -17,21 +17,14 @@ #include <arch/early_variables.h> #include <console/console.h> -#include <cbfs.h> -#include "../chip.h" -#include <device/pci_def.h> -#include <fsp/car.h> #include <fsp/util.h> #include <lib.h> -#include <soc/intel/common/util.h> -#include <soc/iomap.h> #include <soc/pci_devs.h> #include <soc/pm.h> #include <soc/romstage.h> #include <soc/reg_access.h> -#include <string.h> -static const struct reg_script clear_smi_and_wake_events[] = { +static const struct reg_script clear_smi_and_wake_events_script[] = { /* Clear any SMI or wake events */ REG_GPE0_READ(R_QNC_GPE0BLK_GPE0S), REG_GPE0_READ(R_QNC_GPE0BLK_SMIS), @@ -40,221 +33,20 @@ static const struct reg_script clear_smi_and_wake_events[] = { REG_SCRIPT_END }; -static const struct reg_script legacy_gpio_init[] = { - /* Temporarily enable the legacy GPIO controller */ - REG_PCI_WRITE32(R_QNC_LPC_GBA_BASE, IO_ADDRESS_VALID - | LEGACY_GPIO_BASE_ADDRESS), - /* Temporarily enable the GPE controller */ - REG_PCI_WRITE32(R_QNC_LPC_GPE0BLK, IO_ADDRESS_VALID - | GPE0_BASE_ADDRESS), - REG_PCI_OR8(PCI_COMMAND, PCI_COMMAND_IO), - REG_SCRIPT_END -}; - -static const struct reg_script i2c_gpio_controller_init[] = { - /* Temporarily enable the GPIO controller */ - REG_PCI_WRITE32(PCI_BASE_ADDRESS_0, I2C_BASE_ADDRESS), - REG_PCI_WRITE32(PCI_BASE_ADDRESS_1, GPIO_BASE_ADDRESS), - REG_PCI_OR8(PCI_COMMAND, PCI_COMMAND_MEMORY), - REG_SCRIPT_END -}; - -static const struct reg_script hsuart_init[] = { - /* Enable the HSUART */ - REG_PCI_WRITE32(PCI_BASE_ADDRESS_0, UART_BASE_ADDRESS), - REG_PCI_OR8(PCI_COMMAND, PCI_COMMAND_MEMORY), - REG_SCRIPT_END -}; - -asmlinkage void *car_stage_c_entry(void) -{ - post_code(0x20); - if (IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1)) { - FSP_INFO_HEADER *fih; - struct cache_as_ram_params car_params = {0}; - void *top_of_stack; - - /* Copy the FSP binary into ESRAM */ - memcpy((void *)CONFIG_FSP_ESRAM_LOC, (void *)CONFIG_FSP_LOC, - 0x00040000); - - /* Locate the FSP header in ESRAM */ - fih = find_fsp(CONFIG_FSP_ESRAM_LOC); - - /* Start the early verstage/romstage code */ - post_code(0x2A); - car_params.fih = fih; - top_of_stack = cache_as_ram_main(&car_params); - - /* Initialize MTRRs and switch stacks after RAM initialized */ - return top_of_stack; - } - - return NULL; -} - -void car_soc_pre_console_init(void) -{ - /* Initialize the controllers */ - reg_script_run_on_dev(I2CGPIO_BDF, i2c_gpio_controller_init); - reg_script_run_on_dev(LPC_BDF, legacy_gpio_init); - - /* Enable the HSUART */ - if (IS_ENABLED(CONFIG_ENABLE_BUILTIN_HSUART0)) - reg_script_run_on_dev(HSUART0_BDF, hsuart_init); - if (IS_ENABLED(CONFIG_ENABLE_BUILTIN_HSUART1)) - reg_script_run_on_dev(HSUART1_BDF, hsuart_init); -} - -void car_soc_post_console_init(void) -{ - report_platform_info(); -}; - -static struct chipset_power_state power_state CAR_GLOBAL; - -struct chipset_power_state *fill_power_state(void) -{ - struct chipset_power_state *ps = car_get_var_ptr(&power_state); - - ps->prev_sleep_state = ACPI_S0; - printk(BIOS_DEBUG, "prev_sleep_state %d\n", ps->prev_sleep_state); - return ps; -} - -/* Initialize the UPD parameters for MemoryInit */ -void soc_memory_init_params(struct romstage_params *params, - MEMORY_INIT_UPD *upd) +void clear_smi_and_wake_events(void) { - const struct device *dev; - const struct soc_intel_quark_config *config; - struct chipset_power_state *ps = car_get_var_ptr(&power_state); - char *rmu_file; - size_t rmu_file_len; - - /* Locate the configuration data from devicetree.cb */ - dev = dev_find_slot(0, LPC_DEV_FUNC); - if (!dev) { - printk(BIOS_ERR, - "Error! Device (PCI:0:%02x.%01x) not found, " - "soc_memory_init_params!\n", PCI_DEVICE_NUMBER_QNC_LPC, - PCI_FUNCTION_NUMBER_QNC_LPC); - return; - } - config = dev->chip_info; - - /* Display the ROM shadow data */ - hexdump((void *)0x000ffff0, 0x10); + struct chipset_power_state *ps; /* Clear SMI and wake events */ - if (ps->prev_sleep_state != ACPI_S3) { + ps = get_power_state(); + if (ps->prev_sleep_state != 3) { printk(BIOS_SPEW, "Clearing SMI interrupts and wake events\n"); - reg_script_run_on_dev(LPC_BDF, clear_smi_and_wake_events); + reg_script_run_on_dev(LPC_BDF, + clear_smi_and_wake_events_script); } - - /* Locate the RMU data file in flash */ - rmu_file = cbfs_boot_map_with_leak("rmu.bin", CBFS_TYPE_RAW, - &rmu_file_len); - if (!rmu_file) - die("Microcode file (rmu.bin) not found."); - - /* Update the UPD data for MemoryInit */ - printk(BIOS_DEBUG, "Updating UPD values for MemoryInit: 0x%p\n", upd); - upd->AddrMode = config->AddrMode; - upd->ChanMask = config->ChanMask; - upd->ChanWidth = config->ChanWidth; - upd->DramDensity = config->DramDensity; - upd->DramRonVal = config->DramRonVal; - upd->DramRttNomVal = config->DramRttNomVal; - upd->DramRttWrVal = config->DramRttWrVal; - upd->DramSpeed = config->DramSpeed; - upd->DramType = config->DramType; - upd->DramWidth = config->DramWidth; - upd->EccScrubBlkSize = config->EccScrubBlkSize; - upd->EccScrubInterval = config->EccScrubInterval; - upd->Flags = config->Flags; - upd->FspReservedMemoryLength = config->FspReservedMemoryLength; - upd->RankMask = config->RankMask; - upd->RmuBaseAddress = (uintptr_t)rmu_file; - upd->RmuLength = rmu_file_len; - upd->SerialPortBaseAddress = UART_BASE_ADDRESS; - upd->SmmTsegSize = IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) ? - config->SmmTsegSize : 0; - upd->SocRdOdtVal = config->SocRdOdtVal; - upd->SocWrRonVal = config->SocWrRonVal; - upd->SocWrSlewRate = config->SocWrSlewRate; - upd->SrInt = config->SrInt; - upd->SrTemp = config->SrTemp; - upd->tCL = config->tCL; - upd->tFAW = config->tFAW; - upd->tRAS = config->tRAS; - upd->tRRD = config->tRRD; - upd->tWTR = config->tWTR; } -void soc_display_memory_init_params(const MEMORY_INIT_UPD *old, - MEMORY_INIT_UPD *new) -{ - /* Display the parameters for MemoryInit */ - printk(BIOS_SPEW, "UPD values for MemoryInit at: 0x%p\n", new); - fsp_display_upd_value("AddrMode", sizeof(old->AddrMode), - old->AddrMode, new->AddrMode); - fsp_display_upd_value("ChanMask", sizeof(old->ChanMask), - old->ChanMask, new->ChanMask); - fsp_display_upd_value("ChanWidth", sizeof(old->ChanWidth), - old->ChanWidth, new->ChanWidth); - fsp_display_upd_value("DramDensity", sizeof(old->DramDensity), - old->DramDensity, new->DramDensity); - fsp_display_upd_value("DramRonVal", sizeof(old->DramRonVal), - old->DramRonVal, new->DramRonVal); - fsp_display_upd_value("DramRttNomVal", sizeof(old->DramRttNomVal), - old->DramRttNomVal, new->DramRttNomVal); - fsp_display_upd_value("DramRttWrVal", sizeof(old->DramRttWrVal), - old->DramRttWrVal, new->DramRttWrVal); - fsp_display_upd_value("DramSpeed", sizeof(old->DramSpeed), - old->DramSpeed, new->DramSpeed); - fsp_display_upd_value("DramType", sizeof(old->DramType), - old->DramType, new->DramType); - fsp_display_upd_value("DramWidth", sizeof(old->DramWidth), - old->DramWidth, new->DramWidth); - fsp_display_upd_value("EccScrubBlkSize", sizeof(old->EccScrubBlkSize), - old->EccScrubBlkSize, new->EccScrubBlkSize); - fsp_display_upd_value("EccScrubInterval", sizeof(old->EccScrubInterval), - old->EccScrubInterval, new->EccScrubInterval); - fsp_display_upd_value("Flags", sizeof(old->Flags), old->Flags, - new->Flags); - fsp_display_upd_value("FspReservedMemoryLength", - sizeof(old->FspReservedMemoryLength), - old->FspReservedMemoryLength, new->FspReservedMemoryLength); - fsp_display_upd_value("RankMask", sizeof(old->RankMask), old->RankMask, - new->RankMask); - fsp_display_upd_value("RmuBaseAddress", sizeof(old->RmuBaseAddress), - old->RmuBaseAddress, new->RmuBaseAddress); - fsp_display_upd_value("RmuLength", sizeof(old->RmuLength), - old->RmuLength, new->RmuLength); - fsp_display_upd_value("SerialPortBaseAddress", - sizeof(old->SerialPortBaseAddress), - old->SerialPortBaseAddress, new->SerialPortBaseAddress); - fsp_display_upd_value("SmmTsegSize", sizeof(old->SmmTsegSize), - old->SmmTsegSize, new->SmmTsegSize); - fsp_display_upd_value("SocRdOdtVal", sizeof(old->SocRdOdtVal), - old->SocRdOdtVal, new->SocRdOdtVal); - fsp_display_upd_value("SocWrRonVal", sizeof(old->SocWrRonVal), - old->SocWrRonVal, new->SocWrRonVal); - fsp_display_upd_value("SocWrSlewRate", sizeof(old->SocWrSlewRate), - old->SocWrSlewRate, new->SocWrSlewRate); - fsp_display_upd_value("SrInt", sizeof(old->SrInt), old->SrInt, - new->SrInt); - fsp_display_upd_value("SrTemp", sizeof(old->SrTemp), old->SrTemp, - new->SrTemp); - fsp_display_upd_value("tCL", sizeof(old->tCL), old->tCL, new->tCL); - fsp_display_upd_value("tFAW", sizeof(old->tFAW), old->tFAW, new->tFAW); - fsp_display_upd_value("tRAS", sizeof(old->tRAS), old->tRAS, new->tRAS); - fsp_display_upd_value("tRRD", sizeof(old->tRRD), old->tRRD, new->tRRD); - fsp_display_upd_value("tWTR", sizeof(old->tWTR), old->tWTR, new->tWTR); -} - -void soc_after_ram_init(struct romstage_params *params) +void disable_rom_shadow(void) { uint32_t data; @@ -273,7 +65,4 @@ void soc_after_ram_init(struct romstage_params *params) /* Display the DRAM data */ hexdump((void *)0x000ffff0, 0x10); - - /* Initialize the PCIe bridges */ - pcie_init(); }
participants (1)
-
Lee Leahy