coreboot-gerrit July 2016

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: arch/riscv: Unconditionally start payloads in machine mode
by Jonathan Neuschäfer 07 Jul '16

07 Jul '16

Jonathan Neuschäfer (j.neuschaefer(a)gmx.net) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15510 -gerrit commit 889b7d7294d5c11266857219efb17f23a8003a72 Author: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Date: Thu Jul 7 20:53:29 2016 +0200 arch/riscv: Unconditionally start payloads in machine mode Change-Id: I5cbfc90afd3febab33835935f08005136a3f47e9 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> --- src/arch/riscv/boot.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/src/arch/riscv/boot.c b/src/arch/riscv/boot.c index 96526bf..7435490 100644 --- a/src/arch/riscv/boot.c +++ b/src/arch/riscv/boot.c @@ -24,11 +24,9 @@ void arch_prog_run(struct prog *prog) if (ENV_RAMSTAGE && prog_type(prog) == PROG_PAYLOAD) { initVirtualMemory(); - write_csr(mepc, doit); - asm volatile("eret"); - } else { - doit(prog_entry_arg(prog)); } + + doit(prog_entry_arg(prog)); } int arch_supports_bounce_buffer(void)

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Patch set updated for coreboot: spike-riscv: Register RAM resource at 0x80000000
by Jonathan Neuschäfer 07 Jul '16

07 Jul '16

Jonathan Neuschäfer (j.neuschaefer(a)gmx.net) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15511 -gerrit commit 9bd1a9a87b34beef86e3f45aaa28a1080689a920 Author: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Date: Thu Jul 7 20:53:29 2016 +0200 spike-riscv: Register RAM resource at 0x80000000 Without this patch, the CBFS loader won't load segments into the RAM. Change-Id: If05c8edb51f9fe2f7af84178826f93b193cfd8a9 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> --- src/mainboard/emulation/spike-riscv/mainboard.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/src/mainboard/emulation/spike-riscv/mainboard.c b/src/mainboard/emulation/spike-riscv/mainboard.c index 111e9b1..df2bdd6 100644 --- a/src/mainboard/emulation/spike-riscv/mainboard.c +++ b/src/mainboard/emulation/spike-riscv/mainboard.c @@ -19,13 +19,21 @@ static void mainboard_enable(device_t dev) { + /* + * Size of the emulated system RAM. On hardware, this would be external + * DDR memory. + * + * TODO: Get this size from the hardware-supplied configuration string. + */ + const size_t ram_size = 1*GiB; if (!dev) { printk(BIOS_EMERG, "No dev0; die\n"); while (1); } - ram_resource(dev, 0, 2048, 32768); + ram_resource(dev, 0, 0x80000000/KiB, ram_size/KiB); + cbmem_recovery(0); }

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Patch set updated for coreboot: vboot2: tpm2 factory initialization.
by Martin Roth 07 Jul '16

07 Jul '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15571 -gerrit commit 3f1ccfd259886c38eaba41b7abe55a4b07d5dfd4 Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Mon Jun 6 12:12:34 2016 -0700 vboot2: tpm2 factory initialization. This patch adds a TPM2 specific path in the vboot2 initialization sequence when the device is turned on in the factory for the first time, namely two secure NVRAM spaces are created, with different access privileges. The higher privilege space can be modified only be the RO firmware, and the lower privilege space can be modified by both RO and RW firmware. The API is being modified to hide the TPM implementation details from the caller. Some functions previously exported as global are in fact not used anywhere else, they are being defined static. BRANCH=none BUG=chrome-os-partner:50645 TEST=when this code is enabled the two secure spaces are successfully created during factory initialization. Original-Commit-Id: 5f082d6a9b095c3efc283b7a49eac9b4f2bcb6ec Original-Change-Id: I917b2f74dfdbd214d7f651ce3d4b80f4a18def20 Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/353916 Original-Reviewed-by: Bill Richardson <wfrichar(a)chromium.org> Original-Reviewed-by: Darren Krahn <dkrahn(a)chromium.org> squashed: mock tpm: drop unused functions safe_write() and safe_define_space() functions are defined in secdata_mock.c, but not used in mocked TPM mode. The actual functions have been redefined as static recently and their declarations were removed from src/include/antirollback.h, which now causes compilation problems when CONFIG_VBOOT2_MOCK_SECDATA is defined. Dropping the functions from secdata_mock.c solves the problem. BRANCH=none BUG=none TEST=compilation in mock secdata mode does not fail any more. Original-Commit-Id: c6d7824f52534ecd3b02172cb9078f03e318cb2b Original-Change-Id: Ia781ce99630d759469d2bded40952ed21830e611 Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/356291 Original-Tested-by: Caesar Wang <wxt(a)rock-chips.com> Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-by: Randall Spangler <rspangler(a)chromium.org> Change-Id: Icb686c5f9129067eb4bb3ea10bbb85a075b29955 Signed-off-by: Martin Roth <martinroth(a)chromium.org> --- src/include/antirollback.h | 16 -- .../google/chromeos/vboot2/antirollback.c | 187 +++++++++++++++------ .../google/chromeos/vboot2/secdata_mock.c | 10 -- 3 files changed, 131 insertions(+), 82 deletions(-) diff --git a/src/include/antirollback.h b/src/include/antirollback.h index 5ba36f7..f088ee2 100644 --- a/src/include/antirollback.h +++ b/src/include/antirollback.h @@ -63,22 +63,6 @@ uint32_t tpm_extend_pcr(struct vb2_context *ctx, int pcr, uint32_t tpm_clear_and_reenable(void); /** - * Like tlcl_write(), but checks for write errors due to hitting the 64-write - * limit and clears the TPM when that happens. This can only happen when the - * TPM is unowned, so it is OK to clear it (and we really have no choice). - * This is not expected to happen frequently, but it could happen. - */ -uint32_t safe_write(uint32_t index, const void *data, uint32_t length); - -/** - * Similarly to safe_write(), this ensures we don't fail a DefineSpace because - * we hit the TPM write limit. This is even less likely to happen than with - * writes because we only define spaces once at initialization, but we'd rather - * be paranoid about this. - */ -uint32_t safe_define_space(uint32_t index, uint32_t perm, uint32_t size); - -/** * Perform one-time initializations. * * Create the NVRAM spaces, and set their initial values as needed. Sets the diff --git a/src/vendorcode/google/chromeos/vboot2/antirollback.c b/src/vendorcode/google/chromeos/vboot2/antirollback.c index fbc6d42..621758a 100644 --- a/src/vendorcode/google/chromeos/vboot2/antirollback.c +++ b/src/vendorcode/google/chromeos/vboot2/antirollback.c @@ -10,8 +10,8 @@ #include <stdlib.h> #include <string.h> #include <tpm_lite/tlcl.h> -#include <tpm_lite/tss_constants.h> #include <vb2_api.h> +#include <console/console.h> #ifndef offsetof #define offsetof(A,B) __builtin_offsetof(A,B) @@ -36,6 +36,8 @@ } while (0) +static uint32_t safe_write(uint32_t index, const void *data, uint32_t length); + uint32_t tpm_extend_pcr(struct vb2_context *ctx, int pcr, enum vb2_pcr_digest which_digest) { @@ -52,38 +54,6 @@ uint32_t tpm_extend_pcr(struct vb2_context *ctx, int pcr, return tlcl_extend(pcr, buffer, NULL); } -uint32_t tpm_clear_and_reenable(void) -{ - VBDEBUG("TPM: Clear and re-enable\n"); - RETURN_ON_FAILURE(tlcl_force_clear()); - RETURN_ON_FAILURE(tlcl_set_enable()); - RETURN_ON_FAILURE(tlcl_set_deactivated(0)); - - return TPM_SUCCESS; -} - -uint32_t safe_write(uint32_t index, const void *data, uint32_t length) -{ - uint32_t result = tlcl_write(index, data, length); - if (result == TPM_E_MAXNVWRITES) { - RETURN_ON_FAILURE(tpm_clear_and_reenable()); - return tlcl_write(index, data, length); - } else { - return result; - } -} - -uint32_t safe_define_space(uint32_t index, uint32_t perm, uint32_t size) -{ - uint32_t result = tlcl_define_space(index, perm, size); - if (result == TPM_E_MAXNVWRITES) { - RETURN_ON_FAILURE(tpm_clear_and_reenable()); - return tlcl_define_space(index, perm, size); - } else { - return result; - } -} - static uint32_t read_space_firmware(struct vb2_context *ctx) { int attempts = 3; @@ -135,33 +105,110 @@ static uint32_t write_secdata(uint32_t index, return TPM_E_CORRUPTED_STATE; } -uint32_t factory_initialize_tpm(struct vb2_context *ctx) +/* + * This is derived from rollback_index.h of vboot_reference. see struct + * RollbackSpaceKernel for details. + */ +static const uint8_t secdata_kernel[] = { + 0x02, + 0x4C, 0x57, 0x52, 0x47, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, + 0xE8, +}; + +#if IS_ENABLED(CONFIG_TPM2) + +/* Nothing special in the TPM2 path yet. */ +static uint32_t safe_write(uint32_t index, const void *data, uint32_t length) { - TPM_PERMANENT_FLAGS pflags; - uint32_t result; - /* this is derived from rollback_index.h of vboot_reference. see struct - * RollbackSpaceKernel for details. */ - static const uint8_t secdata_kernel[] = { - 0x02, - 0x4C, 0x57, 0x52, 0x47, - 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, - 0xE8, - }; + return tlcl_write(index, data, length); +} - VBDEBUG("TPM: factory initialization\n"); +static uint32_t set_firmware_space(const void *firmware_blob) +{ + RETURN_ON_FAILURE(tlcl_define_space(FIRMWARE_NV_INDEX, + high_privilege, + VB2_SECDATA_SIZE)); + RETURN_ON_FAILURE(safe_write(FIRMWARE_NV_INDEX, firmware_blob, + VB2_SECDATA_SIZE)); + return TPM_SUCCESS; +} - /* - * Do a full test. This only happens the first time the device is - * turned on in the factory, so performance is not an issue. This is - * almost certainly not necessary, but it gives us more confidence - * about some code paths below that are difficult to - * test---specifically the ones that set lifetime flags, and are only - * executed once per physical TPM. - */ - result = tlcl_self_test_full(); - if (result != TPM_SUCCESS) +static uint32_t set_kernel_space(const void *kernel_blob) +{ + RETURN_ON_FAILURE(tlcl_define_space(KERNEL_NV_INDEX, + low_privilege, + sizeof(secdata_kernel))); + RETURN_ON_FAILURE(safe_write(KERNEL_NV_INDEX, kernel_blob, + sizeof(secdata_kernel))); + return TPM_SUCCESS; +} + +static uint32_t _factory_initialize_tpm(struct vb2_context *ctx) +{ + RETURN_ON_FAILURE(set_firmware_space(ctx->secdata)); + RETURN_ON_FAILURE(set_kernel_space(secdata_kernel)); + return TPM_SUCCESS; +} + +uint32_t tpm_clear_and_reenable(void) +{ + VBDEBUG("TPM: Clear and re-enable\n"); + return TPM_SUCCESS; +} + +#else + +uint32_t tpm_clear_and_reenable(void) +{ + VBDEBUG("TPM: Clear and re-enable\n"); + RETURN_ON_FAILURE(tlcl_force_clear()); + RETURN_ON_FAILURE(tlcl_set_enable()); + RETURN_ON_FAILURE(tlcl_set_deactivated(0)); + + return TPM_SUCCESS; +} + +/** + * Like tlcl_write(), but checks for write errors due to hitting the 64-write + * limit and clears the TPM when that happens. This can only happen when the + * TPM is unowned, so it is OK to clear it (and we really have no choice). + * This is not expected to happen frequently, but it could happen. + */ + +static uint32_t safe_write(uint32_t index, const void *data, uint32_t length) +{ + uint32_t result = tlcl_write(index, data, length); + if (result == TPM_E_MAXNVWRITES) { + RETURN_ON_FAILURE(tpm_clear_and_reenable()); + return tlcl_write(index, data, length); + } else { return result; + } +} + +/** + * Similarly to safe_write(), this ensures we don't fail a DefineSpace because + * we hit the TPM write limit. This is even less likely to happen than with + * writes because we only define spaces once at initialization, but we'd + * rather be paranoid about this. + */ +static uint32_t safe_define_space(uint32_t index, uint32_t perm, uint32_t size) +{ + uint32_t result = tlcl_define_space(index, perm, size); + if (result == TPM_E_MAXNVWRITES) { + RETURN_ON_FAILURE(tpm_clear_and_reenable()); + return tlcl_define_space(index, perm, size); + } else { + return result; + } +} + +static uint32_t _factory_initialize_tpm(struct vb2_context *ctx) +{ + TPM_PERMANENT_FLAGS pflags; + uint32_t result; result = tlcl_get_permanent_flags(&pflags); if (result != TPM_SUCCESS) @@ -215,6 +262,34 @@ uint32_t factory_initialize_tpm(struct vb2_context *ctx) RETURN_ON_FAILURE(write_secdata(FIRMWARE_NV_INDEX, ctx->secdata, VB2_SECDATA_SIZE)); + return TPM_SUCCESS; +} +#endif + +uint32_t factory_initialize_tpm(struct vb2_context *ctx) +{ + uint32_t result; + + /* Defines and sets vb2 secdata space */ + vb2api_secdata_create(ctx); + + VBDEBUG("TPM: factory initialization\n"); + + /* + * Do a full test. This only happens the first time the device is + * turned on in the factory, so performance is not an issue. This is + * almost certainly not necessary, but it gives us more confidence + * about some code paths below that are difficult to + * test---specifically the ones that set lifetime flags, and are only + * executed once per physical TPM. + */ + result = tlcl_self_test_full(); + if (result != TPM_SUCCESS) + return result; + + result = _factory_initialize_tpm(ctx); + if (result != TPM_SUCCESS) + return result; VBDEBUG("TPM: factory initialization successful\n"); diff --git a/src/vendorcode/google/chromeos/vboot2/secdata_mock.c b/src/vendorcode/google/chromeos/vboot2/secdata_mock.c index 3bd4b17..03616c1 100644 --- a/src/vendorcode/google/chromeos/vboot2/secdata_mock.c +++ b/src/vendorcode/google/chromeos/vboot2/secdata_mock.c @@ -21,16 +21,6 @@ uint32_t tpm_clear_and_reenable(void) return TPM_SUCCESS; } -uint32_t safe_write(uint32_t index, const void *data, uint32_t length) -{ - return TPM_SUCCESS; -} - -uint32_t safe_define_space(uint32_t index, uint32_t perm, uint32_t size) -{ - return TPM_SUCCESS; -} - uint32_t antirollback_read_space_firmware(struct vb2_context *ctx) { vb2api_secdata_create(ctx);

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Patch set updated for coreboot: Gale: Add LED support.
by Martin Roth 07 Jul '16

07 Jul '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15572 -gerrit commit 02858a2993da8ff7ac39d9e27c7eb066ee95f701 Author: Suresh Rajashekara <sureshraj(a)google.com> Date: Wed May 18 17:48:33 2016 -0700 Gale: Add LED support. Reusing the LED patterns as it was defined for Storm/WW/Platform. BUG=b:29051518 TEST=After about 3 seconds of powering on the device different colors should be seen at the LED ring, depending on the state of the device. Alternatively, move the device to different states manually by appropriate actions (like dev mode, rec mode etc) and observe the colors. BRANCH=None Change-Id: I6f1b23fee15747a402e209a2d06f8794bbc2c5a1 Signed-off-by: Martin Roth <martinroth(a)chromium.org> Original-Commit-Id: be1194b095d9a5cf269710c43a27a5afb3e87b29 Original-Change-Id: Ie82d4e148025c0040cdb26f53f028d9b4cbe2332 Original-Signed-off-by: Suresh Rajashekara <sureshraj(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/355200 Original-Commit-Ready: Suresh Rajashekara <sureshraj(a)chromium.org> Original-Tested-by: Suresh Rajashekara <sureshraj(a)chromium.org> Original-Reviewed-by: Suresh Rajashekara <sureshraj(a)chromium.org> --- src/mainboard/google/gale/blsp.c | 18 ++++++++++++++++++ src/mainboard/google/gale/chromeos.c | 5 +---- 2 files changed, 19 insertions(+), 4 deletions(-) diff --git a/src/mainboard/google/gale/blsp.c b/src/mainboard/google/gale/blsp.c index 3be075f..2bc562a 100644 --- a/src/mainboard/google/gale/blsp.c +++ b/src/mainboard/google/gale/blsp.c @@ -34,6 +34,7 @@ #define IPQ40XX_I2C0_PINGROUP_1 1 #define IPQ40XX_I2C0_PINGROUP_2 (!IPQ40XX_I2C0_PINGROUP_1) +#define IPQ40XX_I2C1_PINGROUP_1 1 #if IPQ40XX_I2C0_PINGROUP_1 @@ -55,6 +56,16 @@ #endif + +#if IPQ40XX_I2C1_PINGROUP_1 + +#define SCL_GPIO_I2C1 34 +#define SDA_GPIO_I2C1 35 +#define GPIO_I2C1_FUNC_SCL 0x1 +#define GPIO_I2C1_FUNC_SDA 0x1 + +#endif + int blsp_i2c_init_board(blsp_qup_id_t id) { switch (id) { @@ -68,6 +79,13 @@ int blsp_i2c_init_board(blsp_qup_id_t id) gpio_tlmm_config_set(SCL_GPIO, GPIO_FUNC_SCL, GPIO_NO_PULL, GPIO_2MA, 1); #endif /* Pin Group 1 or 2 */ + +#if defined(IPQ40XX_I2C1_PINGROUP_1) + gpio_tlmm_config_set(SDA_GPIO_I2C1, GPIO_I2C1_FUNC_SDA, + GPIO_NO_PULL, GPIO_2MA, 1); + gpio_tlmm_config_set(SCL_GPIO_I2C1, GPIO_I2C1_FUNC_SCL, + GPIO_NO_PULL, GPIO_2MA, 1); +#endif break; default: return 1; diff --git a/src/mainboard/google/gale/chromeos.c b/src/mainboard/google/gale/chromeos.c index 7430407..beeb2a5 100644 --- a/src/mainboard/google/gale/chromeos.c +++ b/src/mainboard/google/gale/chromeos.c @@ -78,10 +78,7 @@ enum switch_state { static void display_pattern(int pattern) { -#if IS_ENABLED(notyet) - if (board_id() == BOARD_ID_WHIRLWIND_SP5) - ww_ring_display_pattern(GSBI_ID_7, pattern); -#endif + ww_ring_display_pattern(BLSP_QUP_ID_3, pattern); } #define WIPEOUT_MODE_DELAY_MS (8 * 1000)

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Patch set updated for coreboot: tpm: report firmware version
by Martin Roth 07 Jul '16

07 Jul '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15573 -gerrit commit 6b228f91985cc1738cab221da70a5b22ad5501ae Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Thu Jun 23 18:17:33 2016 -0700 tpm: report firmware version Some devices allow to retrieve firmware version by reading the same 4 byte register repeatedly until the entire version string is read. Let's print out TPM firmware version when available. Just in case something goes wrong limit the version string length to 200 bytes. CQ-DEPEND=CL:355701 BRANCH=none BUG=chrome-os-partner:54723 TEST=built the new firmware and ran it on Gru, observed the following in the coreboot console log: Connected to device vid:did:rid of 1ae0:0028:00 Firmware version: cr50_v1.1.4792-7a44484 Change-Id: Ia9f13a5bf1c34292b866f57c0d14470fe6ca9853 Signed-off-by: Martin Roth <martinroth(a)chromium.org> Original-Commit-Id: 1f54a30cebe808abf1b09478b47924bb722a0ca6 Original-Change-Id: Idb069dabb80d34a0efdf04c3c40a42ab0c8a3f94 Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/355704 Original-Reviewed-by: Scott Collyer <scollyer(a)chromium.org> --- src/drivers/spi/tpm/tpm.c | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/src/drivers/spi/tpm/tpm.c b/src/drivers/spi/tpm/tpm.c index b02fc5f..1b43bfb 100644 --- a/src/drivers/spi/tpm/tpm.c +++ b/src/drivers/spi/tpm/tpm.c @@ -32,6 +32,7 @@ #define TPM_DATA_FIFO_REG (TPM_LOCALITY_0_SPI_BASE + 0x24) #define TPM_DID_VID_REG (TPM_LOCALITY_0_SPI_BASE + 0xf00) #define TPM_RID_REG (TPM_LOCALITY_0_SPI_BASE + 0xf04) +#define TPM_FW_VER (TPM_LOCALITY_0_SPI_BASE + 0xf90) /* SPI Interface descriptor used by the driver. */ struct tpm_spi_if { @@ -355,6 +356,35 @@ int tpm2_init(struct spi_slave *spi_if) printk(BIOS_INFO, "Connected to device vid:did:rid of %4.4x:%4.4x:%2.2x\n", tpm_info.vendor_id, tpm_info.device_id, tpm_info.revision); + /* Let's report device FW version if available. */ + if (tpm_info.vendor_id == 0x1ae0) { + int chunk_count = 0; + char vstr[sizeof(cmd) + 1]; /* room for 4 chars + zero */ + + printk(BIOS_INFO, "Firmware version: "); + + /* + * Does not really matter what's written, this just makes sure + * the version is reported from the beginning. + */ + tpm2_write_reg(TPM_FW_VER, &cmd, sizeof(cmd)); + + /* Print it out in 4 byte chunks. */ + vstr[sizeof(vstr) - 1] = 0; + do { + tpm2_read_reg(TPM_FW_VER, vstr, sizeof(cmd)); + printk(BIOS_INFO, "%s", vstr); + + /* + * While string is not over, and no more than 200 + * characters. + * This is likely result in one extra printk() + * invocation with an empty string, not a big deal. + */ + } while (vstr[0] && (chunk_count++ < (200 / sizeof(cmd)))); + + printk(BIOS_INFO, "\n"); + } return 0; }

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Patch merged into coreboot/master: mainboard/google/reef: apply EVT board changes
by gerrit＠coreboot.org 07 Jul '16

07 Jul '16

the following patch was just integrated into master: commit 8d3c4d1bb39fa354df59abf55b37fc694a2cb7c9 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Jul 6 23:16:01 2016 -0500 mainboard/google/reef: apply EVT board changes Based on the board revision apply the correct GPIO changes. The only differences are the addition of 2 peripheral wake signals and a dedicated peripheral reset line. BUG=chrome-os-partner:54959,chrome-os-partner:54960,chrome-os-partner:54961 BRANCH=None TEST=Built and tested on reef. Change-Id: I9cac82158e70e0af1b454ec4581c2e4622b95b4b Signed-off-by: Aaron Durbin <adurbin(a)chromuim.org> Reviewed-on: https://review.coreboot.org/15562 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan(a)google.com> See https://review.coreboot.org/15562 for details. -gerrit

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Patch merged into coreboot/master: mainboard/google/reef: add board_id() support
by gerrit＠coreboot.org 07 Jul '16

07 Jul '16

the following patch was just integrated into master: commit ebe148d58ee7061c4ee9956e9995bade666a80e4 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Jul 6 22:53:51 2016 -0500 mainboard/google/reef: add board_id() support The board build version is provided by the EC on reef. Provide the necessary functional support for coreboot to differentiate the board versions. BUG=chrome-os-partner:54959,chrome-os-partner:54960,chrome-os-partner:54961 BRANCH=None TEST=Built and tested on reef. Change-Id: I1b7e8b2f4142753cde736148ca9495bcc625f318 Signed-off-by: Aaron Durbin <adurbin(a)chromuim.org> Reviewed-on: https://review.coreboot.org/15561 Tested-by: build bot (Jenkins) Reviewed-by: Werner Zeh <werner.zeh(a)siemens.com> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan(a)google.com> See https://review.coreboot.org/15561 for details. -gerrit

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Patch merged into coreboot/master: mainboard/google/reef: add memory SKU id support
by gerrit＠coreboot.org 07 Jul '16

07 Jul '16

the following patch was just integrated into master: commit fe767a7dc063ce05f546ced7238e5c535960b3ec Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Jul 6 22:51:05 2016 -0500 mainboard/google/reef: add memory SKU id support While the proto boards didn't have a memory SKU notion the EVT boards do. Therefore, provide support for selecting the proper memory SKU information based on the memory id straps. This works on EVT boards because the pins used for the strapping weren't used on proto. However, internal pullups need to be enabled so that proto boards read the correct id. BUG=chrome-os-partner:54949 BRANCH=None TEST=Built and used on reef for memory config. Change-Id: I8653260e5d1b9adc83b78ea2770c683b72535e11 Signed-off-by: Aaron Durbin <adurbin(a)chromuim.org> Reviewed-on: https://review.coreboot.org/15560 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan(a)google.com> See https://review.coreboot.org/15560 for details. -gerrit

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Patch merged into coreboot/master: soc/intel/apollolake: add LPDDR4 sku selection support
by gerrit＠coreboot.org 07 Jul '16

07 Jul '16

the following patch was just integrated into master: commit 87579aee69d8a82eac46f8d1f249560efab8afd4 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Jul 6 22:45:57 2016 -0500 soc/intel/apollolake: add LPDDR4 sku selection support Instead of having all the mainboards put similar logic into their own code provide common mechanism for memory SKU selection. A function, meminit_lpddr4_by_sku(), is added that selects the proper configuration based on the SKU id and configuration passed in. LPDDR4 speed as well as DRAM device density configuration is associated for each logical channel per SKU id. BUG=chrome-os-partner:54949 BRANCH=None TEST=Built and used on reef for memory config. Change-Id: Ifc6a734040bb61a58bc3d4c128a6420a71245c6c Signed-off-by: Aaron Durbin <adurbin(a)chromuim.org> Reviewed-on: https://review.coreboot.org/15559 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan(a)google.com> See https://review.coreboot.org/15559 for details. -gerrit

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Patch merged into coreboot/master: soc/intel/apollolake: make internal pulls weak for gpio inputs
by gerrit＠coreboot.org 07 Jul '16

07 Jul '16

the following patch was just integrated into master: commit a790f1b0852158032b5c6993209b580d0b2c659e Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Jul 6 22:41:24 2016 -0500 soc/intel/apollolake: make internal pulls weak for gpio inputs The internal pulls for gpio_input_pullup() and gpio_input_pulldown() were using fairly strong pulls. Weaken them so that external pulls can override the internal ones. This matches the current assumptions of lib/gpio.c. BUG=chrome-os-partner:54949 BRANCH=None TEST=Built and used on reef for memory config. Change-Id: Ifda1d04d40141325f78db277eb0bd55574994abf Signed-off-by: Aaron Durbin <adurbin(a)chromuim.org> Reviewed-on: https://review.coreboot.org/15558 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Andrey Petrov <andrey.petrov(a)intel.com> Reviewed-by: Furquan Shaikh <furquan(a)google.com> See https://review.coreboot.org/15558 for details. -gerrit

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coreboot-gerrit July 2016