coreboot-gerrit July 2016

coreboot-gerrit@coreboot.org

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Patch merged into coreboot/master: lib/gpio: add pullup & pulldown gpio_base2_value() variants
by gerrit＠coreboot.org 07 Jul '16

07 Jul '16

the following patch was just integrated into master: commit f41ac2298eb61f2a524731a07c915416d562f17c Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Jul 6 22:37:10 2016 -0500 lib/gpio: add pullup & pulldown gpio_base2_value() variants Provide common implementations for gpio_base2_value() variants which configure the gpio for internal pullups and pulldowns. BUG=chrome-os-partner:54949 BRANCH=None TEST=Built and used on reef for memory config. Change-Id: I9be8813328e99d28eb4145501450caab25d51f37 Signed-off-by: Aaron Durbin <adurbin(a)chromuim.org> Reviewed-on: https://review.coreboot.org/15557 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan(a)google.com> See https://review.coreboot.org/15557 for details. -gerrit

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Patch set updated for coreboot: buildgcc: Never set GMP CFLAGS manually in order to get the right flags
by Paul Kocialkowski 07 Jul '16

07 Jul '16

Paul Kocialkowski (contact(a)paulk.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15452 -gerrit commit 557a74533c8c77d8dd881b0e937500e1668c6c0f Author: Paul Kocialkowski <contact(a)paulk.fr> Date: Fri Jun 17 21:41:00 2016 -0700 buildgcc: Never set GMP CFLAGS manually in order to get the right flags When no CFLAGS are explicitly provided to it, the GMP configure script will figure out the best optimization flags to use on its own. In particular, it will setup the march, mfpu and mtune flags based on hardware detection. However, when CFLAGS are provided, they are used as-is and such detection doesn't happen. When the march, mfpu and mtune flags are not provided (which happens when GMP wasn't built already), not only will related optimizations be disabled, but some code might not build because of missing support. This happens with NEON instructions on ARMv7 hosts. Thus, it is better not to set CFLAGS and leave it up to the GMP configure script to get them right and still reuse those later. Change-Id: I6ffcbac1298523d1b8ddf29a8bca1b00298828a7 Signed-off-by: Paul Kocialkowski <contact(a)paulk.fr> --- util/crossgcc/buildgcc | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index 3791cc9..92764b2 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -440,8 +440,7 @@ set_hostcflags_from_gmp() { } build_GMP() { - CC="$CC" CFLAGS="$HOSTCFLAGS" \ - ../${GMP_DIR}/configure --disable-shared --enable-fat \ + CC="$CC" ../${GMP_DIR}/configure --disable-shared --enable-fat \ --prefix=$TARGETDIR $OPTIONS \ || touch .failed $MAKE $JOBS || touch .failed

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New patch to review for coreboot: mock tpm: drop unused functions
by Martin Roth 07 Jul '16

07 Jul '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15574 -gerrit commit ee42678494a4daad393ff6d79ed982685a80a390 Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Sat Jun 25 11:22:12 2016 -0700 mock tpm: drop unused functions safe_write() and safe_define_space() functions are defined in secdata_mock.c, but not used in mocked TPM mode. The actual functions have been redefined as static recently and their declarations were removed from src/include/antirollback.h, which now causes compilation problems when CONFIG_VBOOT2_MOCK_SECDATA is defined. Dropping the functions from secdata_mock.c solves the problem. BRANCH=none BUG=none TEST=compilation in mock secdata mode does not fail any more. Change-Id: I60d33a16decb82d7911c21e5e76b24b33771f0bb Signed-off-by: Martin Roth <martinroth(a)chromium.org> Original-Commit-Id: c6d7824f52534ecd3b02172cb9078f03e318cb2b Original-Change-Id: Ia781ce99630d759469d2bded40952ed21830e611 Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/356291 Original-Tested-by: Caesar Wang <wxt(a)rock-chips.com> Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-by: Randall Spangler <rspangler(a)chromium.org> --- src/vendorcode/google/chromeos/vboot2/secdata_mock.c | 10 ---------- 1 file changed, 10 deletions(-) diff --git a/src/vendorcode/google/chromeos/vboot2/secdata_mock.c b/src/vendorcode/google/chromeos/vboot2/secdata_mock.c index 3bd4b17..03616c1 100644 --- a/src/vendorcode/google/chromeos/vboot2/secdata_mock.c +++ b/src/vendorcode/google/chromeos/vboot2/secdata_mock.c @@ -21,16 +21,6 @@ uint32_t tpm_clear_and_reenable(void) return TPM_SUCCESS; } -uint32_t safe_write(uint32_t index, const void *data, uint32_t length) -{ - return TPM_SUCCESS; -} - -uint32_t safe_define_space(uint32_t index, uint32_t perm, uint32_t size) -{ - return TPM_SUCCESS; -} - uint32_t antirollback_read_space_firmware(struct vb2_context *ctx) { vb2api_secdata_create(ctx);

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New patch to review for coreboot: tpm: report firmware version
by Martin Roth 07 Jul '16

07 Jul '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15573 -gerrit commit da1a1e5058766e47f09eb58552727691b976c7e3 Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Thu Jun 23 18:17:33 2016 -0700 tpm: report firmware version Some devices allow to retrieve firmware version by reading the same 4 byte register repeatedly until the entire version string is read. Let's print out TPM firmware version when available. Just in case something goes wrong limit the version string length to 200 bytes. CQ-DEPEND=CL:355701 BRANCH=none BUG=chrome-os-partner:54723 TEST=built the new firmware and ran it on Gru, observed the following in the coreboot console log: Connected to device vid:did:rid of 1ae0:0028:00 Firmware version: cr50_v1.1.4792-7a44484 Change-Id: Ia9f13a5bf1c34292b866f57c0d14470fe6ca9853 Signed-off-by: Martin Roth <martinroth(a)chromium.org> Original-Commit-Id: 1f54a30cebe808abf1b09478b47924bb722a0ca6 Original-Change-Id: Idb069dabb80d34a0efdf04c3c40a42ab0c8a3f94 Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/355704 Original-Reviewed-by: Scott Collyer <scollyer(a)chromium.org> --- src/drivers/spi/tpm/tpm.c | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/src/drivers/spi/tpm/tpm.c b/src/drivers/spi/tpm/tpm.c index b02fc5f..1b43bfb 100644 --- a/src/drivers/spi/tpm/tpm.c +++ b/src/drivers/spi/tpm/tpm.c @@ -32,6 +32,7 @@ #define TPM_DATA_FIFO_REG (TPM_LOCALITY_0_SPI_BASE + 0x24) #define TPM_DID_VID_REG (TPM_LOCALITY_0_SPI_BASE + 0xf00) #define TPM_RID_REG (TPM_LOCALITY_0_SPI_BASE + 0xf04) +#define TPM_FW_VER (TPM_LOCALITY_0_SPI_BASE + 0xf90) /* SPI Interface descriptor used by the driver. */ struct tpm_spi_if { @@ -355,6 +356,35 @@ int tpm2_init(struct spi_slave *spi_if) printk(BIOS_INFO, "Connected to device vid:did:rid of %4.4x:%4.4x:%2.2x\n", tpm_info.vendor_id, tpm_info.device_id, tpm_info.revision); + /* Let's report device FW version if available. */ + if (tpm_info.vendor_id == 0x1ae0) { + int chunk_count = 0; + char vstr[sizeof(cmd) + 1]; /* room for 4 chars + zero */ + + printk(BIOS_INFO, "Firmware version: "); + + /* + * Does not really matter what's written, this just makes sure + * the version is reported from the beginning. + */ + tpm2_write_reg(TPM_FW_VER, &cmd, sizeof(cmd)); + + /* Print it out in 4 byte chunks. */ + vstr[sizeof(vstr) - 1] = 0; + do { + tpm2_read_reg(TPM_FW_VER, vstr, sizeof(cmd)); + printk(BIOS_INFO, "%s", vstr); + + /* + * While string is not over, and no more than 200 + * characters. + * This is likely result in one extra printk() + * invocation with an empty string, not a big deal. + */ + } while (vstr[0] && (chunk_count++ < (200 / sizeof(cmd)))); + + printk(BIOS_INFO, "\n"); + } return 0; }

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New patch to review for coreboot: Gale: Add LED support.
by Martin Roth 07 Jul '16

07 Jul '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15572 -gerrit commit 09e0b9f1dacf6524ffe8ecbd48975e4db5ab5045 Author: Suresh Rajashekara <sureshraj(a)google.com> Date: Wed May 18 17:48:33 2016 -0700 Gale: Add LED support. Reusing the LED patterns as it was defined for Storm/WW/Platform. BUG=b:29051518 TEST=After about 3 seconds of powering on the device different colors should be seen at the LED ring, depending on the state of the device. Alternatively, move the device to different states manually by appropriate actions (like dev mode, rec mode etc) and observe the colors. BRANCH=None Change-Id: I6f1b23fee15747a402e209a2d06f8794bbc2c5a1 Signed-off-by: Martin Roth <martinroth(a)chromium.org> Original-Commit-Id: be1194b095d9a5cf269710c43a27a5afb3e87b29 Original-Change-Id: Ie82d4e148025c0040cdb26f53f028d9b4cbe2332 Original-Signed-off-by: Suresh Rajashekara <sureshraj(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/355200 Original-Commit-Ready: Suresh Rajashekara <sureshraj(a)chromium.org> Original-Tested-by: Suresh Rajashekara <sureshraj(a)chromium.org> Original-Reviewed-by: Suresh Rajashekara <sureshraj(a)chromium.org> --- src/mainboard/google/gale/blsp.c | 18 ++++++++++++++++++ src/mainboard/google/gale/chromeos.c | 5 +---- 2 files changed, 19 insertions(+), 4 deletions(-) diff --git a/src/mainboard/google/gale/blsp.c b/src/mainboard/google/gale/blsp.c index 3be075f..2bc562a 100644 --- a/src/mainboard/google/gale/blsp.c +++ b/src/mainboard/google/gale/blsp.c @@ -34,6 +34,7 @@ #define IPQ40XX_I2C0_PINGROUP_1 1 #define IPQ40XX_I2C0_PINGROUP_2 (!IPQ40XX_I2C0_PINGROUP_1) +#define IPQ40XX_I2C1_PINGROUP_1 1 #if IPQ40XX_I2C0_PINGROUP_1 @@ -55,6 +56,16 @@ #endif + +#if IPQ40XX_I2C1_PINGROUP_1 + +#define SCL_GPIO_I2C1 34 +#define SDA_GPIO_I2C1 35 +#define GPIO_I2C1_FUNC_SCL 0x1 +#define GPIO_I2C1_FUNC_SDA 0x1 + +#endif + int blsp_i2c_init_board(blsp_qup_id_t id) { switch (id) { @@ -68,6 +79,13 @@ int blsp_i2c_init_board(blsp_qup_id_t id) gpio_tlmm_config_set(SCL_GPIO, GPIO_FUNC_SCL, GPIO_NO_PULL, GPIO_2MA, 1); #endif /* Pin Group 1 or 2 */ + +#if defined(IPQ40XX_I2C1_PINGROUP_1) + gpio_tlmm_config_set(SDA_GPIO_I2C1, GPIO_I2C1_FUNC_SDA, + GPIO_NO_PULL, GPIO_2MA, 1); + gpio_tlmm_config_set(SCL_GPIO_I2C1, GPIO_I2C1_FUNC_SCL, + GPIO_NO_PULL, GPIO_2MA, 1); +#endif break; default: return 1; diff --git a/src/mainboard/google/gale/chromeos.c b/src/mainboard/google/gale/chromeos.c index 7430407..beeb2a5 100644 --- a/src/mainboard/google/gale/chromeos.c +++ b/src/mainboard/google/gale/chromeos.c @@ -78,10 +78,7 @@ enum switch_state { static void display_pattern(int pattern) { -#if IS_ENABLED(notyet) - if (board_id() == BOARD_ID_WHIRLWIND_SP5) - ww_ring_display_pattern(GSBI_ID_7, pattern); -#endif + ww_ring_display_pattern(BLSP_QUP_ID_3, pattern); } #define WIPEOUT_MODE_DELAY_MS (8 * 1000)

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New patch to review for coreboot: vboot2: tpm2 factory initialization.
by Martin Roth 07 Jul '16

07 Jul '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15571 -gerrit commit e52abeb329a179e314d27f50867d3cd30620de0e Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Mon Jun 6 12:12:34 2016 -0700 vboot2: tpm2 factory initialization. This patch adds a TPM2 specific path in the vboot2 initialization sequence when the device is turned on in the factory for the first time, namely two secure NVRAM spaces are created, with different access privileges. The higher privilege space can be modified only be the RO firmware, and the lower privilege space can be modified by both RO and RW firmware. The API is being modified to hide the TPM implementation details from the caller. Some functions previously exported as global are in fact not used anywhere else, they are being defined static. BRANCH=none BUG=chrome-os-partner:50645 TEST=when this code is enabled the two secure spaces are successfully created during factory initialization. Change-Id: Icb686c5f9129067eb4bb3ea10bbb85a075b29955 Signed-off-by: Martin Roth <martinroth(a)chromium.org> Original-Commit-Id: 5f082d6a9b095c3efc283b7a49eac9b4f2bcb6ec Original-Change-Id: I917b2f74dfdbd214d7f651ce3d4b80f4a18def20 Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/353916 Original-Reviewed-by: Bill Richardson <wfrichar(a)chromium.org> Original-Reviewed-by: Darren Krahn <dkrahn(a)chromium.org> --- src/include/antirollback.h | 16 -- .../google/chromeos/vboot2/antirollback.c | 187 +++++++++++++++------ 2 files changed, 131 insertions(+), 72 deletions(-) diff --git a/src/include/antirollback.h b/src/include/antirollback.h index 5ba36f7..f088ee2 100644 --- a/src/include/antirollback.h +++ b/src/include/antirollback.h @@ -63,22 +63,6 @@ uint32_t tpm_extend_pcr(struct vb2_context *ctx, int pcr, uint32_t tpm_clear_and_reenable(void); /** - * Like tlcl_write(), but checks for write errors due to hitting the 64-write - * limit and clears the TPM when that happens. This can only happen when the - * TPM is unowned, so it is OK to clear it (and we really have no choice). - * This is not expected to happen frequently, but it could happen. - */ -uint32_t safe_write(uint32_t index, const void *data, uint32_t length); - -/** - * Similarly to safe_write(), this ensures we don't fail a DefineSpace because - * we hit the TPM write limit. This is even less likely to happen than with - * writes because we only define spaces once at initialization, but we'd rather - * be paranoid about this. - */ -uint32_t safe_define_space(uint32_t index, uint32_t perm, uint32_t size); - -/** * Perform one-time initializations. * * Create the NVRAM spaces, and set their initial values as needed. Sets the diff --git a/src/vendorcode/google/chromeos/vboot2/antirollback.c b/src/vendorcode/google/chromeos/vboot2/antirollback.c index fbc6d42..621758a 100644 --- a/src/vendorcode/google/chromeos/vboot2/antirollback.c +++ b/src/vendorcode/google/chromeos/vboot2/antirollback.c @@ -10,8 +10,8 @@ #include <stdlib.h> #include <string.h> #include <tpm_lite/tlcl.h> -#include <tpm_lite/tss_constants.h> #include <vb2_api.h> +#include <console/console.h> #ifndef offsetof #define offsetof(A,B) __builtin_offsetof(A,B) @@ -36,6 +36,8 @@ } while (0) +static uint32_t safe_write(uint32_t index, const void *data, uint32_t length); + uint32_t tpm_extend_pcr(struct vb2_context *ctx, int pcr, enum vb2_pcr_digest which_digest) { @@ -52,38 +54,6 @@ uint32_t tpm_extend_pcr(struct vb2_context *ctx, int pcr, return tlcl_extend(pcr, buffer, NULL); } -uint32_t tpm_clear_and_reenable(void) -{ - VBDEBUG("TPM: Clear and re-enable\n"); - RETURN_ON_FAILURE(tlcl_force_clear()); - RETURN_ON_FAILURE(tlcl_set_enable()); - RETURN_ON_FAILURE(tlcl_set_deactivated(0)); - - return TPM_SUCCESS; -} - -uint32_t safe_write(uint32_t index, const void *data, uint32_t length) -{ - uint32_t result = tlcl_write(index, data, length); - if (result == TPM_E_MAXNVWRITES) { - RETURN_ON_FAILURE(tpm_clear_and_reenable()); - return tlcl_write(index, data, length); - } else { - return result; - } -} - -uint32_t safe_define_space(uint32_t index, uint32_t perm, uint32_t size) -{ - uint32_t result = tlcl_define_space(index, perm, size); - if (result == TPM_E_MAXNVWRITES) { - RETURN_ON_FAILURE(tpm_clear_and_reenable()); - return tlcl_define_space(index, perm, size); - } else { - return result; - } -} - static uint32_t read_space_firmware(struct vb2_context *ctx) { int attempts = 3; @@ -135,33 +105,110 @@ static uint32_t write_secdata(uint32_t index, return TPM_E_CORRUPTED_STATE; } -uint32_t factory_initialize_tpm(struct vb2_context *ctx) +/* + * This is derived from rollback_index.h of vboot_reference. see struct + * RollbackSpaceKernel for details. + */ +static const uint8_t secdata_kernel[] = { + 0x02, + 0x4C, 0x57, 0x52, 0x47, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, + 0xE8, +}; + +#if IS_ENABLED(CONFIG_TPM2) + +/* Nothing special in the TPM2 path yet. */ +static uint32_t safe_write(uint32_t index, const void *data, uint32_t length) { - TPM_PERMANENT_FLAGS pflags; - uint32_t result; - /* this is derived from rollback_index.h of vboot_reference. see struct - * RollbackSpaceKernel for details. */ - static const uint8_t secdata_kernel[] = { - 0x02, - 0x4C, 0x57, 0x52, 0x47, - 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, - 0xE8, - }; + return tlcl_write(index, data, length); +} - VBDEBUG("TPM: factory initialization\n"); +static uint32_t set_firmware_space(const void *firmware_blob) +{ + RETURN_ON_FAILURE(tlcl_define_space(FIRMWARE_NV_INDEX, + high_privilege, + VB2_SECDATA_SIZE)); + RETURN_ON_FAILURE(safe_write(FIRMWARE_NV_INDEX, firmware_blob, + VB2_SECDATA_SIZE)); + return TPM_SUCCESS; +} - /* - * Do a full test. This only happens the first time the device is - * turned on in the factory, so performance is not an issue. This is - * almost certainly not necessary, but it gives us more confidence - * about some code paths below that are difficult to - * test---specifically the ones that set lifetime flags, and are only - * executed once per physical TPM. - */ - result = tlcl_self_test_full(); - if (result != TPM_SUCCESS) +static uint32_t set_kernel_space(const void *kernel_blob) +{ + RETURN_ON_FAILURE(tlcl_define_space(KERNEL_NV_INDEX, + low_privilege, + sizeof(secdata_kernel))); + RETURN_ON_FAILURE(safe_write(KERNEL_NV_INDEX, kernel_blob, + sizeof(secdata_kernel))); + return TPM_SUCCESS; +} + +static uint32_t _factory_initialize_tpm(struct vb2_context *ctx) +{ + RETURN_ON_FAILURE(set_firmware_space(ctx->secdata)); + RETURN_ON_FAILURE(set_kernel_space(secdata_kernel)); + return TPM_SUCCESS; +} + +uint32_t tpm_clear_and_reenable(void) +{ + VBDEBUG("TPM: Clear and re-enable\n"); + return TPM_SUCCESS; +} + +#else + +uint32_t tpm_clear_and_reenable(void) +{ + VBDEBUG("TPM: Clear and re-enable\n"); + RETURN_ON_FAILURE(tlcl_force_clear()); + RETURN_ON_FAILURE(tlcl_set_enable()); + RETURN_ON_FAILURE(tlcl_set_deactivated(0)); + + return TPM_SUCCESS; +} + +/** + * Like tlcl_write(), but checks for write errors due to hitting the 64-write + * limit and clears the TPM when that happens. This can only happen when the + * TPM is unowned, so it is OK to clear it (and we really have no choice). + * This is not expected to happen frequently, but it could happen. + */ + +static uint32_t safe_write(uint32_t index, const void *data, uint32_t length) +{ + uint32_t result = tlcl_write(index, data, length); + if (result == TPM_E_MAXNVWRITES) { + RETURN_ON_FAILURE(tpm_clear_and_reenable()); + return tlcl_write(index, data, length); + } else { return result; + } +} + +/** + * Similarly to safe_write(), this ensures we don't fail a DefineSpace because + * we hit the TPM write limit. This is even less likely to happen than with + * writes because we only define spaces once at initialization, but we'd + * rather be paranoid about this. + */ +static uint32_t safe_define_space(uint32_t index, uint32_t perm, uint32_t size) +{ + uint32_t result = tlcl_define_space(index, perm, size); + if (result == TPM_E_MAXNVWRITES) { + RETURN_ON_FAILURE(tpm_clear_and_reenable()); + return tlcl_define_space(index, perm, size); + } else { + return result; + } +} + +static uint32_t _factory_initialize_tpm(struct vb2_context *ctx) +{ + TPM_PERMANENT_FLAGS pflags; + uint32_t result; result = tlcl_get_permanent_flags(&pflags); if (result != TPM_SUCCESS) @@ -215,6 +262,34 @@ uint32_t factory_initialize_tpm(struct vb2_context *ctx) RETURN_ON_FAILURE(write_secdata(FIRMWARE_NV_INDEX, ctx->secdata, VB2_SECDATA_SIZE)); + return TPM_SUCCESS; +} +#endif + +uint32_t factory_initialize_tpm(struct vb2_context *ctx) +{ + uint32_t result; + + /* Defines and sets vb2 secdata space */ + vb2api_secdata_create(ctx); + + VBDEBUG("TPM: factory initialization\n"); + + /* + * Do a full test. This only happens the first time the device is + * turned on in the factory, so performance is not an issue. This is + * almost certainly not necessary, but it gives us more confidence + * about some code paths below that are difficult to + * test---specifically the ones that set lifetime flags, and are only + * executed once per physical TPM. + */ + result = tlcl_self_test_full(); + if (result != TPM_SUCCESS) + return result; + + result = _factory_initialize_tpm(ctx); + if (result != TPM_SUCCESS) + return result; VBDEBUG("TPM: factory initialization successful\n");

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New patch to review for coreboot: tpm2: add marshaling/unmarshaling layer
by Martin Roth 07 Jul '16

07 Jul '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15570 -gerrit commit 2f2520f5d9f7667f59f116bf32deb645bb803223 Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Sun Jun 19 12:13:18 2016 -0700 tpm2: add marshaling/unmarshaling layer TPM commands need to be serialized (marshaled) to be sent to the device, and the responses need to be de-serialized (unmarshaled) to be properly interpreted by upper layers. This layer does not exist in TPM1.2 coreboot implementation, all TPM commands used there were hardcoded as binary arrays. Availability of the marshaling/unmarshaling layer makes it much easier to add new TPM commands to the code. Command and response structures used in these functions are defined in Parts 2 and 3 of the TCG issued document Trusted Platform Module Library Family "2.0" Level 00 Revision 01.16 October 30, 2014 BRANCH=none BUG=chrome-os-partner:50645 TEST=with the rest of the patches applied it is possible to successfully initialize firmware and kernel TPM spaces. Change-Id: I80b3f971e347bb30ea08f820ec3dd27e1656c060 Signed-off-by: Martin Roth <martinroth(a)chromium.org> Original-Commit-Id: 0782d9d452efb732e85d1503fccfcb4bf9f69a68 Original-Change-Id: I202276ef9a43c28b5f304f901ac5b91048878b76 Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/353915 Original-Reviewed-by: Bill Richardson <wfrichar(a)chromium.org> Original-Reviewed-by: Darren Krahn <dkrahn(a)chromium.org> --- src/lib/Makefile.inc | 1 + src/lib/tpm2_marshaling.c | 516 ++++++++++++++++++++++++++++++++++++++++++++++ src/lib/tpm2_marshaling.h | 49 +++++ 3 files changed, 566 insertions(+) diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index bc38f67..2272b82 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -55,6 +55,7 @@ ifeq ($(MOCK_TPM),1) libverstage-y += mocked_tlcl.c else libverstage-$(CONFIG_TPM) += tlcl.c +libverstage-$(CONFIG_TPM2) += tpm2_marshaling.c libverstage-$(CONFIG_TPM2) += tpm2_tlcl.c endif diff --git a/src/lib/tpm2_marshaling.c b/src/lib/tpm2_marshaling.c new file mode 100644 index 0000000..6eba826 --- /dev/null +++ b/src/lib/tpm2_marshaling.c @@ -0,0 +1,516 @@ +/* + * Copyright 2016 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include <commonlib/endian.h> +#include <console/console.h> +#include <stdlib.h> +#include <string.h> + +#include "tpm2_marshaling.h" + +static uint16_t tpm_tag; /* Depends on the command type. */ + +/* + * Each unmarshaling function receives a pointer to the buffer pointer and a + * pointer to the size of data still in the buffer. The function extracts data + * from the buffer and adjusts both buffer pointer and remaining data size. + * + * Should there be not enough data in the buffer to unmarshal the required + * object, the remaining data size is set to -1 to indicate the error. The + * remaining data size is expected to be set to zero once the last data item + * has been extracted from the buffer. + */ +static uint16_t unmarshal_u16(void **buffer, int *buffer_space) +{ + uint16_t value; + + if (*buffer_space < sizeof(value)) { + *buffer_space = -1; /* Indicate a failure. */ + return 0; + } + + value = read_be16(*buffer); + *buffer = (void *) ((uintptr_t) (*buffer) + sizeof(value)); + *buffer_space -= sizeof(value); + + return value; +} + +static uint16_t unmarshal_u32(void **buffer, int *buffer_space) +{ + uint32_t value; + + if (*buffer_space < sizeof(value)) { + *buffer_space = -1; /* Indicate a failure. */ + return 0; + } + + value = read_be32(*buffer); + *buffer = (void *) ((uintptr_t) (*buffer) + sizeof(value)); + *buffer_space -= sizeof(value); + + return value; +} + +static uint8_t unmarshal_u8(void **buffer, int *buffer_space) +{ + uint8_t value; + + if (*buffer_space < sizeof(value)) { + *buffer_space = -1; /* Indicate a failure. */ + return 0; + } + + value = ((uint8_t *)(*buffer))[0]; + *buffer = (void *) ((uintptr_t) (*buffer) + sizeof(value)); + *buffer_space -= sizeof(value); + + return value; +} + +#define unmarshal_TPM_CAP(a, b) unmarshal_u32(a, b) +#define unmarshal_TPM_CC(a, b) unmarshal_u32(a, b) +#define unmarshal_TPM_PT(a, b) unmarshal_u32(a, b) +#define unmarshal_TPM_HANDLE(a, b) unmarshal_u32(a, b) + +/* + * Each marshaling function receives a pointer to the buffer to marshal into, + * a pointer to the data item to be marshaled, and a pointer to the remaining + * room in the buffer. + */ + + /* + * Marshaling an arbitrary blob requires its size in addition to common + * parameter set. + */ +static void marshal_blob(void **buffer, void *blob, + size_t blob_size, int *buffer_space) +{ + if (*buffer_space < blob_size) { + *buffer_space = -1; + return; + } + + memcpy(*buffer, blob, blob_size); + buffer_space -= blob_size; + *buffer = (void *)((uintptr_t)(*buffer) + blob_size); +} + +static void marshal_u8(void **buffer, uint8_t value, int *buffer_space) +{ + uint8_t *bp = *buffer; + + if (*buffer_space < sizeof(value)) { + *buffer_space = -1; + return; + } + + *bp++ = value; + *buffer = bp; + *buffer_space -= sizeof(value); +} + +static void marshal_u16(void **buffer, uint16_t value, int *buffer_space) +{ + if (*buffer_space < sizeof(value)) { + *buffer_space = -1; + return; + } + write_be16(*buffer, value); + *buffer = (void *)((uintptr_t)(*buffer) + sizeof(value)); + *buffer_space -= sizeof(value); +} + +static void marshal_u32(void **buffer, uint32_t value, int *buffer_space) +{ + if (*buffer_space < sizeof(value)) { + *buffer_space = -1; + return; + } + + write_be32(*buffer, value); + *buffer = (void *)((uintptr_t)(*buffer) + sizeof(value)); + *buffer_space -= sizeof(value); +} + +#define marshal_TPM_HANDLE(a, b, c) marshal_u32(a, b, c) +#define marshal_TPMI_RH_NV_AUTH(a, b, c) marshal_TPM_HANDLE(a, b, c) +#define marshal_TPMI_RH_NV_INDEX(a, b, c) marshal_TPM_HANDLE(a, b, c) +#define marshal_TPMI_SH_AUTH_SESSION(a, b, c) marshal_TPM_HANDLE(a, b, c) +#define marshal_TPMI_ALG_HASH(a, b, c) marshal_u16(a, b, c) + +static void marshal_startup(void **buffer, + struct tpm2_startup *cmd_body, + int *buffer_space) +{ + marshal_u16(buffer, cmd_body->startup_type, buffer_space); +} + +static void marshal_get_capability(void **buffer, + struct tpm2_get_capability *cmd_body, + int *buffer_space) +{ + marshal_u32(buffer, cmd_body->capability, buffer_space); + marshal_u32(buffer, cmd_body->property, buffer_space); + marshal_u32(buffer, cmd_body->propertyCount, buffer_space); +} + +static void marshal_TPM2B(void **buffer, + TPM2B *data, + int *buffer_space) +{ + size_t total_size = data->size + sizeof(data->size); + + if (total_size > *buffer_space) { + *buffer_space = -1; + return; + } + marshal_u16(buffer, data->size, buffer_space); + memcpy(*buffer, data->buffer, data->size); + *buffer = ((uint8_t *)(*buffer)) + data->size; + *buffer_space -= data->size; +} + +static void marshal_TPMA_NV(void **buffer, + TPMA_NV *nv, + int *buffer_space) +{ + marshal_u32(buffer, *((uint32_t *)nv), buffer_space); +} + +static void marshal_TPMS_NV_PUBLIC(void **buffer, + TPMS_NV_PUBLIC *nvpub, + int *buffer_space) +{ + marshal_TPM_HANDLE(buffer, nvpub->nvIndex, buffer_space); + marshal_TPMI_ALG_HASH(buffer, nvpub->nameAlg, buffer_space); + marshal_TPMA_NV(buffer, &nvpub->attributes, buffer_space); + marshal_TPM2B(buffer, &nvpub->authPolicy.b, buffer_space); + marshal_u16(buffer, nvpub->dataSize, buffer_space); +} + +static void marshal_session_header(void **buffer, + struct tpm2_session_header *session_header, + int *buffer_space) +{ + int base_size; + void *size_location = *buffer; + + /* Skip room for the session header size. */ + *buffer_space -= sizeof(uint32_t); + *buffer = (void *)(((uintptr_t) *buffer) + sizeof(uint32_t)); + + base_size = *buffer_space; + + marshal_u32(buffer, session_header->session_handle, buffer_space); + marshal_u16(buffer, session_header->nonce_size, buffer_space); + marshal_blob(buffer, session_header->nonce, + session_header->nonce_size, buffer_space); + marshal_u8(buffer, session_header->session_attrs, buffer_space); + marshal_u16(buffer, session_header->auth_size, buffer_space); + marshal_blob(buffer, session_header->auth, + session_header->auth_size, buffer_space); + + if (*buffer_space < 0) + return; /* The structure did not fit. */ + + /* Paste in the session size. */ + marshal_u32(&size_location, base_size - *buffer_space, &base_size); +} + +static void marshal_nv_define_space(void **buffer, + struct tpm2_nv_define_space_cmd *nvd_in, + int *buffer_space) +{ + void *size_location; + int base_size; + struct tpm2_session_header session_header; + + marshal_TPM_HANDLE(buffer, TPM_RH_PLATFORM, buffer_space); + memset(&session_header, 0, sizeof(session_header)); + session_header.session_handle = TPM_RS_PW; + marshal_session_header(buffer, &session_header, buffer_space); + tpm_tag = TPM_ST_SESSIONS; + + marshal_TPM2B(buffer, &nvd_in->auth.b, buffer_space); + + /* This is where the TPMS_NV_PUBLIC size will be stored. */ + size_location = *buffer; + + /* Allocate room for the size. */ + *buffer = ((uint8_t *)(*buffer)) + sizeof(uint16_t); + *buffer_space -= sizeof(uint16_t); + base_size = *buffer_space; + + marshal_TPMS_NV_PUBLIC(buffer, &nvd_in->publicInfo, buffer_space); + base_size = base_size - *buffer_space; + marshal_u16(&size_location, (uint16_t)base_size, &base_size); +} + +static void marshal_nv_write(void **buffer, + struct tpm2_nv_write_cmd *command_body, + int *buffer_space) +{ + struct tpm2_session_header session_header; + + marshal_TPM_HANDLE(buffer, TPM_RH_PLATFORM, buffer_space); + marshal_TPM_HANDLE(buffer, command_body->nvIndex, buffer_space); + memset(&session_header, 0, sizeof(session_header)); + session_header.session_handle = TPM_RS_PW; + marshal_session_header(buffer, &session_header, buffer_space); + tpm_tag = TPM_ST_SESSIONS; + + marshal_TPM2B(buffer, &command_body->data.b, buffer_space); + marshal_u16(buffer, command_body->offset, buffer_space); +} + +static void marshal_nv_read(void **buffer, + struct tpm2_nv_read_cmd *command_body, + int *buffer_space) +{ + struct tpm2_session_header session_header; + + marshal_TPM_HANDLE(buffer, TPM_RH_PLATFORM, buffer_space); + marshal_TPM_HANDLE(buffer, command_body->nvIndex, buffer_space); + memset(&session_header, 0, sizeof(session_header)); + session_header.session_handle = TPM_RS_PW; + marshal_session_header(buffer, &session_header, buffer_space); + tpm_tag = TPM_ST_SESSIONS; + marshal_u16(buffer, command_body->size, buffer_space); + marshal_u16(buffer, command_body->offset, buffer_space); +} + +static void marshal_selftest(void **buffer, + struct tpm2_self_test *command_body, + int *buffer_space) +{ + marshal_u8(buffer, command_body->yes_no, buffer_space); +} + +int tpm_marshal_command(TPM_CC command, void *tpm_command_body, + void *buffer, int buffer_size) +{ + void *cmd_body = (uint8_t *)buffer + sizeof(struct tpm_header); + int max_body_size = buffer_size - sizeof(struct tpm_header); + int body_size = max_body_size; + + /* Will be modified when marshaling some commands. */ + tpm_tag = TPM_ST_NO_SESSIONS; + + switch (command) { + case TPM2_Startup: + marshal_startup(&cmd_body, tpm_command_body, &body_size); + break; + + case TPM2_GetCapability: + marshal_get_capability(&cmd_body, tpm_command_body, + &body_size); + break; + + case TPM2_NV_Read: + marshal_nv_read(&cmd_body, tpm_command_body, &body_size); + break; + + case TPM2_NV_DefineSpace: + marshal_nv_define_space(&cmd_body, + tpm_command_body, &body_size); + break; + + case TPM2_NV_Write: + marshal_nv_write(&cmd_body, tpm_command_body, &body_size); + break; + + case TPM2_SelfTest: + marshal_selftest(&cmd_body, tpm_command_body, &body_size); + break; + + default: + body_size = -1; + printk(BIOS_INFO, "%s:%d:Request to marshal unsupported command %#x\n", + __FILE__, __LINE__, command); + } + + if (body_size > 0) { + + /* See how much room was taken by marshaling. */ + body_size = max_body_size - body_size; + + body_size += sizeof(struct tpm_header); + + marshal_u16(&buffer, tpm_tag, &max_body_size); + marshal_u32(&buffer, body_size, &max_body_size); + marshal_u32(&buffer, command, &max_body_size); + } + + return body_size; +} + +static void unmarshal_get_capability(void **buffer, int *size, + struct get_cap_response *gcr) +{ + int i; + + gcr->more_data = unmarshal_u8(buffer, size); + + gcr->cd.capability = unmarshal_TPM_CAP(buffer, size); + if (*size < 0) + return; + + switch (gcr->cd.capability) { + case TPM_CAP_TPM_PROPERTIES: + gcr->cd.data.tpmProperties.count = + unmarshal_u32(buffer, size); + if (*size < 0) + return; + if (gcr->cd.data.tpmProperties.count > ARRAY_SIZE + (gcr->cd.data.tpmProperties.tpmProperty)) { + printk(BIOS_INFO, "%s:%s:%d - %d - too many properties\n", + __FILE__, __func__, __LINE__, + gcr->cd.data.tpmProperties.count); + *size = -1; + return; + } + for (i = 0; i < gcr->cd.data.tpmProperties.count; i++) { + TPMS_TAGGED_PROPERTY *pp; + + pp = gcr->cd.data.tpmProperties.tpmProperty + i; + pp->property = unmarshal_TPM_PT(buffer, size); + pp->value = unmarshal_u32(buffer, size); + } + break; + default: + printk(BIOS_ERR, + "%s:%d - unable to unmarshal capability response", + __func__, __LINE__); + printk(BIOS_ERR, " for %d\n", gcr->cd.capability); + *size = -1; + break; + } +} + +static void unmarshal_TPM2B_MAX_NV_BUFFER(void **buffer, + int *size, + TPM2B_MAX_NV_BUFFER *nv_buffer) +{ + nv_buffer->t.size = unmarshal_u16(buffer, size); + if (nv_buffer->t.size > *size) { + printk(BIOS_ERR, "%s:%d - " + "size mismatch: expected %d, remaining %d\n", + __func__, __LINE__, nv_buffer->t.size, *size); + return; + } + + nv_buffer->t.buffer = *buffer; + + *buffer = ((uint8_t *)(*buffer)) + nv_buffer->t.size; + *size -= nv_buffer->t.size; +} + +static void unmarshal_nv_read(void **buffer, int *size, + struct nv_read_response *nvr) +{ + /* Total size of the parameter field. */ + nvr->params_size = unmarshal_u32(buffer, size); + unmarshal_TPM2B_MAX_NV_BUFFER(buffer, size, &nvr->buffer); + + if (nvr->params_size != + (nvr->buffer.t.size + sizeof(nvr->buffer.t.size))) { + printk(BIOS_ERR, + "%s:%d - parameter/buffer %d/%d size mismatch", + __func__, __LINE__, nvr->params_size, + nvr->buffer.t.size); + return; + } + + if (*size < 0) + return; + /* + * Let's ignore the authorisation section. It should be 5 bytes total, + * just confirm that this is the case and report any discrepancy. + */ + if (*size != 5) + printk(BIOS_ERR, + "%s:%d - unexpected authorisation seciton size %d\n", + __func__, __LINE__, *size); + + *buffer = ((uint8_t *)(*buffer)) + *size; + *size = 0; +} + +struct tpm2_response *tpm_unmarshal_response(TPM_CC command, + void *response_body, + int cr_size) +{ + static struct tpm2_response tpm2_resp; + + if (cr_size < sizeof(struct tpm_header)) + return NULL; + + tpm2_resp.hdr.tpm_tag = unmarshal_u16(&response_body, &cr_size); + tpm2_resp.hdr.tpm_size = unmarshal_u32(&response_body, &cr_size); + tpm2_resp.hdr.tpm_code = unmarshal_TPM_CC(&response_body, &cr_size); + + if (!cr_size) { + if (tpm2_resp.hdr.tpm_size != sizeof(tpm2_resp.hdr)) + printk(BIOS_ERR, + "%s: size mismatch in response to command %#x\n", + __func__, command); + return &tpm2_resp; + } + + switch (command) { + case TPM2_Startup: + break; + + case TPM2_GetCapability: + unmarshal_get_capability(&response_body, &cr_size, + &tpm2_resp.gc); + break; + + case TPM2_NV_Read: + unmarshal_nv_read(&response_body, &cr_size, + &tpm2_resp.nvr); + break; + + case TPM2_NV_DefineSpace: + case TPM2_NV_Write: + /* Session data included in response can be safely ignored. */ + cr_size = 0; + break; + + default: + { + int i; + + printk(BIOS_INFO, "%s:%d:" + "Request to unmarshal unexpected command %#x," + " code %#x", + __func__, __LINE__, command, + tpm2_resp.hdr.tpm_code); + + for (i = 0; i < cr_size; i++) { + if (!(i % 16)) + printk(BIOS_INFO, "\n"); + printk(BIOS_INFO, "%2.2x ", + ((uint8_t *)response_body)[i]); + } + } + printk(BIOS_INFO, "\n"); + return NULL; + } + + if (cr_size) { + printk(BIOS_INFO, + "%s:%d got %d bytes back in response to %#x," + " failed to parse (%d)\n", + __func__, __LINE__, tpm2_resp.hdr.tpm_size, + command, cr_size); + return NULL; + } + + /* The entire message have been parsed. */ + return &tpm2_resp; +} diff --git a/src/lib/tpm2_marshaling.h b/src/lib/tpm2_marshaling.h new file mode 100644 index 0000000..69a345d --- /dev/null +++ b/src/lib/tpm2_marshaling.h @@ -0,0 +1,49 @@ +/* + * Copyright 2016 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ +#ifndef __SRC_LIB_TPM2_MARSHALING_H +#define __SRC_LIB_TPM2_MARSHALING_H + +#include "tpm2_tlcl_structures.h" + +/* The below functions are used to serialize/deserialize TPM2 commands. */ + +/** + * tpm_marshal_command + * + * Given a structure containing a TPM2 command, serialize the structure for + * sending it to the TPM. + * + * @command: code of the TPM2 command to marshal + * @tpm_command_body: a pointer to the command specific structure + * @buffer: buffer where command is marshaled to + * @buffer_size: size of the buffer + * + * Returns number of bytes placed in the buffer, or -1 on error. + * + */ +int tpm_marshal_command(TPM_CC command, void *tpm_command_body, + void *buffer, int buffer_size); + +/** + * tpm_unmarshal_response + * + * Given a buffer received from the TPM in response to a certain command, + * deserialize the buffer into the expeced response structure. + * + * struct tpm2_response is a union of all possible responses. + * + * @command: code of the TPM2 command for which a response is unmarshaled + * @response_body: buffer containing the serialized response. + * @response_size: number of bytes in the buffer containing response + * + * Returns a pointer to the deserialized response or NULL in case of + * unmarshaling problems. + */ +struct tpm2_response *tpm_unmarshal_response(TPM_CC command, + void *response_body, + int response_size); + +#endif // __SRC_LIB_TPM2_MARSHALING_H

1 0

New patch to review for coreboot: tpm2: implement tlcl layer
by Martin Roth 07 Jul '16

07 Jul '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15569 -gerrit commit 1f0a9855149cb8dcca1c02c4df4b58ee20c2aac3 Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Tue Apr 5 16:01:57 2016 -0700 tpm2: implement tlcl layer This is the first approximation of implementing TPM2 support in coreboot. It is very clearly incomplete, some of the larger missing pieces being: - PCR(s) modification - protection NVRAM spaces from unauthorized deletion/modification. - resume handling - cr50 specific factory initialization The existing TPM1.2 firmware API is being implemented for TPM2. Some functions are not required at all, some do not map fully, but the API is not yet being changed, many functions are just stubs. An addition to the API is the new tlcl_define_space() function. It abstracts TMP internals allowing the caller to specify the privilege level of the space to be defined. Two privilege levels are defined, higher for the RO firmware and lower for RW firmware, they determine who can write into the spaces. BRANCH=none BUG=chrome-os-partner:50645 TEST=with the rest of the patches applied Kevin/Gru devices can initialize and use firmware and kernel spaces Change-Id: Ife3301cf161ce38d61f11e4b60f1b43cab9a4eba Signed-off-by: Martin Roth <martinroth(a)chromium.org> Original-Commit-Id: bcc8e62604c705798ca106e7995a0960b92b3f35 Original-Change-Id: Ib340fa8e7db51c10e5080973c16a19b0ebbb61e6 Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/353914 Original-Commit-Ready: Martin Roth <martinroth(a)chromium.org> Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/include/tpm_lite/tlcl.h | 23 +++ src/lib/Makefile.inc | 3 +- src/lib/tpm2_tlcl.c | 284 +++++++++++++++++++++++++++++++++++ src/lib/tpm2_tlcl_structures.h | 325 +++++++++++++++++++++++++++++++++++++++++ 4 files changed, 634 insertions(+), 1 deletion(-) diff --git a/src/include/tpm_lite/tlcl.h b/src/include/tpm_lite/tlcl.h index 7724592..c777ff9 100644 --- a/src/include/tpm_lite/tlcl.h +++ b/src/include/tpm_lite/tlcl.h @@ -12,6 +12,7 @@ #ifndef TPM_LITE_TLCL_H_ #define TPM_LITE_TLCL_H_ #include <stdint.h> +#include <types.h> #include "tss_constants.h" @@ -56,12 +57,34 @@ uint32_t tlcl_self_test_full(void); */ uint32_t tlcl_continue_self_test(void); +#if IS_ENABLED(CONFIG_TPM) /** * Define a space with permission [perm]. [index] is the index for the space, * [size] the usable data size. The TPM error code is returned. */ uint32_t tlcl_define_space(uint32_t index, uint32_t perm, uint32_t size); +#elif IS_ENABLED(CONFIG_TPM2) + +/* + * This enum allows to communicate firmware privilege levels to the TPM layer, + * which can map them into its own attributes. + */ +enum privilege_level { + high_privilege = 1, + low_privilege +}; + +/* + * Define a TPM space. Privilege level describes who can modify the space + * (high_privilege - the RO code only, low_privilege - ether RO or RW. The + * privilege level needs to be dropped below low_privilege before starting the + * kernel. + */ +uint32_t tlcl_define_space(uint32_t space_index, + enum privilege_level priv_level, size_t space_size); +#endif + /** * Write [length] bytes of [data] to space at [index]. The TPM error code is * returned. diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 1028917..bc38f67 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -54,7 +54,8 @@ verstage-$(CONFIG_COMMON_CBFS_SPI_WRAPPER) += cbfs_spi.c ifeq ($(MOCK_TPM),1) libverstage-y += mocked_tlcl.c else -libverstage-y += tlcl.c +libverstage-$(CONFIG_TPM) += tlcl.c +libverstage-$(CONFIG_TPM2) += tpm2_tlcl.c endif verstage-$(CONFIG_GENERIC_UDELAY) += timer.c diff --git a/src/lib/tpm2_tlcl.c b/src/lib/tpm2_tlcl.c new file mode 100644 index 0000000..c352a2c --- /dev/null +++ b/src/lib/tpm2_tlcl.c @@ -0,0 +1,284 @@ +/* + * Copyright 2016 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include <console/console.h> +#include <endian.h> +#include <lib/tpm2_tlcl_structures.h> +#include <string.h> +#include <tpm.h> +#include <vb2_api.h> + +#include "tpm2_marshaling.h" + +/* + * This file provides interface between firmware and TPM2 device. The TPM1.2 + * API was copied as is and relevant functions modified to comply with the + * TPM2 specification. + */ + +static void *tpm_process_command(TPM_CC command, void *command_body) +{ + size_t out_size, in_size; + /* Command/response buffer. */ + static uint8_t cr_buffer[TPM_BUFFER_SIZE]; + + out_size = tpm_marshal_command(command, command_body, + cr_buffer, sizeof(cr_buffer)); + if (out_size < 0) { + printk(BIOS_ERR, "command %#x, cr size %zd\n", + command, out_size); + return NULL; + } + + in_size = sizeof(cr_buffer); + if (tis_sendrecv(cr_buffer, out_size, + cr_buffer, &in_size)) { + printk(BIOS_ERR, "tpm transaction failed\n"); + return NULL; + } + + return tpm_unmarshal_response(command, cr_buffer, in_size); +} + + +uint32_t tlcl_get_permanent_flags(TPM_PERMANENT_FLAGS *pflags) +{ + printk(BIOS_INFO, "%s:%s:%d\n", __FILE__, __func__, __LINE__); + return TPM_SUCCESS; +} + +uint32_t tlcl_resume(void) +{ + printk(BIOS_INFO, "%s:%s:%d\n", __FILE__, __func__, __LINE__); + return TPM_SUCCESS; +} + +uint32_t tlcl_assert_physical_presence(void) +{ + /* + * Nothing to do on TPM2 for this, use platform hierarchy availability + * instead. + */ + return TPM_SUCCESS; +} + +uint32_t tlcl_extend(int pcr_num, const uint8_t *in_digest, + uint8_t *out_digest) +{ + printk(BIOS_INFO, "%s:%s:%d\n", __FILE__, __func__, __LINE__); + return TPM_SUCCESS; +} + +uint32_t tlcl_finalize_physical_presence(void) +{ + /* Nothing needs to be done with tpm2. */ + printk(BIOS_INFO, "%s:%s:%d\n", __FILE__, __func__, __LINE__); + return TPM_SUCCESS; +} + +uint32_t tlcl_force_clear(void) +{ + printk(BIOS_INFO, "%s:%s:%d\n", __FILE__, __func__, __LINE__); + return TPM_SUCCESS; +} + +uint32_t tlcl_get_flags(uint8_t *disable, uint8_t *deactivated, + uint8_t *nvlocked) +{ + /* + * TPM2 does not map directly into these flags TPM1.2 based firmware + * expects to be able to retrieve. + * + * In any case, if any of these conditions are present, the following + * firmware flow would be interrupted and will have a chance to report + * an error. Let's just hardcode an "All OK" response for now. + */ + + if (disable) + *disable = 0; + + if (nvlocked) + *nvlocked = 1; + + if (deactivated) + *deactivated = 0; + + return TPM_SUCCESS; +} + +uint32_t tlcl_lib_init(void) +{ + /* + * This function is called directly by vboot, uses vboot return + * types. + */ + if (tis_init()) + return VB2_ERROR_UNKNOWN; + if (tis_open()) + return VB2_ERROR_UNKNOWN; + return VB2_SUCCESS; +} + +uint32_t tlcl_physical_presence_cmd_enable(void) +{ + printk(BIOS_INFO, "%s:%s:%d\n", __FILE__, __func__, __LINE__); + return TPM_SUCCESS; +} + +uint32_t tlcl_read(uint32_t index, void *data, uint32_t length) +{ + struct tpm2_nv_read_cmd nv_readc; + struct tpm2_response *response; + + memset(&nv_readc, 0, sizeof(nv_readc)); + + nv_readc.nvIndex = HR_NV_INDEX + index; + nv_readc.size = length; + + response = tpm_process_command(TPM2_NV_Read, &nv_readc); + + /* Need to map tpm error codes into internal values. */ + if (!response) + return TPM_E_READ_FAILURE; + + printk(BIOS_INFO, "%s:%d index %#x return code %x\n", + __FILE__, __LINE__, index, response->hdr.tpm_code); + switch (response->hdr.tpm_code) { + case 0: + break; + + case 0x28b: + return TPM_E_BADINDEX; + + default: + return TPM_E_READ_FAILURE; + } + + if (length > response->nvr.buffer.t.size) + return TPM_E_RESPONSE_TOO_LARGE; + + if (length < response->nvr.buffer.t.size) + return TPM_E_READ_EMPTY; + + memcpy(data, response->nvr.buffer.t.buffer, length); + + return TPM_SUCCESS; +} + +uint32_t tlcl_self_test_full(void) +{ + struct tpm2_self_test st; + struct tpm2_response *response; + + st.yes_no = 1; + + response = tpm_process_command(TPM2_SelfTest, &st); + printk(BIOS_INFO, "%s: response is %x\n", + __func__, response ? response->hdr.tpm_code : -1); + return TPM_SUCCESS; +} + +uint32_t tlcl_set_deactivated(uint8_t flag) +{ + printk(BIOS_INFO, "%s:%s:%d\n", __FILE__, __func__, __LINE__); + return TPM_SUCCESS; +} + +uint32_t tlcl_set_enable(void) +{ + printk(BIOS_INFO, "%s:%s:%d\n", __FILE__, __func__, __LINE__); + return TPM_SUCCESS; +} + +uint32_t tlcl_set_global_lock(void) +{ + /* + * This is where the locking of the RO NVram index is supposed to + * happen. The most likely way to achieve it is to extend PCR used for + * policy when defining this space. + */ + printk(BIOS_INFO, "%s:%s:%d\n", __FILE__, __func__, __LINE__); + return TPM_SUCCESS; +} +uint32_t tlcl_set_nv_locked(void) +{ + printk(BIOS_INFO, "%s:%s:%d\n", __FILE__, __func__, __LINE__); + return TPM_SUCCESS; +} + +uint32_t tlcl_startup(void) +{ + struct tpm2_startup startup; + struct tpm2_response *response; + + startup.startup_type = TPM_SU_CLEAR; + response = tpm_process_command(TPM2_Startup, &startup); + if (response && response->hdr.tpm_code && + (response->hdr.tpm_code != TPM_RC_INITIALIZE)) { + printk(BIOS_INFO, "startup return code is %x\n", + response->hdr.tpm_code); + return TPM_E_IOERROR; + } + return TPM_SUCCESS; +} + +uint32_t tlcl_write(uint32_t index, const void *data, uint32_t length) +{ + struct tpm2_nv_write_cmd nv_writec; + struct tpm2_response *response; + + memset(&nv_writec, 0, sizeof(nv_writec)); + + nv_writec.nvIndex = HR_NV_INDEX + index; + nv_writec.data.t.size = length; + nv_writec.data.t.buffer = data; + + response = tpm_process_command(TPM2_NV_Write, &nv_writec); + + /* Need to map tpm error codes into internal values. */ + if (!response) + return TPM_E_WRITE_FAILURE; + + printk(BIOS_INFO, "%s:%d return code %x\n", __func__, __LINE__, + response->hdr.tpm_code); + + return TPM_SUCCESS; +} + +uint32_t tlcl_define_space(uint32_t space_index, + enum privilege_level priv_level, size_t space_size) +{ + struct tpm2_nv_define_space_cmd nvds_cmd; + struct tpm2_response *response; + + /* Prepare the define space command structure. */ + memset(&nvds_cmd, 0, sizeof(nvds_cmd)); + + nvds_cmd.publicInfo.dataSize = space_size; + nvds_cmd.publicInfo.nvIndex = HR_NV_INDEX + space_index; + nvds_cmd.publicInfo.nameAlg = TPM_ALG_SHA256; + + /* Attributes common for all privilege levels. */ + nvds_cmd.publicInfo.attributes.TPMA_NV_PPWRITE = 1; + nvds_cmd.publicInfo.attributes.TPMA_NV_AUTHREAD = 1; + nvds_cmd.publicInfo.attributes.TPMA_NV_PPREAD = 1; + nvds_cmd.publicInfo.attributes.TPMA_NV_PLATFORMCREATE = 1; + + if (priv_level == high_privilege) { + nvds_cmd.publicInfo.attributes.TPMA_NV_WRITE_STCLEAR = 1; + nvds_cmd.publicInfo.attributes.TPMA_NV_POLICY_DELETE = 1; + } + + response = tpm_process_command(TPM2_NV_DefineSpace, &nvds_cmd); + printk(BIOS_INFO, "%s: response is %x\n", + __func__, response ? response->hdr.tpm_code : -1); + + if (!response) + return TPM_E_NO_DEVICE; + + return response->hdr.tpm_code ? TPM_E_INTERNAL_INCONSISTENCY : + TPM_SUCCESS; +} diff --git a/src/lib/tpm2_tlcl_structures.h b/src/lib/tpm2_tlcl_structures.h new file mode 100644 index 0000000..fad9c0d --- /dev/null +++ b/src/lib/tpm2_tlcl_structures.h @@ -0,0 +1,325 @@ +/* + * Copyright 2016 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#ifndef __SRC_LIB_TPM2_TLCL_STRUCTURES_H +#define __SRC_LIB_TPM2_TLCL_STRUCTURES_H + +/* + * This file includes a subset of definitions of TPM protocol version 2.x + * constants and structures needed for functions used in coreboot. + */ +#include <stdint.h> +#include <tpm_lite/tlcl.h> +#include <types.h> + +/* This should be plenty for what firmware needs. */ +#define TPM_BUFFER_SIZE 256 + +/* Basic TPM2 types. */ +typedef uint16_t TPM_SU; +typedef uint16_t TPM_ALG_ID; +typedef uint32_t TPM_CC; +typedef uint32_t TPM_HANDLE; +typedef uint32_t TPM_RC; +typedef uint8_t TPMI_YES_NO; +typedef TPM_HANDLE TPMI_RH_NV_INDEX; +typedef TPM_HANDLE TPMI_RH_PROVISION; +typedef TPM_HANDLE TPMI_SH_AUTH_SESSION; +typedef TPM_HANDLE TPM_RH; +typedef TPM_ALG_ID TPMI_ALG_HASH; + +/* Some hardcoded algorithm values. */ +#define TPM_ALG_HMAC ((TPM_ALG_ID)0x0005) +#define TPM_ALG_NULL ((TPM_ALG_ID)0x0010) +#define TPM_ALG_SHA1 ((TPM_ALG_ID)0x0004) +#define TPM_ALG_SHA256 ((TPM_ALG_ID)0x000b) + +/* Some hardcoded hierarchies. */ +#define TPM_RH_NULL 0x40000007 +#define TPM_RS_PW 0x40000009 +#define TPM_RH_PLATFORM 0x4000000C + +typedef struct { + uint16_t size; + uint8_t *buffer; +} TPM2B; + +typedef union { + uint8_t body[512]; +} TPMU_HA; + +typedef struct { + TPMI_ALG_HASH hashAlg; + TPMU_HA digest; +} TPMT_HA; + +typedef union { + TPMT_HA digest; + TPM_HANDLE handle; +} TPMU_NAME; + +typedef union { + struct { + uint16_t size; + uint8_t name[sizeof(TPMU_NAME)]; + } t; + TPM2B b; +} TPM2B_NAME; + +/* Relevant TPM Command's structures. */ +/* Common command/response header. */ +struct tpm_header { + uint16_t tpm_tag; + uint32_t tpm_size; + TPM_CC tpm_code; +} __attribute__((packed)); + +/* TPM command codes. */ +#define TPM2_NV_DefineSpace ((TPM_CC)0x0000012A) +#define TPM2_NV_Write ((TPM_CC)0x00000137) +#define TPM2_SelfTest ((TPM_CC)0x00000143) +#define TPM2_Startup ((TPM_CC)0x00000144) +#define TPM2_NV_Read ((TPM_CC)0x0000014E) +#define TPM2_GetCapability ((TPM_CC)0x0000017A) + +/* Startup values. */ +#define TPM_SU_CLEAR 0 +#define TPM_SU_STATE 1 + +#define TPM_HT_NV_INDEX 0x01 +#define TPM_HT_HMAC_SESSION 0x02 +#define TPM_HT_POLICY_SESSION 0x03 + +#define HR_SHIFT 24 +#define HR_PCR (TPM_HT_PCR << HR_SHIFT) +#define HR_HMAC_SESSION (TPM_HT_HMAC_SESSION << HR_SHIFT) +#define HR_POLICY_SESSION (TPM_HT_POLICY_SESSION << HR_SHIFT) +#define HR_TRANSIENT (TPM_HT_TRANSIENT << HR_SHIFT) +#define HR_PERSISTENT (TPM_HT_PERSISTENT << HR_SHIFT) +#define HR_NV_INDEX (TPM_HT_NV_INDEX << HR_SHIFT) +#define HR_PERMANENT (TPM_HT_PERMANENT << HR_SHIFT) +#define PCR_FIRST (HR_PCR + 0) +#define PCR_LAST (PCR_FIRST + IMPLEMENTATION_PCR-1) +#define HMAC_SESSION_FIRST (HR_HMAC_SESSION + 0) +#define HMAC_SESSION_LAST (HMAC_SESSION_FIRST+MAX_ACTIVE_SESSIONS-1) +#define LOADED_SESSION_FIRST HMAC_SESSION_FIRST +#define LOADED_SESSION_LAST HMAC_SESSION_LAST +#define POLICY_SESSION_FIRST (HR_POLICY_SESSION + 0) +#define POLICY_SESSION_LAST (POLICY_SESSION_FIRST + MAX_ACTIVE_SESSIONS-1) +#define TRANSIENT_FIRST (HR_TRANSIENT + 0) +#define ACTIVE_SESSION_FIRST POLICY_SESSION_FIRST +#define ACTIVE_SESSION_LAST POLICY_SESSION_LAST +#define TRANSIENT_LAST (TRANSIENT_FIRST+MAX_LOADED_OBJECTS-1) +#define PERSISTENT_FIRST (HR_PERSISTENT + 0) +#define PERSISTENT_LAST (PERSISTENT_FIRST + 0x00FFFFFF) +#define PLATFORM_PERSISTENT (PERSISTENT_FIRST + 0x00800000) +#define NV_INDEX_FIRST (HR_NV_INDEX + 0) +#define NV_INDEX_LAST (NV_INDEX_FIRST + 0x00FFFFFF) +#define PERMANENT_FIRST TPM_RH_FIRST +#define PERMANENT_LAST TPM_RH_LAST + +/* Tpm2 command tags. */ +#define TPM_ST_NO_SESSIONS 0x8001 +#define TPM_ST_SESSIONS 0x8002 + +#define RC_VER1 0x100 +#define TPM_RC_INITIALIZE ((TPM_RC)(RC_VER1 + 0x000)) + +/* TPM command structures. */ + +struct tpm2_startup { + TPM_SU startup_type; +}; + +/* Various TPM capability types to use when querying the device. */ +typedef uint32_t TPM_CAP; +#define TPM_CAP_TPM_PROPERTIES ((TPM_CAP)0x00000006) + +typedef TPM_HANDLE TPMI_RH_NV_AUTH; +typedef TPM_HANDLE TPMI_RH_NV_INDEX; + +/* TPM Property capability constants. */ +typedef uint32_t TPM_PT; +#define PT_GROUP 0x00000100 +#define PT_VAR (PT_GROUP * 2) +#define TPM_PT_PERMANENT ((TPM_PT)(PT_VAR + 0)) + +/* Structures of payloads of various TPM2 commands. */ +struct tpm2_get_capability { + TPM_CAP capability; + uint32_t property; + uint32_t propertyCount; +}; + +/* get_capability response when PT_PERMANENT is requested. */ +typedef struct { + uint32_t ownerAuthSet : 1; + uint32_t endorsementAuthSet : 1; + uint32_t lockoutAuthSet : 1; + uint32_t reserved3_7 : 5; + uint32_t disableClear : 1; + uint32_t inLockout : 1; + uint32_t tpmGeneratedEPS : 1; + uint32_t reserved11_31 : 21; +} TPMA_PERMANENT; + +typedef struct { + uint32_t TPMA_NV_PPWRITE : 1; + uint32_t TPMA_NV_OWNERWRITE : 1; + uint32_t TPMA_NV_AUTHWRITE : 1; + uint32_t TPMA_NV_POLICYWRITE : 1; + uint32_t TPMA_NV_COUNTER : 1; + uint32_t TPMA_NV_BITS : 1; + uint32_t TPMA_NV_EXTEND : 1; + uint32_t reserved7_9 : 3; + uint32_t TPMA_NV_POLICY_DELETE : 1; + uint32_t TPMA_NV_WRITELOCKED : 1; + uint32_t TPMA_NV_WRITEALL : 1; + uint32_t TPMA_NV_WRITEDEFINE : 1; + uint32_t TPMA_NV_WRITE_STCLEAR : 1; + uint32_t TPMA_NV_GLOBALLOCK : 1; + uint32_t TPMA_NV_PPREAD : 1; + uint32_t TPMA_NV_OWNERREAD : 1; + uint32_t TPMA_NV_AUTHREAD : 1; + uint32_t TPMA_NV_POLICYREAD : 1; + uint32_t reserved20_24 : 5; + uint32_t TPMA_NV_NO_DA : 1; + uint32_t TPMA_NV_ORDERLY : 1; + uint32_t TPMA_NV_CLEAR_STCLEAR : 1; + uint32_t TPMA_NV_READLOCKED : 1; + uint32_t TPMA_NV_WRITTEN : 1; + uint32_t TPMA_NV_PLATFORMCREATE : 1; + uint32_t TPMA_NV_READ_STCLEAR : 1; +} TPMA_NV; + +typedef union { + struct { + uint16_t size; + uint8_t buffer[sizeof(TPMU_HA)]; + } t; + TPM2B b; +} TPM2B_DIGEST; + +typedef TPM2B_DIGEST TPM2B_AUTH; +typedef TPM2B_DIGEST TPM2B_NONCE; + +typedef struct { + TPM_PT property; + uint32_t value; +} TPMS_TAGGED_PROPERTY; + +#define MAX_CAP_DATA (TPM_BUFFER_SIZE - sizeof(struct tpm_header) - \ + sizeof(TPMI_YES_NO) - sizeof(TPM_CAP) - sizeof(uint32_t)) +#define MAX_TPM_PROPERTIES (MAX_CAP_DATA/sizeof(TPMS_TAGGED_PROPERTY)) + +/* Somewhat arbitrary, leave enough room for command wrappers. */ +#define MAX_NV_BUFFER_SIZE (TPM_BUFFER_SIZE - sizeof(struct tpm_header) - 50) + +typedef struct { + uint32_t count; + TPMS_TAGGED_PROPERTY tpmProperty[MAX_TPM_PROPERTIES]; +} TPML_TAGGED_TPM_PROPERTY; + +typedef union { + TPML_TAGGED_TPM_PROPERTY tpmProperties; +} TPMU_CAPABILITIES; + +typedef struct { + TPM_CAP capability; + TPMU_CAPABILITIES data; +} TPMS_CAPABILITY_DATA; + +struct get_cap_response { + TPMI_YES_NO more_data; + TPMS_CAPABILITY_DATA cd; +}; + +typedef struct { + TPMI_RH_NV_INDEX nvIndex; + TPMI_ALG_HASH nameAlg; + TPMA_NV attributes; + TPM2B_DIGEST authPolicy; + uint16_t dataSize; +} TPMS_NV_PUBLIC; + +typedef union { + struct { + uint16_t size; + TPMS_NV_PUBLIC nvPublic; + } t; + TPM2B b; +} TPM2B_NV_PUBLIC; + +typedef union { + struct { + uint16_t size; + const uint8_t *buffer; + } t; + TPM2B b; +} TPM2B_MAX_NV_BUFFER; + +struct nv_read_response { + uint32_t params_size; + TPM2B_MAX_NV_BUFFER buffer; +}; + +struct tpm2_session_attrs { + uint8_t continueSession : 1; + uint8_t auditExclusive : 1; + uint8_t auditReset : 1; + uint8_t reserved3_4 : 2; + uint8_t decrypt : 1; + uint8_t encrypt : 1; + uint8_t audit : 1; +}; + +/* + * TPM session header for commands requiring session information. Also + * included in the responses to those commands. + */ +struct tpm2_session_header { + uint32_t session_handle; + uint16_t nonce_size; + uint8_t *nonce; + union { + struct tpm2_session_attrs session_attr_bits; + uint8_t session_attrs; + } __attribute__((packed)); + uint16_t auth_size; + uint8_t *auth; +}; + +struct tpm2_response { + struct tpm_header hdr; + union { + struct get_cap_response gc; + struct nv_read_response nvr; + struct tpm2_session_header def_space; + }; +}; + +struct tpm2_nv_define_space_cmd { + TPM2B_AUTH auth; + TPMS_NV_PUBLIC publicInfo; +}; + +struct tpm2_nv_write_cmd { + TPMI_RH_NV_INDEX nvIndex; + TPM2B_MAX_NV_BUFFER data; + uint16_t offset; +}; + +struct tpm2_self_test { + TPMI_YES_NO yes_no; +}; + +struct tpm2_nv_read_cmd { + TPMI_RH_NV_INDEX nvIndex; + uint16_t size; + uint16_t offset; +}; + +#endif // __SRC_LIB_TPM2_TLCL_STRUCTURES_H

1 0

New patch to review for coreboot: tpm: use proper locality zero SPI bus addresses
by Martin Roth 07 Jul '16

07 Jul '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15568 -gerrit commit 80935eb04354c9fed330c79c8ed27444607a7276 Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Thu Jun 23 12:03:18 2016 -0700 tpm: use proper locality zero SPI bus addresses The "PC Client Protection Profile for TPM 2.0" document defines SPI bus addresses for different localities. That definition is not honored in the cr50 implementation, this patch fixes it: locality zero register file is based off 0xd40000. BRANCH=none BUG=chrome-os-partner:54720 TEST=with the fixed cr50 image and the rest of TPM2 initialization patches applied factory initialization sequence on Gru succeeds. Change-Id: I49b7ed55f0360448b9a6602ebd31a3a531608da3 Signed-off-by: Martin Roth <martinroth(a)chromium.org> Original-Commit-Id: 43344fff5d58ec235e50030413fc38c98dd0a9a1 Original-Change-Id: I2de6fa6c05d3eca989d6785228d5adde1f2a7ab7 Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/355620 Original-Reviewed-by: Bill Richardson <wfrichar(a)chromium.org> --- src/drivers/spi/tpm/tpm.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/src/drivers/spi/tpm/tpm.c b/src/drivers/spi/tpm/tpm.c index a46042d..b02fc5f 100644 --- a/src/drivers/spi/tpm/tpm.c +++ b/src/drivers/spi/tpm/tpm.c @@ -24,12 +24,14 @@ #include "tpm.h" +#define TPM_LOCALITY_0_SPI_BASE 0x00d40000 + /* Assorted TPM2 registers for interface type FIFO. */ -#define TPM_ACCESS_REG 0 -#define TPM_STS_REG 0x18 -#define TPM_DATA_FIFO_REG 0x24 -#define TPM_DID_VID_REG 0xf00 -#define TPM_RID_REG 0xf04 +#define TPM_ACCESS_REG (TPM_LOCALITY_0_SPI_BASE + 0) +#define TPM_STS_REG (TPM_LOCALITY_0_SPI_BASE + 0x18) +#define TPM_DATA_FIFO_REG (TPM_LOCALITY_0_SPI_BASE + 0x24) +#define TPM_DID_VID_REG (TPM_LOCALITY_0_SPI_BASE + 0xf00) +#define TPM_RID_REG (TPM_LOCALITY_0_SPI_BASE + 0xf04) /* SPI Interface descriptor used by the driver. */ struct tpm_spi_if {

1 0

New patch to review for coreboot: google/chromeec: Update EC command header
by Martin Roth 07 Jul '16

07 Jul '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15567 -gerrit commit ed8a2145068fc8500da6909eb3658d28adb01fc9 Author: Gwendal Grignou <gwendal(a)chromium.org> Date: Mon Jun 20 08:49:25 2016 -0700 google/chromeec: Update EC command header In particular, update host_event the original value for MKBP was not set in ToT. CQ-DEPEND=CL:353634 BUG=b:27849483 BRANCH=none TEST=Compile on Samus. Tested in Cyan branch. Change-Id: I0184e4f0e45c3321742d3138ae0178c159cbdd0a Signed-off-by: Martin Roth <martinroth(a)chromium.org> Original-Commit-Id: cc6750b705300f5b94bf23fe5485d6e7a5f9e327 Original-Change-Id: I60df65bfd4053207fa90b1c2a8609eec09f3c475 Original-Signed-off-by: Gwendal Grignou <gwendal(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/354040 --- src/ec/google/chromeec/acpi/ec.asl | 2 +- src/ec/google/chromeec/ec_commands.h | 84 +++++++++++++++++++++++++++++++++++- 2 files changed, 83 insertions(+), 3 deletions(-) diff --git a/src/ec/google/chromeec/acpi/ec.asl b/src/ec/google/chromeec/acpi/ec.asl index 232a5cc..13317f6 100644 --- a/src/ec/google/chromeec/acpi/ec.asl +++ b/src/ec/google/chromeec/acpi/ec.asl @@ -290,7 +290,7 @@ Device (EC0) } // MKBP interrupt. - Method (_Q1A, 0, NotSerialized) + Method (_Q1B, 0, NotSerialized) { Store ("EC: MKBP", Debug) Notify (CREC, 0x80) diff --git a/src/ec/google/chromeec/ec_commands.h b/src/ec/google/chromeec/ec_commands.h index 5c491ca..2e2a695 100644 --- a/src/ec/google/chromeec/ec_commands.h +++ b/src/ec/google/chromeec/ec_commands.h @@ -459,8 +459,11 @@ enum host_event_code { /* Keyboard fastboot combo has been pressed */ EC_HOST_EVENT_KEYBOARD_FASTBOOT = 25, + /* EC RTC event occurred */ + EC_HOST_EVENT_RTC = 26, + /* Emulate MKBP event */ - EC_HOST_EVENT_MKBP = 26, + EC_HOST_EVENT_MKBP = 27, /* * The high bit of the event mask is not used as a host event code. If @@ -1201,6 +1204,7 @@ struct ec_params_pwm_set_fan_target_rpm_v1 { } __packed; /* Get keyboard backlight */ +/* OBSOLETE - Use EC_CMD_PWM_SET_DUTY */ #define EC_CMD_PWM_GET_KEYBOARD_BACKLIGHT 0x22 struct ec_response_pwm_get_keyboard_backlight { @@ -1209,6 +1213,7 @@ struct ec_response_pwm_get_keyboard_backlight { } __packed; /* Set keyboard backlight */ +/* OBSOLETE - Use EC_CMD_PWM_SET_DUTY */ #define EC_CMD_PWM_SET_KEYBOARD_BACKLIGHT 0x23 struct ec_params_pwm_set_keyboard_backlight { @@ -1229,6 +1234,37 @@ struct ec_params_pwm_set_fan_duty_v1 { uint8_t fan_idx; } __packed; +#define EC_CMD_PWM_SET_DUTY 0x25 +/* 16 bit duty cycle, 0xffff = 100% */ +#define EC_PWM_MAX_DUTY 0xffff + +enum ec_pwm_type { + /* All types, indexed by board-specific enum pwm_channel */ + EC_PWM_TYPE_GENERIC = 0, + /* Keyboard backlight */ + EC_PWM_TYPE_KB_LIGHT, + /* Display backlight */ + EC_PWM_TYPE_DISPLAY_LIGHT, + EC_PWM_TYPE_COUNT, +}; + +struct ec_params_pwm_set_duty { + uint16_t duty; /* Duty cycle, EC_PWM_MAX_DUTY = 100% */ + uint8_t pwm_type; /* ec_pwm_type */ + uint8_t index; /* Type-specific index, or 0 if unique */ +} __packed; + +#define EC_CMD_PWM_GET_DUTY 0x26 + +struct ec_params_pwm_get_duty { + uint8_t pwm_type; /* ec_pwm_type */ + uint8_t index; /* Type-specific index, or 0 if unique */ +} __packed; + +struct ec_response_pwm_get_duty { + uint16_t duty; /* Duty cycle, EC_PWM_MAX_DUTY = 100% */ +} __packed; + /*****************************************************************************/ /* * Lightbar commands. This looks worse than it is. Since we only use one HOST @@ -1780,6 +1816,7 @@ enum motionsensor_chip { MOTIONSENSE_CHIP_SI1143 = 5, MOTIONSENSE_CHIP_KX022 = 6, MOTIONSENSE_CHIP_L3GD20H = 7, + MOTIONSENSE_CHIP_BMA255 = 8, }; struct ec_response_motion_sensor_data { @@ -2509,6 +2546,13 @@ struct ec_response_get_next_event { union ec_response_get_next_data data; } __packed; +/* Run keyboard factory test scanning */ +#define EC_CMD_KEYBOARD_FACTORY_TEST 0x68 + +struct ec_response_keyboard_factory_test { + uint16_t shorted; /* Keyboard pins are shorted */ +} __packed; + /*****************************************************************************/ /* Temperature sensor commands */ @@ -3182,6 +3226,27 @@ struct ec_params_entering_mode { #define VBOOT_MODE_RECOVERY 2 /*****************************************************************************/ +/* + * I2C passthru protection command: Protects I2C tunnels against access on + * certain addresses (board-specific). + */ +#define EC_CMD_I2C_PASSTHRU_PROTECT 0xb7 + +enum ec_i2c_passthru_protect_subcmd { + EC_CMD_I2C_PASSTHRU_PROTECT_STATUS = 0x0, + EC_CMD_I2C_PASSTHRU_PROTECT_ENABLE = 0x1, +}; + +struct ec_params_i2c_passthru_protect { + uint8_t subcmd; + uint8_t port; /* I2C port number */ +} __packed; + +struct ec_response_i2c_passthru_protect { + uint8_t status; /* Status flags (0: unlocked, 1: locked) */ +} __packed; + +/*****************************************************************************/ /* System commands */ /* @@ -3609,8 +3674,23 @@ struct ec_params_pd_write_log_entry { uint8_t port; /* port#, or 0 for events unrelated to a given port */ } __packed; -#endif /* !__ACPI__ */ +/* Control USB-PD chip */ +#define EC_CMD_PD_CONTROL 0x119 + +enum ec_pd_control_cmd { + PD_SUSPEND = 0, /* Suspend the PD chip (EC: stop talking to PD) */ + PD_RESUME, /* Resume the PD chip (EC: start talking to PD) */ + PD_RESET, /* Force reset the PD chip */ + PD_CONTROL_DISABLE /* Disable further calls to this command */ +}; + +struct ec_params_pd_control { + uint8_t chip; /* chip id (should be 0) */ + uint8_t subcmd; +} __packed; + +#endif /* !__ACPI__ */ /*****************************************************************************/ /*

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coreboot-gerrit July 2016