coreboot-gerrit July 2016

coreboot-gerrit@coreboot.org

1 participants
1820 discussions

Patch merged into coreboot/master: MAINTAINERS: Add myself as tpm support maintainer.
by gerrit＠coreboot.org 07 Jul '16

07 Jul '16

the following patch was just integrated into master: commit 6507e6f056a38040fe6cb9bc455cbb224f02c981 Author: Philipp Deppenwiese <zaolin(a)das-labor.org> Date: Wed Jun 22 19:01:47 2016 +0200 MAINTAINERS: Add myself as tpm support maintainer. The tpm software stack, drivers and trustedboot needs to be maintained. Change-Id: I7b9ff9c4d7504c861de98ef3d8fcda53b20657c4 Signed-off-by: Philipp Deppenwiese <zaolin(a)das-labor.org> Reviewed-on: https://review.coreboot.org/15312 Reviewed-by: Vadim Bendebury <vbendeb(a)chromium.org> Reviewed-by: Alexander Couzens <lynxis(a)fe80.eu> Tested-by: build bot (Jenkins) See https://review.coreboot.org/15312 for details. -gerrit

1 0

Patch set updated for coreboot: tegra124: Build verstage when CHROMEOS is selected
by Martin Roth 07 Jul '16

07 Jul '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15451 -gerrit commit 93f81f1663688605ad3c4086c5e1beafb9bf2517 Author: Paul Kocialkowski <contact(a)paulk.fr> Date: Mon Jun 27 19:08:59 2016 +0200 tegra124: Build verstage when CHROMEOS is selected This includes the proper Kconfig options (based on the chromium os coreboot configuration) for setting up verstage on tegra124 devices. Change-Id: I4a1976ff684a417cae6fa718ef53cad763cee47d Signed-off-by: Paul Kocialkowski <contact(a)paulk.fr> --- src/soc/nvidia/tegra124/Kconfig | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/soc/nvidia/tegra124/Kconfig b/src/soc/nvidia/tegra124/Kconfig index 49929ad..227efca 100644 --- a/src/soc/nvidia/tegra124/Kconfig +++ b/src/soc/nvidia/tegra124/Kconfig @@ -18,6 +18,9 @@ if SOC_NVIDIA_TEGRA124 config CHROMEOS select VBOOT_OPROM_MATTERS + select VBOOT_STARTS_IN_BOOTBLOCK + select SEPARATE_VERSTAGE + select CHIPSET_PROVIDES_VERSTAGE_MAIN_SYMBOL config TEGRA124_MODEL_TD570D bool "TD570D"

1 0

Patch merged into coreboot/master: board/intel/amenia: Enable LPSS S0ix
by gerrit＠coreboot.org 07 Jul '16

07 Jul '16

the following patch was just integrated into master: commit 7124882aeb45ed863c12dcd9cea2f3ab033b2ee4 Author: Hannah Williams <hannah.williams(a)intel.com> Date: Thu Jun 2 15:00:36 2016 -0700 board/intel/amenia: Enable LPSS S0ix This setting will enable S0ix for LPSS Change-Id: Ie07cb8437d0cee61a03638aa980fd3322fef0c4e Signed-off-by: Hannah Williams <hannah.williams(a)intel.com> Reviewed-on: https://review.coreboot.org/15056 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Tested-by: build bot (Jenkins) See https://review.coreboot.org/15056 for details. -gerrit

1 0

Patch set updated for coreboot: mainboard/google/reef: add board_id() support
by Aaron Durbin 07 Jul '16

07 Jul '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15561 -gerrit commit 8536604ee7958e5e75efbfef04b6307eaa29a104 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Jul 6 22:53:51 2016 -0500 mainboard/google/reef: add board_id() support The board build version is provided by the EC on reef. Provide the necessary functional support for coreboot to differentiate the board versions. BUG=chrome-os-partner:54959,chrome-os-partner:54960,chrome-os-partner:54961 BRANCH=None TEST=Built and tested on reef. Change-Id: I1b7e8b2f4142753cde736148ca9495bcc625f318 Signed-off-by: Aaron Durbin <adurbin(a)chromuim.org> --- src/mainboard/google/reef/Makefile.inc | 2 ++ src/mainboard/google/reef/boardid.c | 28 ++++++++++++++++++++++++++++ 2 files changed, 30 insertions(+) diff --git a/src/mainboard/google/reef/Makefile.inc b/src/mainboard/google/reef/Makefile.inc index f8fbbf3..6db0f2f 100644 --- a/src/mainboard/google/reef/Makefile.inc +++ b/src/mainboard/google/reef/Makefile.inc @@ -2,7 +2,9 @@ bootblock-y += bootblock.c bootblock-y += ec.c romstage-$(CONFIG_CHROMEOS) += chromeos.c +romstage-y += boardid.c +ramstage-y += boardid.c ramstage-$(CONFIG_CHROMEOS) += chromeos.c ramstage-y += ec.c ramstage-y += mainboard.c diff --git a/src/mainboard/google/reef/boardid.c b/src/mainboard/google/reef/boardid.c new file mode 100644 index 0000000..4eb9f48 --- /dev/null +++ b/src/mainboard/google/reef/boardid.c @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Google Inc. + * Copyright (C) 2015 Intel Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <boardid.h> +#include <ec/google/chromeec/ec.h> + +uint8_t board_id(void) +{ + MAYBE_STATIC int id = -1; + + if (id < 0) + id = google_chromeec_get_board_version(); + + return id; +}

1 0

Patch set updated for coreboot: mainboard/google/reef: add memory SKU id support
by Aaron Durbin 07 Jul '16

07 Jul '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15560 -gerrit commit 22a71d8f45d30062d59980f475feeb92456140a0 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Jul 6 22:51:05 2016 -0500 mainboard/google/reef: add memory SKU id support While the proto boards didn't have a memory SKU notion the EVT boards do. Therefore, provide support for selecting the proper memory SKU information based on the memory id straps. This works on EVT boards because the pins used for the strapping weren't used on proto. However, internal pullups need to be enabled so that proto boards read the correct id. BUG=chrome-os-partner:54949 BRANCH=None TEST=Built and used on reef for memory config. Change-Id: I8653260e5d1b9adc83b78ea2770c683b72535e11 Signed-off-by: Aaron Durbin <adurbin(a)chromuim.org> --- src/mainboard/google/reef/gpio.h | 18 +++++++--- src/mainboard/google/reef/romstage.c | 66 +++++++++++++++++++++++++++++++----- 2 files changed, 72 insertions(+), 12 deletions(-) diff --git a/src/mainboard/google/reef/gpio.h b/src/mainboard/google/reef/gpio.h index 91e8bb1..14cf880c 100644 --- a/src/mainboard/google/reef/gpio.h +++ b/src/mainboard/google/reef/gpio.h @@ -243,8 +243,8 @@ static const struct pad_config gpio_table[] = { PAD_CFG_GPI(GPIO_98, UP_20K, DEEP), /* FST_SPI_CS1_B -- unused */ PAD_CFG_NF(GPIO_99, NATIVE, DEEP, NF1), /* FST_SPI_MOSI_IO0 */ PAD_CFG_NF(GPIO_100, NATIVE, DEEP, NF1), /* FST_SPI_MISO_IO1 */ - PAD_CFG_GPI(GPIO_101, UP_20K, DEEP), /* FST_IO2 -- unused */ - PAD_CFG_GPI(GPIO_102, UP_20K, DEEP), /* FST_IO3 -- unused */ + PAD_CFG_GPI(GPIO_101, UP_20K, DEEP), /* FST_IO2 -- MEM_CONFIG0 */ + PAD_CFG_GPI(GPIO_102, UP_20K, DEEP), /* FST_IO3 -- MEM_CONFIG1 */ PAD_CFG_NF(GPIO_103, NATIVE, DEEP, NF1), /* FST_SPI_CLK */ /* SIO_SPI_0 - Used for FP */ @@ -312,7 +312,7 @@ static const struct pad_config gpio_table[] = { PAD_CFG_GPI(GPIO_37, UP_20K, DEEP), /* unused */ /* LPSS_UART[0:2] */ - PAD_CFG_GPI(GPIO_38, UP_20K, DEEP), /* LPSS_UART0_RXD - unused */ + PAD_CFG_GPI(GPIO_38, UP_20K, DEEP), /* LPSS_UART0_RXD - MEM_CONFIG2*/ /* Next 2 are straps. */ PAD_CFG_GPI(GPIO_39, DN_20K, DEEP), /* LPSS_UART0_TXD - unused */ PAD_CFG_GPI(GPIO_40, DN_20K, DEEP), /* LPSS_UART0_RTS - unused */ @@ -320,7 +320,7 @@ static const struct pad_config gpio_table[] = { PAD_CFG_NF(GPIO_42, NATIVE, DEEP, NF1), /* LPSS_UART1_RXD */ PAD_CFG_NF(GPIO_43, NATIVE, DEEP, NF1), /* LPSS_UART1_TXD */ PAD_CFG_NF(GPIO_44, NATIVE, DEEP, NF1), /* LPSS_UART1_RTS */ - PAD_CFG_NF(GPIO_45, NATIVE, DEEP, NF1), /* LPSS_UART1_CTS */ + PAD_CFG_GPI(GPIO_45, UP_20K, DEEP), /* LPSS_UART1_CTS - MEM_CONFIG3 */ PAD_CFG_NF(GPIO_46, NATIVE, DEEP, NF1), /* LPSS_UART2_RXD */ PAD_CFG_NF(GPIO_47, NATIVE, DEEP, NF1), /* LPSS_UART2_TXD */ PAD_CFG_GPI(GPIO_48, UP_20K, DEEP), /* LPSS_UART2_RTS - unused */ @@ -346,5 +346,15 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_GPI(GPIO_75, UP_20K, DEEP), /* I2S1_BCLK -- PCH_WP */ }; +/* + * The proto boards didn't have memory SKU pins, but the same ones can be + * utilized as post proto boards because the pins used were never connected + * or no peripheral utilized the signals on proto boards. + */ +#define MEM_CONFIG3 GPIO_45 +#define MEM_CONFIG2 GPIO_38 +#define MEM_CONFIG1 GPIO_102 +#define MEM_CONFIG0 GPIO_101 + #endif /* __ACPI__ */ #endif /* MAINBOARD_GPIO_H */ diff --git a/src/mainboard/google/reef/romstage.c b/src/mainboard/google/reef/romstage.c index ecf6fa5..2c68b60 100644 --- a/src/mainboard/google/reef/romstage.c +++ b/src/mainboard/google/reef/romstage.c @@ -13,8 +13,10 @@ * GNU General Public License for more details. */ +#include <gpio.h> #include <soc/meminit.h> #include <soc/romstage.h> +#include "gpio.h" static const struct lpddr4_swizzle_cfg board_swizzle = { /* CH0_DQA[0:31] SoC pins -> U22 LPDDR4 module pins */ @@ -60,15 +62,63 @@ static const struct lpddr4_swizzle_cfg board_swizzle = { }, }; +/* + * Proto boards didn't have a memory SKU id. The configuration pins use + * an internal weak pullup with stronger pulldowns for the 0 bits. As + * proto boards didn't use the memory SKU pins the SKU id reads as 4'b1111, + * i.e. 15. + */ +#define PROTO_SKU 15 + +static const struct lpddr4_sku skus[] = { + /* K4F6E304HB-MGCJ - both logical channels */ + [0] = { + .speed = LP4_SPEED_2400, + .ch0_density = LP4_16Gb_DENSITY, + .ch1_density = LP4_16Gb_DENSITY, + }, + /* K4F8E304HB-MGCJ - both logical channels */ + [1] = { + .speed = LP4_SPEED_2400, + .ch0_density = LP4_8Gb_DENSITY, + .ch1_density = LP4_8Gb_DENSITY, + }, + /* MT53B512M32D2NP-062WT:C - both logical channels */ + [2] = { + .speed = LP4_SPEED_2400, + .ch0_density = LP4_16Gb_DENSITY, + .ch1_density = LP4_16Gb_DENSITY, + /* MT53B256M32D1NP-062 WT:C - both logical channels */ + }, + [3] = { + .speed = LP4_SPEED_2400, + .ch0_density = LP4_8Gb_DENSITY, + .ch1_density = LP4_8Gb_DENSITY, + }, + /* K4F8E304HB-MGCH - both logical channels */ + [PROTO_SKU] = { + .speed = LP4_SPEED_2400, + .ch0_density = LP4_8Gb_DENSITY, + .ch1_density = LP4_8Gb_DENSITY, + }, +}; + +static const struct lpddr4_cfg lp4cfg = { + .skus = skus, + .num_skus = ARRAY_SIZE(skus), + .swizzle_config = &board_swizzle, +}; + void mainboard_memory_init_params(struct FSPM_UPD *memupd) { - struct FSP_M_CONFIG *cfg = &memupd->FspmConfig; + int mem_sku; + gpio_t pads[] = { MEM_CONFIG3, MEM_CONFIG2, MEM_CONFIG1, MEM_CONFIG0 }; + + /* + * Read memory SKU id with internal pullups enabled to handle + * proto boards with no SKU id pins. + */ + mem_sku = gpio_pullup_base2_value(pads, ARRAY_SIZE(pads)); - /* Use a default 2400 speed. */ - meminit_lpddr4(cfg, LP4_SPEED_2400); - /* Enable both logical channels with a 8Gb density. */ - meminit_lpddr4_enable_channel(cfg, LP4_LCH0, LP4_8Gb_DENSITY, - &board_swizzle); - meminit_lpddr4_enable_channel(cfg, LP4_LCH1, LP4_8Gb_DENSITY, - &board_swizzle); + meminit_lpddr4_by_sku(&memupd->FspmConfig, &lp4cfg, mem_sku); }

1 0

Patch set updated for coreboot: mainboard/google/reef: apply EVT board changes
by Aaron Durbin 07 Jul '16

07 Jul '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15562 -gerrit commit 049f092ee8b604672dc56174c11b9f1c66b6aa65 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Jul 6 23:16:01 2016 -0500 mainboard/google/reef: apply EVT board changes Based on the board revision apply the correct GPIO changes. The only differences are the addition of 2 peripheral wake signals and a dedicated peripheral reset line. BUG=chrome-os-partner:54959,chrome-os-partner:54960,chrome-os-partner:54961 BRANCH=None TEST=Built and tested on reef. Change-Id: I9cac82158e70e0af1b454ec4581c2e4622b95b4b Signed-off-by: Aaron Durbin <adurbin(a)chromuim.org> --- src/mainboard/google/reef/gpio.h | 16 +++++++++++++--- src/mainboard/google/reef/mainboard.c | 15 +++++++++++++++ 2 files changed, 28 insertions(+), 3 deletions(-) diff --git a/src/mainboard/google/reef/gpio.h b/src/mainboard/google/reef/gpio.h index 14cf880c..cbad4c6 100644 --- a/src/mainboard/google/reef/gpio.h +++ b/src/mainboard/google/reef/gpio.h @@ -274,7 +274,6 @@ static const struct pad_config gpio_table[] = { PAD_CFG_GPI(GPIO_0, UP_20K, DEEP), PAD_CFG_GPI(GPIO_1, UP_20K, DEEP), PAD_CFG_GPI(GPIO_2, UP_20K, DEEP), - PAD_CFG_GPI(GPIO_3, UP_20K, DEEP), PAD_CFG_GPI(GPIO_4, UP_20K, DEEP), PAD_CFG_GPI(GPIO_5, UP_20K, DEEP), PAD_CFG_GPI(GPIO_6, UP_20K, DEEP), @@ -287,7 +286,6 @@ static const struct pad_config gpio_table[] = { PAD_CFG_GPI(GPIO_12, UP_20K, DEEP), /* unused */ PAD_CFG_GPI(GPIO_13, UP_20K, DEEP), /* unused */ PAD_CFG_GPI_APIC(GPIO_14, UP_20K, DEEP, LEVEL, NONE), /* FP IRQ */ - PAD_CFG_GPI(GPIO_15, UP_20K, DEEP), /* unused */ PAD_CFG_GPI(GPIO_16, UP_20K, DEEP), /* unused */ PAD_CFG_GPI(GPIO_17, UP_20K, DEEP), /* unused */ PAD_CFG_GPI_APIC(GPIO_18, NONE, DEEP, LEVEL, NONE), /* Trackpad IRQ */ @@ -319,7 +317,6 @@ static const struct pad_config gpio_table[] = { PAD_CFG_GPI(GPIO_41, NONE, DEEP), /* LPSS_UART0_CTS - EC_IN_RW */ PAD_CFG_NF(GPIO_42, NATIVE, DEEP, NF1), /* LPSS_UART1_RXD */ PAD_CFG_NF(GPIO_43, NATIVE, DEEP, NF1), /* LPSS_UART1_TXD */ - PAD_CFG_NF(GPIO_44, NATIVE, DEEP, NF1), /* LPSS_UART1_RTS */ PAD_CFG_GPI(GPIO_45, UP_20K, DEEP), /* LPSS_UART1_CTS - MEM_CONFIG3 */ PAD_CFG_NF(GPIO_46, NATIVE, DEEP, NF1), /* LPSS_UART2_RXD */ PAD_CFG_NF(GPIO_47, NATIVE, DEEP, NF1), /* LPSS_UART2_TXD */ @@ -356,5 +353,18 @@ static const struct pad_config early_gpio_table[] = { #define MEM_CONFIG1 GPIO_102 #define MEM_CONFIG0 GPIO_101 +static const struct pad_config proto_diff_table[] = { + PAD_CFG_GPI(GPIO_3, UP_20K, DEEP), /* unused */ + PAD_CFG_GPI(GPIO_15, UP_20K, DEEP), /* unused */ + PAD_CFG_NF(GPIO_44, NATIVE, DEEP, NF1), /* LPSS_UART1_RTS */ +}; + +/* Wake peripheral signals post proto. */ +static const struct pad_config nonproto_diff_table[] = { + PAD_CFG_GPI_SCI(GPIO_3, UP_20K, DEEP, LEVEL, NONE), /* FP_INT_L */ + PAD_CFG_GPI_SCI(GPIO_15, NONE, DEEP, LEVEL, NONE), /* TRACKPAD_INT_1V8_ODL */ + PAD_CFG_GPO(GPIO_44, 1, DEEP), /* GPS_RST_ODL */ +}; + #endif /* __ACPI__ */ #endif /* MAINBOARD_GPIO_H */ diff --git a/src/mainboard/google/reef/mainboard.c b/src/mainboard/google/reef/mainboard.c index 2b121ef..def6900 100644 --- a/src/mainboard/google/reef/mainboard.c +++ b/src/mainboard/google/reef/mainboard.c @@ -14,6 +14,7 @@ */ #include <arch/acpi.h> +#include <boardid.h> #include <console/console.h> #include <device/device.h> #include <nhlt.h> @@ -24,7 +25,21 @@ static void mainboard_init(void *chip_info) { + int boardid; + + boardid = board_id(); + printk(BIOS_INFO, "Board ID: %d\n", boardid); + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); + + /* Apply proto board settings if board matches. */ + if (boardid == 0) + gpio_configure_pads(proto_diff_table, + ARRAY_SIZE(proto_diff_table)); + else + gpio_configure_pads(nonproto_diff_table, + ARRAY_SIZE(nonproto_diff_table)); + mainboard_ec_init(); }

1 0

Patch set updated for coreboot: soc/intel/apollolake: add LPDDR4 sku selection support
by Aaron Durbin 07 Jul '16

07 Jul '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15559 -gerrit commit 7c0f1dfc2b6f300e655a3775ac4952b9a538b05a Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Jul 6 22:45:57 2016 -0500 soc/intel/apollolake: add LPDDR4 sku selection support Instead of having all the mainboards put similar logic into their own code provide common mechanism for memory SKU selection. A function, meminit_lpddr4_by_sku(), is added that selects the proper configuration based on the SKU id and configuration passed in. LPDDR4 speed as well as DRAM device density configuration is associated for each logical channel per SKU id. BUG=chrome-os-partner:54949 BRANCH=None TEST=Built and used on reef for memory config. Change-Id: Ifc6a734040bb61a58bc3d4c128a6420a71245c6c Signed-off-by: Aaron Durbin <adurbin(a)chromuim.org> --- src/soc/intel/apollolake/include/soc/meminit.h | 20 ++++++++++++++++ src/soc/intel/apollolake/meminit.c | 32 ++++++++++++++++++++++++++ 2 files changed, 52 insertions(+) diff --git a/src/soc/intel/apollolake/include/soc/meminit.h b/src/soc/intel/apollolake/include/soc/meminit.h index 14b1ef5..94c9032 100644 --- a/src/soc/intel/apollolake/include/soc/meminit.h +++ b/src/soc/intel/apollolake/include/soc/meminit.h @@ -16,6 +16,7 @@ #ifndef _SOC_APOLLOLAKE_MEMINIT_H_ #define _SOC_APOLLOLAKE_MEMINIT_H_ +#include <stddef.h> #include <stdint.h> /* @@ -94,4 +95,23 @@ void meminit_lpddr4_enable_channel(struct FSP_M_CONFIG *cfg, int logical_chan, int device_density, const struct lpddr4_swizzle_cfg *scfg); +struct lpddr4_sku { + int speed; + int ch0_density; + int ch1_density; +}; + +struct lpddr4_cfg { + const struct lpddr4_sku *skus; + size_t num_skus; + const struct lpddr4_swizzle_cfg *swizzle_config; +}; + +/* + * Initialize LPDDR4 settings by the provided lpddr4_cfg information and sku id. + * The sku id is an index into the sku array within the lpddr4_cfg struct. + */ +void meminit_lpddr4_by_sku(struct FSP_M_CONFIG *cfg, + const struct lpddr4_cfg *lpcfg, size_t sku_id); + #endif /* _SOC_APOLLOLAKE_MEMINIT_H_ */ diff --git a/src/soc/intel/apollolake/meminit.c b/src/soc/intel/apollolake/meminit.c index 8b661c9..8954769 100644 --- a/src/soc/intel/apollolake/meminit.c +++ b/src/soc/intel/apollolake/meminit.c @@ -211,3 +211,35 @@ void meminit_lpddr4_enable_channel(struct FSP_M_CONFIG *cfg, int logical_chan, break; } } + +void meminit_lpddr4_by_sku(struct FSP_M_CONFIG *cfg, + const struct lpddr4_cfg *lpcfg, size_t sku_id) +{ + const struct lpddr4_sku *sku; + + if (sku_id >= lpcfg->num_skus) { + printk(BIOS_ERR, "Too few LPDDR4 SKUs: 0x%zx/0x%zx\n", + sku_id, lpcfg->num_skus); + return; + } + + printk(BIOS_INFO, "LPDDR4 SKU id = 0x%zx\n", sku_id); + + sku = &lpcfg->skus[sku_id]; + + meminit_lpddr4(cfg, sku->speed); + + if (sku->ch0_density) { + printk(BIOS_INFO, "LPDDR4 Ch0 density = %d\n", + sku->ch0_density); + meminit_lpddr4_enable_channel(cfg, LP4_LCH0, sku->ch0_density, + lpcfg->swizzle_config); + } + + if (sku->ch1_density) { + printk(BIOS_INFO, "LPDDR4 Ch1 density = %d\n", + sku->ch1_density); + meminit_lpddr4_enable_channel(cfg, LP4_LCH1, sku->ch1_density, + lpcfg->swizzle_config); + } +}

1 0

New patch to review for coreboot: superio/fintek/f81866d: Add support for UART 3/4
by Fabian Kunkel 07 Jul '16

07 Jul '16

Fabian Kunkel (fabi(a)adv.bruhnspace.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15564 -gerrit commit b13b68949fe347dce6707b394915f0acb05957a9 Author: Fabian Kunkel <fabi(a)adv.bruhnspace.com> Date: Thu Jul 7 15:15:18 2016 +0200 superio/fintek/f81866d: Add support for UART 3/4 Pins for UART 3/4 are by default GPIO pins. This patch sets the pins in UART mode. Since uart 1/3 and 2/4 are sharing the same interrupt line, the patch needs to enable also shared interrupts. Datasheet: Name: F81866D/A-I, Release Date: Jan 2012, Version: V0.12P Link: http://www.alldatasheet.com/datasheet-pdf/pdf/459085/FINTEK/F81866AD-I.html Change-Id: Ief5d70c8b25a2fb6cd787c45a52410e20b0eaf2e Signed-off-by: Fabian Kunkel <fabi(a)adv.bruhnspace.com> --- src/mainboard/bap/ode_e20XX/devicetree.cb | 8 ++- src/superio/fintek/f81866d/Makefile.inc | 2 +- src/superio/fintek/f81866d/f81866d_uart.c | 92 ++++++++++++++++++++++++++++ src/superio/fintek/f81866d/fintek_internal.h | 1 + src/superio/fintek/f81866d/superio.c | 8 +++ 5 files changed, 108 insertions(+), 3 deletions(-) diff --git a/src/mainboard/bap/ode_e20XX/devicetree.cb b/src/mainboard/bap/ode_e20XX/devicetree.cb index a598a99..1670d61 100644 --- a/src/mainboard/bap/ode_e20XX/devicetree.cb +++ b/src/mainboard/bap/ode_e20XX/devicetree.cb @@ -88,9 +88,13 @@ chip northbridge/amd/agesa/family16kb/root_complex io 0x60 = 0x2f8 irq 0x70 = 3 end - device pnp 4e.12 off # COM3 + device pnp 4e.12 on # COM3 + io 0x60 = 0x3e8 + irq 0x70 = 4 end - device pnp 4e.13 off # COM4 + device pnp 4e.13 on # COM4 + io 0x60 = 0x2e8 + irq 0x70 = 3 end device pnp 4e.14 off # COM5 end diff --git a/src/superio/fintek/f81866d/Makefile.inc b/src/superio/fintek/f81866d/Makefile.inc index 8654659..b3fd34f 100644 --- a/src/superio/fintek/f81866d/Makefile.inc +++ b/src/superio/fintek/f81866d/Makefile.inc @@ -16,5 +16,5 @@ ## GNU General Public License for more details. ## -ramstage-$(CONFIG_SUPERIO_FINTEK_F81866D) += f81866d_hwm.c +ramstage-$(CONFIG_SUPERIO_FINTEK_F81866D) += f81866d_hwm.c f81866d_uart.c ramstage-$(CONFIG_SUPERIO_FINTEK_F81866D) += superio.c diff --git a/src/superio/fintek/f81866d/f81866d_uart.c b/src/superio/fintek/f81866d/f81866d_uart.c new file mode 100644 index 0000000..64fe66c --- /dev/null +++ b/src/superio/fintek/f81866d/f81866d_uart.c @@ -0,0 +1,92 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 BAP - Bruhnspace Advanced Projects + * (Written by Fabian Kunkel <fabi(a)adv.bruhnspace.com> for BAP) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <console/console.h> +#include <device/device.h> +#include <device/pnp.h> +#include "fintek_internal.h" +#include "f81866d.h" + +#define LDN_REG 0x07 +#define MULTI_FUNC_SEL3_REG 0x29 +#define IRQ_SHARE_REGISTER 0xF0 +#define FIFO_SEL_MODE 0xF6 + +/* + * f81866d_uart_init enables all necessary registers for uart 3/4 + * Fintek needs to know if pins are used as GPIO pins or uarts + * Share interrupt usage needs to be enabled + */ +void f81866d_uart_init(struct device *dev) +{ + struct resource *res = find_resource(dev, PNP_IDX_IO0); + u8 tmp; + + if (!res) { + printk(BIOS_WARNING, "Super I/O Uart: No Uart resource found.\n"); + return; + } + + pnp_enter_conf_mode(dev); + + if (dev->path.pnp.device == F81866D_SP3) { + // Set uart3 function (Bit 4/5), otherwise pin 36-46 are GPIO + tmp = pnp_read_config(dev, MULTI_FUNC_SEL3_REG); + pnp_write_config(dev, MULTI_FUNC_SEL3_REG, tmp | 0x30); + + // Select uart 1 in LDN register + pnp_write_config(dev, LDN_REG, F81866D_SP1 & 0xff); + // Enable share interrupt (Bit 0) + pnp_write_config(dev, IRQ_SHARE_REGISTER, 0x01); + // Set IRQ trigger mode from active low to high (Bit 3) + tmp = pnp_read_config(dev, FIFO_SEL_MODE); + pnp_write_config(dev, FIFO_SEL_MODE, tmp | 0x8); + + // Select uart 3 in LDN register + pnp_write_config(dev, LDN_REG, F81866D_SP3 & 0xff); + // Enable share interrupt (Bit 0) + pnp_write_config(dev, IRQ_SHARE_REGISTER, 0x01); + // Set IRQ trigger mode from active low to high (Bit 3) + tmp = pnp_read_config(dev, FIFO_SEL_MODE); + pnp_write_config(dev, FIFO_SEL_MODE, tmp | 0x8); + } + + if (dev->path.pnp.device == F81866D_SP4) { + // Set uart4 function (Bit 6/7), otherwise pin 44-51 are GPIO + tmp = pnp_read_config(dev, MULTI_FUNC_SEL3_REG); + pnp_write_config(dev, MULTI_FUNC_SEL3_REG, tmp | 0xC0); + + // Select uart 2 in LDN register + pnp_write_config(dev, LDN_REG, F81866D_SP2 & 0xff); + // Enable share interrupt (Bit 0) + pnp_write_config(dev, IRQ_SHARE_REGISTER, 0x01); + // Set IRQ trigger mode from active low to high (Bit 3) + tmp = pnp_read_config(dev, FIFO_SEL_MODE); + pnp_write_config(dev, FIFO_SEL_MODE, tmp | 0x8); + + // Select uart 4 in LDN register + pnp_write_config(dev, LDN_REG, F81866D_SP4 & 0xff); + // Enable share interrupt (Bit 0) + pnp_write_config(dev, IRQ_SHARE_REGISTER, 0x01); + // Set IRQ trigger mode from active low to high (Bit 3) + tmp = pnp_read_config(dev, FIFO_SEL_MODE); + pnp_write_config(dev, FIFO_SEL_MODE, tmp | 0x8); + } + + pnp_exit_conf_mode(dev); +} diff --git a/src/superio/fintek/f81866d/fintek_internal.h b/src/superio/fintek/f81866d/fintek_internal.h index 0405e3e..977a47d 100644 --- a/src/superio/fintek/f81866d/fintek_internal.h +++ b/src/superio/fintek/f81866d/fintek_internal.h @@ -23,5 +23,6 @@ #include <device/pnp.h> void f81866d_hwm_init(struct device *dev); +void f81866d_uart_init(struct device *dev); #endif /* SUPERIO_FINTEK_F81866D_INTERNAL_H */ diff --git a/src/superio/fintek/f81866d/superio.c b/src/superio/fintek/f81866d/superio.c index a616290..c997ce3 100644 --- a/src/superio/fintek/f81866d/superio.c +++ b/src/superio/fintek/f81866d/superio.c @@ -40,6 +40,14 @@ static void f81866d_init(struct device *dev) // Fixing temp sensor read out and init Fan control f81866d_hwm_init(dev); break; + case F81866D_SP3: + // Enable Uart3 and IRQ share register + f81866d_uart_init(dev); + break; + case F81866D_SP4: + // Enable Uart4 and IRQ share register + f81866d_uart_init(dev); + break; } }

1 0

Patch set updated for coreboot: soc/intel/quark/bootblock: Remove clear_smi_and_wake_events
by Jonathan Neuschäfer 07 Jul '16

07 Jul '16

Jonathan Neuschäfer (j.neuschaefer(a)gmx.net) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15552 -gerrit commit 37c1b1cdde0abfe696dac0ecd32b587ab7a55b4c Author: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Date: Wed Jul 6 22:08:46 2016 +0200 soc/intel/quark/bootblock: Remove clear_smi_and_wake_events It is not used in this file. Change-Id: I59bb41370b97b79073c0fd82b1dbcae9fd8a62d0 Reported-by: GCC 6.1.0 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> --- src/soc/intel/quark/bootblock/bootblock.c | 9 --------- 1 file changed, 9 deletions(-) diff --git a/src/soc/intel/quark/bootblock/bootblock.c b/src/soc/intel/quark/bootblock/bootblock.c index 669cd47..4aa774b 100644 --- a/src/soc/intel/quark/bootblock/bootblock.c +++ b/src/soc/intel/quark/bootblock/bootblock.c @@ -21,15 +21,6 @@ #include <soc/pci_devs.h> #include <soc/reg_access.h> -static const struct reg_script clear_smi_and_wake_events[] = { - /* Clear any SMI or wake events */ - REG_GPE0_READ(R_QNC_GPE0BLK_GPE0S), - REG_GPE0_READ(R_QNC_GPE0BLK_SMIS), - REG_GPE0_OR(R_QNC_GPE0BLK_GPE0S, B_QNC_GPE0BLK_GPE0S_ALL), - REG_GPE0_OR(R_QNC_GPE0BLK_SMIS, B_QNC_GPE0BLK_SMIS_ALL), - REG_SCRIPT_END -}; - static const struct reg_script legacy_gpio_init[] = { /* Temporarily enable the legacy GPIO controller */ REG_PCI_WRITE32(R_QNC_LPC_GBA_BASE, IO_ADDRESS_VALID

1 0

Patch set updated for coreboot: siemens/mc_bdx1: Move SCI to IRQ 10
by Werner Zeh 07 Jul '16

07 Jul '16

Werner Zeh (werner.zeh(a)siemens.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15563 -gerrit commit 810efe1aed50876d6c1d798d1a3c54a14ae5da5d Author: Werner Zeh <werner.zeh(a)siemens.com> Date: Thu Jul 7 07:10:50 2016 +0200 siemens/mc_bdx1: Move SCI to IRQ 10 IRQ 9 is used for different purpose on this board so move SCI away to IRQ10. Change-Id: I107bfb5ec8cd05f844ee75550779be7746e77a88 Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- src/mainboard/siemens/mc_bdx1/mainboard.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/src/mainboard/siemens/mc_bdx1/mainboard.c b/src/mainboard/siemens/mc_bdx1/mainboard.c index bad072b..8a5226b 100644 --- a/src/mainboard/siemens/mc_bdx1/mainboard.c +++ b/src/mainboard/siemens/mc_bdx1/mainboard.c @@ -32,6 +32,7 @@ #include <hwilib.h> #include <i210.h> #include <soc/pci_devs.h> +#include <soc/irq.h> #define MAX_PATH_DEPTH 12 #define MAX_NUM_MAPPINGS 10 @@ -91,6 +92,18 @@ static void mainboard_enable(device_t dev) } +static void mainboard_init(void *chip_info) +{ + uint8_t actl = 0; + device_t dev = dev_find_slot(0, PCI_DEVFN(LPC_DEV, LPC_FUNC)); + + /* Route SCI to IRQ 10 to free IRQ 9 slot. */ + actl = pci_read_config8(dev, ACPI_CNTL_OFFSET); + actl &= ~SCIS_MASK; + actl |= SCIS_IRQ10; + pci_write_config8(dev, ACPI_CNTL_OFFSET, actl); +} + static void mainboard_final(void *chip_info) { void *spi_base = NULL; @@ -183,5 +196,6 @@ enum cb_err mainboard_get_mac_address(struct device *dev, uint8_t mac[6]) struct chip_operations mainboard_ops = { .enable_dev = mainboard_enable, + .init = mainboard_init, .final = mainboard_final };

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit July 2016