coreboot-gerrit July 2016

coreboot-gerrit@coreboot.org

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1820 discussions

Patch set updated for coreboot: soc/intel/apollolake: Add handler for SCI
by Shaunak Saha 08 Jul '16

08 Jul '16

Shaunak Saha (shaunak.saha(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15578 -gerrit commit 5ee4ac4ca91db0fff763df385c23b698c795a52c Author: Shaunak Saha <shaunak.saha(a)intel.com> Date: Thu Jul 7 14:48:21 2016 -0700 soc/intel/apollolake: Add handler for SCI This patch adds the handler to enable bit for gpio_tier1_sci_en. gpio_tier1_sci_en enables the setting of the GPIO_TIER1_SCI_STS bit to generate a wake event and/or an SCI or SMI#. Change-Id: I1e1bd3f5c89a5e6bea2d1858569a9d30e6da78fe Signed-off-by: Shaunak Saha <shaunak.saha(a)intel.com> --- src/soc/intel/apollolake/acpi/gpio.asl | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/src/soc/intel/apollolake/acpi/gpio.asl b/src/soc/intel/apollolake/acpi/gpio.asl index 4bf0442..47edd94 100644 --- a/src/soc/intel/apollolake/acpi/gpio.asl +++ b/src/soc/intel/apollolake/acpi/gpio.asl @@ -142,3 +142,9 @@ scope (\_SB) { } } } + +Scope(\_GPE) +{ + /* Dummy method for the Tier 1 GPIO SCI enable bit */ + Method(_L0F, 0) {} +}

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Patch set updated for coreboot: intel/amenia: Add GPE routing settings
by Shaunak Saha 08 Jul '16

08 Jul '16

Shaunak Saha (shaunak.saha(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15325 -gerrit commit 1a65a8205927f8075b3b61f779b80fcad40cd0a9 Author: Shaunak Saha <shaunak.saha(a)intel.com> Date: Fri Jun 10 19:36:49 2016 -0700 intel/amenia: Add GPE routing settings This patch sets the devicetree for gpe0_dw configuration and also confgigures the GPIO lines for SCI.EC_SCI_GPI is configured to proper value. BUG = chrome-os-partner:53438 TEST = Toggle pch_sci_l from ec console using gpioset command and see that the sci counter increases in /sys/firmware/acpi/interrupt and also 9 in /proc/interrupt Change-Id: I3ae9ef7c6a3c8688bcb6cb4c73f5618e7cde342c Signed-off-by: Shaunak Saha <shaunak.saha(a)intel.com> --- src/mainboard/intel/amenia/devicetree.cb | 9 +++++++++ src/mainboard/intel/amenia/ec.h | 8 +++++--- src/mainboard/intel/amenia/gpio.h | 2 +- 3 files changed, 15 insertions(+), 4 deletions(-) diff --git a/src/mainboard/intel/amenia/devicetree.cb b/src/mainboard/intel/amenia/devicetree.cb index 2080d6f..711b96d 100644 --- a/src/mainboard/intel/amenia/devicetree.cb +++ b/src/mainboard/intel/amenia/devicetree.cb @@ -15,6 +15,15 @@ chip soc/intel/apollolake # 0x1A[6:0] stands for 26*125 = 3250 pSec delay for SDR104/HS200 register "emmc_tx_data_cntl1" = "0x1A1A" # HS400 required + # GPE configuration + # Note that GPE events called out in ASL code rely on this + # route, i.e., If this route changes then the affected GPE + # offset bits also needs to be changed. This sets the PMC register + # GPE_CFG fields. + register "gpe0_dw1" = "PMC_GPE_N_31_0" + register "gpe0_dw2" = "PMC_GPE_N_63_32" + register "gpe0_dw3" = "PMC_GPE_SW_31_0" + device domain 0 on device pci 00.0 on end # - Host Bridge device pci 00.1 on end # - DPTF diff --git a/src/mainboard/intel/amenia/ec.h b/src/mainboard/intel/amenia/ec.h index 91890fd..ba3962a 100644 --- a/src/mainboard/intel/amenia/ec.h +++ b/src/mainboard/intel/amenia/ec.h @@ -20,9 +20,11 @@ #include <ec/google/chromeec/ec_commands.h> -/* This is the GPE status bit. - TODO: Fix this to proper bit matching GPE routing table */ -#define EC_SCI_GPI 15 +/* + * GPIO_11 for SCI is routed to GPE0_DW1 and maps to group GPIO_GPE_N_31_0 + * which is North community + */ +#define EC_SCI_GPI GPE0_DW1_11 #define MAINBOARD_EC_SCI_EVENTS \ (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED) |\ diff --git a/src/mainboard/intel/amenia/gpio.h b/src/mainboard/intel/amenia/gpio.h index 87d6190..a39cca3 100644 --- a/src/mainboard/intel/amenia/gpio.h +++ b/src/mainboard/intel/amenia/gpio.h @@ -239,7 +239,7 @@ static const struct pad_config gpio_table[] = { PAD_CFG_NF(GPIO_8, NATIVE, DEEP, NF1), PAD_CFG_GPI(GPIO_9, UP_20K, DEEP), /* SPI_TPM_IRQ_N */ PAD_NC(GPIO_10, DN_20K), /* RSVD for MIPI (unused) */ - PAD_CFG_GPI_SCI(GPIO_11, UP_20K, DEEP, LEVEL, NONE), + PAD_CFG_GPI_SCI(GPIO_11, UP_20K, DEEP, EDGE_SINGLE, INVERT), /* SOC_WAKE_SCI_N */ PAD_NC(GPIO_12, DN_20K), PAD_NC(GPIO_13, DN_20K),

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New patch to review for coreboot: soc/intel/apollolake: Add handler for SCI
by Shaunak Saha 08 Jul '16

08 Jul '16

Shaunak Saha (shaunak.saha(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15578 -gerrit commit d9c3b221f338d56252003db7efd41c55156a26f3 Author: Shaunak Saha <shaunak.saha(a)intel.com> Date: Thu Jul 7 14:48:21 2016 -0700 soc/intel/apollolake: Add handler for SCI This patch adds the handler to enable bit for gpio_tier1_sci_en. gpio_tier1_sci_en enables the setting of the GPIO_TIER1_SCI_STS bit to generate a wake event and/or an SCI or SMI#. Change-Id: I1e1bd3f5c89a5e6bea2d1858569a9d30e6da78fe Signed-off-by: Shaunak Saha <shaunak.saha(a)intel.com> --- src/soc/intel/apollolake/acpi/gpio.asl | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/src/soc/intel/apollolake/acpi/gpio.asl b/src/soc/intel/apollolake/acpi/gpio.asl index 4bf0442..47edd94 100644 --- a/src/soc/intel/apollolake/acpi/gpio.asl +++ b/src/soc/intel/apollolake/acpi/gpio.asl @@ -142,3 +142,9 @@ scope (\_SB) { } } } + +Scope(\_GPE) +{ + /* Dummy method for the Tier 1 GPIO SCI enable bit */ + Method(_L0F, 0) {} +}

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New patch to review for coreboot: Documentation: Add doxygen_platform target
by Martin Roth 07 Jul '16

07 Jul '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15577 -gerrit commit 62714d7be16e5c0e1354f93a4135a4cdf85c7392 Author: Martin Roth <martinroth(a)google.com> Date: Thu Jul 7 15:50:28 2016 -0600 Documentation: Add doxygen_platform target Create a doxygen target that builds documentation just for the platform that is currently selected in Kconfig. This gives us something that is much more useful to most people. Change-Id: I25c3cdac2dd383b89df6389ba9011dac913a0a9b Signed-off-by: Martin Roth <martinroth(a)google.com> --- Documentation/doxygen/Doxyfile.coreboot_platform | 319 +++++++++++++++++++++++ Makefile | 10 + 2 files changed, 329 insertions(+) diff --git a/Documentation/doxygen/Doxyfile.coreboot_platform b/Documentation/doxygen/Doxyfile.coreboot_platform new file mode 100644 index 0000000..a7770bb --- /dev/null +++ b/Documentation/doxygen/Doxyfile.coreboot_platform @@ -0,0 +1,319 @@ +# Doxyfile 1.8.11 + +#--------------------------------------------------------------------------- +# Project related configuration options +#--------------------------------------------------------------------------- +DOXYFILE_ENCODING = UTF-8 +PROJECT_NAME = "coreboot for $(DOXYGEN_PLATFORM)" +PROJECT_NUMBER = +PROJECT_BRIEF = "coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers." +PROJECT_LOGO = Documentation/coreboot_logo.png +OUTPUT_DIRECTORY = $(DOXYGEN_OUTPUT_DIR) +CREATE_SUBDIRS = YES +ALLOW_UNICODE_NAMES = NO +OUTPUT_LANGUAGE = English +BRIEF_MEMBER_DESC = YES +REPEAT_BRIEF = YES +ABBREVIATE_BRIEF = +ALWAYS_DETAILED_SEC = YES +INLINE_INHERITED_MEMB = NO +FULL_PATH_NAMES = YES +STRIP_FROM_PATH = +STRIP_FROM_INC_PATH = +SHORT_NAMES = NO +JAVADOC_AUTOBRIEF = YES +QT_AUTOBRIEF = NO +MULTILINE_CPP_IS_BRIEF = NO +INHERIT_DOCS = YES +SEPARATE_MEMBER_PAGES = NO +TAB_SIZE = 8 +ALIASES = +TCL_SUBST = +OPTIMIZE_OUTPUT_FOR_C = YES +OPTIMIZE_OUTPUT_JAVA = NO +OPTIMIZE_FOR_FORTRAN = NO +OPTIMIZE_OUTPUT_VHDL = NO +EXTENSION_MAPPING = +MARKDOWN_SUPPORT = YES +AUTOLINK_SUPPORT = YES +BUILTIN_STL_SUPPORT = NO +CPP_CLI_SUPPORT = NO +SIP_SUPPORT = NO +IDL_PROPERTY_SUPPORT = YES +DISTRIBUTE_GROUP_DOC = NO +GROUP_NESTED_COMPOUNDS = NO +SUBGROUPING = YES +INLINE_GROUPED_CLASSES = NO +INLINE_SIMPLE_STRUCTS = NO +TYPEDEF_HIDES_STRUCT = NO +LOOKUP_CACHE_SIZE = 0 +#--------------------------------------------------------------------------- +# Build related configuration options +#--------------------------------------------------------------------------- +EXTRACT_ALL = YES +EXTRACT_PRIVATE = NO +EXTRACT_PACKAGE = NO +EXTRACT_STATIC = YES +EXTRACT_LOCAL_CLASSES = YES +EXTRACT_LOCAL_METHODS = NO +EXTRACT_ANON_NSPACES = NO +HIDE_UNDOC_MEMBERS = NO +HIDE_UNDOC_CLASSES = NO +HIDE_FRIEND_COMPOUNDS = NO +HIDE_IN_BODY_DOCS = NO +INTERNAL_DOCS = NO +CASE_SENSE_NAMES = YES +HIDE_SCOPE_NAMES = NO +HIDE_COMPOUND_REFERENCE= NO +SHOW_INCLUDE_FILES = YES +SHOW_GROUPED_MEMB_INC = NO +FORCE_LOCAL_INCLUDES = NO +INLINE_INFO = YES +SORT_MEMBER_DOCS = YES +SORT_BRIEF_DOCS = NO +SORT_MEMBERS_CTORS_1ST = NO +SORT_GROUP_NAMES = NO +SORT_BY_SCOPE_NAME = NO +STRICT_PROTO_MATCHING = NO +GENERATE_TODOLIST = YES +GENERATE_TESTLIST = YES +GENERATE_BUGLIST = YES +GENERATE_DEPRECATEDLIST= YES +ENABLED_SECTIONS = +MAX_INITIALIZER_LINES = 30 +SHOW_USED_FILES = YES +SHOW_FILES = YES +SHOW_NAMESPACES = YES +FILE_VERSION_FILTER = +LAYOUT_FILE = +CITE_BIB_FILES = +#--------------------------------------------------------------------------- +# Configuration options related to warning and progress messages +#--------------------------------------------------------------------------- +QUIET = YES +WARNINGS = YES +WARN_IF_UNDOCUMENTED = YES +WARN_IF_DOC_ERROR = YES +WARN_NO_PARAMDOC = YES +WARN_AS_ERROR = NO +WARN_FORMAT = "$file:$line: $text" +WARN_LOGFILE = +#--------------------------------------------------------------------------- +# Configuration options related to the input files +#--------------------------------------------------------------------------- +INPUT = $(DOXYFILES) +INPUT_ENCODING = UTF-8 +FILE_PATTERNS = +RECURSIVE = NO +EXCLUDE = +EXCLUDE_SYMLINKS = NO +EXCLUDE_PATTERNS = +EXCLUDE_SYMBOLS = +EXAMPLE_PATH = +EXAMPLE_PATTERNS = +EXAMPLE_RECURSIVE = NO +IMAGE_PATH = +INPUT_FILTER = +FILTER_PATTERNS = +FILTER_SOURCE_FILES = NO +FILTER_SOURCE_PATTERNS = +USE_MDFILE_AS_MAINPAGE = +#--------------------------------------------------------------------------- +# Configuration options related to source browsing +#--------------------------------------------------------------------------- +SOURCE_BROWSER = YES +INLINE_SOURCES = NO +STRIP_CODE_COMMENTS = NO +REFERENCED_BY_RELATION = YES +REFERENCES_RELATION = YES +REFERENCES_LINK_SOURCE = YES +SOURCE_TOOLTIPS = YES +USE_HTAGS = NO +VERBATIM_HEADERS = YES +CLANG_ASSISTED_PARSING = NO +CLANG_OPTIONS = +#--------------------------------------------------------------------------- +# Configuration options related to the alphabetical class index +#--------------------------------------------------------------------------- +ALPHABETICAL_INDEX = YES +COLS_IN_ALPHA_INDEX = 5 +IGNORE_PREFIX = +#--------------------------------------------------------------------------- +# Configuration options related to the HTML output +#--------------------------------------------------------------------------- +GENERATE_HTML = YES +HTML_OUTPUT = html +HTML_FILE_EXTENSION = .html +HTML_HEADER = +HTML_FOOTER = +HTML_STYLESHEET = +HTML_EXTRA_STYLESHEET = +HTML_EXTRA_FILES = +HTML_COLORSTYLE_HUE = 220 +HTML_COLORSTYLE_SAT = 100 +HTML_COLORSTYLE_GAMMA = 80 +HTML_TIMESTAMP = NO +HTML_DYNAMIC_SECTIONS = NO +HTML_INDEX_NUM_ENTRIES = 100 +GENERATE_DOCSET = NO +DOCSET_FEEDNAME = "Doxygen documentation" +DOCSET_BUNDLE_ID = org.doxygen.Project +DOCSET_PUBLISHER_ID = org.doxygen.Publisher +DOCSET_PUBLISHER_NAME = Publisher +GENERATE_HTMLHELP = NO +CHM_FILE = +HHC_LOCATION = +GENERATE_CHI = NO +CHM_INDEX_ENCODING = +BINARY_TOC = NO +TOC_EXPAND = NO +GENERATE_QHP = NO +QCH_FILE = +QHP_NAMESPACE = org.doxygen.Project +QHP_VIRTUAL_FOLDER = doc +QHP_CUST_FILTER_NAME = +QHP_CUST_FILTER_ATTRS = +QHP_SECT_FILTER_ATTRS = +QHG_LOCATION = +GENERATE_ECLIPSEHELP = NO +ECLIPSE_DOC_ID = org.doxygen.Project +DISABLE_INDEX = NO +GENERATE_TREEVIEW = YES +ENUM_VALUES_PER_LINE = 4 +TREEVIEW_WIDTH = 250 +EXT_LINKS_IN_WINDOW = NO +FORMULA_FONTSIZE = 10 +FORMULA_TRANSPARENT = YES +USE_MATHJAX = NO +MATHJAX_FORMAT = HTML-CSS +MATHJAX_RELPATH = http://cdn.mathjax.org/mathjax/latest +MATHJAX_EXTENSIONS = +MATHJAX_CODEFILE = +SEARCHENGINE = YES +SERVER_BASED_SEARCH = NO +EXTERNAL_SEARCH = NO +SEARCHENGINE_URL = +SEARCHDATA_FILE = searchdata.xml +EXTERNAL_SEARCH_ID = +EXTRA_SEARCH_MAPPINGS = +#--------------------------------------------------------------------------- +# Configuration options related to the LaTeX output +#--------------------------------------------------------------------------- +GENERATE_LATEX = NO +LATEX_OUTPUT = latex +LATEX_CMD_NAME = latex +MAKEINDEX_CMD_NAME = makeindex +COMPACT_LATEX = NO +PAPER_TYPE = a4wide +EXTRA_PACKAGES = +LATEX_HEADER = +LATEX_FOOTER = +LATEX_EXTRA_STYLESHEET = +LATEX_EXTRA_FILES = +PDF_HYPERLINKS = NO +USE_PDFLATEX = NO +LATEX_BATCHMODE = NO +LATEX_HIDE_INDICES = NO +LATEX_SOURCE_CODE = NO +LATEX_BIB_STYLE = plain +LATEX_TIMESTAMP = NO +#--------------------------------------------------------------------------- +# Configuration options related to the RTF output +#--------------------------------------------------------------------------- +GENERATE_RTF = NO +RTF_OUTPUT = rtf +COMPACT_RTF = NO +RTF_HYPERLINKS = NO +RTF_STYLESHEET_FILE = +RTF_EXTENSIONS_FILE = +RTF_SOURCE_CODE = NO +#--------------------------------------------------------------------------- +# Configuration options related to the man page output +#--------------------------------------------------------------------------- +GENERATE_MAN = NO +MAN_OUTPUT = man +MAN_EXTENSION = .3 +MAN_SUBDIR = +MAN_LINKS = NO +#--------------------------------------------------------------------------- +# Configuration options related to the XML output +#--------------------------------------------------------------------------- +GENERATE_XML = NO +XML_OUTPUT = xml +XML_PROGRAMLISTING = YES +#--------------------------------------------------------------------------- +# Configuration options related to the DOCBOOK output +#--------------------------------------------------------------------------- +GENERATE_DOCBOOK = NO +DOCBOOK_OUTPUT = docbook +DOCBOOK_PROGRAMLISTING = NO +#--------------------------------------------------------------------------- +# Configuration options for the AutoGen Definitions output +#--------------------------------------------------------------------------- +GENERATE_AUTOGEN_DEF = NO +#--------------------------------------------------------------------------- +# Configuration options related to the Perl module output +#--------------------------------------------------------------------------- +GENERATE_PERLMOD = NO +PERLMOD_LATEX = NO +PERLMOD_PRETTY = YES +PERLMOD_MAKEVAR_PREFIX = +#--------------------------------------------------------------------------- +# Configuration options related to the preprocessor +#--------------------------------------------------------------------------- +ENABLE_PREPROCESSING = YES +MACRO_EXPANSION = YES +EXPAND_ONLY_PREDEF = YES +SEARCH_INCLUDES = YES +INCLUDE_PATH = +INCLUDE_FILE_PATTERNS = +PREDEFINED = __attribute__(x)= +EXPAND_AS_DEFINED = +SKIP_FUNCTION_MACROS = YES +#--------------------------------------------------------------------------- +# Configuration options related to external references +#--------------------------------------------------------------------------- +TAGFILES = +GENERATE_TAGFILE = +ALLEXTERNALS = NO +EXTERNAL_GROUPS = YES +EXTERNAL_PAGES = YES +PERL_PATH = /usr/bin/perl +#--------------------------------------------------------------------------- +# Configuration options related to the dot tool +#--------------------------------------------------------------------------- +CLASS_DIAGRAMS = YES +MSCGEN_PATH = +DIA_PATH = +HIDE_UNDOC_RELATIONS = NO +HAVE_DOT = NO +DOT_NUM_THREADS = 0 +DOT_FONTNAME = Helvetica +DOT_FONTSIZE = 10 +DOT_FONTPATH = +CLASS_GRAPH = YES +COLLABORATION_GRAPH = YES +GROUP_GRAPHS = YES +UML_LOOK = YES +UML_LIMIT_NUM_FIELDS = 10 +TEMPLATE_RELATIONS = NO +INCLUDE_GRAPH = YES +INCLUDED_BY_GRAPH = YES +CALL_GRAPH = YES +CALLER_GRAPH = YES +GRAPHICAL_HIERARCHY = YES +DIRECTORY_GRAPH = YES +DOT_IMAGE_FORMAT = png +INTERACTIVE_SVG = NO +DOT_PATH = +DOTFILE_DIRS = +MSCFILE_DIRS = +DIAFILE_DIRS = +PLANTUML_JAR_PATH = +PLANTUML_INCLUDE_PATH = +DOT_GRAPH_MAX_NODES = 50 +MAX_DOT_GRAPH_DEPTH = 0 +DOT_TRANSPARENT = NO +DOT_MULTI_TARGETS = YES +GENERATE_LEGEND = YES +DOT_CLEANUP = YES diff --git a/Makefile b/Makefile index c502d2c..dcdd212 100644 --- a/Makefile +++ b/Makefile @@ -101,6 +101,7 @@ help_coreboot help:: @echo ' clean - Remove coreboot build artifacts' @echo ' distclean - Remove build artifacts and config files' @echo ' doxygen - Build doxygen documentation for coreboot' + @echo ' doxyplatform - Build doxygen documentation for the current platform' @echo ' what-jenkins-does - Run platform build tests (Use CPUS=# for more cores)' @echo ' printall - print makefile info for debugging' @echo ' lint / lint-stable - run coreboot lint tools (all / minimal)' @@ -305,6 +306,15 @@ doxygen: doxygen_simple: $(DOXYGEN) Documentation/Doxyfile.coreboot_simple +doxyplatform doxygen_platform: $(obj)/project_filelist.txt + echo + echo "Building doxygen documentation for $(CONFIG_MAINBOARD_PART_NUMBER)" + export DOXYGEN_OUTPUT_DIR="$(DOXYGEN_OUTPUT_DIR)/$(CONFIG_MAINBOARD_VENDOR)/$(CONFIG_MAINBOARD_PART_NUMBER)"; \ + mkdir -p "$$DOXYGEN_OUTPUT_DIR"; \ + export DOXYFILES="$$(cat $(obj)/project_filelist.txt | grep -v '\.ld$$' | sed 's/\.aml/\.dsl/' | tr '\n' ' ')"; \ + export DOXYGEN_PLATFORM="$(CONFIG_MAINBOARD_DIR) ($(CONFIG_MAINBOARD_PART_NUMBER)) version $(KERNELVERSION)"; \ + $(DOXYGEN) Documentation/doxygen/Doxyfile.coreboot_platform + doxyclean: doxygen-clean doxygen-clean: rm -rf $(DOXYGEN_OUTPUT_DIR)

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Patch set updated for coreboot: google/reef: Add GPE routing settings
by Shaunak Saha 07 Jul '16

07 Jul '16

Shaunak Saha (shaunak.saha(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15556 -gerrit commit f4a7ab1a741e56b357de6b20c43e96a7a62bce17 Author: Shaunak Saha <shaunak.saha(a)intel.com> Date: Wed Jul 6 15:50:48 2016 -0700 google/reef: Add GPE routing settings This patch sets the devicetree for gpe0_dw configuration and also confgigures the GPIO lines for SCI.EC_SCI_GPI is configured to proper value. BUG = chrome-os-partner:53438 TEST = Toggle pch_sci_l from ec console using gpioset command and see that the sci counter increases in /sys/firmware/acpi/interrupt and also 9 in /proc/interrupt Change-Id: If258bece12768edb1e612c982514ce95c756c438 Signed-off-by: Shaunak Saha <shaunak.saha(a)intel.com> --- src/mainboard/google/reef/devicetree.cb | 9 +++++++++ src/mainboard/google/reef/ec.h | 8 +++++--- src/mainboard/google/reef/gpio.h | 2 +- 3 files changed, 15 insertions(+), 4 deletions(-) diff --git a/src/mainboard/google/reef/devicetree.cb b/src/mainboard/google/reef/devicetree.cb index e0831f4..7f6d189 100644 --- a/src/mainboard/google/reef/devicetree.cb +++ b/src/mainboard/google/reef/devicetree.cb @@ -36,6 +36,15 @@ chip soc/intel/apollolake # 0x1C[6:0] stands for 28*125 = 3500 pSec delay for HS200 register "emmc_rx_cmd_data_cntl2" = "0x1001C" + # GPE configuration + # Note that GPE events called out in ASL code rely on this + # route, i.e., If this route changes then the affected GPE + # offset bits also needs to be changed. This sets the PMC register + # GPE_CFG fields. + register "gpe0_dw1" = "PMC_GPE_N_31_0" + register "gpe0_dw2" = "PMC_GPE_N_63_32" + register "gpe0_dw3" = "PMC_GPE_SW_31_0" + device domain 0 on device pci 00.0 on end # - Host Bridge device pci 00.1 on end # - DPTF diff --git a/src/mainboard/google/reef/ec.h b/src/mainboard/google/reef/ec.h index 5a32697..3619c04 100644 --- a/src/mainboard/google/reef/ec.h +++ b/src/mainboard/google/reef/ec.h @@ -18,9 +18,11 @@ #include <ec/google/chromeec/ec_commands.h> -/* This is the GPE status bit. - TODO: Fix this to proper bit matching GPE routing table */ -#define EC_SCI_GPI 15 +/* + * GPIO_11 for SCI is routed to GPE0_DW1 and maps to group GPIO_GPE_N_31_0 + * which is North community + */ +#define EC_SCI_GPI GPE0_DW1_11 #define MAINBOARD_EC_SCI_EVENTS \ (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED) |\ diff --git a/src/mainboard/google/reef/gpio.h b/src/mainboard/google/reef/gpio.h index 91e8bb1..eddefeb 100644 --- a/src/mainboard/google/reef/gpio.h +++ b/src/mainboard/google/reef/gpio.h @@ -283,7 +283,7 @@ static const struct pad_config gpio_table[] = { PAD_CFG_GPI_APIC(GPIO_9, NONE, DEEP, LEVEL, NONE), /* dTPM IRQ */ PAD_CFG_GPI(GPIO_10, UP_20K, DEEP), /* unused */ - PAD_CFG_GPI_SCI(GPIO_11, NONE, DEEP, LEVEL, NONE), /* EC SCI */ + PAD_CFG_GPI_SCI(GPIO_11, NONE, DEEP, EDGE_SINGLE, INVERT), /* EC SCI */ PAD_CFG_GPI(GPIO_12, UP_20K, DEEP), /* unused */ PAD_CFG_GPI(GPIO_13, UP_20K, DEEP), /* unused */ PAD_CFG_GPI_APIC(GPIO_14, UP_20K, DEEP, LEVEL, NONE), /* FP IRQ */

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Patch set updated for coreboot: google/reef: GPE routing settings for reef board
by Shaunak Saha 07 Jul '16

07 Jul '16

Shaunak Saha (shaunak.saha(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15556 -gerrit commit 2b417c0eea424662d37b059cbe0d4113be1ba6e6 Author: Shaunak Saha <shaunak.saha(a)intel.com> Date: Wed Jul 6 15:50:48 2016 -0700 google/reef: GPE routing settings for reef board This patch sets the devicetree for gpe0_dw configuration and also confgigures the GPIO lines for SCI.EC_SCI_GPI is configured to proper value. BUG = chrome-os-partner:53438 TEST = Toggle pch_sci_l from ec console using gpioset command and see that the sci counter increases in /sys/firmware/acpi/interrupt and also 9 in /proc/interrupt Change-Id: If258bece12768edb1e612c982514ce95c756c438 Signed-off-by: Shaunak Saha <shaunak.saha(a)intel.com> --- src/mainboard/google/reef/devicetree.cb | 9 +++++++++ src/mainboard/google/reef/ec.h | 8 +++++--- src/mainboard/google/reef/gpio.h | 2 +- 3 files changed, 15 insertions(+), 4 deletions(-) diff --git a/src/mainboard/google/reef/devicetree.cb b/src/mainboard/google/reef/devicetree.cb index e0831f4..7f6d189 100644 --- a/src/mainboard/google/reef/devicetree.cb +++ b/src/mainboard/google/reef/devicetree.cb @@ -36,6 +36,15 @@ chip soc/intel/apollolake # 0x1C[6:0] stands for 28*125 = 3500 pSec delay for HS200 register "emmc_rx_cmd_data_cntl2" = "0x1001C" + # GPE configuration + # Note that GPE events called out in ASL code rely on this + # route, i.e., If this route changes then the affected GPE + # offset bits also needs to be changed. This sets the PMC register + # GPE_CFG fields. + register "gpe0_dw1" = "PMC_GPE_N_31_0" + register "gpe0_dw2" = "PMC_GPE_N_63_32" + register "gpe0_dw3" = "PMC_GPE_SW_31_0" + device domain 0 on device pci 00.0 on end # - Host Bridge device pci 00.1 on end # - DPTF diff --git a/src/mainboard/google/reef/ec.h b/src/mainboard/google/reef/ec.h index 5a32697..3619c04 100644 --- a/src/mainboard/google/reef/ec.h +++ b/src/mainboard/google/reef/ec.h @@ -18,9 +18,11 @@ #include <ec/google/chromeec/ec_commands.h> -/* This is the GPE status bit. - TODO: Fix this to proper bit matching GPE routing table */ -#define EC_SCI_GPI 15 +/* + * GPIO_11 for SCI is routed to GPE0_DW1 and maps to group GPIO_GPE_N_31_0 + * which is North community + */ +#define EC_SCI_GPI GPE0_DW1_11 #define MAINBOARD_EC_SCI_EVENTS \ (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED) |\ diff --git a/src/mainboard/google/reef/gpio.h b/src/mainboard/google/reef/gpio.h index 91e8bb1..eddefeb 100644 --- a/src/mainboard/google/reef/gpio.h +++ b/src/mainboard/google/reef/gpio.h @@ -283,7 +283,7 @@ static const struct pad_config gpio_table[] = { PAD_CFG_GPI_APIC(GPIO_9, NONE, DEEP, LEVEL, NONE), /* dTPM IRQ */ PAD_CFG_GPI(GPIO_10, UP_20K, DEEP), /* unused */ - PAD_CFG_GPI_SCI(GPIO_11, NONE, DEEP, LEVEL, NONE), /* EC SCI */ + PAD_CFG_GPI_SCI(GPIO_11, NONE, DEEP, EDGE_SINGLE, INVERT), /* EC SCI */ PAD_CFG_GPI(GPIO_12, UP_20K, DEEP), /* unused */ PAD_CFG_GPI(GPIO_13, UP_20K, DEEP), /* unused */ PAD_CFG_GPI_APIC(GPIO_14, UP_20K, DEEP, LEVEL, NONE), /* FP IRQ */

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New patch to review for coreboot: FSP1_0 does not support HAVE_ACPI_RESUME
by Kyösti Mälkki 07 Jul '16

07 Jul '16

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15576 -gerrit commit 4b57582f124a4aa1c84562a78f9b5c963e3b18ac Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Jul 5 09:41:59 2016 +0300 FSP1_0 does not support HAVE_ACPI_RESUME There is no possibility of making low-memory backup with FSP1_0 so S3 resume would cause OS memory corruption. Change-Id: I5b9dd4069082e022b01b0d6a9ad5dec28a06e8b0 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/mainboard/esd/atom15/Kconfig | 1 - src/mainboard/intel/minnowmax/Kconfig | 1 - 2 files changed, 2 deletions(-) diff --git a/src/mainboard/esd/atom15/Kconfig b/src/mainboard/esd/atom15/Kconfig index 3f4b76b..814177e 100644 --- a/src/mainboard/esd/atom15/Kconfig +++ b/src/mainboard/esd/atom15/Kconfig @@ -23,7 +23,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE select TSC_MONOTONIC_TIMER - select HAVE_ACPI_RESUME config MAINBOARD_DIR string diff --git a/src/mainboard/intel/minnowmax/Kconfig b/src/mainboard/intel/minnowmax/Kconfig index 2f23270..f0c4526 100644 --- a/src/mainboard/intel/minnowmax/Kconfig +++ b/src/mainboard/intel/minnowmax/Kconfig @@ -23,7 +23,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE select TSC_MONOTONIC_TIMER - select HAVE_ACPI_RESUME config MAINBOARD_DIR string

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New patch to review for coreboot: AMD binaryPI: Use common romstage ram stack
by Kyösti Mälkki 07 Jul '16

07 Jul '16

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15575 -gerrit commit d875c818a8fc24061d2f7a34092d45aa7936d4c3 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sat Jun 18 17:55:08 2016 +0300 AMD binaryPI: Use common romstage ram stack Note that no binaryPI board has HAVE_ACPI_RESUME. Change-Id: I52d0bd7dac86822242400f68f6dc202f02d6e0f1 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/cpu/amd/pi/s3_resume.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/src/cpu/amd/pi/s3_resume.c b/src/cpu/amd/pi/s3_resume.c index 830d174..6426c97 100644 --- a/src/cpu/amd/pi/s3_resume.c +++ b/src/cpu/amd/pi/s3_resume.c @@ -25,6 +25,7 @@ #include <device/device.h> #include <arch/io.h> #include <arch/acpi.h> +#include <program_loading.h> #include <string.h> #include "Porting.h" #include <northbridge/amd/pi/BiosCallOuts.h> @@ -137,12 +138,13 @@ void restore_mtrr(void) #ifdef __PRE_RAM__ static void move_stack_high_mem(void) { - void *high_stack = cbmem_find(CBMEM_ID_ROMSTAGE_RAM_STACK); - if (high_stack == NULL) + uintptr_t high_stack = romstage_ram_stack_base(HIGH_ROMSTAGE_STACK_SIZE, + ROMSTAGE_STACK_CBMEM); + if (!high_stack) halt(); /* TODO: Make the switch with empty stack instead. */ - memcpy(high_stack, (void *)BSP_STACK_BASE_ADDR, HIGH_ROMSTAGE_STACK_SIZE); + memcpy((void*)high_stack, (void *)BSP_STACK_BASE_ADDR, HIGH_ROMSTAGE_STACK_SIZE); #ifdef __x86_64__ __asm__

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Patch set updated for coreboot: intel/sandybridge: Use common ACPI S3 recovery
by Kyösti Mälkki 07 Jul '16

07 Jul '16

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15248 -gerrit commit eb13bfc10188faba93bd3d48063e55e87234e666 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Fri Jun 17 22:54:22 2016 +0300 intel/sandybridge: Use common ACPI S3 recovery There is some 20ms delay with ACPI S3 wakeup time due to MTRR setup being done after the backup copy. Change-Id: Ib72ff914f5dfef8611f5f6cf9687495779013b02 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/cpu/intel/model_206ax/cache_as_ram.inc | 21 --------------------- src/northbridge/intel/sandybridge/early_init.c | 10 ++-------- src/northbridge/intel/sandybridge/sandybridge.h | 6 ------ 3 files changed, 2 insertions(+), 35 deletions(-) diff --git a/src/cpu/intel/model_206ax/cache_as_ram.inc b/src/cpu/intel/model_206ax/cache_as_ram.inc index a1f5cc9..e31d42a 100644 --- a/src/cpu/intel/model_206ax/cache_as_ram.inc +++ b/src/cpu/intel/model_206ax/cache_as_ram.inc @@ -281,27 +281,6 @@ before_romstage: /* Invalidate the cache again. */ invd - post_code(0x3c) - -#if CONFIG_HAVE_ACPI_RESUME - movl CBMEM_BOOT_MODE, %eax - cmpl $0x2, %eax // Resume? - jne __acpi_resume_backup_done - - /* copy 1MB - 64K to high tables ram_base to prevent memory corruption - * through stage 2. We could keep stuff like stack and heap in high - * tables memory completely, but that's a wonderful clean up task for - * another day. - */ - cld - movl $CONFIG_RAMBASE, %esi - movl CBMEM_RESUME_BACKUP, %edi - movl $HIGH_MEMORY_SAVE >> 2, %ecx - rep movsl - -__acpi_resume_backup_done: -#endif - post_code(0x3d) __main: diff --git a/src/northbridge/intel/sandybridge/early_init.c b/src/northbridge/intel/sandybridge/early_init.c index 779f29b..a013ec3 100644 --- a/src/northbridge/intel/sandybridge/early_init.c +++ b/src/northbridge/intel/sandybridge/early_init.c @@ -233,15 +233,9 @@ void northbridge_romstage_finalize(int s3resume) * this is not a resume. In that case we just create the cbmem toc. */ - *(u32 *)CBMEM_BOOT_MODE = 0; - *(u32 *)CBMEM_RESUME_BACKUP = 0; - if (s3resume) { - void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME); - if (resume_backup_memory) { - *(u32 *)CBMEM_BOOT_MODE = 2; - *(u32 *)CBMEM_RESUME_BACKUP = (u32)resume_backup_memory; - } + acpi_prepare_for_resume(); + /* Magic for S3 resume */ pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafed00d); } else { diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h index 7b0efd1..af5bd48 100644 --- a/src/northbridge/intel/sandybridge/sandybridge.h +++ b/src/northbridge/intel/sandybridge/sandybridge.h @@ -196,12 +196,6 @@ #define DMIDRCCFG 0xeb4 /* 32bit */ -/* Delegation of resume backup memory so we don't have to - * (slowly) handle backing up OS memory in romstage.c - */ -#define CBMEM_BOOT_MODE 0x610 -#define CBMEM_RESUME_BACKUP 0x614 - #ifndef __ASSEMBLER__ static inline void barrier(void) { asm("" ::: "memory"); }

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Patch set updated for coreboot: AMD binaryPI: Use common ACPI S3 recovery
by Kyösti Mälkki 07 Jul '16

07 Jul '16

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15254 -gerrit commit 2740b1f8a90346bb99880f09769e185470780572 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sat Jun 18 17:55:08 2016 +0300 AMD binaryPI: Use common ACPI S3 recovery Note that no binaryPI board has HAVE_ACPI_RESUME. Change-Id: Ic7d87aa81c75374dd1570cef412a3ca245285d58 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/cpu/amd/pi/s3_resume.c | 31 ++++++------------------------- 1 file changed, 6 insertions(+), 25 deletions(-) diff --git a/src/cpu/amd/pi/s3_resume.c b/src/cpu/amd/pi/s3_resume.c index b6d3633..576a208 100644 --- a/src/cpu/amd/pi/s3_resume.c +++ b/src/cpu/amd/pi/s3_resume.c @@ -28,6 +28,7 @@ #include <string.h> #include "Porting.h" #include <northbridge/amd/pi/BiosCallOuts.h> +#include <halt.h> #include "s3_resume.h" /* The size needs to be 4k aligned, which is the sector size of most flashes. */ @@ -134,24 +135,6 @@ void restore_mtrr(void) } #ifdef __PRE_RAM__ -static void *backup_resume(void) -{ - void *resume_backup_memory; - - if (cbmem_recovery(1)) - return NULL; - - resume_backup_memory = cbmem_find(CBMEM_ID_RESUME); - if (((u32) resume_backup_memory == 0) - || ((u32) resume_backup_memory == -1)) { - printk(BIOS_ERR, "Error: resume_backup_memory: %x\n", - (u32) resume_backup_memory); - for (;;) ; - } - - return resume_backup_memory; -} - static void move_stack_high_mem(void) { void *high_stack; @@ -289,13 +272,14 @@ static void set_resume_cache(void) void prepare_for_resume(void) { - printk(BIOS_DEBUG, "Find resume memory location\n"); - void *resume_backup_memory = backup_resume(); + if (cbmem_recovery(1)) { + printk(BIOS_EMERG, "Unable to recover CBMEM\n"); + halt(); + } post_code(0x62); printk(BIOS_DEBUG, "Move CAR stack.\n"); move_stack_high_mem(); - printk(BIOS_DEBUG, "stack moved to: 0x%x\n", (u32) (resume_backup_memory + HIGH_MEMORY_SAVE)); post_code(0x63); disable_cache_as_ram(); @@ -306,9 +290,6 @@ void prepare_for_resume(void) * Copy the system memory that is in the ramstage area to the * reserved area. */ - if (resume_backup_memory) - memcpy(resume_backup_memory, (void *)(CONFIG_RAMBASE), HIGH_MEMORY_SAVE); - - printk(BIOS_DEBUG, "System memory saved. OK to load ramstage.\n"); + acpi_prepare_for_resume(); } #endif

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coreboot-gerrit July 2016