coreboot-gerrit July 2016

coreboot-gerrit@coreboot.org

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New patch to review for coreboot: gru: include ram_code in coreboot table
by Martin Roth 07 Jul '16

07 Jul '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15566 -gerrit commit 8779acee43915761a1778e13963a2fd8349a7b2b Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Tue Jun 21 19:07:32 2016 -0700 gru: include ram_code in coreboot table This is needed to ensure that the ram-code node is included in the device tree by depthcharge. BRANCH=none BUG=chrome-os-partner:54566 TEST=built updated firmware, booted on kevin into Linux shell, checked the device tree contents: localhost ~ # od -tx1 /proc/device-tree/firmware/coreboot/ram-code 0000000 00 00 00 01 0000004 localhost # Change-Id: Ibe96e3bc8fc0106013241738f5726783d74bd78b Signed-off-by: Martin Roth <martinroth(a)chromium.org> Original-Commit-Id: 53c002114f7044b88728c9e17150cd3a2cf1f80f Original-Change-Id: Iba573fba9f9b88b87867c6963e48215e254319ed Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/354705 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/mainboard/google/gru/Kconfig | 1 + src/mainboard/google/gru/Makefile.inc | 1 + src/mainboard/google/gru/boardid.c | 5 ----- src/mainboard/google/gru/sdram_configs.c | 22 ++++++++++++++++------ 4 files changed, 18 insertions(+), 11 deletions(-) diff --git a/src/mainboard/google/gru/Kconfig b/src/mainboard/google/gru/Kconfig index 170e358..1b42059 100644 --- a/src/mainboard/google/gru/Kconfig +++ b/src/mainboard/google/gru/Kconfig @@ -30,6 +30,7 @@ config BOARD_SPECIFIC_OPTIONS select MAINBOARD_DO_NATIVE_VGA_INIT select MAINBOARD_HAS_CHROMEOS select MAINBOARD_HAS_NATIVE_VGA_INIT + select RAM_CODE_SUPPORT select RTC select SOC_ROCKCHIP_RK3399 select SPI_FLASH diff --git a/src/mainboard/google/gru/Makefile.inc b/src/mainboard/google/gru/Makefile.inc index a209d1b..9e87fad 100644 --- a/src/mainboard/google/gru/Makefile.inc +++ b/src/mainboard/google/gru/Makefile.inc @@ -33,3 +33,4 @@ ramstage-y += chromeos.c ramstage-y += mainboard.c ramstage-y += memlayout.ld ramstage-y += reset.c +ramstage-y += sdram_configs.c # Needed for ram_code() diff --git a/src/mainboard/google/gru/boardid.c b/src/mainboard/google/gru/boardid.c index 1d37a86..b0c1eaf 100644 --- a/src/mainboard/google/gru/boardid.c +++ b/src/mainboard/google/gru/boardid.c @@ -59,8 +59,3 @@ uint8_t board_id(void) adc_reading); return 0; } - -uint32_t ram_code(void) -{ - return 0; -} diff --git a/src/mainboard/google/gru/sdram_configs.c b/src/mainboard/google/gru/sdram_configs.c index 92e00ef..f1f889c 100644 --- a/src/mainboard/google/gru/sdram_configs.c +++ b/src/mainboard/google/gru/sdram_configs.c @@ -38,19 +38,29 @@ enum dram_speeds { /* dram_928MHz = 4, */ }; -const struct rk3399_sdram_params *get_sdram_config() +static enum dram_speeds get_sdram_index(void) { - enum dram_speeds speed; - if (IS_ENABLED(CONFIG_BOARD_GOOGLE_KEVIN)) - speed = dram_300MHz; + return dram_300MHz; else if (IS_ENABLED(CONFIG_BOARD_GOOGLE_GRU)) - speed = dram_800MHz; + return dram_800MHz; else - speed = dram_200MHz; + return dram_200MHz; +} + +const struct rk3399_sdram_params *get_sdram_config() +{ + + enum dram_speeds speed = get_sdram_index(); printk(BIOS_INFO, "Using SDRAM configuration for %d MHz\n", sdram_configs[speed].ddr_freq / (1000 * 1000)); return &sdram_configs[speed]; } + + +uint32_t ram_code(void) +{ + return get_sdram_index(); +}

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Patch set updated for coreboot: Add support for F2950 single-board computer
by Andrey Korolyov 07 Jul '16

07 Jul '16

Andrey Korolyov (andrey(a)xdel.ru) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15565 -gerrit commit a1b3519d35a1ecb31fbfadd94a6b70d602e23554 Author: Andrey Korolyov <andrey(a)xdel.ru> Date: Fri Jul 1 20:06:37 2016 +0300 Add support for F2950 single-board computer This platform, also known as TONK 1201/TONK 1202, was originally produced as a Centerm F2950. Common configuration does include a 600 MHz GeodeLX CPU underclocked to 500 or 400 Mhz, 128 or 512 Mb of RAM in the single SODIMM slot and 128 or 512 IDE DOM. The board does have three USB 2.0 ports, PS/2, VGA, Geode audio controller and the serial port. EEPROM needs to be soldered out and flashed externally at the time of this message because flashrom would neither be able to dump BIOS correctly while running vendor BIOS neither write flash contents. At this moment GeodeVGA does not work out-of-box after initialization by SeaBIOS, thereby preventing selection of the bootable media, Linux lxfb driver works well. Except this, all peripheral components (USB, serial, IDE, PS/2, audio) are working well too. Change-Id: I93f13ecb53bd05abc0e07e0bd7ba40e646dcb4c4 --- src/mainboard/amd/f2950/Kconfig | 27 ++++++++++++ src/mainboard/amd/f2950/Kconfig.name | 2 + src/mainboard/amd/f2950/board_info.txt | 6 +++ src/mainboard/amd/f2950/cmos.layout | 36 +++++++++++++++ src/mainboard/amd/f2950/devicetree.cb | 67 ++++++++++++++++++++++++++++ src/mainboard/amd/f2950/irq_tables.c | 64 +++++++++++++++++++++++++++ src/mainboard/amd/f2950/romstage.c | 80 ++++++++++++++++++++++++++++++++++ 7 files changed, 282 insertions(+) diff --git a/src/mainboard/amd/f2950/Kconfig b/src/mainboard/amd/f2950/Kconfig new file mode 100644 index 0000000..5bfe120 --- /dev/null +++ b/src/mainboard/amd/f2950/Kconfig @@ -0,0 +1,27 @@ +if BOARD_AMD_F2950 + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select CPU_AMD_GEODE_LX + select NORTHBRIDGE_AMD_LX + select SOUTHBRIDGE_AMD_CS5536 + select SUPERIO_WINBOND_W83627HF + select HAVE_PIRQ_TABLE + select PIRQ_ROUTE + select UDELAY_TSC + select BOARD_ROMSIZE_KB_512 + select POWER_BUTTON_FORCE_ENABLE + +config MAINBOARD_DIR + string + default amd/f2950 + +config MAINBOARD_PART_NUMBER + string + default "F2950" + +config IRQ_SLOT_COUNT + int + default 3 + +endif # BOARD_AMD_F2950 diff --git a/src/mainboard/amd/f2950/Kconfig.name b/src/mainboard/amd/f2950/Kconfig.name new file mode 100644 index 0000000..8f6073a --- /dev/null +++ b/src/mainboard/amd/f2950/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_AMD_F2950 + bool "F2950" diff --git a/src/mainboard/amd/f2950/board_info.txt b/src/mainboard/amd/f2950/board_info.txt new file mode 100644 index 0000000..e957623 --- /dev/null +++ b/src/mainboard/amd/f2950/board_info.txt @@ -0,0 +1,6 @@ +Board name: F2950 +Category: mini +ROM package: PLCC +ROM protocol: FWH +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/amd/f2950/cmos.layout b/src/mainboard/amd/f2950/cmos.layout new file mode 100644 index 0000000..6de5ab6 --- /dev/null +++ b/src/mainboard/amd/f2950/cmos.layout @@ -0,0 +1,36 @@ +entries + +0 384 r 0 reserved_memory +384 1 e 4 boot_option +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +456 1 e 1 ECC_memory +1008 16 h 0 check_sum + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew + +checksums + +checksum 392 1007 1008 diff --git a/src/mainboard/amd/f2950/devicetree.cb b/src/mainboard/amd/f2950/devicetree.cb new file mode 100644 index 0000000..4e563d2 --- /dev/null +++ b/src/mainboard/amd/f2950/devicetree.cb @@ -0,0 +1,67 @@ +chip northbridge/amd/lx + device domain 0 on + device pci 1.0 on end # Northbridge + device pci 1.1 on end # Graphics + device pci 1.2 on end # Integrated cryptoaccelerator + chip southbridge/amd/cs5536 + # IRQ 12 and 1 unmasked, Keyboard and Mouse IRQs. OK + # SIRQ Mode = Active(Quiet) mode. Save power.... + # Invert mask = IRQ 12 and 1 are active high. Keyboard and Mouse, UARTs, etc IRQs. OK + register "lpc_serirq_enable" = "0x0000105a" + register "lpc_serirq_polarity" = "0x0000EFA5" + register "lpc_serirq_mode" = "1" + register "enable_gpio_int_route" = "0x0D0C0700" + register "enable_ide_nand_flash" = "0" # 0:ide mode, 1:flash + register "enable_USBP4_device" = "1" # 0: host, 1:device + register "enable_USBP4_overcurrent" = "0" #0:off, xxxx:overcurrent setting CS5536 Data Book (pages 380-381) + register "com1_enable" = "0" + register "com1_address" = "0x3F8" + register "com1_irq" = "4" + register "com2_enable" = "0" + register "com2_address" = "0x2F8" + register "com2_irq" = "3" + register "unwanted_vpci[0]" = "0" # End of list has a zero + device pci d.0 on end # Ethernet + device pci f.0 on # ISA Bridge + chip superio/winbond/w83627hf + device pnp 2e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 off # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.2 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 off end # Com2 + device pnp 2e.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 + end + device pnp 2e.6 off end # CIR + device pnp 2e.7 off end # GAME_MIDI_GIPO1 + device pnp 2e.8 off end # GPIO2 + device pnp 2e.9 off end # GPIO3 + device pnp 2e.a off end # ACPI + device pnp 2e.b off end # HW Monitor + end + end + device pci f.2 on end # IDE Controller + device pci f.3 on end # Audio + device pci f.4 on end # OHCI + device pci f.5 on end # EHCI + end + end + # APIC cluster is late CPU init. + device cpu_cluster 0 on + chip cpu/amd/geode_lx + device lapic 0 on end + end + end +end diff --git a/src/mainboard/amd/f2950/irq_tables.c b/src/mainboard/amd/f2950/irq_tables.c new file mode 100644 index 0000000..b438f02 --- /dev/null +++ b/src/mainboard/amd/f2950/irq_tables.c @@ -0,0 +1,64 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/pirq_routing.h> +#include <console/console.h> +#include <arch/io.h> +#include <arch/pirq_routing.h> +#include "southbridge/amd/cs5536/cs5536.h" + +/* Platform IRQs */ +#define PIRQA 11 +#define PIRQB 5 +#define PIRQC 10 +#define PIRQD 10 + +/* Map */ +#define M_PIRQA (1 << PIRQA) /* Bitmap of supported IRQs */ +#define M_PIRQB (1 << PIRQB) /* Bitmap of supported IRQs */ +#define M_PIRQC (1 << PIRQC) /* Bitmap of supported IRQs */ +#define M_PIRQD (1 << PIRQD) /* Bitmap of supported IRQs */ + +/* Link */ +#define L_PIRQA 1 /* Means Slot INTx# Connects To Chipset INTA# */ +#define L_PIRQB 2 /* Means Slot INTx# Connects To Chipset INTB# */ +#define L_PIRQC 3 /* Means Slot INTx# Connects To Chipset INTC# */ +#define L_PIRQD 4 /* Means Slot INTx# Connects To Chipset INTD# */ + +static const struct irq_routing_table intel_irq_routing_table = { + PIRQ_SIGNATURE, /* u32 signature */ + PIRQ_VERSION, /* u16 version */ + 32 + 16 * CONFIG_IRQ_SLOT_COUNT, /* there can be total CONFIG_IRQ_SLOT_COUNT devices on the bus */ + 0x00, /* Where the interrupt router lies (bus) */ + (0x0F << 3) | 0x0, /* Where the interrupt router lies (dev) */ + 0x00, /* IRQs devoted exclusively to PCI usage */ + 0x100B, /* Vendor */ + 0x002B, /* Device */ + 0, /* Miniport data */ + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* u8 rfu[11] */ + 0x00, /* u8 checksum , this has to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */ + { + /* If you change the number of entries, change the CONFIG_IRQ_SLOT_COUNT above! */ + /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ + {0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* cpu */ + {0x00, (0x0F << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x0, 0x0}, /* chipset */ + {0x00, (0x0D << 3) | 0x0, {{L_PIRQB, M_PIRQB}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* ethernet */ + } +}; + +unsigned long write_pirq_routing_table(unsigned long addr) +{ + return copy_pirq_routing_table(addr, &intel_irq_routing_table); +} diff --git a/src/mainboard/amd/f2950/romstage.c b/src/mainboard/amd/f2950/romstage.c new file mode 100644 index 0000000..318149d --- /dev/null +++ b/src/mainboard/amd/f2950/romstage.c @@ -0,0 +1,80 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdint.h> +#include <stdlib.h> +#include <device/pci_def.h> +#include <arch/io.h> +#include <device/pnp_def.h> +#include <console/console.h> +#include <cpu/x86/bist.h> +#include <cpu/x86/msr.h> +#include <cpu/amd/car.h> +#include <cpu/amd/lxdef.h> +#include <southbridge/amd/cs5536/cs5536.h> +#include <spd.h> +#include "southbridge/amd/cs5536/early_smbus.c" +#include "southbridge/amd/cs5536/early_setup.c" +#include <superio/winbond/common/winbond.h> +#include <superio/winbond/w83627hf/w83627hf.h> +#include <northbridge/amd/lx/raminit.h> + +#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) + +int spd_read_byte(unsigned int device, unsigned int address) +{ + if (device != DIMM0) + return 0xFF; + + return smbus_read_byte(device, address); +} + +#include "northbridge/amd/lx/pll_reset.c" +#include "lib/generic_sdram.c" +#include "cpu/amd/geode_lx/cpureginit.c" +#include "cpu/amd/geode_lx/syspreinit.c" +#include "cpu/amd/geode_lx/msrinit.c" + +void main(unsigned long bist) +{ + + static const struct mem_controller memctrl[] = { + {.channel0 = {DIMM0, DIMM1}} + }; + + SystemPreInit(); + msr_init(); + + cs5536_early_setup(); + + /* Note: must do this AFTER the early_setup! It is counting on some + * early MSR setup for CS5536. + */ + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + console_init(); + + /* Halt if there was a built in self test failure */ + report_bist_failure(bist); + + pll_reset(); + + cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED); + + sdram_initialize(1, memctrl); + + /* Memory is setup. Return to cache_as_ram.inc and continue to boot. */ + return; +}

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New patch to review for coreboot: Add support for F2950 single-board computer
by Andrey Korolyov 07 Jul '16

07 Jul '16

Andrey Korolyov (andrey(a)xdel.ru) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15565 -gerrit commit e991e84d47bd091b456c010d75a09028ed8730a3 Author: Andrey Korolyov <andrey(a)xdel.ru> Date: Fri Jul 1 20:06:37 2016 +0300 Add support for F2950 single-board computer This platform, also known as TONK 1201/TONK 1202, was originally produced as a Centerm F2950. Common configuration does include a 600 MHz GeodeLX CPU underclocked to 500 or 400 Mhz, 128 or 512 Mb of RAM in the single SODIMM slot and 128 or 512 IDE DOM. The board does have three USB 2.0 ports, PS/2, VGA, Geode audio controller and the serial port. EEPROM needs to be soldered out and flashed externally at the time of this message because flashrom would neither be able to dump BIOS correcly while running vendor BIOS neither write flash contents. At this moment GeodeVGA does not work out-of-box after initialization by SeaBIOS, thereby preventing selection of the bootable media, Linux lxfb driver works well. Except this, all peripheral components (USB, serial, IDE, PS/2, audio) are working well. Change-Id: I93f13ecb53bd05abc0e07e0bd7ba40e646dcb4c4 --- src/mainboard/amd/f2950/Kconfig | 27 ++++++++++++ src/mainboard/amd/f2950/Kconfig.name | 2 + src/mainboard/amd/f2950/board_info.txt | 6 +++ src/mainboard/amd/f2950/cmos.layout | 36 +++++++++++++++ src/mainboard/amd/f2950/devicetree.cb | 67 ++++++++++++++++++++++++++++ src/mainboard/amd/f2950/irq_tables.c | 64 +++++++++++++++++++++++++++ src/mainboard/amd/f2950/romstage.c | 80 ++++++++++++++++++++++++++++++++++ 7 files changed, 282 insertions(+) diff --git a/src/mainboard/amd/f2950/Kconfig b/src/mainboard/amd/f2950/Kconfig new file mode 100644 index 0000000..5bfe120 --- /dev/null +++ b/src/mainboard/amd/f2950/Kconfig @@ -0,0 +1,27 @@ +if BOARD_AMD_F2950 + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select CPU_AMD_GEODE_LX + select NORTHBRIDGE_AMD_LX + select SOUTHBRIDGE_AMD_CS5536 + select SUPERIO_WINBOND_W83627HF + select HAVE_PIRQ_TABLE + select PIRQ_ROUTE + select UDELAY_TSC + select BOARD_ROMSIZE_KB_512 + select POWER_BUTTON_FORCE_ENABLE + +config MAINBOARD_DIR + string + default amd/f2950 + +config MAINBOARD_PART_NUMBER + string + default "F2950" + +config IRQ_SLOT_COUNT + int + default 3 + +endif # BOARD_AMD_F2950 diff --git a/src/mainboard/amd/f2950/Kconfig.name b/src/mainboard/amd/f2950/Kconfig.name new file mode 100644 index 0000000..8f6073a --- /dev/null +++ b/src/mainboard/amd/f2950/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_AMD_F2950 + bool "F2950" diff --git a/src/mainboard/amd/f2950/board_info.txt b/src/mainboard/amd/f2950/board_info.txt new file mode 100644 index 0000000..e957623 --- /dev/null +++ b/src/mainboard/amd/f2950/board_info.txt @@ -0,0 +1,6 @@ +Board name: F2950 +Category: mini +ROM package: PLCC +ROM protocol: FWH +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/amd/f2950/cmos.layout b/src/mainboard/amd/f2950/cmos.layout new file mode 100644 index 0000000..6de5ab6 --- /dev/null +++ b/src/mainboard/amd/f2950/cmos.layout @@ -0,0 +1,36 @@ +entries + +0 384 r 0 reserved_memory +384 1 e 4 boot_option +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +456 1 e 1 ECC_memory +1008 16 h 0 check_sum + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew + +checksums + +checksum 392 1007 1008 diff --git a/src/mainboard/amd/f2950/devicetree.cb b/src/mainboard/amd/f2950/devicetree.cb new file mode 100644 index 0000000..4e563d2 --- /dev/null +++ b/src/mainboard/amd/f2950/devicetree.cb @@ -0,0 +1,67 @@ +chip northbridge/amd/lx + device domain 0 on + device pci 1.0 on end # Northbridge + device pci 1.1 on end # Graphics + device pci 1.2 on end # Integrated cryptoaccelerator + chip southbridge/amd/cs5536 + # IRQ 12 and 1 unmasked, Keyboard and Mouse IRQs. OK + # SIRQ Mode = Active(Quiet) mode. Save power.... + # Invert mask = IRQ 12 and 1 are active high. Keyboard and Mouse, UARTs, etc IRQs. OK + register "lpc_serirq_enable" = "0x0000105a" + register "lpc_serirq_polarity" = "0x0000EFA5" + register "lpc_serirq_mode" = "1" + register "enable_gpio_int_route" = "0x0D0C0700" + register "enable_ide_nand_flash" = "0" # 0:ide mode, 1:flash + register "enable_USBP4_device" = "1" # 0: host, 1:device + register "enable_USBP4_overcurrent" = "0" #0:off, xxxx:overcurrent setting CS5536 Data Book (pages 380-381) + register "com1_enable" = "0" + register "com1_address" = "0x3F8" + register "com1_irq" = "4" + register "com2_enable" = "0" + register "com2_address" = "0x2F8" + register "com2_irq" = "3" + register "unwanted_vpci[0]" = "0" # End of list has a zero + device pci d.0 on end # Ethernet + device pci f.0 on # ISA Bridge + chip superio/winbond/w83627hf + device pnp 2e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 off # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.2 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 off end # Com2 + device pnp 2e.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 + end + device pnp 2e.6 off end # CIR + device pnp 2e.7 off end # GAME_MIDI_GIPO1 + device pnp 2e.8 off end # GPIO2 + device pnp 2e.9 off end # GPIO3 + device pnp 2e.a off end # ACPI + device pnp 2e.b off end # HW Monitor + end + end + device pci f.2 on end # IDE Controller + device pci f.3 on end # Audio + device pci f.4 on end # OHCI + device pci f.5 on end # EHCI + end + end + # APIC cluster is late CPU init. + device cpu_cluster 0 on + chip cpu/amd/geode_lx + device lapic 0 on end + end + end +end diff --git a/src/mainboard/amd/f2950/irq_tables.c b/src/mainboard/amd/f2950/irq_tables.c new file mode 100644 index 0000000..b438f02 --- /dev/null +++ b/src/mainboard/amd/f2950/irq_tables.c @@ -0,0 +1,64 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/pirq_routing.h> +#include <console/console.h> +#include <arch/io.h> +#include <arch/pirq_routing.h> +#include "southbridge/amd/cs5536/cs5536.h" + +/* Platform IRQs */ +#define PIRQA 11 +#define PIRQB 5 +#define PIRQC 10 +#define PIRQD 10 + +/* Map */ +#define M_PIRQA (1 << PIRQA) /* Bitmap of supported IRQs */ +#define M_PIRQB (1 << PIRQB) /* Bitmap of supported IRQs */ +#define M_PIRQC (1 << PIRQC) /* Bitmap of supported IRQs */ +#define M_PIRQD (1 << PIRQD) /* Bitmap of supported IRQs */ + +/* Link */ +#define L_PIRQA 1 /* Means Slot INTx# Connects To Chipset INTA# */ +#define L_PIRQB 2 /* Means Slot INTx# Connects To Chipset INTB# */ +#define L_PIRQC 3 /* Means Slot INTx# Connects To Chipset INTC# */ +#define L_PIRQD 4 /* Means Slot INTx# Connects To Chipset INTD# */ + +static const struct irq_routing_table intel_irq_routing_table = { + PIRQ_SIGNATURE, /* u32 signature */ + PIRQ_VERSION, /* u16 version */ + 32 + 16 * CONFIG_IRQ_SLOT_COUNT, /* there can be total CONFIG_IRQ_SLOT_COUNT devices on the bus */ + 0x00, /* Where the interrupt router lies (bus) */ + (0x0F << 3) | 0x0, /* Where the interrupt router lies (dev) */ + 0x00, /* IRQs devoted exclusively to PCI usage */ + 0x100B, /* Vendor */ + 0x002B, /* Device */ + 0, /* Miniport data */ + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* u8 rfu[11] */ + 0x00, /* u8 checksum , this has to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */ + { + /* If you change the number of entries, change the CONFIG_IRQ_SLOT_COUNT above! */ + /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ + {0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* cpu */ + {0x00, (0x0F << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x0, 0x0}, /* chipset */ + {0x00, (0x0D << 3) | 0x0, {{L_PIRQB, M_PIRQB}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* ethernet */ + } +}; + +unsigned long write_pirq_routing_table(unsigned long addr) +{ + return copy_pirq_routing_table(addr, &intel_irq_routing_table); +} diff --git a/src/mainboard/amd/f2950/romstage.c b/src/mainboard/amd/f2950/romstage.c new file mode 100644 index 0000000..318149d --- /dev/null +++ b/src/mainboard/amd/f2950/romstage.c @@ -0,0 +1,80 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdint.h> +#include <stdlib.h> +#include <device/pci_def.h> +#include <arch/io.h> +#include <device/pnp_def.h> +#include <console/console.h> +#include <cpu/x86/bist.h> +#include <cpu/x86/msr.h> +#include <cpu/amd/car.h> +#include <cpu/amd/lxdef.h> +#include <southbridge/amd/cs5536/cs5536.h> +#include <spd.h> +#include "southbridge/amd/cs5536/early_smbus.c" +#include "southbridge/amd/cs5536/early_setup.c" +#include <superio/winbond/common/winbond.h> +#include <superio/winbond/w83627hf/w83627hf.h> +#include <northbridge/amd/lx/raminit.h> + +#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) + +int spd_read_byte(unsigned int device, unsigned int address) +{ + if (device != DIMM0) + return 0xFF; + + return smbus_read_byte(device, address); +} + +#include "northbridge/amd/lx/pll_reset.c" +#include "lib/generic_sdram.c" +#include "cpu/amd/geode_lx/cpureginit.c" +#include "cpu/amd/geode_lx/syspreinit.c" +#include "cpu/amd/geode_lx/msrinit.c" + +void main(unsigned long bist) +{ + + static const struct mem_controller memctrl[] = { + {.channel0 = {DIMM0, DIMM1}} + }; + + SystemPreInit(); + msr_init(); + + cs5536_early_setup(); + + /* Note: must do this AFTER the early_setup! It is counting on some + * early MSR setup for CS5536. + */ + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + console_init(); + + /* Halt if there was a built in self test failure */ + report_bist_failure(bist); + + pll_reset(); + + cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED); + + sdram_initialize(1, memctrl); + + /* Memory is setup. Return to cache_as_ram.inc and continue to boot. */ + return; +}

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Patch merged into coreboot/master: acpigen_write_package: Return pointer to package element counter
by gerrit＠coreboot.org 07 Jul '16

07 Jul '16

the following patch was just integrated into master: commit 85d80276281e179b4e6a896e731090e9580ce8b9 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Sat Jul 2 19:53:54 2016 -0700 acpigen_write_package: Return pointer to package element counter Have acpigen_write_package() return a pointer to the package element counter so it can be used for dynamic package generation where needed. Change-Id: Id7f6dd03511069211ba3ee3eb29a6ca1742de847 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://review.coreboot.org/15536 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See https://review.coreboot.org/15536 for details. -gerrit

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Patch merged into coreboot/master: soc: Remove newline from `CHIP_NAME`
by gerrit＠coreboot.org 07 Jul '16

07 Jul '16

the following patch was just integrated into master: commit 3727776a8b423c55d40cf7627e27b8b03175d74d Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Sun Jul 3 09:45:26 2016 +0200 soc: Remove newline from `CHIP_NAME` The name must not terminated with a newline character `\n` as it would make it hard to use it strings. So, remove the newline from the two SoCs with it. Change-Id: I7570442b38a455e7c497d7f461c208fb0a88296d Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-on: https://review.coreboot.org/15540 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> See https://review.coreboot.org/15540 for details. -gerrit

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Patch merged into coreboot/master: lenovo/t530: Don't enforce native gfx init
by gerrit＠coreboot.org 07 Jul '16

07 Jul '16

the following patch was just integrated into master: commit 5b2d55ed95092b41bd1cde7d0a0882cff24a9ff3 Author: Alexander Couzens <lynxis(a)fe80.eu> Date: Thu Jun 16 20:54:36 2016 -0700 lenovo/t530: Don't enforce native gfx init Change-Id: I6d51f46240c62fcd6089411e8681e0b6e7d5bfe4 Signed-off-by: Philipp Deppenwiese <zaolin(a)das-labor.org> Signed-off-by: Alexander Couzens <lynxis(a)fe80.eu> Reviewed-on: https://review.coreboot.org/15222 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h(a)gmx.de> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See https://review.coreboot.org/15222 for details. -gerrit

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Patch merged into coreboot/master: lenovo/t530: add VGA device ID 8086, 0106
by gerrit＠coreboot.org 07 Jul '16

07 Jul '16

the following patch was just integrated into master: commit 7f78c9d03b8a1b27b8ca3d56c9e3230a67aea6d5 Author: Alexander Couzens <lynxis(a)fe80.eu> Date: Thu Jun 16 22:25:26 2016 -0700 lenovo/t530: add VGA device ID 8086,0106 Change-Id: I3cffe9d832edbbea79cabca639d9d920b7ffcf9a Signed-off-by: Philipp Deppenwiese <zaolin(a)das-labor.org> Signed-off-by: Alexander Couzens <lynxis(a)fe80.eu> Reviewed-on: https://review.coreboot.org/8178 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h(a)gmx.de> See https://review.coreboot.org/8178 for details. -gerrit

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Patch merged into coreboot/master: nyan: Avoid running early_mainboard_init twice in vboot context
by gerrit＠coreboot.org 07 Jul '16

07 Jul '16

the following patch was just integrated into master: commit 7b0e0d98101a49b1e53567ff1bfa3d6a3bda6cf5 Author: Paul Kocialkowski <contact(a)paulk.fr> Date: Mon Jun 27 18:17:14 2016 +0200 nyan: Avoid running early_mainboard_init twice in vboot context A call to early_mainboard_init is already present in verstage, thus it is only necessary to call it from romstage when not in vboot context. Change-Id: I2e0b5a369c5fb24efae4ac40d83a31f5cf4a078d Signed-off-by: Paul Kocialkowski <contact(a)paulk.fr> Reviewed-on: https://review.coreboot.org/15450 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> Reviewed-by: Julius Werner <jwerner(a)chromium.org> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See https://review.coreboot.org/15450 for details. -gerrit

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Patch merged into coreboot/master: tegra124: Build verstage when CHROMEOS is selected
by gerrit＠coreboot.org 07 Jul '16

07 Jul '16

the following patch was just integrated into master: commit 2d0281c6c9303a8d375de1f710f0282e9b8a1617 Author: Paul Kocialkowski <contact(a)paulk.fr> Date: Mon Jun 27 19:08:59 2016 +0200 tegra124: Build verstage when CHROMEOS is selected This includes the proper Kconfig options (based on the chromium os coreboot configuration) for setting up verstage on tegra124 devices. Change-Id: I4a1976ff684a417cae6fa718ef53cad763cee47d Signed-off-by: Paul Kocialkowski <contact(a)paulk.fr> Reviewed-on: https://review.coreboot.org/15451 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner <jwerner(a)chromium.org> See https://review.coreboot.org/15451 for details. -gerrit

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Patch merged into coreboot/master: intel/sandybridge: read correct leaf for cpu family
by gerrit＠coreboot.org 07 Jul '16

07 Jul '16

the following patch was just integrated into master: commit e4da9aa8974578eb35eea00bff0490d9a9f1b8e2 Author: Ryan Salsamendi <rsalsamendi(a)hotmail.com> Date: Fri Jun 24 12:01:11 2016 -0700 intel/sandybridge: read correct leaf for cpu family Reading cpuid leaf 0 is incorrect for testing cpu family. Use leaf 1 instead. See Intel SDM 2a Table 3-17. Change-Id: Ib2c95cdd1fb93db06a08ecd7266f6b88700caf83 Signed-off-by: Ryan Salsamendi <rsalsamendi(a)hotmail.com> Reviewed-on: https://review.coreboot.org/15346 Tested-by: build bot (Jenkins) Reviewed-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Reviewed-by: Patrick Rudolph <siro(a)das-labor.org> See https://review.coreboot.org/15346 for details. -gerrit

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coreboot-gerrit July 2016