coreboot-gerrit July 2016

coreboot-gerrit@coreboot.org

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New patch to review for coreboot: rockchip/rk3399: Fix pinctrl pull bias settings
by Martin Roth 08 Jul '16

08 Jul '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15587 -gerrit commit f7ad45582b854e45ecaf02c4b9e5d4c5207b3962 Author: Shunqian Zheng <zhengsq(a)rock-chips.com> Date: Tue May 17 14:00:04 2016 +0800 rockchip/rk3399: Fix pinctrl pull bias settings The pull bias settings for GPIO0_A, GPIO0_B, GPIO2_C and GPIO2_D are different from the other GPIO banks. This patch adds a callback function to get the GPIO pull value of each SoC(rk3288 and rk3399) so we can still use the common GPIO driver. BRANCH=none BUG=chrome-os-partner:53251 TEST=Jerry and Gru still boot Change-Id: I2a00b7ffd2699190582f5f50a1e21b61c500bf4f Signed-off-by: Martin Roth <martinroth(a)chromium.org> Original-Commit-Id: 46d5fa7297693216a2da9bcf15ccce4af796e80e Original-Change-Id: If53f47181bdc235a1ccfefeeb2a77e0eb0e3b1ca Original-Signed-off-by: Shunqian Zheng <zhengsq(a)rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/358110 Original-Commit-Ready: Julius Werner <jwerner(a)chromium.org> Original-Tested-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- src/soc/rockchip/common/gpio.c | 11 +++------- src/soc/rockchip/common/include/soc/gpio.h | 10 +++++++++ src/soc/rockchip/rk3288/gpio.c | 6 ++++++ src/soc/rockchip/rk3399/gpio.c | 33 ++++++++++++++++++++++++++++++ 4 files changed, 52 insertions(+), 8 deletions(-) diff --git a/src/soc/rockchip/common/gpio.c b/src/soc/rockchip/common/gpio.c index 6f30229..6ea38d4 100644 --- a/src/soc/rockchip/common/gpio.c +++ b/src/soc/rockchip/common/gpio.c @@ -21,21 +21,16 @@ #include <soc/soc.h> #include <stdlib.h> -enum { - PULLNONE = 0, - PULLUP, - PULLDOWN -}; - static void __gpio_input(gpio_t gpio, u32 pull) { + u32 pull_val = gpio_get_pull_val(gpio, pull); clrbits_le32(&gpio_port[gpio.port]->swporta_ddr, 1 << gpio.num); if (is_pmu_gpio(gpio)) clrsetbits_le32(gpio_grf_reg(gpio), 3 << (gpio.idx * 2), - pull << (gpio.idx * 2)); + pull_val << (gpio.idx * 2)); else write32(gpio_grf_reg(gpio), RK_CLRSETBITS(3 << (gpio.idx * 2), - pull << (gpio.idx * 2))); + pull_val << (gpio.idx * 2))); } void gpio_input(gpio_t gpio) diff --git a/src/soc/rockchip/common/include/soc/gpio.h b/src/soc/rockchip/common/include/soc/gpio.h index 55eb41d..2c72435 100644 --- a/src/soc/rockchip/common/include/soc/gpio.h +++ b/src/soc/rockchip/common/include/soc/gpio.h @@ -72,4 +72,14 @@ int is_pmu_gpio(gpio_t gpio); /* Return the io addr of gpio register */ void *gpio_grf_reg(gpio_t gpio); + +enum { + PULLNONE = 0, + PULLUP, + PULLDOWN +}; + +/* The gpio pull bias setting may be different between SoCs */ +u32 gpio_get_pull_val(gpio_t gpio, u32 pull); + #endif diff --git a/src/soc/rockchip/rk3288/gpio.c b/src/soc/rockchip/rk3288/gpio.c index 8a15b85..c610408 100644 --- a/src/soc/rockchip/rk3288/gpio.c +++ b/src/soc/rockchip/rk3288/gpio.c @@ -50,3 +50,9 @@ void *gpio_grf_reg(gpio_t gpio) /* There is one pmu gpio, gpio0 , so " - 1" */ return &rk3288_grf->gpio1_p[(gpio.port - 1)][gpio.bank]; } + +u32 gpio_get_pull_val(gpio_t gpio, u32 pull) +{ + /* use the default gpio pull bias setting defined in soc/gpio.h */ + return pull; +} diff --git a/src/soc/rockchip/rk3399/gpio.c b/src/soc/rockchip/rk3399/gpio.c index 18e0b70..a0cf059 100644 --- a/src/soc/rockchip/rk3399/gpio.c +++ b/src/soc/rockchip/rk3399/gpio.c @@ -47,3 +47,36 @@ void *gpio_grf_reg(gpio_t gpio) /* There are two pmu gpio, 0 and 1, so " - 2" */ return &rk3399_grf->gpio2_p[(gpio.port - 2)][gpio.bank]; } + +#define IS_GPIO_BANK(g, p, b) (g.port == p && g.bank == GPIO_##b) + +enum { + PULLNONE_1V8 = 0, + PULLDOWN_1V8 = 1, + PULLUP_1V8 = 3, +}; + +u32 gpio_get_pull_val(gpio_t gpio, u32 pull) +{ + /* The default pull bias setting defined in soc/gpio.h */ + u32 pull_val = pull; + + /* GPIO0_A, GPIO0_B, GPIO2_C, GPIO2_D use the 1V8 pull bias setting. + * Defined in TRM V.03 Part1 Page 331 and Page 458 + */ + if (IS_GPIO_BANK(gpio, 0, A) || IS_GPIO_BANK(gpio, 0, B) || + IS_GPIO_BANK(gpio, 2, C) || IS_GPIO_BANK(gpio, 2, D)) { + switch (pull) { + case PULLUP: + pull_val = PULLUP_1V8; + break; + case PULLDOWN: + pull_val = PULLDOWN_1V8; + break; + default: + pull_val = PULLNONE_1V8; + } + } + + return pull_val; +}

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New patch to review for coreboot: google/gru: Read RAM & board ids from the ADC
by Martin Roth 08 Jul '16

08 Jul '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15586 -gerrit commit 99fae6b6eea44d2ea0d5468db7ae335fa2beb7e5 Author: Shelley Chen <shchen(a)chromium.org> Date: Mon Jun 27 18:21:34 2016 -0700 google/gru: Read RAM & board ids from the ADC - Update so that the RAM id is read from ADC instead of hard-coded from the config array. - Update the boardid readings so that they are bucketed instead of within an error margin. BRANCH=None BUG=chrome-os-partner:54566,chrome-os-partner:53988 TEST=hexdump /proc/device-tree/firmware/coreboot/ram-code and boardid when OS boots up. Also verified that voltage read in debug output returns correct id. Change-Id: I963406d8c440cd90c3024c814c0de61d35ebe2fd Signed-off-by: Martin Roth <martinroth(a)chromium.org> Original-Commit-Id: 068705a38734d2604f71c8a7b5bf2cc15b0f7045 Original-Change-Id: I1c847558d54a0f7f9427904eeda853074ebb0e2e Original-Signed-off-by: Shelley Chen <shchen(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/356584 Original-Reviewed-by: Duncan Laurie <dlaurie(a)google.com> --- src/mainboard/google/gru/boardid.c | 60 ++++++++++++++++++-------------- src/mainboard/google/gru/sdram_configs.c | 6 ---- 2 files changed, 33 insertions(+), 33 deletions(-) diff --git a/src/mainboard/google/gru/boardid.c b/src/mainboard/google/gru/boardid.c index b0c1eaf..eb1c378 100644 --- a/src/mainboard/google/gru/boardid.c +++ b/src/mainboard/google/gru/boardid.c @@ -19,43 +19,49 @@ #include <soc/saradc.h> /* - * This matches Kevin/Gru ADC value for board id. + * ID info: + * ID : Volts : ADC value : Bucket + * == ===== ========= ====== + * 0 : 0.074V: 37.888 : 0 - <=82 + * 1 : 0.211V: 108.032 : 82- <=136 + * 2 : 0.319V: 163.328 : 136-<=191 + * 3 : 0.427V: 218.624 : 191-<=248 + * 4 : 0.542V: 277.504 : 248-<=309 + * 5 : 0.666V: 340.992 : 309-<=370 + * 6 : 0.781V: 399.872 : 370- 512 */ -static const int board_id_readings[] = { 42, 120, 181, 242, 307, 378, 444, - 511, 581, 646, 704, 763, 828, - 895, 956, 1023 }; +static const int id_readings[] = { 82, 136, 191, 248, 309, 370, 512 }; +static int cached_board_id = -1; +static int cached_ram_id = -1; -/* - * The ADC produces a 10 bit value, the resistor accuracy is 1%, let's leave - * 2% room for error on both sides, total variation would be 4%, which is - * approximately 40 points with a 10 bit ADC. The hardware specification - * guarantees valid readings to be at least 64 bits (2^6) apart. - */ -#define ACCEPTABLE_DELTA (int)(1024 * .02) - -uint8_t board_id(void) +static uint32_t get_index(uint32_t channel, int *cached_id) { - static int cached_board_id = -1; int i; int adc_reading; - if (cached_board_id != -1) - return cached_board_id; - - adc_reading = get_saradc_value(1); - for (i = 0; i < ARRAY_SIZE(board_id_readings); i++) { - int delta = board_id_readings[i] - adc_reading; + if (*cached_id != -1) + return *cached_id; - if ((delta < ACCEPTABLE_DELTA) && (delta > -ACCEPTABLE_DELTA)) { - printk(BIOS_DEBUG, "ADC reading %d, " - "expected value %d board ID %d\n", - adc_reading, delta + adc_reading, i); - cached_board_id = i; + adc_reading = get_saradc_value(channel); + for (i = 0; i < ARRAY_SIZE(id_readings); i++) { + if (adc_reading <= id_readings[i]) { + printk(BIOS_DEBUG, "ADC reading %d, ID %d\n", + adc_reading, i); + *cached_id = i; return i; } } - printk(BIOS_ERR, "Unmatched ADC reading of %d, using Board ID of 0\n", - adc_reading); + printk(BIOS_DEBUG, "ERROR: Unmatched ADC reading of %d\n", adc_reading); return 0; } + +uint8_t board_id(void) +{ + return get_index(1, &cached_board_id); +} + +uint32_t ram_code(void) +{ + return get_index(0, &cached_ram_id); +} diff --git a/src/mainboard/google/gru/sdram_configs.c b/src/mainboard/google/gru/sdram_configs.c index f1f889c..562055d 100644 --- a/src/mainboard/google/gru/sdram_configs.c +++ b/src/mainboard/google/gru/sdram_configs.c @@ -58,9 +58,3 @@ const struct rk3399_sdram_params *get_sdram_config() return &sdram_configs[speed]; } - - -uint32_t ram_code(void) -{ - return get_sdram_index(); -}

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New patch to review for coreboot: google/gru: Enable coreboot read recovery event
by Martin Roth 08 Jul '16

08 Jul '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15585 -gerrit commit 18efd43c0858ff0edf85452d45c83c84bc774f62 Author: Shelley Chen <shchen(a)chromium.org> Date: Thu Jun 30 12:51:57 2016 -0700 google/gru: Enable coreboot read recovery event Enable reading of keyboard recovery host event from coreboot. BUG=None BRANCH=None TEST=esc+refresh+power combo and make sure you see recovery fw screen. Change-Id: I166619d6202e23569395434e9dc1adb2a6a53296 Signed-off-by: Martin Roth <martinroth(a)chromium.org> Original-Commit-Id: f9279c8c06abb170589b1b11bf5287fbf38c9905 Original-Change-Id: Id980c77c8d7695b2c1b3343d968ad2a302d42aaa Original-Signed-off-by: Shelley Chen <shchen(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/357841 Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-by: Shawn N <shawnn(a)chromium.org> --- src/mainboard/google/gru/chromeos.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/src/mainboard/google/gru/chromeos.c b/src/mainboard/google/gru/chromeos.c index 912d13c..f8aa4fa 100644 --- a/src/mainboard/google/gru/chromeos.c +++ b/src/mainboard/google/gru/chromeos.c @@ -15,6 +15,8 @@ */ #include <boot/coreboot_tables.h> +#include <ec/google/chromeec/ec.h> +#include <ec/google/chromeec/ec_commands.h> #include <gpio.h> #include <vendorcode/google/chromeos/chromeos.h> @@ -24,6 +26,7 @@ void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { {GPIO_WP.raw, ACTIVE_LOW, gpio_get(GPIO_WP), "write protect"}, + {-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"}, {GPIO_BACKLIGHT.raw, ACTIVE_HIGH, -1, "backlight"}, {GPIO_EC_IN_RW.raw, ACTIVE_HIGH, -1, "EC in RW"}, {GPIO_EC_IRQ.raw, ACTIVE_LOW, -1, "EC interrupt"}, @@ -40,7 +43,11 @@ int get_developer_mode_switch(void) int get_recovery_mode_switch(void) { - return 0; + uint32_t ec_events; + + ec_events = google_chromeec_get_events_b(); + return !!(ec_events & + EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY)); } int get_write_protect_state(void)

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Patch set updated for coreboot: intel/amenia: Add GPE routing settings
by Shaunak Saha 08 Jul '16

08 Jul '16

Shaunak Saha (shaunak.saha(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15325 -gerrit commit c68a82e3b34d08d653fa84bef1c9de74db186459 Author: Shaunak Saha <shaunak.saha(a)intel.com> Date: Fri Jun 10 19:36:49 2016 -0700 intel/amenia: Add GPE routing settings This patch sets the devicetree for gpe0_dw configuration and also configures the GPIO lines for SCI. EC_SCI_GPI is configured to proper value. BUG = chrome-os-partner:53438 TEST = Toggle pch_sci_l from ec console using gpioset command and see that the sci counter increases in /sys/firmware/acpi/interrupt and also 9 in /proc/interrupt Change-Id: I3ae9ef7c6a3c8688bcb6cb4c73f5618e7cde342c Signed-off-by: Shaunak Saha <shaunak.saha(a)intel.com> --- src/mainboard/intel/amenia/devicetree.cb | 9 +++++++++ src/mainboard/intel/amenia/ec.h | 8 +++++--- src/mainboard/intel/amenia/gpio.h | 2 +- 3 files changed, 15 insertions(+), 4 deletions(-) diff --git a/src/mainboard/intel/amenia/devicetree.cb b/src/mainboard/intel/amenia/devicetree.cb index 2080d6f..711b96d 100644 --- a/src/mainboard/intel/amenia/devicetree.cb +++ b/src/mainboard/intel/amenia/devicetree.cb @@ -15,6 +15,15 @@ chip soc/intel/apollolake # 0x1A[6:0] stands for 26*125 = 3250 pSec delay for SDR104/HS200 register "emmc_tx_data_cntl1" = "0x1A1A" # HS400 required + # GPE configuration + # Note that GPE events called out in ASL code rely on this + # route, i.e., If this route changes then the affected GPE + # offset bits also needs to be changed. This sets the PMC register + # GPE_CFG fields. + register "gpe0_dw1" = "PMC_GPE_N_31_0" + register "gpe0_dw2" = "PMC_GPE_N_63_32" + register "gpe0_dw3" = "PMC_GPE_SW_31_0" + device domain 0 on device pci 00.0 on end # - Host Bridge device pci 00.1 on end # - DPTF diff --git a/src/mainboard/intel/amenia/ec.h b/src/mainboard/intel/amenia/ec.h index 91890fd..ba3962a 100644 --- a/src/mainboard/intel/amenia/ec.h +++ b/src/mainboard/intel/amenia/ec.h @@ -20,9 +20,11 @@ #include <ec/google/chromeec/ec_commands.h> -/* This is the GPE status bit. - TODO: Fix this to proper bit matching GPE routing table */ -#define EC_SCI_GPI 15 +/* + * GPIO_11 for SCI is routed to GPE0_DW1 and maps to group GPIO_GPE_N_31_0 + * which is North community + */ +#define EC_SCI_GPI GPE0_DW1_11 #define MAINBOARD_EC_SCI_EVENTS \ (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED) |\ diff --git a/src/mainboard/intel/amenia/gpio.h b/src/mainboard/intel/amenia/gpio.h index 87d6190..a39cca3 100644 --- a/src/mainboard/intel/amenia/gpio.h +++ b/src/mainboard/intel/amenia/gpio.h @@ -239,7 +239,7 @@ static const struct pad_config gpio_table[] = { PAD_CFG_NF(GPIO_8, NATIVE, DEEP, NF1), PAD_CFG_GPI(GPIO_9, UP_20K, DEEP), /* SPI_TPM_IRQ_N */ PAD_NC(GPIO_10, DN_20K), /* RSVD for MIPI (unused) */ - PAD_CFG_GPI_SCI(GPIO_11, UP_20K, DEEP, LEVEL, NONE), + PAD_CFG_GPI_SCI(GPIO_11, UP_20K, DEEP, EDGE_SINGLE, INVERT), /* SOC_WAKE_SCI_N */ PAD_NC(GPIO_12, DN_20K), PAD_NC(GPIO_13, DN_20K),

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New patch to review for coreboot: google/gru: enable EC software sync
by Martin Roth 08 Jul '16

08 Jul '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15584 -gerrit commit 014ca2c634b2bd86692607be5b9fc6efe93289c7 Author: Shelley Chen <shchen(a)chromium.org> Date: Thu Jun 30 09:39:12 2016 -0700 google/gru: enable EC software sync Enable CONFIG_EC_SOFTWARE_SYNC. Crossystem needs this to get ec RW/RO info. BUG=chrome-os-partner:54566 BRANCH=None TEST=1. apreset from ec console. Check for "VbEcSoftwareSync() check for RW update" string in ap console. 2. Run "ectool version" from OS to check that RO/RW version are different and that we're in RW: RO version: kevin_v1.1.4818-8243672 RW version: kevin_v1.1.4762-1957187 Firmware copy: RW 3. Run crossystem ecfw_act. check for RW return value. Change-Id: If6524f2cca4a6223ab9704d0af827e8c1072670f Signed-off-by: Martin Roth <martinroth(a)chromium.org> Original-Commit-Id: 0deb0e1c69d6bf21acf7640bf76f9196e14437d7 Original-Change-Id: I0db8235cf7d472f0aa642eea1998282d010d3433 Original-Signed-off-by: Shelley Chen <shchen(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/357811 Original-Reviewed-by: Vadim Bendebury <vbendeb(a)chromium.org> --- src/mainboard/google/gru/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mainboard/google/gru/Kconfig b/src/mainboard/google/gru/Kconfig index 1b42059..56b362f 100644 --- a/src/mainboard/google/gru/Kconfig +++ b/src/mainboard/google/gru/Kconfig @@ -39,6 +39,7 @@ config BOARD_SPECIFIC_OPTIONS config CHROMEOS select CHROMEOS_VBNV_FLASH + select EC_SOFTWARE_SYNC select VBOOT2_MOCK_SECDATA select VIRTUAL_DEV_SWITCH

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New patch to review for coreboot: rockchip/rk3399: initialize apll_b
by Martin Roth 08 Jul '16

08 Jul '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15583 -gerrit commit 79a3c6e3fdfbb405db2230ab5d696fc00f910420 Author: Lin Huang <hl(a)rock-chips.com> Date: Tue Jun 28 15:21:20 2016 +0800 rockchip/rk3399: initialize apll_b coreboot boots from the little core, and doesn't use the big core for now, but if apll_b is set to the default 24MHz, it will take a long time to enable the big core. This will cause a watchdog crash, so apll_b initialization to 600MHz needs to be done in coreboot. BRANCH=none BUG=chrome-os-partner:54817 TEST=Pick CL:353762 and see big CPU clocks look right TEST=Boot from Gru and see no cpufreq warnings Change-Id: Ie45cd2271555942e4321e9a9e523dc10f63d8107 Signed-off-by: Martin Roth <martinroth(a)chromium.org> Original-Commit-Id: Original-Change-Id: I20b8b591db3171e27740d85edce11f9e8797d849 Original-Signed-off-by: Martin Roth <martinroth(a)chromium.org> Original-Original-Commit-Id: 16bc916174042620bebe19ae73d241002491aecc Original-Original-Change-Id: Id3487138b383b6643ba7e3ce1eae501a6622da10 Original-Original-Signed-off-by: Lin Huang <hl(a)rock-chips.com> Original-Original-Signed-off-by: Douglas Anderson <dianders(a)chromium.org> Original-Original-Reviewed-on: https://chromium-review.googlesource.com/356399 Original-Original-Reviewed-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Original-Tested-by: Vadim Bendebury <vbendeb(a)chromium.org> --- src/soc/rockchip/rk3399/bootblock.c | 2 +- src/soc/rockchip/rk3399/clock.c | 81 ++++++++++++++++------------- src/soc/rockchip/rk3399/include/soc/clock.h | 2 +- 3 files changed, 47 insertions(+), 38 deletions(-) diff --git a/src/soc/rockchip/rk3399/bootblock.c b/src/soc/rockchip/rk3399/bootblock.c index 3e95a17..4f85e94 100644 --- a/src/soc/rockchip/rk3399/bootblock.c +++ b/src/soc/rockchip/rk3399/bootblock.c @@ -22,7 +22,7 @@ void bootblock_soc_init(void) { rkclk_init(); - rkclk_configure_cpu(APLL_600_MHZ); + rkclk_configure_cpu(APLL_600_MHZ, false); /* all ddr range non-secure */ write32(&rk3399_pmusgrf->ddr_rgn_con[16], 0xff << 16 | 0); diff --git a/src/soc/rockchip/rk3399/clock.c b/src/soc/rockchip/rk3399/clock.c index 9388487..cfe363c 100644 --- a/src/soc/rockchip/rk3399/clock.c +++ b/src/soc/rockchip/rk3399/clock.c @@ -104,23 +104,23 @@ enum { /* PMUCRU_CLKSEL_CON3 */ I2C4_DIV_CON_SHIFT = 0, - /* CLKSEL_CON0 */ - ACLKM_CORE_L_DIV_CON_MASK = 0x1f, - ACLKM_CORE_L_DIV_CON_SHIFT = 8, - CLK_CORE_L_PLL_SEL_MASK = 3, - CLK_CORE_L_PLL_SEL_SHIFT = 6, - CLK_CORE_L_PLL_SEL_ALPLL = 0x0, - CLK_CORE_L_PLL_SEL_ABPLL = 0x1, - CLK_CORE_L_PLL_SEL_DPLL = 0x10, - CLK_CORE_L_PLL_SEL_GPLL = 0x11, - CLK_CORE_L_DIV_MASK = 0x1f, - CLK_CORE_L_DIV_SHIFT = 0, - - /* CLKSEL_CON1 */ - PCLK_DBG_L_DIV_MASK = 0x1f, - PCLK_DBG_L_DIV_SHIFT = 0x8, - ATCLK_CORE_L_DIV_MASK = 0x1f, - ATCLK_CORE_L_DIV_SHIFT = 0, + /* CLKSEL_CON0 / CLKSEL_CON2 */ + ACLKM_CORE_DIV_CON_MASK = 0x1f, + ACLKM_CORE_DIV_CON_SHIFT = 8, + CLK_CORE_PLL_SEL_MASK = 3, + CLK_CORE_PLL_SEL_SHIFT = 6, + CLK_CORE_PLL_SEL_ALPLL = 0x0, + CLK_CORE_PLL_SEL_ABPLL = 0x1, + CLK_CORE_PLL_SEL_DPLL = 0x10, + CLK_CORE_PLL_SEL_GPLL = 0x11, + CLK_CORE_DIV_MASK = 0x1f, + CLK_CORE_DIV_SHIFT = 0, + + /* CLKSEL_CON1 / CLKSEL_CON3 */ + PCLK_DBG_DIV_MASK = 0x1f, + PCLK_DBG_DIV_SHIFT = 0x8, + ATCLK_CORE_DIV_MASK = 0x1f, + ATCLK_CORE_DIV_SHIFT = 0, /* CLKSEL_CON14 */ PCLK_PERIHP_DIV_CON_MASK = 0x7, @@ -411,6 +411,13 @@ void rkclk_init(void) rkclk_set_pll(&cru_ptr->gpll_con[0], &gpll_init_cfg); rkclk_set_pll(&cru_ptr->cpll_con[0], &cpll_init_cfg); + /* + * coreboot boot from little core, but it seem if apll_b use defalut + * 24MHz it will take a long time to enable big core, and will cause + * a watchdog crash, so we should do apll_b initialization here + */ + rkclk_configure_cpu(APLL_600_MHZ, true); + /* configure perihp aclk, hclk, pclk */ aclk_div = GPLL_HZ / PERIHP_ACLK_HZ - 1; assert((aclk_div + 1) * PERIHP_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f); @@ -487,16 +494,20 @@ void rkclk_init(void) HCLK_PERILP1_PLL_SEL_SHIFT)); } -void rkclk_configure_cpu(enum apll_frequencies apll_l_freq) +void rkclk_configure_cpu(enum apll_frequencies apll_freq, bool is_big) { u32 aclkm_div; u32 pclk_dbg_div; u32 atclk_div; u32 apll_l_hz; + int con_base = is_big ? 2 : 0; + int parent = is_big ? CLK_CORE_PLL_SEL_ABPLL : CLK_CORE_PLL_SEL_ALPLL; + u32 *pll_con = is_big ? &cru_ptr->apll_b_con[0] : + &cru_ptr->apll_l_con[0]; - apll_l_hz = apll_cfgs[apll_l_freq]->freq; + apll_l_hz = apll_cfgs[apll_freq]->freq; - rkclk_set_pll(&cru_ptr->apll_l_con[0], apll_cfgs[apll_l_freq]); + rkclk_set_pll(pll_con, apll_cfgs[apll_freq]); aclkm_div = div_round_up(apll_l_hz, ACLKM_CORE_HZ) - 1; @@ -504,22 +515,20 @@ void rkclk_configure_cpu(enum apll_frequencies apll_l_freq) atclk_div = div_round_up(apll_l_hz, ATCLK_CORE_HZ) - 1; - write32(&cru_ptr->clksel_con[0], - RK_CLRSETBITS(ACLKM_CORE_L_DIV_CON_MASK << - ACLKM_CORE_L_DIV_CON_SHIFT | - CLK_CORE_L_PLL_SEL_MASK << - CLK_CORE_L_PLL_SEL_SHIFT | - CLK_CORE_L_DIV_MASK << CLK_CORE_L_DIV_SHIFT, - aclkm_div << ACLKM_CORE_L_DIV_CON_SHIFT | - CLK_CORE_L_PLL_SEL_ALPLL << - CLK_CORE_L_PLL_SEL_SHIFT | - 0 << CLK_CORE_L_DIV_SHIFT)); - - write32(&cru_ptr->clksel_con[1], - RK_CLRSETBITS(PCLK_DBG_L_DIV_MASK << PCLK_DBG_L_DIV_SHIFT | - ATCLK_CORE_L_DIV_MASK << ATCLK_CORE_L_DIV_SHIFT, - pclk_dbg_div << PCLK_DBG_L_DIV_SHIFT | - atclk_div << ATCLK_CORE_L_DIV_SHIFT)); + write32(&cru_ptr->clksel_con[con_base], + RK_CLRSETBITS(ACLKM_CORE_DIV_CON_MASK << + ACLKM_CORE_DIV_CON_SHIFT | + CLK_CORE_PLL_SEL_MASK << CLK_CORE_PLL_SEL_SHIFT | + CLK_CORE_DIV_MASK << CLK_CORE_DIV_SHIFT, + aclkm_div << ACLKM_CORE_DIV_CON_SHIFT | + parent << CLK_CORE_PLL_SEL_SHIFT | + 0 << CLK_CORE_DIV_SHIFT)); + + write32(&cru_ptr->clksel_con[con_base + 1], + RK_CLRSETBITS(PCLK_DBG_DIV_MASK << PCLK_DBG_DIV_SHIFT | + ATCLK_CORE_DIV_MASK << ATCLK_CORE_DIV_SHIFT, + pclk_dbg_div << PCLK_DBG_DIV_SHIFT | + atclk_div << ATCLK_CORE_DIV_SHIFT)); } void rkclk_configure_ddr(unsigned int hz) diff --git a/src/soc/rockchip/rk3399/include/soc/clock.h b/src/soc/rockchip/rk3399/include/soc/clock.h index 70b819a..19e315b 100644 --- a/src/soc/rockchip/rk3399/include/soc/clock.h +++ b/src/soc/rockchip/rk3399/include/soc/clock.h @@ -103,7 +103,7 @@ enum apll_frequencies { void rkclk_init(void); int rkclk_configure_vop_dclk(u32 vop_id, u32 dclk_hz); -void rkclk_configure_cpu(enum apll_frequencies apll_l_freq); +void rkclk_configure_cpu(enum apll_frequencies apll_freq, bool is_big); void rkclk_configure_ddr(unsigned int hz); void rkclk_configure_emmc(void); void rkclk_configure_i2s(unsigned int hz);

1 0

New patch to review for coreboot: rockchip/rk3399: Use apll instead of apll_l define
by Martin Roth 08 Jul '16

08 Jul '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15582 -gerrit commit 0ccee537f9ecc7e22db6f5ca38a97025e90b7e89 Author: Lin Huang <hl(a)rock-chips.com> Date: Tue Jun 28 14:19:18 2016 +0800 rockchip/rk3399: Use apll instead of apll_l define Use the apll define instead of the apll_l define so it can be reused when setting apll_b. BRANCH=None BUG=None TEST=Boot from Gru Change-Id: Iebc4ce3b66a86c33653292340b9855265ac4fc07 Signed-off-by: Martin Roth <martinroth(a)chromium.org> Original-Commit-Id: eb578110d19a35ef04f8749fdc202055abd50fd1 Original-Change-Id: I63966e98af48eaf49837eb0b781eea001a376ef4 Original-Signed-off-by: Lin Huang <hl(a)rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/356398 Original-Reviewed-by: Douglas Anderson <dianders(a)chromium.org> Original-Tested-by: Douglas Anderson <dianders(a)chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Commit-Queue: Douglas Anderson <dianders(a)chromium.org> --- src/soc/rockchip/rk3399/bootblock.c | 2 +- src/soc/rockchip/rk3399/clock.c | 16 ++++++++-------- src/soc/rockchip/rk3399/include/soc/clock.h | 8 ++++---- 3 files changed, 13 insertions(+), 13 deletions(-) diff --git a/src/soc/rockchip/rk3399/bootblock.c b/src/soc/rockchip/rk3399/bootblock.c index 4f3d57c..3e95a17 100644 --- a/src/soc/rockchip/rk3399/bootblock.c +++ b/src/soc/rockchip/rk3399/bootblock.c @@ -22,7 +22,7 @@ void bootblock_soc_init(void) { rkclk_init(); - rkclk_configure_cpu(APLL_L_600_MHZ); + rkclk_configure_cpu(APLL_600_MHZ); /* all ddr range non-secure */ write32(&rk3399_pmusgrf->ddr_rgn_con[16], 0xff << 16 | 0); diff --git a/src/soc/rockchip/rk3399/clock.c b/src/soc/rockchip/rk3399/clock.c index 8b27454..9388487 100644 --- a/src/soc/rockchip/rk3399/clock.c +++ b/src/soc/rockchip/rk3399/clock.c @@ -47,12 +47,12 @@ static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1); static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2, 2); static const struct pll_div ppll_init_cfg = PLL_DIVISORS(PPLL_HZ, 2, 2, 1); -static const struct pll_div apll_l_1600_cfg = PLL_DIVISORS(1600*MHz, 3, 1, 1); -static const struct pll_div apll_l_600_cfg = PLL_DIVISORS(600*MHz, 1, 2, 1); +static const struct pll_div apll_1600_cfg = PLL_DIVISORS(1600*MHz, 3, 1, 1); +static const struct pll_div apll_600_cfg = PLL_DIVISORS(600*MHz, 1, 2, 1); -static const struct pll_div *apll_l_cfgs[] = { - [APLL_L_1600_MHZ] = &apll_l_1600_cfg, - [APLL_L_600_MHZ] = &apll_l_600_cfg, +static const struct pll_div *apll_cfgs[] = { + [APLL_1600_MHZ] = &apll_1600_cfg, + [APLL_600_MHZ] = &apll_600_cfg, }; enum { @@ -487,16 +487,16 @@ void rkclk_init(void) HCLK_PERILP1_PLL_SEL_SHIFT)); } -void rkclk_configure_cpu(enum apll_l_frequencies apll_l_freq) +void rkclk_configure_cpu(enum apll_frequencies apll_l_freq) { u32 aclkm_div; u32 pclk_dbg_div; u32 atclk_div; u32 apll_l_hz; - apll_l_hz = apll_l_cfgs[apll_l_freq]->freq; + apll_l_hz = apll_cfgs[apll_l_freq]->freq; - rkclk_set_pll(&cru_ptr->apll_l_con[0], apll_l_cfgs[apll_l_freq]); + rkclk_set_pll(&cru_ptr->apll_l_con[0], apll_cfgs[apll_l_freq]); aclkm_div = div_round_up(apll_l_hz, ACLKM_CORE_HZ) - 1; diff --git a/src/soc/rockchip/rk3399/include/soc/clock.h b/src/soc/rockchip/rk3399/include/soc/clock.h index 6781b5c..70b819a 100644 --- a/src/soc/rockchip/rk3399/include/soc/clock.h +++ b/src/soc/rockchip/rk3399/include/soc/clock.h @@ -96,14 +96,14 @@ static struct rk3399_cru_reg * const cru_ptr = (void *)CRU_BASE; #define PWM_CLOCK_HZ PMU_PCLK_HZ -enum apll_l_frequencies { - APLL_L_1600_MHZ, - APLL_L_600_MHZ, +enum apll_frequencies { + APLL_1600_MHZ, + APLL_600_MHZ, }; void rkclk_init(void); int rkclk_configure_vop_dclk(u32 vop_id, u32 dclk_hz); -void rkclk_configure_cpu(enum apll_l_frequencies apll_l_freq); +void rkclk_configure_cpu(enum apll_frequencies apll_l_freq); void rkclk_configure_ddr(unsigned int hz); void rkclk_configure_emmc(void); void rkclk_configure_i2s(unsigned int hz);

1 0

New patch to review for coreboot: rockchip/rk3399: calculate clocks based on parent clock speed
by Martin Roth 08 Jul '16

08 Jul '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15581 -gerrit commit 25d33dba3297d12495b23664bb0af4d64c57542a Author: Lin Huang <hl(a)rock-chips.com> Date: Tue Jun 28 11:10:54 2016 +0800 rockchip/rk3399: calculate clocks based on parent clock speed Currently aclkm pclkdbg atclk clocks use apll_l as a parent, but the apll_l frequency may change in firmware, so we need to caculate the div value based on the apll_l frequency. BRANCH=None BUG=chrome-os-partner:54376 TEST=Boot from Gru Change-Id: I2bd8886168453ce98efec58b5490c2430762769b Signed-off-by: Martin Roth <martinroth(a)chromium.org> Original-Commit-Id: 116ae863a504630e2aff056564836d84198fcae2 Original-Change-Id: I7e3a5d9e3f608ddf15592d893117c92767fcd015 Original-Signed-off-by: Lin Huang <hl(a)rock-chips.com> Original-Signed-off-by: Douglas Anderson <dianders(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/356397 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/soc/rockchip/rk3399/clock.c | 18 ++++++++---------- src/soc/rockchip/rk3399/include/soc/clock.h | 1 - 2 files changed, 8 insertions(+), 11 deletions(-) diff --git a/src/soc/rockchip/rk3399/clock.c b/src/soc/rockchip/rk3399/clock.c index 6d40cd2..8b27454 100644 --- a/src/soc/rockchip/rk3399/clock.c +++ b/src/soc/rockchip/rk3399/clock.c @@ -31,12 +31,13 @@ struct pll_div { u32 postdiv1; u32 postdiv2; u32 frac; + u32 freq; }; #define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\ .refdiv = _refdiv,\ .fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ),\ - .postdiv1 = _postdiv1, .postdiv2 = _postdiv2};\ + .postdiv1 = _postdiv1, .postdiv2 = _postdiv2, .freq = hz};\ _Static_assert(((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ) *\ OSC_HZ / (_refdiv * _postdiv1 * _postdiv2) == hz,\ #hz "Hz cannot be hit with PLL "\ @@ -491,20 +492,17 @@ void rkclk_configure_cpu(enum apll_l_frequencies apll_l_freq) u32 aclkm_div; u32 pclk_dbg_div; u32 atclk_div; + u32 apll_l_hz; + + apll_l_hz = apll_l_cfgs[apll_l_freq]->freq; rkclk_set_pll(&cru_ptr->apll_l_con[0], apll_l_cfgs[apll_l_freq]); - aclkm_div = APLL_HZ / ACLKM_CORE_HZ - 1; - assert((aclkm_div + 1) * ACLKM_CORE_HZ == APLL_HZ && - aclkm_div < 0x1f); + aclkm_div = div_round_up(apll_l_hz, ACLKM_CORE_HZ) - 1; - pclk_dbg_div = APLL_HZ / PCLK_DBG_HZ - 1; - assert((pclk_dbg_div + 1) * PCLK_DBG_HZ == APLL_HZ && - pclk_dbg_div < 0x1f); + pclk_dbg_div = div_round_up(apll_l_hz, PCLK_DBG_HZ) - 1; - atclk_div = APLL_HZ / ATCLK_CORE_HZ - 1; - assert((atclk_div + 1) * ATCLK_CORE_HZ == APLL_HZ && - atclk_div < 0x1f); + atclk_div = div_round_up(apll_l_hz, ATCLK_CORE_HZ) - 1; write32(&cru_ptr->clksel_con[0], RK_CLRSETBITS(ACLKM_CORE_L_DIV_CON_MASK << diff --git a/src/soc/rockchip/rk3399/include/soc/clock.h b/src/soc/rockchip/rk3399/include/soc/clock.h index 806e1ce..6781b5c 100644 --- a/src/soc/rockchip/rk3399/include/soc/clock.h +++ b/src/soc/rockchip/rk3399/include/soc/clock.h @@ -73,7 +73,6 @@ static struct rk3399_pmucru_reg * const pmucru_ptr = (void *)PMUCRU_BASE; static struct rk3399_cru_reg * const cru_ptr = (void *)CRU_BASE; #define OSC_HZ (24*MHz) -#define APLL_HZ (600*MHz) #define GPLL_HZ (594*MHz) #define CPLL_HZ (384*MHz) #define PPLL_HZ (594*MHz)

1 0

New patch to review for coreboot: tpm: use 4 byte quantities when retrieving firmware version
by Martin Roth 08 Jul '16

08 Jul '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15580 -gerrit commit 500837c19b2e49d87798aee54af3df10e8e32705 Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Mon Jun 27 19:05:41 2016 -0700 tpm: use 4 byte quantities when retrieving firmware version The CR50 device is capable of reporting its firmware version in 4 byte quantities, but the recently introduced code retrieves the version one byte at a time. With this fix the version is retrieved in 4 byte chunks. BRANCH=none BUG=none TEST=the version is still reported properly, as reported by the AP firmware console log: localhost ~ # grep cr50 /sys/firmware/log Firmware version: cr50_v1.1.4804-c64cf24 localhost ~ # Change-Id: Ia7461b758be2287e69a1ba6f038c257f50338199 Signed-off-by: Martin Roth <martinroth(a)chromium.org> Original-Commit-Id: 3111537e7b66d8507b6608ef665e4cde76403818 Original-Change-Id: I04116881a30001e35e989e51ec1567263f9149a6 Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/356542 Original-Reviewed-by: Andrey Pronin <apronin(a)chromium.org> --- src/drivers/spi/tpm/tpm.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/src/drivers/spi/tpm/tpm.c b/src/drivers/spi/tpm/tpm.c index 1b43bfb..4de62d9 100644 --- a/src/drivers/spi/tpm/tpm.c +++ b/src/drivers/spi/tpm/tpm.c @@ -359,7 +359,8 @@ int tpm2_init(struct spi_slave *spi_if) /* Let's report device FW version if available. */ if (tpm_info.vendor_id == 0x1ae0) { int chunk_count = 0; - char vstr[sizeof(cmd) + 1]; /* room for 4 chars + zero */ + uint32_t chunk = 0; + char vstr[sizeof(chunk) + 1]; /* room for 4 chars + zero */ printk(BIOS_INFO, "Firmware version: "); @@ -367,12 +368,12 @@ int tpm2_init(struct spi_slave *spi_if) * Does not really matter what's written, this just makes sure * the version is reported from the beginning. */ - tpm2_write_reg(TPM_FW_VER, &cmd, sizeof(cmd)); + tpm2_write_reg(TPM_FW_VER, &chunk, sizeof(chunk)); /* Print it out in 4 byte chunks. */ vstr[sizeof(vstr) - 1] = 0; do { - tpm2_read_reg(TPM_FW_VER, vstr, sizeof(cmd)); + tpm2_read_reg(TPM_FW_VER, vstr, sizeof(chunk)); printk(BIOS_INFO, "%s", vstr); /* @@ -381,7 +382,7 @@ int tpm2_init(struct spi_slave *spi_if) * This is likely result in one extra printk() * invocation with an empty string, not a big deal. */ - } while (vstr[0] && (chunk_count++ < (200 / sizeof(cmd)))); + } while (vstr[0] && (chunk_count++ < (200 / sizeof(chunk)))); printk(BIOS_INFO, "\n"); }

1 0

New patch to review for coreboot: rockchip/rk3399: Cleanup comments in sdram.c
by Martin Roth 08 Jul '16

08 Jul '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15579 -gerrit commit cda03e9022f6363e55021ff116c685ef9ab2c4c9 Author: Derek Basehore <dbasehore(a)chromium.org> Date: Wed Jun 22 16:42:30 2016 -0700 rockchip/rk3399: Cleanup comments in sdram.c Cleans up the comments in sdram.c to make them consistent. BRANCH=none BUG=none TEST=make sure gru/kevin build and boot also, run "stressapptest -M 1024 -s 3600" to make sure it passes Change-Id: I1daf72b847374d549389bacd2fa0a9f8f231b190 Signed-off-by: Martin Roth <martinroth(a)chromium.org> Original-Commit-Id: 63a224d6f4b0e4d13bc372c05c4b9196895d553f Original-Change-Id: Iaf8a32cfe2b22c4ccff71952f90d162ad8c2d3e7 Original-Signed-off-by: Derek Basehore <dbasehore(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/355665 Original-Reviewed-by: Martin Roth <martinroth(a)chromium.org> --- src/soc/rockchip/rk3399/sdram.c | 65 +++++++++++++++++++++++------------------ 1 file changed, 36 insertions(+), 29 deletions(-) diff --git a/src/soc/rockchip/rk3399/sdram.c b/src/soc/rockchip/rk3399/sdram.c index 4ad7b0e..f56ac17 100644 --- a/src/soc/rockchip/rk3399/sdram.c +++ b/src/soc/rockchip/rk3399/sdram.c @@ -119,8 +119,7 @@ static void phy_dll_bypass_set(u32 channel, struct rk3399_ddr_publ_regs *ddr_publ_regs, u32 freq) { if (freq <= 125*MHz) { - /* phy_sw_master_mode_X */ - /* PHY_86/214/342/470 4bits offset_8 */ + /* phy_sw_master_mode_X PHY_86/214/342/470 4bits offset_8 */ setbits_le32(&ddr_publ_regs->denali_phy[86], (0x3 << 2) << 8); setbits_le32(&ddr_publ_regs->denali_phy[214], @@ -130,8 +129,7 @@ static void phy_dll_bypass_set(u32 channel, setbits_le32(&ddr_publ_regs->denali_phy[470], (0x3 << 2) << 8); - /* phy_adrctl_sw_master_mode */ - /* PHY_547/675/803 4bits offset_16 */ + /* phy_adrctl_sw_master_mode PHY_547/675/803 4bits offset_16 */ setbits_le32(&ddr_publ_regs->denali_phy[547], (0x3 << 2) << 16); setbits_le32(&ddr_publ_regs->denali_phy[675], @@ -139,8 +137,7 @@ static void phy_dll_bypass_set(u32 channel, setbits_le32(&ddr_publ_regs->denali_phy[803], (0x3 << 2) << 16); } else { - /* phy_sw_master_mode_X */ - /* PHY_86/214/342/470 4bits offset_8 */ + /* phy_sw_master_mode_X PHY_86/214/342/470 4bits offset_8 */ clrbits_le32(&ddr_publ_regs->denali_phy[86], (0x3 << 2) << 8); clrbits_le32(&ddr_publ_regs->denali_phy[214], @@ -150,8 +147,7 @@ static void phy_dll_bypass_set(u32 channel, clrbits_le32(&ddr_publ_regs->denali_phy[470], (0x3 << 2) << 8); - /* phy_adrctl_sw_master_mode */ - /* PHY_547/675/803 4bits offset_16 */ + /* phy_adrctl_sw_master_mode PHY_547/675/803 4bits offset_16 */ clrbits_le32(&ddr_publ_regs->denali_phy[547], (0x3 << 2) << 16); clrbits_le32(&ddr_publ_regs->denali_phy[675], @@ -274,7 +270,7 @@ static void set_ds_odt(u32 channel, clrsetbits_le32(&ddr_publ_regs->denali_phy[672], 0xff, reg_value); clrsetbits_le32(&ddr_publ_regs->denali_phy[800], 0xff, reg_value); - /* phy_pad_addr_drive 29bits DENALI_PHY_928 offset_0 */ + /* phy_pad_addr_drive 8bits DENALI_PHY_928 offset_0 */ clrsetbits_le32((&ddr_publ_regs->denali_phy[928]), 0xff, reg_value); /* phy_pad_rst_drive 8bits DENALI_PHY_937 offset_0 */ @@ -329,6 +325,7 @@ static void set_ds_odt(u32 channel, clrsetbits_le32(&ddr_publ_regs->denali_phy[936], 0x1 << 17, reg_value); clrsetbits_le32(&ddr_publ_regs->denali_phy[940], 0x1 << 17, reg_value); clrsetbits_le32(&ddr_publ_regs->denali_phy[934], 0x1 << 17, reg_value); + /* phy_pad_fdbk_term 1bit DENALI_PHY_930 offset_17 */ clrsetbits_le32(&ddr_publ_regs->denali_phy[930], 0x1 << 17, reg_value); } @@ -368,13 +365,11 @@ static void phy_io_config(u32 channel, clrsetbits_le32(&ddr_publ_regs->denali_phy[915], 0xfff << 16, reg_value << 16); - /* mode setting */ if (sdram_params->dramtype == LPDDR4) mode_sel = 0x6; else if (sdram_params->dramtype == LPDDR3) mode_sel = 0x0; else if (sdram_params->dramtype == DDR3) - /* DDR3L */ mode_sel = 0x1; /* PHY_924 PHY_PAD_FDBK_DRIVE */ @@ -402,7 +397,6 @@ static void phy_io_config(u32 channel, clrsetbits_le32(&ddr_publ_regs->denali_phy[939], 0x7 << 14, mode_sel << 14); - /* SPEED */ if (sdram_params->ddr_freq < 400 * MHz) speed = 0x0; else if (sdram_params->ddr_freq < 800 * MHz) @@ -448,7 +442,8 @@ static void pctl_cfg(u32 channel, u32 tmp, tmp1, tmp2; u32 pwrup_srefresh_exit; - /* workaround controller bug: + /* + * work around controller bug: * Do not program DRAM_CLASS until NO_PHY_IND_TRAIN_INT is programmed */ copy_to_reg(&ddr_pctl_regs->denali_ctl[1], @@ -528,8 +523,10 @@ static void pctl_cfg(u32 channel, clrsetbits_le32(&ddr_publ_regs->denali_phy[468], 0xff << 8, (tmp + 0x10) << 8); - /* phy_dqs_tsel_wr_timing_X 8bits DENALI_PHY_83/211/339/467 offset_8 */ - /* dq_tsel_wr_end[7:4] add Half cycle */ + /* + * phy_dqs_tsel_wr_timing_X 8bits DENALI_PHY_83/211/339/467 offset_8 + * dq_tsel_wr_end[7:4] add Half cycle + */ tmp = (read32(&ddr_publ_regs->denali_phy[83]) >> 16) & 0xff; clrsetbits_le32(&ddr_publ_regs->denali_phy[83], 0xff << 16, (tmp + 0x10) << 16); @@ -549,7 +546,8 @@ static void pctl_cfg(u32 channel, clrsetbits_le32(&ddr_publ_regs->denali_phy[957], 0x3 << 24, 0x2 << 24); - /* FIXME: + /* + * FIXME: * need to care ERROR bit */ while (!(read32(&ddr_pctl_regs->denali_ctl[203]) & (1 << 3))) @@ -563,11 +561,12 @@ static void select_per_cs_training_index(u32 channel, u32 rank) { struct rk3399_ddr_publ_regs *ddr_publ_regs = rk3399_ddr_publ[channel]; - /*PHY_84 PHY_PER_CS_TRAINING_EN_0 1bit offset_16*/ + /* PHY_84 PHY_PER_CS_TRAINING_EN_0 1bit offset_16 */ if ((read32(&ddr_publ_regs->denali_phy[84])>>16) & 1) { - /*PHY_8/136/264/392 - *phy_per_cs_training_index_X 1bit offset_24 - */ + /* + * PHY_8/136/264/392 + * phy_per_cs_training_index_X 1bit offset_24 + */ clrsetbits_le32(&ddr_publ_regs->denali_phy[8], 0x1 << 24, rank << 24); clrsetbits_le32(&ddr_publ_regs->denali_phy[136], @@ -738,8 +737,10 @@ static int data_training(u32 channel, while (1) { /* PI_174 PI_INT_STATUS:RD:8:18 */ tmp = read32(&ddr_pi_regs->denali_pi[174]) >> 8; - /* check status obs */ - /* PHY_532/660/789 phy_adr_calvl_obs1_:0:32 */ + /* + * check status obs + * PHY_532/660/789 phy_adr_calvl_obs1_:0:32 + */ obs_0 = read32(&ddr_publ_regs->denali_phy[532]); obs_1 = read32(&ddr_publ_regs->denali_phy[660]); obs_2 = read32(&ddr_publ_regs->denali_phy[789]); @@ -775,7 +776,7 @@ static int data_training(u32 channel, select_per_cs_training_index(channel, i); while (1) { - /*PI_174 PI_INT_STATUS:RD:8:18*/ + /* PI_174 PI_INT_STATUS:RD:8:18 */ tmp = read32(&ddr_pi_regs->denali_pi[174]) >> 8; /* @@ -816,8 +817,10 @@ static int data_training(u32 channel, clrsetbits_le32(&ddr_pi_regs->denali_pi[80], 0x3 << 24, 0x2 << 24); - /* PI_74 PI_RDLVL_GATE_REQ:WR:16:1 */ - /* PI_RDLVL_CS:RW:24:2 */ + /* + * PI_74 PI_RDLVL_GATE_REQ:WR:16:1 + * PI_RDLVL_CS:RW:24:2 + */ clrsetbits_le32(&ddr_pi_regs->denali_pi[74], (0x1 << 16) | (0x3 << 24), (0x1 << 16) | (i << 24)); @@ -826,7 +829,8 @@ static int data_training(u32 channel, while (1) { /* PI_174 PI_INT_STATUS:RD:8:18 */ tmp = read32(&ddr_pi_regs->denali_pi[174]) >> 8; - /* check status obs + /* + * check status obs * PHY_43/171/299/427 * PHY_GTLVL_STATUS_OBS_x:16:8 */ @@ -869,7 +873,8 @@ static int data_training(u32 channel, while (1) { /* PI_174 PI_INT_STATUS:RD:8:18 */ tmp = read32(&ddr_pi_regs->denali_pi[174]) >> 8; - /* make sure status obs not report error bit + /* + * make sure status obs not report error bit * PHY_46/174/302/430 * phy_rdlvl_status_obs_X:16:8 */ @@ -888,8 +893,10 @@ static int data_training(u32 channel, /* wdq leveling(LPDDR4 support) */ if ((training_flag & PI_WDQ_LEVELING) == PI_WDQ_LEVELING) { for (i = 0; i < rank; i++) { - /* disable PI_WDQLVL_VREF_EN before wdq leveling? */ - /* PI_181 PI_WDQLVL_VREF_EN:RW:8:1 */ + /* + * disable PI_WDQLVL_VREF_EN before wdq leveling? + * PI_181 PI_WDQLVL_VREF_EN:RW:8:1 + */ clrbits_le32(&ddr_pi_regs->denali_pi[181], 0x1 << 8); /* PI_124 PI_WDQLVL_EN:RW:16:2 */ clrsetbits_le32(&ddr_pi_regs->denali_pi[124],

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coreboot-gerrit July 2016