coreboot-gerrit July 2016

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Patch set updated for coreboot: intel post-car: Consolidate choose_top_of_stack()
by Kyösti Mälkki 07 Jul '16

07 Jul '16

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15463 -gerrit commit b54476d6efd82f3a5ad62f8354dbb4eb2b9013bd Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Mon Jun 27 14:50:27 2016 +0300 intel post-car: Consolidate choose_top_of_stack() Change-Id: I2c49d68ea9a8f52737b6064bc4fa703bdb1af1df Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/cpu/intel/haswell/romstage.c | 16 +--------- src/drivers/intel/fsp1_1/Kconfig | 4 --- src/drivers/intel/fsp1_1/stack.c | 23 ++------------ src/include/program_loading.h | 6 ++++ src/lib/Makefile.inc | 1 + src/lib/romstage_stack.c | 48 ++++++++++++++++++++++++++++++ src/soc/intel/baytrail/romstage/romstage.c | 16 +--------- src/soc/intel/broadwell/romstage/stack.c | 17 ++--------- 8 files changed, 62 insertions(+), 69 deletions(-) diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c index cde9441..9154316 100644 --- a/src/cpu/intel/haswell/romstage.c +++ b/src/cpu/intel/haswell/romstage.c @@ -65,20 +65,6 @@ static inline u32 *stack_push(u32 *stack, u32 value) return stack; } -/* Romstage needs quite a bit of stack for decompressing images since the lzma - * lib keeps its state on the stack during romstage. */ -#define ROMSTAGE_RAM_STACK_SIZE 0x5000 -static unsigned long choose_top_of_stack(void) -{ - unsigned long stack_top; - - /* cbmem_add() does a find() before add(). */ - stack_top = (unsigned long)cbmem_add(CBMEM_ID_ROMSTAGE_RAM_STACK, - ROMSTAGE_RAM_STACK_SIZE); - stack_top += ROMSTAGE_RAM_STACK_SIZE; - return stack_top; -} - /* setup_romstage_stack_after_car() determines the stack to use after * cache-as-ram is torn down as well as the MTRR settings to use. */ static void *setup_romstage_stack_after_car(void) @@ -90,7 +76,7 @@ static void *setup_romstage_stack_after_car(void) u32 top_of_ram; /* Top of stack needs to be aligned to a 4-byte boundary. */ - top_of_stack = choose_top_of_stack() & ~3; + top_of_stack = romstage_ram_stack_top() & ~3; slot = (void *)top_of_stack; num_mtrrs = 0; diff --git a/src/drivers/intel/fsp1_1/Kconfig b/src/drivers/intel/fsp1_1/Kconfig index 86f6c7b..59b4797 100644 --- a/src/drivers/intel/fsp1_1/Kconfig +++ b/src/drivers/intel/fsp1_1/Kconfig @@ -99,10 +99,6 @@ config GOP_SUPPORT bool "Enable GOP support" default n -config ROMSTAGE_RAM_STACK_SIZE - hex "Size of the romstage RAM stack in bytes" - default 0x5000 - config USE_GENERIC_FSP_CAR_INC bool default n diff --git a/src/drivers/intel/fsp1_1/stack.c b/src/drivers/intel/fsp1_1/stack.c index 65ba235..8d0759a 100644 --- a/src/drivers/intel/fsp1_1/stack.c +++ b/src/drivers/intel/fsp1_1/stack.c @@ -21,23 +21,7 @@ #include <fsp/romstage.h> #include <fsp/stack.h> #include <stdlib.h> - -const unsigned long romstage_ram_stack_size = CONFIG_ROMSTAGE_RAM_STACK_SIZE; - -/* - * Romstage needs quite a bit of stack for decompressing images since the lzma - * lib keeps its state on the stack during romstage. - */ -static unsigned long choose_top_of_stack(void) -{ - unsigned long stack_top; - - /* cbmem_add() does a find() before add(). */ - stack_top = (unsigned long)cbmem_add(CBMEM_ID_ROMSTAGE_RAM_STACK, - romstage_ram_stack_size); - stack_top += romstage_ram_stack_size; - return stack_top; -} +#include <program_loading.h> /* * setup_stack_and_mtrrs() determines the stack to use after @@ -57,7 +41,7 @@ void *setup_stack_and_mtrrs(void) soc_display_mtrrs(); /* Top of stack needs to be aligned to a 8-byte boundary. */ - top_of_stack = choose_top_of_stack(); + top_of_stack = romstage_ram_stack_top(); slot = (void *)top_of_stack; num_mtrrs = 0; max_mtrrs = soc_get_variable_mtrr_count(NULL); @@ -68,8 +52,7 @@ void *setup_stack_and_mtrrs(void) */ mtrr_mask_upper = (1 << ((cpuid_eax(0x80000008) & 0xff) - 32)) - 1; alignment = mmap_region_granularity(); - aligned_ram = ALIGN_DOWN(top_of_stack - romstage_ram_stack_size, - alignment); + aligned_ram = ALIGN_DOWN(romstage_ram_stack_bottom(), alignment); /* * The order for each MTRR is value then base with upper 32-bits of diff --git a/src/include/program_loading.h b/src/include/program_loading.h index 42addb8..e265b18 100644 --- a/src/include/program_loading.h +++ b/src/include/program_loading.h @@ -170,6 +170,12 @@ void run_ramstage(void); /* Called when the stage cache couldn't load ramstage on resume. */ void ramstage_cache_invalid(void); +/* Determine where stack for ramstage loader is located. */ +enum { ROMSTAGE_STACK_CBMEM, ROMSTAGE_STACK_LOW_MEM }; +uintptr_t romstage_ram_stack_base(size_t size, int src); +uintptr_t romstage_ram_stack_top(void); +uintptr_t romstage_ram_stack_bottom(void); + /*********************** * PAYLOAD LOADING * ***********************/ diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 1028917..0c34b75 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -78,6 +78,7 @@ romstage-$(CONFIG_PRIMITIVE_MEMTEST) += primitive_memtest.c ramstage-$(CONFIG_PRIMITIVE_MEMTEST) += primitive_memtest.c romstage-$(CONFIG_CACHE_AS_RAM) += ramtest.c romstage-$(CONFIG_GENERIC_GPIO_LIB) += gpio.c +romstage-y += romstage_stack.c romstage-y += stack.c ramstage-y += rtc.c diff --git a/src/lib/romstage_stack.c b/src/lib/romstage_stack.c new file mode 100644 index 0000000..fde9d1b --- /dev/null +++ b/src/lib/romstage_stack.c @@ -0,0 +1,48 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015-2016 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <program_loading.h> +#include <cbmem.h> + +/* + * Romstage needs quite a bit of stack for decompressing images since the lzma + * lib keeps its state on the stack during romstage. + */ +#define ROMSTAGE_RAM_STACK_SIZE 0x5000 + +uintptr_t romstage_ram_stack_base(size_t size, int src) +{ + /* cbmem_add() does a find() before add(). */ + if (src == ROMSTAGE_STACK_CBMEM) + return (uintptr_t)cbmem_add(CBMEM_ID_ROMSTAGE_RAM_STACK, size); + if (src == ROMSTAGE_STACK_LOW_MEM) + return CONFIG_RAMTOP - size; + return 0; +} + +uintptr_t romstage_ram_stack_bottom(void) +{ + return romstage_ram_stack_base(ROMSTAGE_RAM_STACK_SIZE, + ROMSTAGE_STACK_CBMEM); +} + +uintptr_t romstage_ram_stack_top(void) +{ + uintptr_t stack_top = romstage_ram_stack_base(ROMSTAGE_RAM_STACK_SIZE, + ROMSTAGE_STACK_CBMEM); + stack_top += ROMSTAGE_RAM_STACK_SIZE; + return stack_top; +} diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c index a167c90..d7e8b17 100644 --- a/src/soc/intel/baytrail/romstage/romstage.c +++ b/src/soc/intel/baytrail/romstage/romstage.c @@ -258,20 +258,6 @@ static inline uint32_t *stack_push(u32 *stack, u32 value) return stack; } -/* Romstage needs quite a bit of stack for decompressing images since the lzma - * lib keeps its state on the stack during romstage. */ -static unsigned long choose_top_of_stack(void) -{ - unsigned long stack_top; - const unsigned long romstage_ram_stack_size = 0x5000; - - /* cbmem_add() does a find() before add(). */ - stack_top = (unsigned long)cbmem_add(CBMEM_ID_ROMSTAGE_RAM_STACK, - romstage_ram_stack_size); - stack_top += romstage_ram_stack_size; - return stack_top; -} - /* setup_stack_and_mttrs() determines the stack to use after * cache-as-ram is torn down as well as the MTRR settings to use. */ static void *setup_stack_and_mttrs(void) @@ -283,7 +269,7 @@ static void *setup_stack_and_mttrs(void) uint32_t top_of_ram; /* Top of stack needs to be aligned to a 4-byte boundary. */ - top_of_stack = choose_top_of_stack() & ~3; + top_of_stack = romstage_ram_stack_top() & ~3; slot = (void *)top_of_stack; num_mtrrs = 0; diff --git a/src/soc/intel/broadwell/romstage/stack.c b/src/soc/intel/broadwell/romstage/stack.c index 6c602a8..76307cf 100644 --- a/src/soc/intel/broadwell/romstage/stack.c +++ b/src/soc/intel/broadwell/romstage/stack.c @@ -21,6 +21,7 @@ #include <cbmem.h> #include <cpu/x86/mtrr.h> #include <soc/romstage.h> +#include <program_loading.h> static inline uint32_t *stack_push(u32 *stack, u32 value) { @@ -29,20 +30,6 @@ static inline uint32_t *stack_push(u32 *stack, u32 value) return stack; } -/* Romstage needs quite a bit of stack for decompressing images since the lzma - * lib keeps its state on the stack during romstage. */ -static unsigned long choose_top_of_stack(void) -{ - unsigned long stack_top; - const unsigned long romstage_ram_stack_size = 0x5000; - - /* cbmem_add() does a find() before add(). */ - stack_top = (unsigned long)cbmem_add(CBMEM_ID_ROMSTAGE_RAM_STACK, - romstage_ram_stack_size); - stack_top += romstage_ram_stack_size; - return stack_top; -} - /* setup_stack_and_mttrs() determines the stack to use after * cache-as-ram is torn down as well as the MTRR settings to use. */ void *setup_stack_and_mttrs(void) @@ -54,7 +41,7 @@ void *setup_stack_and_mttrs(void) uint32_t top_of_ram; /* Top of stack needs to be aligned to a 4-byte boundary. */ - top_of_stack = choose_top_of_stack() & ~3; + top_of_stack = romstage_ram_stack_top() & ~3; slot = (void *)top_of_stack; num_mtrrs = 0;

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Patch set updated for coreboot: ACPI S3: Remove HIGH_MEMORY_SAVE where possible
by Kyösti Mälkki 07 Jul '16

07 Jul '16

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15255 -gerrit commit c842a2b3aba50fb29cb3e9d8d3bf4117c423848e Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Jun 28 07:38:46 2016 +0300 ACPI S3: Remove HIGH_MEMORY_SAVE where possible Use actual requirements of ramstage size for S3 resume backup in CBMEM. The backup covers complete pages of 4 KiB. AMD k8 and fam10 platforms have not been adapted yet. Change-Id: Ide7ce013f3727c2928cdb00fbcc7e7e84e859ff1 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/Kconfig | 4 + src/arch/x86/acpi_s3.c | 133 ++++++++++++++++++++++++++---- src/arch/x86/include/arch/acpi.h | 12 +-- src/cpu/amd/car/post_cache_as_ram.c | 4 +- src/cpu/amd/family_10h-family_15h/Kconfig | 1 + src/cpu/amd/model_fxx/Kconfig | 1 + src/include/cbfs.h | 3 + src/include/program_loading.h | 4 + src/lib/cbfs.c | 12 +++ src/lib/prog_loaders.c | 14 +++- 10 files changed, 162 insertions(+), 26 deletions(-) diff --git a/src/Kconfig b/src/Kconfig index daba05a..91b594e 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -516,6 +516,10 @@ config HAVE_ACPI_RESUME bool default n +config ACPI_HUGE_LOWMEM_BACKUP + bool + default n + config RESUME_PATH_SAME_AS_BOOT bool default y if ARCH_X86 diff --git a/src/arch/x86/acpi_s3.c b/src/arch/x86/acpi_s3.c index 7855a2f..eb56b43 100644 --- a/src/arch/x86/acpi_s3.c +++ b/src/arch/x86/acpi_s3.c @@ -19,8 +19,10 @@ #include <cbmem.h> #include <cpu/cpu.h> #include <timestamp.h> +#include <program_loading.h> #include <romstage_handoff.h> #include <rules.h> +#include <symbols.h> #if ENV_RAMSTAGE @@ -79,30 +81,121 @@ void acpi_fail_wakeup(void) } #endif /* ENV_RAMSTAGE */ +struct resume_backup { + uint64_t cbmem; + uint64_t lowmem; + uint64_t size; + uint8_t valid; +}; + +#define BACKUP_PAGE_SZ 4096 + +static int backup_create_or_update(struct resume_backup *backup_mem, + uintptr_t base, size_t size) +{ + uintptr_t top; + + if (IS_ENABLED(CONFIG_ACPI_HUGE_LOWMEM_BACKUP)) { + base = CONFIG_RAMBASE; + size = HIGH_MEMORY_SAVE; + } + + /* Align backup region to complete pages. */ + top = ALIGN_UP(base + size, BACKUP_PAGE_SZ); + base = ALIGN_DOWN(base, BACKUP_PAGE_SZ); + size = top - base; + + /* Cannot extend existing region, should not happen. */ + if (backup_mem && (backup_mem->size < size)) + return -1; + + /* Allocate backup with room for header. */ + if (!backup_mem) { + size_t header_sz = ALIGN_UP(sizeof(*backup_mem), BACKUP_PAGE_SZ); + backup_mem = cbmem_add(CBMEM_ID_RESUME, header_sz + size); + if (!backup_mem) + return -1; + + /* Container starts from boundary after header. */ + backup_mem->cbmem = (uintptr_t)backup_mem + header_sz; + } + + backup_mem->valid = 0; + backup_mem->lowmem = base; + backup_mem->size = size; + return 0; +} + +void *acpi_backup_container(uintptr_t base, size_t size) +{ + struct resume_backup *backup_mem = cbmem_find(CBMEM_ID_RESUME); + if (!backup_mem) + return NULL; + + if (!IS_ALIGNED(base, BACKUP_PAGE_SZ) || !IS_ALIGNED(size, BACKUP_PAGE_SZ)) + return NULL; + + if (backup_create_or_update(backup_mem, base, size) < 0) + return NULL; + + backup_mem->valid = 1; + return (void*)(uintptr_t)backup_mem->cbmem; +} + +void backup_ramstage_section(uintptr_t base, size_t size) +{ + struct resume_backup *backup_mem = cbmem_find(CBMEM_ID_RESUME); + if (!backup_mem) + return; + + /* Check that the backup is not done twice. */ + if (backup_mem->valid) + return; + + /* When we are called from ramstage loader, update header with + * properties of the ramstage we will load. + */ + if (backup_create_or_update(backup_mem, base, size) < 0) + return; + + /* Back up the OS-controlled memory where ramstage will be loaded. */ + memcpy((void*)(uintptr_t)backup_mem->cbmem, + (void*)(uintptr_t)backup_mem->lowmem, (size_t)backup_mem->size); + backup_mem->valid = 1; +} + +/* Make backup of low-memory region, relying on the base and size + * of the ramstage that was loaded before entry to ACPI S3. + * + * DEPRECATED + */ void acpi_prepare_for_resume(void) { - if (!HIGH_MEMORY_SAVE) + struct resume_backup *backup_mem = cbmem_find(CBMEM_ID_RESUME); + if (!backup_mem) return; /* Back up the OS-controlled memory where ramstage will be loaded. */ - void *src = (void *)CONFIG_RAMBASE; - void *dest = cbmem_find(CBMEM_ID_RESUME); - if (dest != NULL) - memcpy(dest, src, HIGH_MEMORY_SAVE); + memcpy((void*)(uintptr_t)backup_mem->cbmem, + (void*)(uintptr_t)backup_mem->lowmem, (size_t)backup_mem->size); + backup_mem->valid = 1; } +/* Let's prepare the ACPI S3 Resume area now already, so we can rely on + * it being there during reboot time. If this fails, ACPI resume will + * be disabled. We assume that ramstage does not change while in suspend, + * so base and size of the currently running ramstage are used + * for allocation. + */ void acpi_prepare_resume_backup(void) { if (!acpi_s3_resume_allowed()) return; - /* Let's prepare the ACPI S3 Resume area now already, so we can rely on - * it being there during reboot time. We don't need the pointer, nor - * the result right now. If it fails, ACPI resume will be disabled. - */ + if (IS_ENABLED(CONFIG_RELOCATABLE_RAMSTAGE)) + return; - if (HIGH_MEMORY_SAVE) - cbmem_add(CBMEM_ID_RESUME, HIGH_MEMORY_SAVE); + backup_create_or_update(NULL, (uintptr_t)_program, _program_size); } #define WAKEUP_BASE 0x600 @@ -115,17 +208,22 @@ extern unsigned int __wakeup_size; static void acpi_jump_to_wakeup(void *vector) { - uintptr_t acpi_backup_memory = 0; + uintptr_t source = 0, target = 0; + size_t size = 0; if (!acpi_s3_resume_allowed()) { printk(BIOS_WARNING, "ACPI: S3 resume not allowed.\n"); return; } - if (HIGH_MEMORY_SAVE) { - acpi_backup_memory = (uintptr_t)cbmem_find(CBMEM_ID_RESUME); - - if (!acpi_backup_memory) { + if (!IS_ENABLED(CONFIG_RELOCATABLE_RAMSTAGE)) { + struct resume_backup *backup_mem = cbmem_find(CBMEM_ID_RESUME); + if (backup_mem && backup_mem->valid) { + backup_mem->valid = 0; + target = backup_mem->lowmem; + source = backup_mem->cbmem; + size = backup_mem->size; + } else { printk(BIOS_WARNING, "ACPI: Backup memory missing. " "No S3 resume.\n"); return; @@ -137,8 +235,7 @@ static void acpi_jump_to_wakeup(void *vector) timestamp_add_now(TS_ACPI_WAKE_JUMP); - acpi_do_wakeup((uintptr_t)vector, acpi_backup_memory, CONFIG_RAMBASE, - HIGH_MEMORY_SAVE); + acpi_do_wakeup((uintptr_t)vector, source, target, size); } void __attribute__((weak)) mainboard_suspend_resume(void) diff --git a/src/arch/x86/include/arch/acpi.h b/src/arch/x86/include/arch/acpi.h index 7434000..489edac 100644 --- a/src/arch/x86/include/arch/acpi.h +++ b/src/arch/x86/include/arch/acpi.h @@ -24,12 +24,7 @@ #ifndef __ASM_ACPI_H #define __ASM_ACPI_H -#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) && \ - ! IS_ENABLED(CONFIG_RELOCATABLE_RAMSTAGE) #define HIGH_MEMORY_SAVE (CONFIG_RAMTOP - CONFIG_RAMBASE) -#else -#define HIGH_MEMORY_SAVE 0 -#endif #ifndef __ASSEMBLER__ #include <stdint.h> @@ -623,6 +618,13 @@ static inline int acpi_s3_resume_allowed(void) return IS_ENABLED(CONFIG_HAVE_ACPI_RESUME); } +/* Return address in reserved memory where to backup low memory + * while platform resumes from S3 suspend. Caller is responsible of + * making a complete copy of the region base..base+size, with + * parameteres base and size that meet page alignment requirement. + */ +void *acpi_backup_container(uintptr_t base, size_t size); + #if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) extern int acpi_slp_type; diff --git a/src/cpu/amd/car/post_cache_as_ram.c b/src/cpu/amd/car/post_cache_as_ram.c index 15b2642..22f39ba 100644 --- a/src/cpu/amd/car/post_cache_as_ram.c +++ b/src/cpu/amd/car/post_cache_as_ram.c @@ -69,7 +69,7 @@ static void prepare_romstage_ramstack(int s3resume) print_car_debug("Prepare CAR migration and stack regions..."); if (s3resume) { - void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME); + void *resume_backup_memory = acpi_backup_container(CONFIG_RAMBASE, HIGH_MEMORY_SAVE); if (resume_backup_memory) memcpy_(resume_backup_memory + HIGH_MEMORY_SAVE - backup_top, (void *)(CONFIG_RAMTOP - backup_top), backup_top); @@ -85,7 +85,7 @@ static void prepare_ramstage_region(int s3resume) print_car_debug("Prepare ramstage memory region..."); if (s3resume) { - void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME); + void *resume_backup_memory = acpi_backup_container(CONFIG_RAMBASE, HIGH_MEMORY_SAVE); if (resume_backup_memory) memcpy_(resume_backup_memory, (void *) CONFIG_RAMBASE, HIGH_MEMORY_SAVE - backup_top); diff --git a/src/cpu/amd/family_10h-family_15h/Kconfig b/src/cpu/amd/family_10h-family_15h/Kconfig index fda7fc8..30c7dee 100644 --- a/src/cpu/amd/family_10h-family_15h/Kconfig +++ b/src/cpu/amd/family_10h-family_15h/Kconfig @@ -10,6 +10,7 @@ config CPU_AMD_MODEL_10XXX select TSC_SYNC_LFENCE select UDELAY_LAPIC select HAVE_MONOTONIC_TIMER + select ACPI_HUGE_LOWMEM_BACKUP select SUPPORT_CPU_UCODE_IN_CBFS select CPU_MICROCODE_MULTIPLE_FILES if !CPU_MICROCODE_CBFS_NONE diff --git a/src/cpu/amd/model_fxx/Kconfig b/src/cpu/amd/model_fxx/Kconfig index c8bae33..3eb5b94 100644 --- a/src/cpu/amd/model_fxx/Kconfig +++ b/src/cpu/amd/model_fxx/Kconfig @@ -9,6 +9,7 @@ config CPU_AMD_MODEL_FXX select SSE2 select TSC_SYNC_LFENCE select UDELAY_LAPIC + select ACPI_HUGE_LOWMEM_BACKUP select SUPPORT_CPU_UCODE_IN_CBFS if CPU_AMD_MODEL_FXX diff --git a/src/include/cbfs.h b/src/include/cbfs.h index 2d19218..7c16308 100644 --- a/src/include/cbfs.h +++ b/src/include/cbfs.h @@ -43,6 +43,9 @@ void *cbfs_boot_map_with_leak(const char *name, uint32_t type, size_t *size); size_t cbfs_load_and_decompress(const struct region_device *rdev, size_t offset, size_t in_size, void *buffer, size_t buffer_size, uint32_t compression); +/* Return the size and fill base of the memory pstage will occupy after loaded. */ +size_t cbfs_prog_stage_section(struct prog *pstage, uintptr_t *base); + /* Load stage into memory filling in prog. Return 0 on success. < 0 on error. */ int cbfs_prog_stage_load(struct prog *prog); diff --git a/src/include/program_loading.h b/src/include/program_loading.h index e265b18..86b14d1 100644 --- a/src/include/program_loading.h +++ b/src/include/program_loading.h @@ -176,6 +176,10 @@ uintptr_t romstage_ram_stack_base(size_t size, int src); uintptr_t romstage_ram_stack_top(void); uintptr_t romstage_ram_stack_bottom(void); +/* Backup OS memory to CBMEM_ID_RESUME on ACPI S3 resume path, + * if ramstage overwrites low memory. */ +void backup_ramstage_section(uintptr_t base, size_t size); + /*********************** * PAYLOAD LOADING * ***********************/ diff --git a/src/lib/cbfs.c b/src/lib/cbfs.c index aa652c2..92d5b74 100644 --- a/src/lib/cbfs.c +++ b/src/lib/cbfs.c @@ -166,6 +166,18 @@ void *cbfs_boot_load_stage_by_name(const char *name) return prog_entry(&stage); } +size_t cbfs_prog_stage_section(struct prog *pstage, uintptr_t *base) +{ + struct cbfs_stage stage; + const struct region_device *fh = prog_rdev(pstage); + + if (rdev_readat(fh, &stage, 0, sizeof(stage)) != sizeof(stage)) + return 0; + + *base = (uintptr_t)stage.load; + return stage.memlen; +} + int cbfs_prog_stage_load(struct prog *pstage) { struct cbfs_stage stage; diff --git a/src/lib/prog_loaders.c b/src/lib/prog_loaders.c index ecbc679..d70f936 100644 --- a/src/lib/prog_loaders.c +++ b/src/lib/prog_loaders.c @@ -101,6 +101,18 @@ static int load_relocatable_ramstage(struct prog *ramstage) return rmodule_stage_load(&rmod_ram); } +static int load_nonrelocatable_ramstage(struct prog *ramstage) +{ + if (IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)) { + uintptr_t base = 0; + size_t size = cbfs_prog_stage_section(ramstage, &base); + if (size) + backup_ramstage_section(base, size); + } + + return cbfs_prog_stage_load(ramstage); +} + void run_ramstage(void) { struct prog ramstage = @@ -126,7 +138,7 @@ void run_ramstage(void) if (IS_ENABLED(CONFIG_RELOCATABLE_RAMSTAGE)) { if (load_relocatable_ramstage(&ramstage)) goto fail; - } else if (cbfs_prog_stage_load(&ramstage)) + } else if (load_nonrelocatable_ramstage(&ramstage)) goto fail; stage_cache_add(STAGE_RAMSTAGE, &ramstage);

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Patch set updated for coreboot: AGESA: Use common ACPI S3 recovery
by Kyösti Mälkki 07 Jul '16

07 Jul '16

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15253 -gerrit commit ef7cd7d08b794ed39c0f271d9985fbf18abd10e0 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sat Jun 18 16:55:51 2016 +0300 AGESA: Use common ACPI S3 recovery Previous behaviour was to halt() on S3 wakeup in case resume backup memory was missing. In this odd case we now continue to normal boot. Change-Id: I8ce91088c5fa1a2d2abc53b23e423939fe759117 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/cpu/amd/agesa/s3_resume.c | 32 +++++++------------------------- 1 file changed, 7 insertions(+), 25 deletions(-) diff --git a/src/cpu/amd/agesa/s3_resume.c b/src/cpu/amd/agesa/s3_resume.c index 3a60b8d..54e41c1 100644 --- a/src/cpu/amd/agesa/s3_resume.c +++ b/src/cpu/amd/agesa/s3_resume.c @@ -25,29 +25,11 @@ #include <halt.h> #include "s3_resume.h" -static void *backup_resume(void) -{ - void *resume_backup_memory; - - printk(BIOS_DEBUG, "Find resume memory location\n"); - - if (cbmem_recovery(1)) { - printk(BIOS_EMERG, "Unable to recover CBMEM\n"); - halt(); - } - - resume_backup_memory = cbmem_find(CBMEM_ID_RESUME); - if (resume_backup_memory == NULL) { - printk(BIOS_EMERG, "No storage for low-memory backup\n"); - halt(); - } - - return resume_backup_memory; -} - static void move_stack_high_mem(void) { void *high_stack = cbmem_find(CBMEM_ID_ROMSTAGE_RAM_STACK); + if (high_stack == NULL) + halt(); /* TODO: Make the switch with empty stack instead. */ memcpy(high_stack, (void *)BSP_STACK_BASE_ADDR, HIGH_ROMSTAGE_STACK_SIZE); @@ -93,7 +75,10 @@ static void set_resume_cache(void) void prepare_for_resume(void) { - void *resume_backup_memory = backup_resume(); + if (cbmem_recovery(1)) { + printk(BIOS_EMERG, "Unable to recover CBMEM\n"); + halt(); + } post_code(0x62); printk(BIOS_DEBUG, "Move CAR stack.\n"); @@ -108,8 +93,5 @@ void prepare_for_resume(void) * Copy the system memory that is in the ramstage area to the * reserved area. */ - if (resume_backup_memory) - memcpy(resume_backup_memory, (void *)(CONFIG_RAMBASE), HIGH_MEMORY_SAVE); - - printk(BIOS_DEBUG, "System memory saved. OK to load ramstage.\n"); + acpi_prepare_for_resume(); }

1 0

Patch set updated for coreboot: AGESA: Use common romstage ram stack
by Kyösti Mälkki 07 Jul '16

07 Jul '16

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15466 -gerrit commit 4544807a9650743d626fae9c99d7287d188e6ad5 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Mon Jun 27 16:15:02 2016 +0300 AGESA: Use common romstage ram stack Change-Id: Ie120360fa79aa0f6f6d82606838404bb0b0d9681 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/cpu/amd/agesa/s3_resume.c | 8 +++++--- src/lib/Makefile.inc | 1 + src/northbridge/amd/agesa/oem_s3.c | 4 ++-- 3 files changed, 8 insertions(+), 5 deletions(-) diff --git a/src/cpu/amd/agesa/s3_resume.c b/src/cpu/amd/agesa/s3_resume.c index 54e41c1..e74c5b3 100644 --- a/src/cpu/amd/agesa/s3_resume.c +++ b/src/cpu/amd/agesa/s3_resume.c @@ -21,18 +21,20 @@ #include <cpu/amd/mtrr.h> #include <cpu/x86/cache.h> #include <cbmem.h> +#include <program_loading.h> #include <string.h> #include <halt.h> #include "s3_resume.h" static void move_stack_high_mem(void) { - void *high_stack = cbmem_find(CBMEM_ID_ROMSTAGE_RAM_STACK); - if (high_stack == NULL) + uintptr_t high_stack = romstage_ram_stack_base(HIGH_ROMSTAGE_STACK_SIZE, + ROMSTAGE_STACK_CBMEM); + if (!high_stack) halt(); /* TODO: Make the switch with empty stack instead. */ - memcpy(high_stack, (void *)BSP_STACK_BASE_ADDR, HIGH_ROMSTAGE_STACK_SIZE); + memcpy((void*)high_stack, (void *)BSP_STACK_BASE_ADDR, HIGH_ROMSTAGE_STACK_SIZE); /* TODO: We only switch stack on BSP. */ #ifdef __x86_64__ diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 0c34b75..9012321 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -79,6 +79,7 @@ ramstage-$(CONFIG_PRIMITIVE_MEMTEST) += primitive_memtest.c romstage-$(CONFIG_CACHE_AS_RAM) += ramtest.c romstage-$(CONFIG_GENERIC_GPIO_LIB) += gpio.c romstage-y += romstage_stack.c +ramstage-y += romstage_stack.c romstage-y += stack.c ramstage-y += rtc.c diff --git a/src/northbridge/amd/agesa/oem_s3.c b/src/northbridge/amd/agesa/oem_s3.c index 8cce0e7..4f2788e 100644 --- a/src/northbridge/amd/agesa/oem_s3.c +++ b/src/northbridge/amd/agesa/oem_s3.c @@ -17,6 +17,7 @@ #include <spi_flash.h> #include <string.h> #include <cbmem.h> +#include <program_loading.h> #include <cpu/amd/agesa/s3_resume.h> #include <northbridge/amd/agesa/agesawrapper.h> #include <AGESA.h> @@ -119,8 +120,7 @@ AGESA_STATUS OemS3Save(AMD_S3SAVE_PARAMS *S3SaveParams) u32 MTRRStorageSize = 0; uintptr_t pos, size; - if (HIGH_ROMSTAGE_STACK_SIZE) - cbmem_add(CBMEM_ID_ROMSTAGE_RAM_STACK, HIGH_ROMSTAGE_STACK_SIZE); + romstage_ram_stack_base(HIGH_ROMSTAGE_STACK_SIZE, ROMSTAGE_STACK_CBMEM); /* To be consumed in AmdInitResume. */ get_s3nv_data(S3DataTypeNonVolatile, &pos, &size);

1 0

Patch set updated for coreboot: AMD binaryPI: Split romstage ram stack
by Kyösti Mälkki 07 Jul '16

07 Jul '16

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15467 -gerrit commit b480d95b432e9f401c591a8b833d47724432adc1 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Mon Jun 27 15:25:14 2016 +0300 AMD binaryPI: Split romstage ram stack Change-Id: Ibbff1fdb1af247550815532ef12f078229f12321 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/cpu/amd/pi/heapmanager.c | 10 +++------- src/cpu/amd/pi/s3_resume.c | 9 +++++---- src/cpu/amd/pi/s3_resume.h | 8 ++++++++ 3 files changed, 16 insertions(+), 11 deletions(-) diff --git a/src/cpu/amd/pi/heapmanager.c b/src/cpu/amd/pi/heapmanager.c index c5e4202..d4a79b8 100644 --- a/src/cpu/amd/pi/heapmanager.c +++ b/src/cpu/amd/pi/heapmanager.c @@ -25,13 +25,9 @@ UINT32 GetHeapBase(AMD_CONFIG_PARAMS *StdHeader) { UINT32 heap = BIOS_HEAP_START_ADDRESS; -#if CONFIG_HAVE_ACPI_RESUME - /* Both romstage and ramstage has this S3 detect. */ - if (acpi_get_sleep_type() == 3) - heap = (UINT32) cbmem_find(CBMEM_ID_RESUME_SCRATCH) + - (CONFIG_HIGH_SCRATCH_MEMORY_SIZE - BIOS_HEAP_SIZE); - /* himem_heap_base + high_stack_size */ -#endif + if (acpi_is_wakeup_s3()) + heap = (UINT32) cbmem_find(CBMEM_ID_RESUME_SCRATCH); + return heap; } diff --git a/src/cpu/amd/pi/s3_resume.c b/src/cpu/amd/pi/s3_resume.c index 576a208..830d174 100644 --- a/src/cpu/amd/pi/s3_resume.c +++ b/src/cpu/amd/pi/s3_resume.c @@ -137,11 +137,12 @@ void restore_mtrr(void) #ifdef __PRE_RAM__ static void move_stack_high_mem(void) { - void *high_stack; + void *high_stack = cbmem_find(CBMEM_ID_ROMSTAGE_RAM_STACK); + if (high_stack == NULL) + halt(); - high_stack = cbmem_find(CBMEM_ID_RESUME_SCRATCH); - memcpy(high_stack, (void *)BSP_STACK_BASE_ADDR, - (CONFIG_HIGH_SCRATCH_MEMORY_SIZE - BIOS_HEAP_SIZE)); + /* TODO: Make the switch with empty stack instead. */ + memcpy(high_stack, (void *)BSP_STACK_BASE_ADDR, HIGH_ROMSTAGE_STACK_SIZE); #ifdef __x86_64__ __asm__ diff --git a/src/cpu/amd/pi/s3_resume.h b/src/cpu/amd/pi/s3_resume.h index f952055..3b6ecfa 100644 --- a/src/cpu/amd/pi/s3_resume.h +++ b/src/cpu/amd/pi/s3_resume.h @@ -31,4 +31,12 @@ void OemAgesaSaveMtrr (void); void spi_SaveS3info(u32 pos, u32 size, u8 *buf, u32 len); +#if 1 +/* This covers node 0 only. */ +#define HIGH_ROMSTAGE_STACK_SIZE (0x48000 - BSP_STACK_BASE_ADDR) +#else +/* This covers total of 8 nodes. */ +#define HIGH_ROMSTAGE_STACK_SIZE (0xA0000 - BSP_STACK_BASE_ADDR) +#endif + #endif

1 0

Patch set updated for coreboot: intel post-car: Separate romstage ramstack (WIP)
by Kyösti Mälkki 07 Jul '16

07 Jul '16

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15468 -gerrit commit 76c3ba129bab9cb0c61cce50a15677f0e64fa0bb Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Mon Jun 27 13:24:11 2016 +0300 intel post-car: Separate romstage ramstack (WIP) TODO: Need to fix MTRRs before placing stack high. TODO: Case LATE_CBMEM_INIT Change-Id: I221e207bcd0031048876f29100a1770a444d435b Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/cpu/intel/car/romstage.c | 20 +++++++++++++++++++- 1 file changed, 19 insertions(+), 1 deletion(-) diff --git a/src/cpu/intel/car/romstage.c b/src/cpu/intel/car/romstage.c index c6df446..215a6a2 100644 --- a/src/cpu/intel/car/romstage.c +++ b/src/cpu/intel/car/romstage.c @@ -1,7 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + #include <cpu/intel/romstage.h> +#include <program_loading.h> void * asmlinkage romstage_main(unsigned long bist) { mainboard_romstage_entry(bist); - return (void*)CONFIG_RAMTOP; + + if (IS_ENABLED(CONFIG_LATE_CBMEM_INIT)) + return (void*)CONFIG_RAMTOP; + + return (void*)romstage_ram_stack_top(); }

1 0

Patch set updated for coreboot: arch/riscv: Move CBMEM into RAM
by Jonathan Neuschäfer 07 Jul '16

07 Jul '16

Jonathan Neuschäfer (j.neuschaefer(a)gmx.net) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15284 -gerrit commit 9824e6b7f65ff62bff12b4c28da49b3a895a303b Author: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Date: Thu Jul 7 20:53:29 2016 +0200 arch/riscv: Move CBMEM into RAM CBMEM should be placed at the top of RAM, which can be found by parsing the configuration string. Configuration string parsing isn't yet implemented, so I'll hard-code the CBMEM location for now. Change-Id: If4092d094a856f6783887c062d6682dd13a73b8f Signed-off-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> --- src/soc/ucb/riscv/cbmem.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/soc/ucb/riscv/cbmem.c b/src/soc/ucb/riscv/cbmem.c index 3aabf19..a013e01 100644 --- a/src/soc/ucb/riscv/cbmem.c +++ b/src/soc/ucb/riscv/cbmem.c @@ -16,5 +16,5 @@ void *cbmem_top(void) { // TODO: find out how RISCV stores this. - return (void *)0x1fff000; + return (void *)0xc0000000; }

1 0

Patch set updated for coreboot: spike-riscv: Look for the CBFS in RAM
by Jonathan Neuschäfer 07 Jul '16

07 Jul '16

Jonathan Neuschäfer (j.neuschaefer(a)gmx.net) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15285 -gerrit commit 5420eed91c53fdfd363e9bdd739a93f1a241c937 Author: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Date: Thu Jul 7 20:53:28 2016 +0200 spike-riscv: Look for the CBFS in RAM Change-Id: I98927a70adc45d9aca916bd985932b94287921de Signed-off-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> --- src/arch/riscv/Makefile.inc | 3 --- src/arch/riscv/rom_media.c | 26 -------------------- src/mainboard/emulation/qemu-riscv/Makefile.inc | 3 +++ src/mainboard/emulation/qemu-riscv/rom_media.c | 26 ++++++++++++++++++++ src/mainboard/emulation/spike-riscv/Makefile.inc | 3 +++ src/mainboard/emulation/spike-riscv/rom_media.c | 30 ++++++++++++++++++++++++ 6 files changed, 62 insertions(+), 29 deletions(-) diff --git a/src/arch/riscv/Makefile.inc b/src/arch/riscv/Makefile.inc index 243fa53..c1c62ef 100644 --- a/src/arch/riscv/Makefile.inc +++ b/src/arch/riscv/Makefile.inc @@ -33,7 +33,6 @@ bootblock-y += trap_util.S bootblock-y += trap_handler.c bootblock-y += virtual_memory.c bootblock-y += boot.c -bootblock-y += rom_media.c bootblock-y += misc.c bootblock-y += \ $(top)/src/lib/memchr.c \ @@ -60,7 +59,6 @@ ifeq ($(CONFIG_ARCH_ROMSTAGE_RISCV),y) romstage-y += boot.c romstage-y += stages.c -romstage-y += rom_media.c romstage-y += misc.c romstage-y += \ $(top)/src/lib/memchr.c \ @@ -90,7 +88,6 @@ ifeq ($(CONFIG_ARCH_RAMSTAGE_RISCV),y) ramstage-y = ramstage-y += trap_handler.c ramstage-y += virtual_memory.c -ramstage-y += rom_media.c ramstage-y += stages.c ramstage-y += misc.c ramstage-y += boot.c diff --git a/src/arch/riscv/rom_media.c b/src/arch/riscv/rom_media.c deleted file mode 100644 index c171307..0000000 --- a/src/arch/riscv/rom_media.c +++ /dev/null @@ -1,26 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2015 Google Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ -#include <boot_device.h> - -/* This assumes that the CBFS resides at 0x0, which is true for the default - * configuration. */ -static const struct mem_region_device boot_dev = - MEM_REGION_DEV_RO_INIT(NULL, CONFIG_ROM_SIZE); - -const struct region_device *boot_device_ro(void) -{ - return &boot_dev.rdev; -} diff --git a/src/mainboard/emulation/qemu-riscv/Makefile.inc b/src/mainboard/emulation/qemu-riscv/Makefile.inc index 87bc39a..b8a62f7 100644 --- a/src/mainboard/emulation/qemu-riscv/Makefile.inc +++ b/src/mainboard/emulation/qemu-riscv/Makefile.inc @@ -15,11 +15,14 @@ bootblock-y += bootblock.c bootblock-y += uart.c bootblock-y += qemu_util.c +bootblock-y += rom_media.c romstage-y += romstage.c romstage-y += qemu_util.c romstage-y += uart.c +romstage-y += rom_media.c ramstage-y += uart.c ramstage-y += qemu_util.c +ramstage-y += rom_media.c bootblock-y += memlayout.ld romstage-y += memlayout.ld diff --git a/src/mainboard/emulation/qemu-riscv/rom_media.c b/src/mainboard/emulation/qemu-riscv/rom_media.c new file mode 100644 index 0000000..c171307 --- /dev/null +++ b/src/mainboard/emulation/qemu-riscv/rom_media.c @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include <boot_device.h> + +/* This assumes that the CBFS resides at 0x0, which is true for the default + * configuration. */ +static const struct mem_region_device boot_dev = + MEM_REGION_DEV_RO_INIT(NULL, CONFIG_ROM_SIZE); + +const struct region_device *boot_device_ro(void) +{ + return &boot_dev.rdev; +} diff --git a/src/mainboard/emulation/spike-riscv/Makefile.inc b/src/mainboard/emulation/spike-riscv/Makefile.inc index dff4758..91c1369 100644 --- a/src/mainboard/emulation/spike-riscv/Makefile.inc +++ b/src/mainboard/emulation/spike-riscv/Makefile.inc @@ -15,11 +15,14 @@ bootblock-y += bootblock.c bootblock-y += uart.c bootblock-y += spike_util.c +bootblock-y += rom_media.c romstage-y += romstage.c romstage-y += uart.c romstage-y += spike_util.c +romstage-y += rom_media.c ramstage-y += uart.c ramstage-y += spike_util.c +ramstage-y += rom_media.c bootblock-y += memlayout.ld romstage-y += memlayout.ld diff --git a/src/mainboard/emulation/spike-riscv/rom_media.c b/src/mainboard/emulation/spike-riscv/rom_media.c new file mode 100644 index 0000000..10952a3 --- /dev/null +++ b/src/mainboard/emulation/spike-riscv/rom_media.c @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 Google Inc. + * Copyright 2016 Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include <boot_device.h> + +/* + * 0x80000000 is this start of RAM. We currently need to load coreboot.rom into + * RAM on SPIKE, because SPIKE doesn't support loading custom code into the + * boot ROM. + */ +static const struct mem_region_device boot_dev = + MEM_REGION_DEV_RO_INIT(0x80000000, CONFIG_ROM_SIZE); + +const struct region_device *boot_device_ro(void) +{ + return &boot_dev.rdev; +}

1 0

Patch set updated for coreboot: util/riscvtools: Provide a tohost/fromhost symbols so Spike doesn't hang
by Jonathan Neuschäfer 07 Jul '16

07 Jul '16

Jonathan Neuschäfer (j.neuschaefer(a)gmx.net) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15288 -gerrit commit 573669dca9b36ff0dda3e5d08df0b1a815b191d2 Author: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Date: Thu Jul 7 20:53:28 2016 +0200 util/riscvtools: Provide a tohost/fromhost symbols so Spike doesn't hang See https://github.com/riscv/riscv-isa-sim/issues/54 for more information. Change-Id: I8cda8dc07866d395eb3ce5d94df8232840fa8b82 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> --- util/riscvtools/spike-elf.ld | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/util/riscvtools/spike-elf.ld b/util/riscvtools/spike-elf.ld index 341a16f..44114f7 100644 --- a/util/riscvtools/spike-elf.ld +++ b/util/riscvtools/spike-elf.ld @@ -8,4 +8,8 @@ SECTIONS .data : { *(.data) } + + tohost = .; + . = . + 8; + fromhost = .; }

1 0

Patch set updated for coreboot: spike-riscv: Remove HTIF related code
by Jonathan Neuschäfer 07 Jul '16

07 Jul '16

Jonathan Neuschäfer (j.neuschaefer(a)gmx.net) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15289 -gerrit commit 1b7805ed9d55e30b621222a182828e3b95627e4c Author: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Date: Thu Jul 7 20:53:28 2016 +0200 spike-riscv: Remove HTIF related code The HTIF is deprecated and the newest RISC-V binutils don't know the mtohost/mfromhost CSRs anymore. The SBI implementation still needs to be restructured. Change-Id: I13f01e45b714f1bd919e27b84aff8db772504b1f Signed-off-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> --- src/mainboard/emulation/spike-riscv/spike_util.c | 110 ++--------------------- 1 file changed, 7 insertions(+), 103 deletions(-) diff --git a/src/mainboard/emulation/spike-riscv/spike_util.c b/src/mainboard/emulation/spike-riscv/spike_util.c index fca7d56..358cb44 100644 --- a/src/mainboard/emulation/spike-riscv/spike_util.c +++ b/src/mainboard/emulation/spike-riscv/spike_util.c @@ -55,14 +55,7 @@ uintptr_t mcall_query_memory(uintptr_t id, memory_block_info *p) uintptr_t mcall_send_ipi(uintptr_t recipient) { - //if (recipient >= num_harts) - //return -1; - - if (atomic_swap(&OTHER_HLS(recipient)->ipi_pending, 1) == 0) { - mb(); - write_csr(send_ipi, recipient); - } - + die("mcall_send_ipi is currently not implemented"); return 0; } @@ -79,50 +72,26 @@ uintptr_t mcall_clear_ipi(void) uintptr_t mcall_shutdown(void) { - while (1) write_csr(mtohost, 1); + die("mcall_shutdown is currently not implemented"); return 0; } uintptr_t mcall_set_timer(unsigned long long when) { - write_csr(mtimecmp, when); - clear_csr(mip, MIP_STIP); - set_csr(mie, MIP_MTIP); + die("mcall_set_timer is currently not implemented"); return 0; } uintptr_t mcall_dev_req(sbi_device_message *m) { - if ((m->dev > 0xFFU) | (m->cmd > 0xFFU) | (m->data > 0x0000FFFFFFFFFFFFU)) return -EINVAL; - - while (swap_csr(mtohost, TOHOST_CMD(m->dev, m->cmd, m->data)) != 0); - - m->sbi_private_data = (uintptr_t)HLS()->device_request_queue_head; - HLS()->device_request_queue_head = m; - HLS()->device_request_queue_size++; - + die("mcall_dev_req is currently not implemented"); return 0; } uintptr_t mcall_dev_resp(void) { - htif_interrupt(0, 0); - - sbi_device_message* m = HLS()->device_response_queue_head; - if (m) { - //printm("resp %p\n", m); - sbi_device_message* next = (void*)atomic_read(&m->sbi_private_data); - HLS()->device_response_queue_head = next; - if (!next) { - HLS()->device_response_queue_tail = 0; - - // only clear SSIP if no other events are pending - clear_csr(mip, MIP_SSIP); - mb(); - if (HLS()->ipi_pending) set_csr(mip, MIP_SSIP); - } - } - return (uintptr_t)m; + die("mcall_dev_resp is currently not implemented"); + return 0; } uintptr_t mcall_hart_id(void) @@ -136,74 +105,9 @@ void hls_init(uint32_t hart_id) HLS()->hart_id = hart_id; } -uintptr_t htif_interrupt(uintptr_t mcause, uintptr_t* regs) { - uintptr_t fromhost = swap_csr(mfromhost, 0); - if (!fromhost) - return 0; - - uintptr_t dev = FROMHOST_DEV(fromhost); - uintptr_t cmd = FROMHOST_CMD(fromhost); - uintptr_t data = FROMHOST_DATA(fromhost); - - sbi_device_message* m = HLS()->device_request_queue_head; - sbi_device_message* prev = 0x0; - unsigned long i, n; - for (i = 0, n = HLS()->device_request_queue_size; i < n; i++) { - /* - if (!supervisor_paddr_valid(m, sizeof(*m)) - && EXTRACT_FIELD(read_csr(mstatus), MSTATUS_PRV1) != PRV_M) - panic("htif: page fault"); - */ - - sbi_device_message* next = (void*)m->sbi_private_data; - if (m->dev == dev && m->cmd == cmd) { - m->data = data; - - // dequeue from request queue - if (prev) - prev->sbi_private_data = (uintptr_t)next; - else - HLS()->device_request_queue_head = next; - HLS()->device_request_queue_size = n-1; - m->sbi_private_data = 0; - - // enqueue to response queue - if (HLS()->device_response_queue_tail) - { - HLS()->device_response_queue_tail->sbi_private_data = (uintptr_t)m; - } - else - { - HLS()->device_response_queue_head = m; - } - HLS()->device_response_queue_tail = m; - - // signal software interrupt - set_csr(mip, MIP_SSIP); - return 0; - } - - prev = m; - m = (void*)atomic_read(&m->sbi_private_data); - } - //HLT(); - return 0; - //panic("htif: no record"); -} - uintptr_t mcall_console_putchar(uint8_t ch) { - while (swap_csr(mtohost, TOHOST_CMD(1, 1, ch)) != 0); - while (1) { - uintptr_t fromhost = read_csr(mfromhost); - if (FROMHOST_DEV(fromhost) != 1 || FROMHOST_CMD(fromhost) != 1) { - if (fromhost) - htif_interrupt(0, 0); - continue; - } - write_csr(mfromhost, 0); - break; - } + do_putchar(ch); return 0; }

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coreboot-gerrit July 2016