coreboot-gerrit June 2016

coreboot-gerrit@coreboot.org

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1491 discussions

Patch merged into coreboot/master: lib/nhlt: add helper functions for adding endpoints
by gerrit＠coreboot.org 29 Jun '16

29 Jun '16

the following patch was just integrated into master: commit ed0f6d7cb762b40d282101cf847f3d45209a5f26 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Jun 28 14:59:21 2016 -0500 lib/nhlt: add helper functions for adding endpoints In order to ease the porting of supporting NHLT endpoints introduce a nhlt_endpoint_descriptor structure as well as corresponding helper functions. Change-Id: I68edaf681b4e60502f6ddbbd04de21d8aa072296 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://review.coreboot.org/15486 Reviewed-by: Furquan Shaikh <furquan(a)google.com> Tested-by: build bot (Jenkins) See https://review.coreboot.org/15486 for details. -gerrit

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New patch to review for coreboot: google/reef: Enable touchscreen in ACPI
by Furquan Shaikh 29 Jun '16

29 Jun '16

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15499 -gerrit commit ad1123017b504795e613ec6004e7d1eac4f74f5f Author: Furquan Shaikh <furquan(a)google.com> Date: Wed Jun 29 13:06:52 2016 -0700 google/reef: Enable touchscreen in ACPI Add support for ELAN touchscreen on I2C3. Change-Id: Id8b07a3a3fd4beca0d7ce804ba8d6859275c70d9 Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- src/mainboard/google/reef/acpi/mainboard.asl | 32 ++++++++++++++++++++++++++++ src/mainboard/google/reef/gpio.h | 1 + 2 files changed, 33 insertions(+) diff --git a/src/mainboard/google/reef/acpi/mainboard.asl b/src/mainboard/google/reef/acpi/mainboard.asl index 5471488..d6f9289 100644 --- a/src/mainboard/google/reef/acpi/mainboard.asl +++ b/src/mainboard/google/reef/acpi/mainboard.asl @@ -33,6 +33,38 @@ Scope (\_SB) } } +Scope (\_SB.PCI0.I2C3) +{ + Device (ETSA) + { + Name (_HID, "ELAN0001") + Name (_DDN, "Elan Touchscreen") + Name (_UID, 1) + Name (ISTP, 0) /* TouchScreen */ + Name (_S0W, 4) + + Name (_CRS, ResourceTemplate() + { + I2cSerialBus ( + 0x10, // SlaveAddress + ControllerInitiated, // SlaveMode + 400000, // ConnectionSpeed + AddressingMode7Bit, // AddressingMode + "\\_SB.PCI0.I2C3", // ResourceSource + ) + Interrupt (ResourceConsumer, Edge, ActiveLow) + { + TOUCHSCREEN_INT + } + }) + + Method (_STA) + { + Return (0xF) + } + } +} + Scope (\_SB.PCI0.I2C4) { /* Standard Mode: HCNT, LCNT, SDA Hold Register */ diff --git a/src/mainboard/google/reef/gpio.h b/src/mainboard/google/reef/gpio.h index b41f5f9..b491dfe 100644 --- a/src/mainboard/google/reef/gpio.h +++ b/src/mainboard/google/reef/gpio.h @@ -20,6 +20,7 @@ /* Input device interrupt configuration */ #define TOUCHPAD_INT GPIO_18_IRQ +#define TOUCHSCREEN_INT GPIO_21_IRQ #ifndef __ACPI__ /*

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New patch to review for coreboot: vbnv: Do not initialize vbnv_copy in vbnv layer
by Furquan Shaikh 29 Jun '16

29 Jun '16

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15498 -gerrit commit 3afe52e05ed70baf971ccc98a52df8b8bde74b64 Author: Furquan Shaikh <furquan(a)google.com> Date: Wed Jun 29 11:26:27 2016 -0700 vbnv: Do not initialize vbnv_copy in vbnv layer If read_vbnv finds that the vbnv_copy is not valid, it initializes it with the correct HEADER_SIGNATURE and other attributes. However, the vbnv copy is checked for validity and initialized at the vboot layer as well. Since, vboot is the owner of this data, it should be the one initializing it. Thus, if read_vbnv sees that the data is not valid, simply reset it to all 0s and let vboot layer take care of it. This also removes the need for additional checks to ensure that the dirty vbnv copy is properly updated on storage. Change-Id: I6101ac41f31f720a6e357c9c56e571d62e0f2f47 Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- src/vendorcode/google/chromeos/vbnv.c | 14 +++----------- src/vendorcode/google/chromeos/vbnv.h | 7 +------ src/vendorcode/google/chromeos/vboot2/vboot_logic.c | 8 ++------ 3 files changed, 6 insertions(+), 23 deletions(-) diff --git a/src/vendorcode/google/chromeos/vbnv.c b/src/vendorcode/google/chromeos/vbnv.c index baccb23..d900775 100644 --- a/src/vendorcode/google/chromeos/vbnv.c +++ b/src/vendorcode/google/chromeos/vbnv.c @@ -63,10 +63,6 @@ static uint8_t crc8_vbnv(const uint8_t *data, int len) static void reset_vbnv(uint8_t *vbnv_copy) { memset(vbnv_copy, 0, VBNV_BLOCK_SIZE); - vbnv_copy[HEADER_OFFSET] = HEADER_SIGNATURE | - HEADER_FIRMWARE_SETTINGS_RESET | - HEADER_KERNEL_SETTINGS_RESET; - vbnv_copy[CRC_OFFSET] = crc8_vbnv(vbnv_copy, CRC_OFFSET); } /* Read VBNV data into cache. */ @@ -88,9 +84,8 @@ int verify_vbnv(uint8_t *vbnv_copy) /* * Read VBNV data from configured storage backend. * If VBNV verification fails, reset the vbnv copy. - * Returns 1 if write-back of vbnv copy is required. Else, returns 0. */ -int read_vbnv(uint8_t *vbnv_copy) +void read_vbnv(uint8_t *vbnv_copy) { if (IS_ENABLED(CONFIG_CHROMEOS_VBNV_CMOS)) read_vbnv_cmos(vbnv_copy); @@ -100,11 +95,8 @@ int read_vbnv(uint8_t *vbnv_copy) read_vbnv_flash(vbnv_copy); /* Check data for consistency */ - if (verify_vbnv(vbnv_copy)) - return 0; - - reset_vbnv(vbnv_copy); - return 1; + if (!verify_vbnv(vbnv_copy)) + reset_vbnv(vbnv_copy); } /* diff --git a/src/vendorcode/google/chromeos/vbnv.h b/src/vendorcode/google/chromeos/vbnv.h index a66d687..5d21cc8 100644 --- a/src/vendorcode/google/chromeos/vbnv.h +++ b/src/vendorcode/google/chromeos/vbnv.h @@ -19,12 +19,7 @@ #include <types.h> /* Generic functions */ -/* - * Return value for read_vbnv: - * 1 = write-back of vbnv copy is required. - * 0 = otherwise - */ -int read_vbnv(uint8_t *vbnv_copy); +void read_vbnv(uint8_t *vbnv_copy); void save_vbnv(const uint8_t *vbnv_copy); int verify_vbnv(uint8_t *vbnv_copy); int get_recovery_mode_from_vbnv(void); diff --git a/src/vendorcode/google/chromeos/vboot2/vboot_logic.c b/src/vendorcode/google/chromeos/vboot2/vboot_logic.c index 116c949..4c799c9 100644 --- a/src/vendorcode/google/chromeos/vboot2/vboot_logic.c +++ b/src/vendorcode/google/chromeos/vboot2/vboot_logic.c @@ -301,12 +301,8 @@ void verstage_main(void) /* Set up context and work buffer */ vb2_init_work_context(&ctx); - /* - * Read nvdata from a non-volatile storage and mark data as changed - * if instructed. - */ - if (read_vbnv(ctx.nvdata)) - ctx.flags |= VB2_CONTEXT_NVDATA_CHANGED; + /* Read nvdata from a non-volatile storage. */ + read_vbnv(ctx.nvdata); /* Set S3 resume flag if vboot should behave differently when selecting * which slot to boot. This is only relevant to vboot if the platform

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New patch to review for coreboot: intel/amenia: keep ISH enabled for now
by Lijian Zhao 29 Jun '16

29 Jun '16

Lijian Zhao (lijian.zhao(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15497 -gerrit commit 98f79223491a46c1204a8dd275b78d423c5662c4 Author: Zhao, Lijian <lijian.zhao(a)intel.com> Date: Tue Jun 28 11:34:29 2016 -0700 intel/amenia: keep ISH enabled for now Disable ISH causes reset in FSP, this should be fixed in later stepping, util then keep ISH enabled. BUG= None TEST=Boot up into OS Change-Id: I6319cd9f2fd27893b389ea0f10c8fe5a5a191432 Signed-off-by: Zhao, Lijian <lijian.zhao(a)intel.com> --- src/mainboard/intel/amenia/devicetree.cb | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/intel/amenia/devicetree.cb b/src/mainboard/intel/amenia/devicetree.cb index 2080d6f..36abe97 100644 --- a/src/mainboard/intel/amenia/devicetree.cb +++ b/src/mainboard/intel/amenia/devicetree.cb @@ -8,7 +8,7 @@ chip soc/intel/apollolake register "pcie_rp2_clkreq_pin" = "0" # SSD # Integrated Sensor Hub - register "integrated_sensor_hub_enable" = "0" + register "integrated_sensor_hub_enable" = "1" # EMMC TX DATA Delay 1# # 0x1A[14:8] stands for 26*125 = 3250 pSec delay for HS400

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Patch merged into coreboot/master: soc/intel/apollolake: Change PCI macros to match Skylake
by gerrit＠coreboot.org 29 Jun '16

29 Jun '16

the following patch was just integrated into master: commit 78461a9d55de07f3187b48dfd6abca48db90e906 Author: Andrey Petrov <andrey.petrov(a)intel.com> Date: Tue Jun 28 12:14:33 2016 -0700 soc/intel/apollolake: Change PCI macros to match Skylake Change PCI macros in such a way they can be transparently used across romstage and ramstage. Change-Id: Idc708c1990f2fc1d941bb82efcb0a697524f2eca Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> Reviewed-on: https://review.coreboot.org/15483 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See https://review.coreboot.org/15483 for details. -gerrit

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Patch set updated for coreboot: soc/intel/skylake: fix nhlt/ssm4567.c indention
by Aaron Durbin 29 Jun '16

29 Jun '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15487 -gerrit commit 43fe48ac1292ec2a59cbfe561c6ee5fbfa77a066 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Jun 28 15:18:39 2016 -0500 soc/intel/skylake: fix nhlt/ssm4567.c indention Whitespace fix for improper space usage for indention. Change-Id: Ia6470bf152c57786d2d7f3d35bbf0609a2ee3ba2 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/soc/intel/skylake/nhlt/ssm4567.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/src/soc/intel/skylake/nhlt/ssm4567.c b/src/soc/intel/skylake/nhlt/ssm4567.c index 9248209..55d9481 100644 --- a/src/soc/intel/skylake/nhlt/ssm4567.c +++ b/src/soc/intel/skylake/nhlt/ssm4567.c @@ -29,14 +29,14 @@ static const struct nhlt_format_config ssm4567_render_cfg[] = { /* Capture Blob used for IV feedback for Speaker Protection Algorithm */ static const struct nhlt_format_config ssm4567_capture_cfg[] = { - /* 48 KHz 32-bits per sample. */ - { - .num_channels = 4, - .sample_freq_khz = 48, - .container_bits_per_sample = 32, - .valid_bits_per_sample = 32, - .settings_file = "ssm4567-capture-4ch-48khz-32b.bin", - }, + /* 48 KHz 32-bits per sample. */ + { + .num_channels = 4, + .sample_freq_khz = 48, + .container_bits_per_sample = 32, + .valid_bits_per_sample = 32, + .settings_file = "ssm4567-capture-4ch-48khz-32b.bin", + }, }; int nhlt_soc_add_ssm4567(struct nhlt *nhlt, int hwlink)

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Patch set updated for coreboot: lib/nhlt: drop nhlt_soc_add_endpoint()
by Aaron Durbin 29 Jun '16

29 Jun '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15489 -gerrit commit 45443cc72a0efb5dfc91639a2120ded3043a51dd Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Jun 28 15:36:01 2016 -0500 lib/nhlt: drop nhlt_soc_add_endpoint() The nhlt_soc_add_endpoint() is no longer used. Drop its declaration. Change-Id: I3b68471650a43c5faae44bde523abca7ba250a34 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/include/nhlt.h | 10 ++-------- 1 file changed, 2 insertions(+), 8 deletions(-) diff --git a/src/include/nhlt.h b/src/include/nhlt.h index 3300d43..17b7d11 100644 --- a/src/include/nhlt.h +++ b/src/include/nhlt.h @@ -45,7 +45,7 @@ struct nhlt_format_config; * An example sequence: * * nhlt = nhlt_init() - * ep = nhlt_soc_add_endpoint() + * ep = nhlt_add_endpoint() * nhlt_endpoint_append_config(ep) * nhlt_endpoint_add_formats(ep) * nhlt_soc_serialize() @@ -97,19 +97,13 @@ int nhlt_add_ssp_endpoints(struct nhlt *nhlt, int virtual_bus_id, /* * Add endpoint to NHLT object. Returns NULL on error. * - * Note that the SoC variant uses SoC-specifc types for the hardware interface - * and device types. This is to allow the SoC code to validate its particular - * device support for specific hardware interfaces. - * - * The more generic nhlt_add_endpoint() is called by the SoC code to provide + * generic nhlt_add_endpoint() is called by the SoC code to provide * the specific assumptions/uses for NHLT for that platform. All fields * are the NHLT enumerations found within this header file. */ struct nhlt_endpoint *nhlt_add_endpoint(struct nhlt *nhlt, int link_type, int device_type, int dir, uint16_t vid, uint16_t did); -struct nhlt_endpoint *nhlt_soc_add_endpoint(struct nhlt *nhlt, int soc_hwintf, - int soc_devtype, int dir); /* * Append blob of configuration to the endpoint proper. Returns 0 on

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Patch set updated for coreboot: lib/nhlt: add helper functions for adding endpoints
by Aaron Durbin 29 Jun '16

29 Jun '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15486 -gerrit commit 36870838dc67148a1d1f8a768e399f1323c2cd70 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Jun 28 14:59:21 2016 -0500 lib/nhlt: add helper functions for adding endpoints In order to ease the porting of supporting NHLT endpoints introduce a nhlt_endpoint_descriptor structure as well as corresponding helper functions. Change-Id: I68edaf681b4e60502f6ddbbd04de21d8aa072296 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/include/nhlt.h | 37 +++++++++++++++++++++++++++++++++ src/lib/nhlt.c | 60 +++++++++++++++++++++++++++++++++++++++++++++++++++++- 2 files changed, 96 insertions(+), 1 deletion(-) diff --git a/src/include/nhlt.h b/src/include/nhlt.h index f0b3b6f..3300d43 100644 --- a/src/include/nhlt.h +++ b/src/include/nhlt.h @@ -58,6 +58,43 @@ struct nhlt *nhlt_init(void); size_t nhlt_current_size(struct nhlt *nhlt); /* + * Helper functions for adding NHLT devices utilizing an nhlt_endp_descriptor + * to drive the logic. + */ + +struct nhlt_endp_descriptor { + /* NHLT endpoint types. */ + int link; + int device; + int direction; + uint16_t vid; + uint16_t did; + /* Optional endpoint specific configuration data. */ + const void *cfg; + size_t cfg_size; + /* Formats supported for endpoint. */ + const struct nhlt_format_config *formats; + size_t num_formats; +}; + +/* + * Add the number of endpoints described by each descriptor. The virtual bus + * id for each descriptor is the default value of 0. + * Returns < 0 on error, 0 on success. + */ +int nhlt_add_endpoints(struct nhlt *nhlt, + const struct nhlt_endp_descriptor *epds, + size_t num_epds); + +/* + * Add the number of endpoints associated with a single NHLT SSP instance id. + * Each endpoint described in the endpoint descriptor array uses the provided + * virtual bus id. Returns < 0 on error, 0 on success. + */ +int nhlt_add_ssp_endpoints(struct nhlt *nhlt, int virtual_bus_id, + const struct nhlt_endp_descriptor *epds, size_t num_epds); + +/* * Add endpoint to NHLT object. Returns NULL on error. * * Note that the SoC variant uses SoC-specifc types for the hardware interface diff --git a/src/lib/nhlt.c b/src/lib/nhlt.c index 11a397c..7bf8ce8 100644 --- a/src/lib/nhlt.c +++ b/src/lib/nhlt.c @@ -24,6 +24,7 @@ #define NHLT_RID 1 #define NHLT_SSID 1 #define WAVEFORMAT_TAG 0xfffe +#define DEFAULT_VIRTUAL_BUS_ID 0 static const struct sub_format pcm_subformat = { .data1 = 0x00000001, @@ -68,7 +69,7 @@ struct nhlt_endpoint *nhlt_add_endpoint(struct nhlt *nhlt, int link_type, endp->subsystem_id = NHLT_SSID; endp->device_type = device_type; endp->direction = dir; - endp->virtual_bus_id = 0; + endp->virtual_bus_id = DEFAULT_VIRTUAL_BUS_ID; nhlt->num_endpoints++; @@ -437,3 +438,60 @@ uintptr_t nhlt_serialize_oem_overrides(struct nhlt *nhlt, return acpi_addr; } + +static int _nhlt_add_single_endpoint(struct nhlt *nhlt, int virtual_bus_id, + const struct nhlt_endp_descriptor *epd) +{ + struct nhlt_endpoint *endp; + + endp = nhlt_add_endpoint(nhlt, epd->link, epd->device, epd->direction, + epd->vid, epd->did); + + if (endp == NULL) + return -1; + + endp->virtual_bus_id = virtual_bus_id; + + if (nhlt_endpoint_append_config(endp, epd->cfg, epd->cfg_size)) + return -1; + + if (nhlt_endpoint_add_formats(endp, epd->formats, epd->num_formats)) + return -1; + + return 0; +} + +static int _nhlt_add_endpoints(struct nhlt *nhlt, int virtual_bus_id, + const struct nhlt_endp_descriptor *epds, + size_t num_epds) +{ + size_t i; + + for (i = 0; i < num_epds; i++) + if (_nhlt_add_single_endpoint(nhlt, virtual_bus_id, &epds[i])) + return -1; + + return 0; +} + +int nhlt_add_endpoints(struct nhlt *nhlt, + const struct nhlt_endp_descriptor *epds, + size_t num_epds) +{ + int ret; + ret = _nhlt_add_endpoints(nhlt, DEFAULT_VIRTUAL_BUS_ID, epds, num_epds); + return ret; +} + +int nhlt_add_ssp_endpoints(struct nhlt *nhlt, int virtual_bus_id, + const struct nhlt_endp_descriptor *epds, size_t num_epds) +{ + int ret; + + ret = _nhlt_add_endpoints(nhlt, virtual_bus_id, epds, num_epds); + + if (!ret) + nhlt_next_instance(nhlt, NHLT_LINK_SSP); + + return ret; +}

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Patch set updated for coreboot: soc/intel/skylake: refactor nhlt support
by Aaron Durbin 29 Jun '16

29 Jun '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15488 -gerrit commit 058be3c79d8677bc0eaea3e8ffcff6ccf0dcf75d Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Jun 28 15:00:30 2016 -0500 soc/intel/skylake: refactor nhlt support Utilize the new NHLT helper functions by driving the NHLT endpoints through data descriptors. Change-Id: I80838214d3615b83d4939ec2d96a4fd7050d5920 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/soc/intel/skylake/include/soc/nhlt.h | 15 +++--- src/soc/intel/skylake/nhlt/dmic.c | 81 +++++++++++++++++++------------- src/soc/intel/skylake/nhlt/max98357.c | 33 +++++++------ src/soc/intel/skylake/nhlt/nau88l25.c | 74 ++++++++++++++--------------- src/soc/intel/skylake/nhlt/nhlt.c | 70 +-------------------------- src/soc/intel/skylake/nhlt/ssm4567.c | 57 +++++++++++----------- 6 files changed, 136 insertions(+), 194 deletions(-) diff --git a/src/soc/intel/skylake/include/soc/nhlt.h b/src/soc/intel/skylake/include/soc/nhlt.h index 3800bb9..008dd0d 100644 --- a/src/soc/intel/skylake/include/soc/nhlt.h +++ b/src/soc/intel/skylake/include/soc/nhlt.h @@ -18,9 +18,14 @@ #include <nhlt.h> +#define NHLT_VID 0x8086 +#define NHLT_DID_DMIC 0xae20 +#define NHLT_DID_BT 0xae30 +#define NHLT_DID_SSP 0xae34 + /* - * Skylake NHLT device and hardware link types. These values are to be used - * with nhlt_soc_add_endpoint(). + * Skylake NHLT link types. These values are to be used for the hwlink + * fields in the functions below to specify which link a device is on. */ enum { @@ -30,12 +35,6 @@ enum { AUDIO_LINK_DMIC, }; -enum { - AUDIO_DEV_I2S, - AUDIO_DEV_DMIC, - AUDIO_DEV_BT, -}; - /* * Add a dmic array composed of the provided number of channels. The skylake * SoC currently only supports dmic arrays on the dmic signals. Either 2 diff --git a/src/soc/intel/skylake/nhlt/dmic.c b/src/soc/intel/skylake/nhlt/dmic.c index 6e14891..a7684bd 100644 --- a/src/soc/intel/skylake/nhlt/dmic.c +++ b/src/soc/intel/skylake/nhlt/dmic.c @@ -14,9 +14,8 @@ */ #include <soc/nhlt.h> -#include <string.h> -static const struct nhlt_format_config dmic_2ch_cfg[] = { +static const struct nhlt_format_config dmic_2ch_formats[] = { /* 48 KHz 16-bits per sample. */ { .num_channels = 2, @@ -37,7 +36,28 @@ static const struct nhlt_format_config dmic_2ch_cfg[] = { }, }; -static const struct nhlt_format_config dmic_4ch_cfg[] = { +static const struct nhlt_dmic_array_config dmic_2ch_mic_config = { + .tdm_config = { + .config_type = NHLT_TDM_MIC_ARRAY, + }, + .array_type = NHLT_MIC_ARRAY_2CH_SMALL, +}; + +static const struct nhlt_endp_descriptor dmic_2ch_descriptors[] = { + { + .link = NHLT_LINK_PDM, + .device = NHLT_PDM_DEV, + .direction = NHLT_DIR_CAPTURE, + .vid = NHLT_VID, + .did = NHLT_DID_DMIC, + .cfg = &dmic_2ch_mic_config, + .cfg_size = sizeof(dmic_2ch_mic_config), + .formats = dmic_2ch_formats, + .num_formats = ARRAY_SIZE(dmic_2ch_formats), + }, +}; + +static const struct nhlt_format_config dmic_4ch_formats[] = { /* 48 KHz 16-bits per sample. */ { .num_channels = 4, @@ -60,42 +80,37 @@ static const struct nhlt_format_config dmic_4ch_cfg[] = { }, }; -int nhlt_soc_add_dmic_array(struct nhlt *nhlt, int num_channels) -{ - struct nhlt_endpoint *endp; - struct nhlt_dmic_array_config mic_config; - const struct nhlt_format_config *formats; - size_t num_formats; - - if (num_channels != 2 && num_channels != 4) - return -1; - - endp = nhlt_soc_add_endpoint(nhlt, AUDIO_LINK_DMIC, AUDIO_DEV_DMIC, - NHLT_DIR_CAPTURE); - - if (endp == NULL) - return -1; +static const struct nhlt_dmic_array_config dmic_4ch_mic_config = { + .tdm_config = { + .config_type = NHLT_TDM_MIC_ARRAY, + }, + .array_type = NHLT_MIC_ARRAY_4CH_L_SHAPED, +}; - memset(&mic_config, 0, sizeof(mic_config)); - mic_config.tdm_config.config_type = NHLT_TDM_MIC_ARRAY; +static const struct nhlt_endp_descriptor dmic_4ch_descriptors[] = { + { + .link = NHLT_LINK_PDM, + .device = NHLT_PDM_DEV, + .direction = NHLT_DIR_CAPTURE, + .vid = NHLT_VID, + .did = NHLT_DID_DMIC, + .cfg = &dmic_4ch_mic_config, + .cfg_size = sizeof(dmic_4ch_mic_config), + .formats = dmic_4ch_formats, + .num_formats = ARRAY_SIZE(dmic_4ch_formats), + }, +}; +int nhlt_soc_add_dmic_array(struct nhlt *nhlt, int num_channels) +{ switch (num_channels) { case 2: - formats = dmic_2ch_cfg; - num_formats = ARRAY_SIZE(dmic_2ch_cfg); - mic_config.array_type = NHLT_MIC_ARRAY_2CH_SMALL; - break; + return nhlt_add_endpoints(nhlt, dmic_2ch_descriptors, + ARRAY_SIZE(dmic_2ch_descriptors)); case 4: - formats = dmic_4ch_cfg; - num_formats = ARRAY_SIZE(dmic_4ch_cfg); - mic_config.array_type = NHLT_MIC_ARRAY_4CH_L_SHAPED; - break; + return nhlt_add_endpoints(nhlt, dmic_4ch_descriptors, + ARRAY_SIZE(dmic_4ch_descriptors)); default: return -1; } - - if (nhlt_endpoint_append_config(endp, &mic_config, sizeof(mic_config))) - return -1; - - return nhlt_endpoint_add_formats(endp, formats, num_formats); } diff --git a/src/soc/intel/skylake/nhlt/max98357.c b/src/soc/intel/skylake/nhlt/max98357.c index fa14dd2..b2abc26 100644 --- a/src/soc/intel/skylake/nhlt/max98357.c +++ b/src/soc/intel/skylake/nhlt/max98357.c @@ -15,7 +15,7 @@ #include <soc/nhlt.h> -static const struct nhlt_format_config max98357_render_cfg[] = { +static const struct nhlt_format_config max98357_render_formats[] = { /* 48 KHz 24-bits per sample. */ { .num_channels = 2, @@ -27,22 +27,21 @@ static const struct nhlt_format_config max98357_render_cfg[] = { }, }; +static const struct nhlt_endp_descriptor max98357_descriptors[] = { + { + .link = NHLT_LINK_SSP, + .device = NHLT_SSP_DEV_I2S, + .direction = NHLT_DIR_RENDER, + .vid = NHLT_VID, + .did = NHLT_DID_SSP, + .formats = max98357_render_formats, + .num_formats = ARRAY_SIZE(max98357_render_formats), + }, +}; + int nhlt_soc_add_max98357(struct nhlt *nhlt, int hwlink) { - struct nhlt_endpoint *endp; - - /* Render Endpoint */ - endp = nhlt_soc_add_endpoint(nhlt, hwlink, AUDIO_DEV_I2S, - NHLT_DIR_RENDER); - - if (endp == NULL) - return -1; - - if (nhlt_endpoint_add_formats(endp, max98357_render_cfg, - ARRAY_SIZE(max98357_render_cfg))) - return -1; - - nhlt_next_instance(nhlt, NHLT_LINK_SSP); - - return 0; + /* Virtual bus id of SSP links are the hardware port ids proper. */ + return nhlt_add_ssp_endpoints(nhlt, hwlink, max98357_descriptors, + ARRAY_SIZE(max98357_descriptors)); } diff --git a/src/soc/intel/skylake/nhlt/nau88l25.c b/src/soc/intel/skylake/nhlt/nau88l25.c index 0a6dd1b..dd91435 100644 --- a/src/soc/intel/skylake/nhlt/nau88l25.c +++ b/src/soc/intel/skylake/nhlt/nau88l25.c @@ -17,7 +17,7 @@ /* The same DSP firmware settings are used for both the capture and * render endpoints. */ -static const struct nhlt_format_config nau88l25_cfg[] = { +static const struct nhlt_format_config nau88l25_formats[] = { /* 48 KHz 24-bits per sample. */ { .num_channels = 2, @@ -29,45 +29,43 @@ static const struct nhlt_format_config nau88l25_cfg[] = { }, }; -int nhlt_soc_add_nau88l25(struct nhlt *nhlt, int hwlink) -{ - struct nhlt_endpoint *endp; - /* The nau88l25 just has headphones and a mic. Both the capture and - * render endpoints occupy the same virtual slot. */ - struct nhlt_tdm_config tdm_config = { - .virtual_slot = 0, - .config_type = NHLT_TDM_BASIC, - }; - const void *fmt_cfg = nau88l25_cfg; - size_t fmt_sz = ARRAY_SIZE(nau88l25_cfg); +/* The nau88l25 just has headphones and a mic. Both the capture and render + * endpoints occupy the same virtual slot. */ +static const struct nhlt_tdm_config tdm_config = { + .virtual_slot = 0, + .config_type = NHLT_TDM_BASIC, +}; +static const struct nhlt_endp_descriptor nau88l25_descriptors[] = { /* Render Endpoint */ - endp = nhlt_soc_add_endpoint(nhlt, hwlink, AUDIO_DEV_I2S, - NHLT_DIR_RENDER); - - if (endp == NULL) - return -1; - - if (nhlt_endpoint_append_config(endp, &tdm_config, sizeof(tdm_config))) - return -1; - - if (nhlt_endpoint_add_formats(endp, fmt_cfg, fmt_sz)) - return -1; - + { + .link = NHLT_LINK_SSP, + .device = NHLT_SSP_DEV_I2S, + .direction = NHLT_DIR_RENDER, + .vid = NHLT_VID, + .did = NHLT_DID_SSP, + .cfg = &tdm_config, + .cfg_size = sizeof(tdm_config), + .formats = nau88l25_formats, + .num_formats = ARRAY_SIZE(nau88l25_formats), + }, /* Capture Endpoint */ - endp = nhlt_soc_add_endpoint(nhlt, hwlink, AUDIO_DEV_I2S, - NHLT_DIR_CAPTURE); - - if (endp == NULL) - return -1; - - if (nhlt_endpoint_append_config(endp, &tdm_config, sizeof(tdm_config))) - return -1; - - if (nhlt_endpoint_add_formats(endp, fmt_cfg, fmt_sz)) - return -1; - - nhlt_next_instance(nhlt, NHLT_LINK_SSP); + { + .link = NHLT_LINK_SSP, + .device = NHLT_SSP_DEV_I2S, + .direction = NHLT_DIR_CAPTURE, + .vid = NHLT_VID, + .did = NHLT_DID_SSP, + .cfg = &tdm_config, + .cfg_size = sizeof(tdm_config), + .formats = nau88l25_formats, + .num_formats = ARRAY_SIZE(nau88l25_formats), + }, +}; - return 0; +int nhlt_soc_add_nau88l25(struct nhlt *nhlt, int hwlink) +{ + /* Virtual bus id of SSP links are the hardware port ids proper. */ + return nhlt_add_ssp_endpoints(nhlt, hwlink, nau88l25_descriptors, + ARRAY_SIZE(nau88l25_descriptors)); } diff --git a/src/soc/intel/skylake/nhlt/nhlt.c b/src/soc/intel/skylake/nhlt/nhlt.c index 6ef906a..d498152 100644 --- a/src/soc/intel/skylake/nhlt/nhlt.c +++ b/src/soc/intel/skylake/nhlt/nhlt.c @@ -14,76 +14,8 @@ */ #include <cbmem.h> +#include <nhlt.h> #include <soc/acpi.h> -#include <soc/nhlt.h> - -#define NHLT_VID 0x8086 -#define NHLT_DID_DMIC 0xae20 -#define NHLT_DID_BT 0xae30 -#define NHLT_DID_SSP 0xae34 - -struct nhlt_endpoint *nhlt_soc_add_endpoint(struct nhlt *nhlt, int soc_hwintf, - int soc_devtype, int dir) -{ - int nhlt_link_type; - int nhlt_dev_type; - uint16_t did; - struct nhlt_endpoint *endp; - - /* Check link type and device type. */ - switch (soc_hwintf) { - case AUDIO_LINK_SSP0: - case AUDIO_LINK_SSP1: - /* Only I2S devices on SSP0 and SSP1. */ - if (soc_devtype != AUDIO_DEV_I2S) - return NULL; - nhlt_link_type = NHLT_LINK_SSP; - break; - case AUDIO_LINK_SSP2: - /* Only Bluetooth devices on SSP2. */ - if (soc_devtype != AUDIO_DEV_BT) - return NULL; - nhlt_link_type = NHLT_LINK_SSP; - break; - case AUDIO_LINK_DMIC: - /* Only DMIC devices on DMIC links. */ - if (soc_devtype != AUDIO_DEV_DMIC) - return NULL; - nhlt_link_type = NHLT_LINK_PDM; - break; - default: - return NULL; - } - - switch (soc_devtype) { - case AUDIO_DEV_I2S: - nhlt_dev_type = NHLT_SSP_DEV_I2S; - did = NHLT_DID_SSP; - break; - case AUDIO_DEV_DMIC: - nhlt_dev_type = NHLT_PDM_DEV; - did = NHLT_DID_DMIC; - break; - case AUDIO_DEV_BT: - nhlt_dev_type = NHLT_SSP_DEV_BT; - did = NHLT_DID_BT; - break; - default: - return NULL; - } - - endp = nhlt_add_endpoint(nhlt, nhlt_link_type, nhlt_dev_type, dir, - NHLT_VID, did); - - if (endp == NULL) - return NULL; - - /* Virtual bus id of SSP links are the hardware port ids proper. */ - if (nhlt_link_type == NHLT_LINK_SSP) - endp->virtual_bus_id = soc_hwintf; - - return endp; -} uintptr_t nhlt_soc_serialize(struct nhlt *nhlt, uintptr_t acpi_addr) { diff --git a/src/soc/intel/skylake/nhlt/ssm4567.c b/src/soc/intel/skylake/nhlt/ssm4567.c index 55d9481..6808bff 100644 --- a/src/soc/intel/skylake/nhlt/ssm4567.c +++ b/src/soc/intel/skylake/nhlt/ssm4567.c @@ -15,7 +15,7 @@ #include <soc/nhlt.h> -static const struct nhlt_format_config ssm4567_render_cfg[] = { +static const struct nhlt_format_config ssm4567_render_formats[] = { /* 48 KHz 24-bits per sample. */ { .num_channels = 2, @@ -28,7 +28,7 @@ static const struct nhlt_format_config ssm4567_render_cfg[] = { }; /* Capture Blob used for IV feedback for Speaker Protection Algorithm */ -static const struct nhlt_format_config ssm4567_capture_cfg[] = { +static const struct nhlt_format_config ssm4567_capture_formats[] = { /* 48 KHz 32-bits per sample. */ { .num_channels = 4, @@ -39,33 +39,32 @@ static const struct nhlt_format_config ssm4567_capture_cfg[] = { }, }; -int nhlt_soc_add_ssm4567(struct nhlt *nhlt, int hwlink) -{ - struct nhlt_endpoint *endp; - +static const struct nhlt_endp_descriptor ssm4567_descriptors[] = { /* Render Endpoint */ - endp = nhlt_soc_add_endpoint(nhlt, hwlink, AUDIO_DEV_I2S, - NHLT_DIR_RENDER); - - if (endp == NULL) - return -1; - - if (nhlt_endpoint_add_formats(endp, ssm4567_render_cfg, - ARRAY_SIZE(ssm4567_render_cfg))) - return -1; - - /* Capture Endpoint for IV Feedback */ - endp = nhlt_soc_add_endpoint(nhlt, hwlink, AUDIO_DEV_I2S, - NHLT_DIR_CAPTURE); - - if (endp == NULL) - return -1; - - if (nhlt_endpoint_add_formats(endp, ssm4567_capture_cfg, - ARRAY_SIZE(ssm4567_capture_cfg))) - return -1; - - nhlt_next_instance(nhlt, NHLT_LINK_SSP); + { + .link = NHLT_LINK_SSP, + .device = NHLT_SSP_DEV_I2S, + .direction = NHLT_DIR_RENDER, + .vid = NHLT_VID, + .did = NHLT_DID_SSP, + .formats = ssm4567_render_formats, + .num_formats = ARRAY_SIZE(ssm4567_render_formats), + }, + /* Capture Endpoint */ + { + .link = NHLT_LINK_SSP, + .device = NHLT_SSP_DEV_I2S, + .direction = NHLT_DIR_CAPTURE, + .vid = NHLT_VID, + .did = NHLT_DID_SSP, + .formats = ssm4567_capture_formats, + .num_formats = ARRAY_SIZE(ssm4567_capture_formats), + }, +}; - return 0; +int nhlt_soc_add_ssm4567(struct nhlt *nhlt, int hwlink) +{ + /* Virtual bus id of SSP links are the hardware port ids proper. */ + return nhlt_add_ssp_endpoints(nhlt, hwlink, ssm4567_descriptors, + ARRAY_SIZE(ssm4567_descriptors)); }

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Patch set updated for coreboot: soc/intel/{common, skylake}: provide common NHLT SoC support
by Aaron Durbin 29 Jun '16

29 Jun '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15490 -gerrit commit 032a427437eca33dff1f67c4e6af3e80d7652ba9 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Jun 28 15:41:07 2016 -0500 soc/intel/{common,skylake}: provide common NHLT SoC support The nhlt_soc_serialize() and nhlt_soc_serialize_oem_overrides() functions should be able to be leveraged on all Intel SoCs which support NHLT. Therefore provide that functionality and make skylake use it. Change-Id: Ib5535cc874f2680ec22554cecaf97b09753cacd0 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/soc/intel/common/Kconfig | 4 ++++ src/soc/intel/common/Makefile.inc | 1 + src/soc/intel/common/nhlt.c | 41 +++++++++++++++++++++++++++++++++ src/soc/intel/skylake/Kconfig | 1 + src/soc/intel/skylake/nhlt/Makefile.inc | 1 - src/soc/intel/skylake/nhlt/nhlt.c | 41 --------------------------------- 6 files changed, 47 insertions(+), 42 deletions(-) diff --git a/src/soc/intel/common/Kconfig b/src/soc/intel/common/Kconfig index fdd8f04..776004b 100644 --- a/src/soc/intel/common/Kconfig +++ b/src/soc/intel/common/Kconfig @@ -99,4 +99,8 @@ config SOC_INTEL_COMMON_ACPI bool default n +config SOC_INTEL_COMMON_NHLT + bool + default n + endif # SOC_INTEL_COMMON diff --git a/src/soc/intel/common/Makefile.inc b/src/soc/intel/common/Makefile.inc index 88d5fd2..e9ad508 100644 --- a/src/soc/intel/common/Makefile.inc +++ b/src/soc/intel/common/Makefile.inc @@ -20,6 +20,7 @@ ramstage-$(CONFIG_SOC_INTEL_COMMON_ACPI_WAKE_SOURCE) += acpi_wake_source.c ramstage-y += vbt.c ramstage-$(CONFIG_SOC_INTEL_COMMON_GFX_OPREGION) += opregion.c ramstage-$(CONFIG_SOC_INTEL_COMMON_ACPI) += ./acpi/acpi.c +ramstage-$(CONFIG_SOC_INTEL_COMMON_NHLT) += nhlt.c smm-$(CONFIG_SOC_INTEL_COMMON_SMI) += smihandler.c diff --git a/src/soc/intel/common/nhlt.c b/src/soc/intel/common/nhlt.c new file mode 100644 index 0000000..d498152 --- /dev/null +++ b/src/soc/intel/common/nhlt.c @@ -0,0 +1,41 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 Google, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <cbmem.h> +#include <nhlt.h> +#include <soc/acpi.h> + +uintptr_t nhlt_soc_serialize(struct nhlt *nhlt, uintptr_t acpi_addr) +{ + return nhlt_soc_serialize_oem_overrides(nhlt, acpi_addr, NULL, NULL); +} + +uintptr_t nhlt_soc_serialize_oem_overrides(struct nhlt *nhlt, + uintptr_t acpi_addr, const char *oem_id, const char *oem_table_id) +{ + global_nvs_t *gnvs; + + gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); + + if (gnvs == NULL) + return acpi_addr; + + /* Update NHLT GNVS Data */ + gnvs->nhla = (uintptr_t)acpi_addr; + gnvs->nhll = nhlt_current_size(nhlt); + + return nhlt_serialize_oem_overrides(nhlt, acpi_addr, + oem_id, oem_table_id); +} diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index a134d1c..6843cef 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -38,6 +38,7 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE select SOC_INTEL_COMMON_LPSS_I2C + select SOC_INTEL_COMMON_NHLT select SOC_INTEL_COMMON_RESET select SMM_TSEG select SMP diff --git a/src/soc/intel/skylake/nhlt/Makefile.inc b/src/soc/intel/skylake/nhlt/Makefile.inc index aff182c..e022482 100644 --- a/src/soc/intel/skylake/nhlt/Makefile.inc +++ b/src/soc/intel/skylake/nhlt/Makefile.inc @@ -1,4 +1,3 @@ -ramstage-y += nhlt.c ramstage-y += dmic.c ramstage-y += nau88l25.c ramstage-y += max98357.c diff --git a/src/soc/intel/skylake/nhlt/nhlt.c b/src/soc/intel/skylake/nhlt/nhlt.c deleted file mode 100644 index d498152..0000000 --- a/src/soc/intel/skylake/nhlt/nhlt.c +++ /dev/null @@ -1,41 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2015 Google, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <cbmem.h> -#include <nhlt.h> -#include <soc/acpi.h> - -uintptr_t nhlt_soc_serialize(struct nhlt *nhlt, uintptr_t acpi_addr) -{ - return nhlt_soc_serialize_oem_overrides(nhlt, acpi_addr, NULL, NULL); -} - -uintptr_t nhlt_soc_serialize_oem_overrides(struct nhlt *nhlt, - uintptr_t acpi_addr, const char *oem_id, const char *oem_table_id) -{ - global_nvs_t *gnvs; - - gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); - - if (gnvs == NULL) - return acpi_addr; - - /* Update NHLT GNVS Data */ - gnvs->nhla = (uintptr_t)acpi_addr; - gnvs->nhll = nhlt_current_size(nhlt); - - return nhlt_serialize_oem_overrides(nhlt, acpi_addr, - oem_id, oem_table_id); -}

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coreboot-gerrit June 2016