coreboot-gerrit June 2016

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: AMD k8 fam10: Use common ACPI S3 recovery
by Kyösti Mälkki 29 Jun '16

29 Jun '16

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15474 -gerrit commit e9417cd3f94f7259430e99bff11fbe5854696bab Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Mon Jun 27 12:53:00 2016 +0300 AMD k8 fam10: Use common ACPI S3 recovery Change-Id: I62bbba8cfe515b3cae413582ff8d062a20e6741b Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/cpu/amd/car/post_cache_as_ram.c | 43 +++++++------------------------ src/cpu/amd/family_10h-family_15h/Kconfig | 1 - src/cpu/amd/model_fxx/Kconfig | 1 - 3 files changed, 9 insertions(+), 36 deletions(-) diff --git a/src/cpu/amd/car/post_cache_as_ram.c b/src/cpu/amd/car/post_cache_as_ram.c index 9ed9769..24182cb 100644 --- a/src/cpu/amd/car/post_cache_as_ram.c +++ b/src/cpu/amd/car/post_cache_as_ram.c @@ -45,12 +45,6 @@ static void memcpy_(void *d, const void *s, size_t len) memcpy(d, s, len); } -static void memset_(void *d, int val, size_t len) -{ - print_car_debug(" Fill [%08x-%08x] ...", (uint32_t) d, (uint32_t) (d + len - 1)); - memset(d, val, len); -} - static int memcmp_(void *d, const void *s, size_t len) { print_car_debug(" Compare [%08x-%08x] with [%08x - %08x] ...", @@ -58,33 +52,6 @@ static int memcmp_(void *d, const void *s, size_t len) return memcmp(d, s, len); } -static void prepare_ramstage_region(int s3resume) -{ - print_car_debug("Prepare ramstage memory region..."); - - if (s3resume) { - void *resume_backup_memory = acpi_backup_container(CONFIG_RAMBASE, HIGH_MEMORY_SAVE); - if (resume_backup_memory) - memcpy_(resume_backup_memory, (void *) CONFIG_RAMBASE, - HIGH_MEMORY_SAVE); - memset_((void*) CONFIG_RAMBASE, 0, HIGH_MEMORY_SAVE); - } else { - memset_((void*)0, 0, CONFIG_RAMTOP); - } - -#if IS_ENABLED(CONFIG_HAVE_ROMSTAGE_CONSOLE_SPINLOCK) - initialize_romstage_console_lock(); -#endif -#if IS_ENABLED(CONFIG_HAVE_ROMSTAGE_NVRAM_CBFS_SPINLOCK) - initialize_romstage_nvram_cbfs_lock(); -#endif - - print_car_debug(" Done\n"); - - if (s3resume) - acpi_backup_validate(); -} - /* Disable Erratum 343 Workaround, see RevGuide for Fam10h, Pub#41322 Rev 3.33 * and RevGuide for Fam12h, Pub#44739 Rev 3.10 */ @@ -166,7 +133,15 @@ void cache_as_ram_new_stack (void) set_var_mtrr(0, 0x00000000, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK); enable_cache(); - prepare_ramstage_region(acpi_is_wakeup_s3()); + if (acpi_is_wakeup_s3()) + acpi_prepare_for_resume(); + +#if IS_ENABLED(CONFIG_HAVE_ROMSTAGE_CONSOLE_SPINLOCK) + initialize_romstage_console_lock(); +#endif +#if IS_ENABLED(CONFIG_HAVE_ROMSTAGE_NVRAM_CBFS_SPINLOCK) + initialize_romstage_nvram_cbfs_lock(); +#endif set_sysinfo_in_ram(1); // So other core0 could start to train mem diff --git a/src/cpu/amd/family_10h-family_15h/Kconfig b/src/cpu/amd/family_10h-family_15h/Kconfig index 30c7dee..fda7fc8 100644 --- a/src/cpu/amd/family_10h-family_15h/Kconfig +++ b/src/cpu/amd/family_10h-family_15h/Kconfig @@ -10,7 +10,6 @@ config CPU_AMD_MODEL_10XXX select TSC_SYNC_LFENCE select UDELAY_LAPIC select HAVE_MONOTONIC_TIMER - select ACPI_HUGE_LOWMEM_BACKUP select SUPPORT_CPU_UCODE_IN_CBFS select CPU_MICROCODE_MULTIPLE_FILES if !CPU_MICROCODE_CBFS_NONE diff --git a/src/cpu/amd/model_fxx/Kconfig b/src/cpu/amd/model_fxx/Kconfig index 3eb5b94..c8bae33 100644 --- a/src/cpu/amd/model_fxx/Kconfig +++ b/src/cpu/amd/model_fxx/Kconfig @@ -9,7 +9,6 @@ config CPU_AMD_MODEL_FXX select SSE2 select TSC_SYNC_LFENCE select UDELAY_LAPIC - select ACPI_HUGE_LOWMEM_BACKUP select SUPPORT_CPU_UCODE_IN_CBFS if CPU_AMD_MODEL_FXX

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Patch set updated for coreboot: AMD k8 fam10: Separate romstage ramstack (WIP)
by Kyösti Mälkki 29 Jun '16

29 Jun '16

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15473 -gerrit commit f0b2ee8ed4882e6815aee992c180054c777c70ca Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Mon Jun 27 19:45:19 2016 +0300 AMD k8 fam10: Separate romstage ramstack (WIP) Romstage ram stack was placed below RAMTOP. This is vulnerable location as a large ramstage could overwrite it. Location also prevents optimizing S3 resume path since all low memory between RAMBASE..RAMTOP has to be backed to CBMEM. When possible, place ram stack high. Change-Id: I4106e91ed3256aca5d0d115d4aa7e46b75b27eec Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/cpu/amd/car/post_cache_as_ram.c | 37 +++++++++---------------------------- 1 file changed, 9 insertions(+), 28 deletions(-) diff --git a/src/cpu/amd/car/post_cache_as_ram.c b/src/cpu/amd/car/post_cache_as_ram.c index 1951084..9ed9769 100644 --- a/src/cpu/amd/car/post_cache_as_ram.c +++ b/src/cpu/amd/car/post_cache_as_ram.c @@ -23,6 +23,7 @@ #include <cpu/amd/mtrr.h> #include <cpu/amd/car.h> #include <arch/acpi.h> +#include <program_loading.h> #include <romstage_handoff.h> #include "cbmem.h" #include "cpu/amd/car/disable_cache_as_ram.c" @@ -37,12 +38,6 @@ #define print_car_debug(format, arg...) #endif -static size_t backup_size(void) -{ - size_t car_size = car_data_size(); - return ALIGN(car_size + 1024, 1024); -} - static void memcpy_(void *d, const void *s, size_t len) { print_car_debug(" Copy [%08x-%08x] to [%08x - %08x] ...", @@ -63,35 +58,18 @@ static int memcmp_(void *d, const void *s, size_t len) return memcmp(d, s, len); } -static void prepare_romstage_ramstack(int s3resume) -{ - size_t backup_top = backup_size(); - print_car_debug("Prepare CAR migration and stack regions..."); - - if (s3resume) { - void *resume_backup_memory = acpi_backup_container(CONFIG_RAMBASE, HIGH_MEMORY_SAVE); - if (resume_backup_memory) - memcpy_(resume_backup_memory + HIGH_MEMORY_SAVE - backup_top, - (void *)(CONFIG_RAMTOP - backup_top), backup_top); - } - memset_((void *)(CONFIG_RAMTOP - backup_top), 0, backup_top); - - print_car_debug(" Done\n"); -} - static void prepare_ramstage_region(int s3resume) { - size_t backup_top = backup_size(); print_car_debug("Prepare ramstage memory region..."); if (s3resume) { void *resume_backup_memory = acpi_backup_container(CONFIG_RAMBASE, HIGH_MEMORY_SAVE); if (resume_backup_memory) memcpy_(resume_backup_memory, (void *) CONFIG_RAMBASE, - HIGH_MEMORY_SAVE - backup_top); - memset_((void*) CONFIG_RAMBASE, 0, HIGH_MEMORY_SAVE - backup_top); + HIGH_MEMORY_SAVE); + memset_((void*) CONFIG_RAMBASE, 0, HIGH_MEMORY_SAVE); } else { - memset_((void*)0, 0, CONFIG_RAMTOP - backup_top); + memset_((void*)0, 0, CONFIG_RAMTOP); } #if IS_ENABLED(CONFIG_HAVE_ROMSTAGE_CONSOLE_SPINLOCK) @@ -138,7 +116,10 @@ void post_cache_as_ram(void) if (IS_ENABLED(CONFIG_EARLY_CBMEM_INIT) || s3resume) cbmem_recovery(s3resume); - prepare_romstage_ramstack(s3resume); + /* FIXME: CBMEM stack is not wb-cacheable yet. */ + uintptr_t ramtop; + if (s3resume) + ramtop = romstage_ram_stack_top(); if (IS_ENABLED(CONFIG_EARLY_CBMEM_INIT)) { struct romstage_handoff *handoff; @@ -156,7 +137,7 @@ void post_cache_as_ram(void) } size_t car_size = car_data_size(); - void *migrated_car = (void *)(CONFIG_RAMTOP - car_size); + void *migrated_car = (void *)(ramtop - car_size); print_car_debug("Copying data from cache to RAM..."); memcpy_(migrated_car, _car_relocatable_data_start, car_size);

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Patch set updated for coreboot: AMD k8 fam10: Fix romstage handoff
by Kyösti Mälkki 29 Jun '16

29 Jun '16

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15472 -gerrit commit 9411d66e431b75a61244c28507b6e69ddf549436 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sun Jun 26 15:44:05 2016 +0300 AMD k8 fam10: Fix romstage handoff It is not possible for cbmem_add() to complete succesfully before cbmem_recovery() is called. Adding more tables on S3 resume path is also not possible. Change-Id: Ic14857eeef2932562acee4a36f59c22ff4ca1a84 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/cpu/amd/car/post_cache_as_ram.c | 19 +++++++++++-------- 1 file changed, 11 insertions(+), 8 deletions(-) diff --git a/src/cpu/amd/car/post_cache_as_ram.c b/src/cpu/amd/car/post_cache_as_ram.c index 7c03888..1951084 100644 --- a/src/cpu/amd/car/post_cache_as_ram.c +++ b/src/cpu/amd/car/post_cache_as_ram.c @@ -133,19 +133,22 @@ void post_cache_as_ram(void) if ((*lower_stack_boundary) != 0xdeadbeef) printk(BIOS_WARNING, "BSP overran lower stack boundary. Undefined behaviour may result!\n"); - struct romstage_handoff *handoff; - handoff = romstage_handoff_find_or_add(); - if (handoff != NULL) - handoff->s3_resume = acpi_is_wakeup_s3(); - else - printk(BIOS_DEBUG, "Romstage handoff structure not added!\n"); - int s3resume = acpi_is_wakeup_s3(); - if (s3resume) + + if (IS_ENABLED(CONFIG_EARLY_CBMEM_INIT) || s3resume) cbmem_recovery(s3resume); prepare_romstage_ramstack(s3resume); + if (IS_ENABLED(CONFIG_EARLY_CBMEM_INIT)) { + struct romstage_handoff *handoff; + handoff = romstage_handoff_find_or_add(); + if (handoff != NULL) + handoff->s3_resume = s3resume; + else + printk(BIOS_DEBUG, "Romstage handoff structure not added!\n"); + } + /* from here don't store more data in CAR */ if (family >= 0x1f && family <= 0x3f) { /* Family 10h and 12h, 11h until shown otherwise */

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Patch set updated for coreboot: quick_ram_check: Remove reference to RAMBASE (WIP)
by Kyösti Mälkki 29 Jun '16

29 Jun '16

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15239 -gerrit commit c69ffa919b6bb07bee1f14a61cae15821d89d963 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Fri Jun 17 23:31:42 2016 +0300 quick_ram_check: Remove reference to RAMBASE (WIP) TODO: Test at address cbmem_top() instead? TODO: lib/ramtest.c builds for arch/x86-only Change-Id: Ieb8f11690fb0e9b287d866be56010bb9adefd21d Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/lib/ramtest.c | 27 ++++++++++++++++----------- 1 file changed, 16 insertions(+), 11 deletions(-) diff --git a/src/lib/ramtest.c b/src/lib/ramtest.c index a29fa25..6d12060 100644 --- a/src/lib/ramtest.c +++ b/src/lib/ramtest.c @@ -181,32 +181,37 @@ int ram_check_noprint_nodie(unsigned long start, unsigned long stop) return failures; } -void quick_ram_check(void) +static void __quick_ram_check(uintptr_t dst) { int fail = 0; u32 backup; - backup = read_phys(CONFIG_RAMBASE); - write_phys(CONFIG_RAMBASE, 0x55555555); + backup = read_phys(dst); + write_phys(dst, 0x55555555); phys_memory_barrier(); - if (read_phys(CONFIG_RAMBASE) != 0x55555555) + if (read_phys(dst) != 0x55555555) fail=1; - write_phys(CONFIG_RAMBASE, 0xaaaaaaaa); + write_phys(dst, 0xaaaaaaaa); phys_memory_barrier(); - if (read_phys(CONFIG_RAMBASE) != 0xaaaaaaaa) + if (read_phys(dst) != 0xaaaaaaaa) fail=1; - write_phys(CONFIG_RAMBASE, 0x00000000); + write_phys(dst, 0x00000000); phys_memory_barrier(); - if (read_phys(CONFIG_RAMBASE) != 0x00000000) + if (read_phys(dst) != 0x00000000) fail=1; - write_phys(CONFIG_RAMBASE, 0xffffffff); + write_phys(dst, 0xffffffff); phys_memory_barrier(); - if (read_phys(CONFIG_RAMBASE) != 0xffffffff) + if (read_phys(dst) != 0xffffffff) fail=1; - write_phys(CONFIG_RAMBASE, backup); + write_phys(dst, backup); if (fail) { post_code(0xea); die("RAM INIT FAILURE!\n"); } phys_memory_barrier(); } + +void quick_ram_check(void) +{ + __quick_ram_check(0x100000); +}

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Patch set updated for coreboot: ACPI S3: Remove HIGH_MEMORY_SAVE where possible
by Kyösti Mälkki 29 Jun '16

29 Jun '16

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15255 -gerrit commit 4b4a17144a058ee82eb8e7a064d2c4b3952bea81 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Jun 28 07:38:46 2016 +0300 ACPI S3: Remove HIGH_MEMORY_SAVE where possible Use actual requirements of ramstage size for S3 resume backup in CBMEM. The backup covers complete pages of 4 KiB. AMD k8 and fam10 platforms have not been adapted yet. Change-Id: Ide7ce013f3727c2928cdb00fbcc7e7e84e859ff1 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/Kconfig | 4 ++ src/arch/x86/acpi_s3.c | 115 +++++++++++++++++++++++++----- src/arch/x86/include/arch/acpi.h | 8 +-- src/cpu/amd/car/post_cache_as_ram.c | 7 +- src/cpu/amd/family_10h-family_15h/Kconfig | 1 + src/cpu/amd/model_fxx/Kconfig | 1 + src/include/cbfs.h | 3 + src/include/program_loading.h | 4 ++ src/lib/cbfs.c | 12 ++++ src/lib/prog_loaders.c | 14 +++- 10 files changed, 142 insertions(+), 27 deletions(-) diff --git a/src/Kconfig b/src/Kconfig index 7043851..b4c3cbe 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -516,6 +516,10 @@ config HAVE_ACPI_RESUME bool default n +config ACPI_HUGE_LOWMEM_BACKUP + bool + default n + config RESUME_PATH_SAME_AS_BOOT bool default y if ARCH_X86 diff --git a/src/arch/x86/acpi_s3.c b/src/arch/x86/acpi_s3.c index 7855a2f..c744eb5 100644 --- a/src/arch/x86/acpi_s3.c +++ b/src/arch/x86/acpi_s3.c @@ -19,8 +19,10 @@ #include <cbmem.h> #include <cpu/cpu.h> #include <timestamp.h> +#include <program_loading.h> #include <romstage_handoff.h> #include <rules.h> +#include <symbols.h> #if ENV_RAMSTAGE @@ -79,30 +81,101 @@ void acpi_fail_wakeup(void) } #endif /* ENV_RAMSTAGE */ -void acpi_prepare_for_resume(void) +struct resume_backup { + uintptr_t cbmem; + uintptr_t lowmem; + size_t size; + int valid; +}; + +#define BACKUP_PAGE_SZ 4096 + +void *acpi_backup_container(uintptr_t base, size_t size) { - if (!HIGH_MEMORY_SAVE) + struct resume_backup *backup_mem; + uintptr_t top, target; + + if (IS_ENABLED(CONFIG_ACPI_HUGE_LOWMEM_BACKUP)) { + base = CONFIG_RAMBASE; + size = HIGH_MEMORY_SAVE; + } + + /* Align backup region to complete pages. */ + top = ALIGN_UP(base + size, BACKUP_PAGE_SZ); + base = ALIGN_DOWN(base, BACKUP_PAGE_SZ); + + /* FIXME: Check previous CBMEM allocation. */ + + /* Allocate storage with struct resume_backup. */ + size = 2*BACKUP_PAGE_SZ + (top - base); + backup_mem = cbmem_add(CBMEM_ID_RESUME, size); + if (backup_mem == NULL) + return NULL; + + /* Force alignment on the container itself.*/ + target = (uintptr_t)backup_mem + sizeof(*backup_mem); + target = ALIGN_UP(target, BACKUP_PAGE_SZ); + + backup_mem->valid = 0; + backup_mem->cbmem = target; + backup_mem->lowmem = base; + backup_mem->size = top - base; + + return (void*)target; +} + +void acpi_backup_validate(void) +{ + struct resume_backup *backup_mem = cbmem_find(CBMEM_ID_RESUME); + if (backup_mem) + backup_mem->valid = 1; +} + +void backup_ramstage_section(uintptr_t base, size_t size) +{ + struct resume_backup *backup_mem = cbmem_find(CBMEM_ID_RESUME); + if (backup_mem == NULL) + return; + + /* Check that the backup is not done twice. */ + if (backup_mem->valid) return; + /* We are called from ramstage loader, do not rely on previously + * loaded ramstage for location. */ + if (size) + acpi_backup_container(base, size); + /* Back up the OS-controlled memory where ramstage will be loaded. */ - void *src = (void *)CONFIG_RAMBASE; - void *dest = cbmem_find(CBMEM_ID_RESUME); - if (dest != NULL) - memcpy(dest, src, HIGH_MEMORY_SAVE); + memcpy((void*)backup_mem->cbmem, (void*)backup_mem->lowmem, backup_mem->size); + backup_mem->valid = 1; +} + +/* Make backup of low-memory region, relying on the base and size + * of the ramstage that was loaded before entry to ACPI S3. + * + * DEPRECATED + */ +void acpi_prepare_for_resume(void) +{ + backup_ramstage_section(0, 0); } +/* Let's prepare the ACPI S3 Resume area now already, so we can rely on + * it being there during reboot time. If this fails, ACPI resume will + * be disabled. We assume that ramstage does not change while in suspend, + * so base and size of the currently running ramstage are used + * for allocation. + */ void acpi_prepare_resume_backup(void) { if (!acpi_s3_resume_allowed()) return; - /* Let's prepare the ACPI S3 Resume area now already, so we can rely on - * it being there during reboot time. We don't need the pointer, nor - * the result right now. If it fails, ACPI resume will be disabled. - */ + if (IS_ENABLED(CONFIG_RELOCATABLE_RAMSTAGE)) + return; - if (HIGH_MEMORY_SAVE) - cbmem_add(CBMEM_ID_RESUME, HIGH_MEMORY_SAVE); + acpi_backup_container((uintptr_t)_program, _program_size); } #define WAKEUP_BASE 0x600 @@ -115,17 +188,22 @@ extern unsigned int __wakeup_size; static void acpi_jump_to_wakeup(void *vector) { - uintptr_t acpi_backup_memory = 0; + uintptr_t source = 0, target = 0; + size_t size = 0; if (!acpi_s3_resume_allowed()) { printk(BIOS_WARNING, "ACPI: S3 resume not allowed.\n"); return; } - if (HIGH_MEMORY_SAVE) { - acpi_backup_memory = (uintptr_t)cbmem_find(CBMEM_ID_RESUME); - - if (!acpi_backup_memory) { + if (!IS_ENABLED(CONFIG_RELOCATABLE_RAMSTAGE)) { + struct resume_backup *backup_mem = cbmem_find(CBMEM_ID_RESUME); + if (backup_mem && backup_mem->valid) { + backup_mem->valid = 0; + target = backup_mem->lowmem; + source = backup_mem->cbmem; + size = backup_mem->size; + } else { printk(BIOS_WARNING, "ACPI: Backup memory missing. " "No S3 resume.\n"); return; @@ -137,8 +215,7 @@ static void acpi_jump_to_wakeup(void *vector) timestamp_add_now(TS_ACPI_WAKE_JUMP); - acpi_do_wakeup((uintptr_t)vector, acpi_backup_memory, CONFIG_RAMBASE, - HIGH_MEMORY_SAVE); + acpi_do_wakeup((uintptr_t)vector, source, target, size); } void __attribute__((weak)) mainboard_suspend_resume(void) diff --git a/src/arch/x86/include/arch/acpi.h b/src/arch/x86/include/arch/acpi.h index 7434000..f40b9df 100644 --- a/src/arch/x86/include/arch/acpi.h +++ b/src/arch/x86/include/arch/acpi.h @@ -24,12 +24,7 @@ #ifndef __ASM_ACPI_H #define __ASM_ACPI_H -#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) && \ - ! IS_ENABLED(CONFIG_RELOCATABLE_RAMSTAGE) #define HIGH_MEMORY_SAVE (CONFIG_RAMTOP - CONFIG_RAMBASE) -#else -#define HIGH_MEMORY_SAVE 0 -#endif #ifndef __ASSEMBLER__ #include <stdint.h> @@ -623,6 +618,9 @@ static inline int acpi_s3_resume_allowed(void) return IS_ENABLED(CONFIG_HAVE_ACPI_RESUME); } +void *acpi_backup_container(uintptr_t base, size_t size); +void acpi_backup_validate(void); + #if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) extern int acpi_slp_type; diff --git a/src/cpu/amd/car/post_cache_as_ram.c b/src/cpu/amd/car/post_cache_as_ram.c index 15b2642..7c03888 100644 --- a/src/cpu/amd/car/post_cache_as_ram.c +++ b/src/cpu/amd/car/post_cache_as_ram.c @@ -69,7 +69,7 @@ static void prepare_romstage_ramstack(int s3resume) print_car_debug("Prepare CAR migration and stack regions..."); if (s3resume) { - void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME); + void *resume_backup_memory = acpi_backup_container(CONFIG_RAMBASE, HIGH_MEMORY_SAVE); if (resume_backup_memory) memcpy_(resume_backup_memory + HIGH_MEMORY_SAVE - backup_top, (void *)(CONFIG_RAMTOP - backup_top), backup_top); @@ -85,7 +85,7 @@ static void prepare_ramstage_region(int s3resume) print_car_debug("Prepare ramstage memory region..."); if (s3resume) { - void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME); + void *resume_backup_memory = acpi_backup_container(CONFIG_RAMBASE, HIGH_MEMORY_SAVE); if (resume_backup_memory) memcpy_(resume_backup_memory, (void *) CONFIG_RAMBASE, HIGH_MEMORY_SAVE - backup_top); @@ -102,6 +102,9 @@ static void prepare_ramstage_region(int s3resume) #endif print_car_debug(" Done\n"); + + if (s3resume) + acpi_backup_validate(); } /* Disable Erratum 343 Workaround, see RevGuide for Fam10h, Pub#41322 Rev 3.33 diff --git a/src/cpu/amd/family_10h-family_15h/Kconfig b/src/cpu/amd/family_10h-family_15h/Kconfig index fda7fc8..30c7dee 100644 --- a/src/cpu/amd/family_10h-family_15h/Kconfig +++ b/src/cpu/amd/family_10h-family_15h/Kconfig @@ -10,6 +10,7 @@ config CPU_AMD_MODEL_10XXX select TSC_SYNC_LFENCE select UDELAY_LAPIC select HAVE_MONOTONIC_TIMER + select ACPI_HUGE_LOWMEM_BACKUP select SUPPORT_CPU_UCODE_IN_CBFS select CPU_MICROCODE_MULTIPLE_FILES if !CPU_MICROCODE_CBFS_NONE diff --git a/src/cpu/amd/model_fxx/Kconfig b/src/cpu/amd/model_fxx/Kconfig index c8bae33..3eb5b94 100644 --- a/src/cpu/amd/model_fxx/Kconfig +++ b/src/cpu/amd/model_fxx/Kconfig @@ -9,6 +9,7 @@ config CPU_AMD_MODEL_FXX select SSE2 select TSC_SYNC_LFENCE select UDELAY_LAPIC + select ACPI_HUGE_LOWMEM_BACKUP select SUPPORT_CPU_UCODE_IN_CBFS if CPU_AMD_MODEL_FXX diff --git a/src/include/cbfs.h b/src/include/cbfs.h index 2d19218..6a9e054 100644 --- a/src/include/cbfs.h +++ b/src/include/cbfs.h @@ -43,6 +43,9 @@ void *cbfs_boot_map_with_leak(const char *name, uint32_t type, size_t *size); size_t cbfs_load_and_decompress(const struct region_device *rdev, size_t offset, size_t in_size, void *buffer, size_t buffer_size, uint32_t compression); +/* Fill base and size of the memory pstage will occupy when loaded. */ +void cbfs_prog_stage_section(struct prog *pstage, uint32_t *base, uint32_t *size); + /* Load stage into memory filling in prog. Return 0 on success. < 0 on error. */ int cbfs_prog_stage_load(struct prog *prog); diff --git a/src/include/program_loading.h b/src/include/program_loading.h index 4cadab6..8da6ada 100644 --- a/src/include/program_loading.h +++ b/src/include/program_loading.h @@ -176,6 +176,10 @@ uintptr_t romstage_ram_stack_source(size_t size, int src); uintptr_t romstage_ram_stack_top(void); uintptr_t romstage_ram_stack_bottom(void); +/* Backup OS memory to CBMEM_ID_RESUME on ACPI S3 resume path, + * if ramstage overwrites low memory. */ +void backup_ramstage_section(uintptr_t base, size_t size); + /*********************** * PAYLOAD LOADING * ***********************/ diff --git a/src/lib/cbfs.c b/src/lib/cbfs.c index aa652c2..c00e6aa 100644 --- a/src/lib/cbfs.c +++ b/src/lib/cbfs.c @@ -166,6 +166,18 @@ void *cbfs_boot_load_stage_by_name(const char *name) return prog_entry(&stage); } +void cbfs_prog_stage_section(struct prog *pstage, uint32_t *base, uint32_t *size) +{ + struct cbfs_stage stage; + const struct region_device *fh = prog_rdev(pstage); + + if (rdev_readat(fh, &stage, 0, sizeof(stage)) != sizeof(stage)) + return; + + *base = stage.load; + *size = stage.memlen; +} + int cbfs_prog_stage_load(struct prog *pstage) { struct cbfs_stage stage; diff --git a/src/lib/prog_loaders.c b/src/lib/prog_loaders.c index ecbc679..d659abe 100644 --- a/src/lib/prog_loaders.c +++ b/src/lib/prog_loaders.c @@ -101,6 +101,18 @@ static int load_relocatable_ramstage(struct prog *ramstage) return rmodule_stage_load(&rmod_ram); } +static int load_nonrelocatable_ramstage(struct prog *ramstage) +{ + if (IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)) { + uint32_t base = 0, size = 0; + cbfs_prog_stage_section(ramstage, &base, &size); + if (size) + backup_ramstage_section(base, size); + } + + return cbfs_prog_stage_load(ramstage); +} + void run_ramstage(void) { struct prog ramstage = @@ -126,7 +138,7 @@ void run_ramstage(void) if (IS_ENABLED(CONFIG_RELOCATABLE_RAMSTAGE)) { if (load_relocatable_ramstage(&ramstage)) goto fail; - } else if (cbfs_prog_stage_load(&ramstage)) + } else if (load_nonrelocatable_ramstage(&ramstage)) goto fail; stage_cache_add(STAGE_RAMSTAGE, &ramstage);

1 0

Patch set updated for coreboot: ACPI S3: Drop early resume backup
by Kyösti Mälkki 29 Jun '16

29 Jun '16

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15477 -gerrit commit ca025e05c5d522b45aab939b39dcaadf89d10ff5 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Mon Jun 27 13:09:56 2016 +0300 ACPI S3: Drop early resume backup No longer needed as low memory backup is implemented as part of the ramstage loader, after MTRRs are set to write-back cache for better performance. Change-Id: I5f5ad94bae2afef915927b9737c79431b6f75f22 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/x86/acpi_s3.c | 10 ---------- src/arch/x86/include/arch/acpi.h | 2 -- 2 files changed, 12 deletions(-) diff --git a/src/arch/x86/acpi_s3.c b/src/arch/x86/acpi_s3.c index c744eb5..5404332 100644 --- a/src/arch/x86/acpi_s3.c +++ b/src/arch/x86/acpi_s3.c @@ -151,16 +151,6 @@ void backup_ramstage_section(uintptr_t base, size_t size) backup_mem->valid = 1; } -/* Make backup of low-memory region, relying on the base and size - * of the ramstage that was loaded before entry to ACPI S3. - * - * DEPRECATED - */ -void acpi_prepare_for_resume(void) -{ - backup_ramstage_section(0, 0); -} - /* Let's prepare the ACPI S3 Resume area now already, so we can rely on * it being there during reboot time. If this fails, ACPI resume will * be disabled. We assume that ramstage does not change while in suspend, diff --git a/src/arch/x86/include/arch/acpi.h b/src/arch/x86/include/arch/acpi.h index f40b9df..6fecd8c 100644 --- a/src/arch/x86/include/arch/acpi.h +++ b/src/arch/x86/include/arch/acpi.h @@ -634,14 +634,12 @@ int acpi_is_wakeup(void); int acpi_is_wakeup_s3(void); int acpi_is_wakeup_s4(void); #endif -void acpi_prepare_for_resume(void); #else #define acpi_slp_type 0 static inline int acpi_is_wakeup(void) { return 0; } static inline int acpi_is_wakeup_s3(void) { return 0; } static inline int acpi_is_wakeup_s4(void) { return 0; } -static inline void acpi_prepare_for_resume(void) { } #endif static inline uintptr_t acpi_align_current(uintptr_t current)

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Patch set updated for coreboot: ACPI S3: Drop ACPI_HUGE_LOWMEM_BACKUP
by Kyösti Mälkki 29 Jun '16

29 Jun '16

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15476 -gerrit commit 5d4399c38015ccde2af30204c901bbc8981786fe Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Jun 28 07:50:48 2016 +0300 ACPI S3: Drop ACPI_HUGE_LOWMEM_BACKUP Change-Id: Ifae41b51b359010ec02269c674936a87bd15623b Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/Kconfig | 4 ---- src/arch/x86/acpi_s3.c | 5 ----- 2 files changed, 9 deletions(-) diff --git a/src/Kconfig b/src/Kconfig index b4c3cbe..7043851 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -516,10 +516,6 @@ config HAVE_ACPI_RESUME bool default n -config ACPI_HUGE_LOWMEM_BACKUP - bool - default n - config RESUME_PATH_SAME_AS_BOOT bool default y if ARCH_X86 diff --git a/src/arch/x86/acpi_s3.c b/src/arch/x86/acpi_s3.c index 5404332..792842c 100644 --- a/src/arch/x86/acpi_s3.c +++ b/src/arch/x86/acpi_s3.c @@ -95,11 +95,6 @@ void *acpi_backup_container(uintptr_t base, size_t size) struct resume_backup *backup_mem; uintptr_t top, target; - if (IS_ENABLED(CONFIG_ACPI_HUGE_LOWMEM_BACKUP)) { - base = CONFIG_RAMBASE; - size = HIGH_MEMORY_SAVE; - } - /* Align backup region to complete pages. */ top = ALIGN_UP(base + size, BACKUP_PAGE_SZ); base = ALIGN_DOWN(base, BACKUP_PAGE_SZ);

1 0

Patch set updated for coreboot: AGESA: Delay ACPI S3 backup until ramstage loader
by Kyösti Mälkki 29 Jun '16

29 Jun '16

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15470 -gerrit commit cf14e049d9b40dfff478579286d6d8299151e7fa Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Mon Jun 27 12:14:39 2016 +0300 AGESA: Delay ACPI S3 backup until ramstage loader Change-Id: I59773161f22c1ec6a52050245f9ad3e6cc74a934 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/cpu/amd/agesa/s3_resume.c | 5 ----- 1 file changed, 5 deletions(-) diff --git a/src/cpu/amd/agesa/s3_resume.c b/src/cpu/amd/agesa/s3_resume.c index c5436ed..8d47e7f 100644 --- a/src/cpu/amd/agesa/s3_resume.c +++ b/src/cpu/amd/agesa/s3_resume.c @@ -91,9 +91,4 @@ void prepare_for_resume(void) printk(BIOS_DEBUG, "CAR disabled.\n"); set_resume_cache(); - /* - * Copy the system memory that is in the ramstage area to the - * reserved area. - */ - acpi_prepare_for_resume(); }

1 0

Patch set updated for coreboot: AMD binaryPI: Delay ACPI S3 backup until ramstage loader
by Kyösti Mälkki 29 Jun '16

29 Jun '16

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15471 -gerrit commit bb32b67f59f6cc5046377110bd522751a26ba89d Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Mon Jun 27 12:14:49 2016 +0300 AMD binaryPI: Delay ACPI S3 backup until ramstage loader Change-Id: I482cf93fe5dfab95817c87c32aad33df2e0a6439 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/cpu/amd/pi/s3_resume.c | 5 ----- 1 file changed, 5 deletions(-) diff --git a/src/cpu/amd/pi/s3_resume.c b/src/cpu/amd/pi/s3_resume.c index 830d174..b6e1e92 100644 --- a/src/cpu/amd/pi/s3_resume.c +++ b/src/cpu/amd/pi/s3_resume.c @@ -287,10 +287,5 @@ void prepare_for_resume(void) printk(BIOS_DEBUG, "CAR disabled.\n"); set_resume_cache(); - /* - * Copy the system memory that is in the ramstage area to the - * reserved area. - */ - acpi_prepare_for_resume(); } #endif

1 0

Patch set updated for coreboot: intel post-car: Delay ACPI S3 backup until ramstage loader
by Kyösti Mälkki 29 Jun '16

29 Jun '16

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15469 -gerrit commit e15c5457a50d62f448d179f992bf8e56b76d9520 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Mon Jun 27 12:13:48 2016 +0300 intel post-car: Delay ACPI S3 backup until ramstage loader Change-Id: If0060b9ad8703a3d6524004fb69cb2171f8d89a3 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/mainboard/lenovo/t400/romstage.c | 1 - src/mainboard/lenovo/x200/romstage.c | 1 - src/mainboard/lenovo/x201/romstage.c | 1 - src/mainboard/packardbell/ms2290/romstage.c | 1 - src/mainboard/roda/rk9/romstage.c | 1 - src/northbridge/intel/i945/early_init.c | 1 - src/northbridge/intel/sandybridge/early_init.c | 1 - 7 files changed, 7 deletions(-) diff --git a/src/mainboard/lenovo/t400/romstage.c b/src/mainboard/lenovo/t400/romstage.c index f518775..0e7309d 100644 --- a/src/mainboard/lenovo/t400/romstage.c +++ b/src/mainboard/lenovo/t400/romstage.c @@ -179,7 +179,6 @@ void mainboard_romstage_entry(unsigned long bist) * this is not a resume. In that case we just create the cbmem toc. */ if (s3resume && cbmem_initted) { - acpi_prepare_for_resume(); /* Magic for S3 resume */ pci_write_config32(PCI_DEV(0, 0, 0), D0F0_SKPD, SKPAD_ACPI_S3_MAGIC); diff --git a/src/mainboard/lenovo/x200/romstage.c b/src/mainboard/lenovo/x200/romstage.c index 1deab65..db1d62f 100644 --- a/src/mainboard/lenovo/x200/romstage.c +++ b/src/mainboard/lenovo/x200/romstage.c @@ -179,7 +179,6 @@ void mainboard_romstage_entry(unsigned long bist) * this is not a resume. In that case we just create the cbmem toc. */ if (s3resume && cbmem_initted) { - acpi_prepare_for_resume(); /* Magic for S3 resume */ pci_write_config32(PCI_DEV(0, 0, 0), D0F0_SKPD, SKPAD_ACPI_S3_MAGIC); diff --git a/src/mainboard/lenovo/x201/romstage.c b/src/mainboard/lenovo/x201/romstage.c index 2bfa19c..7b8d7f9 100644 --- a/src/mainboard/lenovo/x201/romstage.c +++ b/src/mainboard/lenovo/x201/romstage.c @@ -282,7 +282,6 @@ void mainboard_romstage_entry(unsigned long bist) * this is not a resume. In that case we just create the cbmem toc. */ if (s3resume) { - acpi_prepare_for_resume(); /* Magic for S3 resume */ pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafed00d); diff --git a/src/mainboard/packardbell/ms2290/romstage.c b/src/mainboard/packardbell/ms2290/romstage.c index 92ee021..04c9513 100644 --- a/src/mainboard/packardbell/ms2290/romstage.c +++ b/src/mainboard/packardbell/ms2290/romstage.c @@ -272,7 +272,6 @@ void mainboard_romstage_entry(unsigned long bist) * this is not a resume. In that case we just create the cbmem toc. */ if (s3resume) { - acpi_prepare_for_resume(); /* Magic for S3 resume */ pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafed00d); diff --git a/src/mainboard/roda/rk9/romstage.c b/src/mainboard/roda/rk9/romstage.c index fc0c8d3..e8bd1e2 100644 --- a/src/mainboard/roda/rk9/romstage.c +++ b/src/mainboard/roda/rk9/romstage.c @@ -192,7 +192,6 @@ void mainboard_romstage_entry(unsigned long bist) * this is not a resume. In that case we just create the cbmem toc. */ if (s3resume && cbmem_initted) { - acpi_prepare_for_resume(); /* Magic for S3 resume */ pci_write_config32(PCI_DEV(0, 0, 0), D0F0_SKPD, SKPAD_ACPI_S3_MAGIC); diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c index ade120f..3164f25 100644 --- a/src/northbridge/intel/i945/early_init.c +++ b/src/northbridge/intel/i945/early_init.c @@ -900,7 +900,6 @@ static void i945_prepare_resume(int s3resume) * this is not a resume. In that case we just create the cbmem toc. */ if (s3resume && cbmem_was_initted) { - acpi_prepare_for_resume(); /* Magic for S3 resume */ pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, diff --git a/src/northbridge/intel/sandybridge/early_init.c b/src/northbridge/intel/sandybridge/early_init.c index a013ec3..86d1c00 100644 --- a/src/northbridge/intel/sandybridge/early_init.c +++ b/src/northbridge/intel/sandybridge/early_init.c @@ -234,7 +234,6 @@ void northbridge_romstage_finalize(int s3resume) */ if (s3resume) { - acpi_prepare_for_resume(); /* Magic for S3 resume */ pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafed00d);

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coreboot-gerrit June 2016