coreboot-gerrit June 2016

coreboot-gerrit@coreboot.org

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New patch to review for coreboot: intel/amenia: Write Protect GPIO relative to Bank offset
by Susendra Selvaraj 29 Jun '16

29 Jun '16

Susendra Selvaraj (susendra.selvaraj(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15496 -gerrit commit d0f20cc1a9e20837dd40961ba11544e06c5ed433 Author: sselvar2 <susendra.selvaraj(a)intel.com> Date: Thu Jun 9 21:06:34 2016 +0530 intel/amenia: Write Protect GPIO relative to Bank offset Update the write protect GPIO reported in ACPI to 0x8023 w.r.t bank offset. ALso update the controller ID to Broxton which will point at the goldmont device and includes write protect GPIO. BUG=none BRANCH=none TEST=verify crossystem output for wpsw_cur. Change-Id: Id6b172e289976072836746c1814e0300544a06cb Signed-off-by: sselvar2 <susendra.selvaraj(a)intel.com> Reviewed-on: https://coreboot.intel.com/7771 Reviewed-by: Sparry, Icarus W <icarus.w.sparry(a)intel.com> Reviewed-by: Petrov, Andrey <andrey.petrov(a)intel.com> Tested-by: Petrov, Andrey <andrey.petrov(a)intel.com> --- .../intel/amenia/acpi/chromeos_amenia.asl | 24 ++++++++++++++++++++++ src/mainboard/intel/amenia/dsdt.asl | 7 +++++++ 2 files changed, 31 insertions(+) diff --git a/src/mainboard/intel/amenia/acpi/chromeos_amenia.asl b/src/mainboard/intel/amenia/acpi/chromeos_amenia.asl new file mode 100644 index 0000000..5b5565b --- /dev/null +++ b/src/mainboard/intel/amenia/acpi/chromeos_amenia.asl @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2016 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <soc/gpio_defs.h> + +Name (OIPG, Package () { + /* No physical recovery GPIO. */ + Package () { 0x0001, 0, 0xFFFFFFFF, "Broxton" }, + /* Firmware write protect GPIO. */ + Package () { 0x0003, 1, 0x8023, "Broxton" }, +}) diff --git a/src/mainboard/intel/amenia/dsdt.asl b/src/mainboard/intel/amenia/dsdt.asl index 4a64f87..19450d8 100644 --- a/src/mainboard/intel/amenia/dsdt.asl +++ b/src/mainboard/intel/amenia/dsdt.asl @@ -37,6 +37,13 @@ DefinitionBlock( #include <soc/intel/apollolake/acpi/southbridge.asl> } } + + #if IS_ENABLED(CONFIG_CHROMEOS) + /* Chrome OS specific */ + #include "acpi/chromeos_amenia.asl" + #include <vendorcode/google/chromeos/acpi/chromeos.asl> + #endif + /* Mainboard Specific devices */ #include "acpi/mainboard.asl"

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Patch merged into coreboot/master: vbnv: Do not silently reset cache in read_vbnv
by gerrit＠coreboot.org 29 Jun '16

29 Jun '16

the following patch was just integrated into master: commit 165b6cf5c1192439838df83158c92313451f7777 Author: Furquan Shaikh <furquan(a)google.com> Date: Mon Jun 27 16:19:09 2016 -0700 vbnv: Do not silently reset cache in read_vbnv Currently, read_vbnv performs a reset of the vbnv cache if it is not valid. However, this information is not passed up to the vboot layer, thus resulting in missed write-back of vbnv cache to storage if vboot does not update the cache itself. Update read_vbnv to return a value depending upon whether it wants a write-back to be performed when save is called. Return value: 0 = No write-back required 1 = Write-back of VBNV cache is required. Change-Id: I239939d5f9731d89a9d53fe662321b93fc1ab113 Signed-off-by: Furquan Shaikh <furquan(a)google.com> Reviewed-on: https://review.coreboot.org/15457 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See https://review.coreboot.org/15457 for details. -gerrit

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Patch merged into coreboot/master: AMD k8 fam10: Refactor S3 recovery
by gerrit＠coreboot.org 29 Jun '16

29 Jun '16

the following patch was just integrated into master: commit c30bfcaa9ebbe4d3e2ea0cac11784e13e56fe281 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Jun 28 07:38:03 2016 +0300 AMD k8 fam10: Refactor S3 recovery Change-Id: I09c218ca05391e8d80880be0aa5bdfd5079acf85 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/15465 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See https://review.coreboot.org/15465 for details. -gerrit

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Patch merged into coreboot/master: intel/haswell: No need for ACPI S3 resume backup
by gerrit＠coreboot.org 29 Jun '16

29 Jun '16

the following patch was just integrated into master: commit 1891bfdac65f02769a5581d274b668a9e0dbf176 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sun Jun 26 14:03:55 2016 +0300 intel/haswell: No need for ACPI S3 resume backup Platform is with RELOCATABLE_RAMSTAGE so nothing to backup. Change-Id: I2397db8affb084e34ca89dac4840f966b994e636 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/15462 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See https://review.coreboot.org/15462 for details. -gerrit

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Patch merged into coreboot/master: intel romstage: Use run_ramstage()
by gerrit＠coreboot.org 29 Jun '16

29 Jun '16

the following patch was just integrated into master: commit 65e8f647bc55ee28bd389789788e666279537510 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Mon Jun 27 11:27:56 2016 +0300 intel romstage: Use run_ramstage() Change-Id: I22a33e6027a4e807f7157a0dfafbd6377bc1285d Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/15461 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See https://review.coreboot.org/15461 for details. -gerrit

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New patch to review for coreboot: fsp_broadwell_de: Enable Super-IO address range decode
by Werner Zeh 29 Jun '16

29 Jun '16

Werner Zeh (werner.zeh(a)siemens.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15495 -gerrit commit 47acf27099391b30ac5f40501eb2213dcbdf198e Author: Werner Zeh <werner.zeh(a)siemens.com> Date: Wed Jun 29 07:17:21 2016 +0200 fsp_broadwell_de: Enable Super-IO address range decode If there is an external 16550 like UART, one need to enable the appropriate address ranges before console_init() is called so that the init sequence can reach the external UART. Otherwise the UART will only start working in ramstage and will produce unreadable characters in romstage due to the lack of initialization. Change-Id: Iafc5b5b6df14916c5ed778928521d4a8f539cf46 Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- src/soc/intel/fsp_broadwell_de/include/soc/lpc.h | 4 +++- src/soc/intel/fsp_broadwell_de/romstage/romstage.c | 3 +++ 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/src/soc/intel/fsp_broadwell_de/include/soc/lpc.h b/src/soc/intel/fsp_broadwell_de/include/soc/lpc.h index 2c02ebd..0408f7f 100644 --- a/src/soc/intel/fsp_broadwell_de/include/soc/lpc.h +++ b/src/soc/intel/fsp_broadwell_de/include/soc/lpc.h @@ -21,6 +21,8 @@ #define REVID 0x08 #define PIRQ_RCR1 0x60 #define PIRQ_RCR2 0x68 +#define LPC_IO_DEC 0x80 +#define LPC_EN 0x82 #define GEN_PMCON_1 0xA0 #define GEN_PMCON_2 0xA2 #define GEN_PMCON_3 0xA4 @@ -83,4 +85,4 @@ #define TCO_TMR_HALT (1 << 11) #define TCO_TMR 0x70 -#endif /* _SOC_LPC_H_ */ \ No newline at end of file +#endif /* _SOC_LPC_H_ */ diff --git a/src/soc/intel/fsp_broadwell_de/romstage/romstage.c b/src/soc/intel/fsp_broadwell_de/romstage/romstage.c index dc883a4..925d284 100644 --- a/src/soc/intel/fsp_broadwell_de/romstage/romstage.c +++ b/src/soc/intel/fsp_broadwell_de/romstage/romstage.c @@ -48,6 +48,9 @@ static void init_rtc(void) void *asmlinkage main(FSP_INFO_HEADER *fsp_info_header) { post_code(0x40); + /* Enable decoding of I/O locations for SuperIO devices */ + pci_write_config16(PCI_DEV(0x0, LPC_DEV, LPC_FUNC), LPC_IO_DEC, 0x0010); + pci_write_config16(PCI_DEV(0x0, LPC_DEV, LPC_FUNC), LPC_EN, 0x340f); console_init(); init_rtc();

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Patch set updated for coreboot: vendorcode/siemens: Add extended info block support to hwilib
by Werner Zeh 29 Jun '16

29 Jun '16

Werner Zeh (werner.zeh(a)siemens.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15478 -gerrit commit 7a76215cfd9a6c7fa05a4811ee70ba92c122aecd Author: Werner Zeh <werner.zeh(a)siemens.com> Date: Tue Jun 28 14:31:30 2016 +0200 vendorcode/siemens: Add extended info block support to hwilib Add support for a fourth info block type to hwilib. This block provides new values and is now variable in length. Change-Id: Ia928b4a98b806ba3e80fb576b78f60bb8f2ea3fc Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- src/vendorcode/siemens/hwilib/hwilib.c | 228 ++++++++++++++++++++++++++++++++- src/vendorcode/siemens/hwilib/hwilib.h | 74 ++++++++++- 2 files changed, 293 insertions(+), 9 deletions(-) diff --git a/src/vendorcode/siemens/hwilib/hwilib.c b/src/vendorcode/siemens/hwilib/hwilib.c index 5d47881..b6cdd90 100644 --- a/src/vendorcode/siemens/hwilib/hwilib.c +++ b/src/vendorcode/siemens/hwilib/hwilib.c @@ -21,13 +21,15 @@ #include "hwilib.h" -#define MAX_BLOCK_NUM 3 +#define MAX_BLOCK_NUM 4 #define LEN_HIB 0x1fd #define LEN_SIB 0x121 #define LEN_EIB 0x0b5 +#define MIN_LEN_XIB 0x201 #define NEXT_OFFSET_HIB 0x1dc #define NEXT_OFFSET_SIB 0x104 #define NEXT_OFFSET_EIB 0x0b0 +#define NEXT_OFFSET_XIB 0x014 #define LEN_UNIQUEL_NUM 0x010 #define LEN_HW_REV 0x002 #define LEN_MAC_ADDRESS 0x006 @@ -43,6 +45,7 @@ enum { BLK_HIB, BLK_SIB, BLK_EIB, + BLK_XIB }; /* This structure holds a valid position for a given field @@ -71,6 +74,12 @@ struct param_info { */ static uint8_t *all_blocks[MAX_BLOCK_NUM] CAR_GLOBAL; +/* As the length of extended block is variable, save all length to a global + * variable so that they can be used later to check boundaries. + */ +static uint16_t all_blk_size[MAX_BLOCK_NUM] CAR_GLOBAL; + + static uint32_t hwilib_read_bytes (const struct param_info *param, uint8_t *dst, uint32_t maxlen); @@ -89,6 +98,9 @@ static const struct param_info params[] = { [EIB_VerID] = { .pos[0] = {.blk_type = BLK_EIB, .offset = 0x8, .len = 4}, .get_field = hwilib_read_bytes }, + [XIB_VerID] = { + .pos[0] = {.blk_type = BLK_XIB, .offset = 0x8, .len = 4}, + .get_field = hwilib_read_bytes }, [HIB_HwRev] = { .pos[0] = {.blk_type = BLK_HIB, .offset = 0xbe, .len = 2}, .get_field = hwilib_read_bytes }, @@ -151,6 +163,9 @@ static const struct param_info params[] = { [MacMapping4] = { .pos[0] = {.blk_type = BLK_HIB, .offset = 0x1d8, .len = 4}, .get_field = hwilib_read_bytes }, + [RTCType] = { + .pos[0] = {.blk_type = BLK_HIB, .offset = 0x1e8, .len = 1}, + .get_field = hwilib_read_bytes }, [PF_Color_Depth] = { .pos[0] = {.blk_type = BLK_SIB, .offset = 0xea, .len = 1}, .mask = 0x03, @@ -168,6 +183,196 @@ static const struct param_info params[] = { [VddRef] = { .pos[0] = {.blk_type = BLK_EIB, .offset = 0x90, .len = 2}, .get_field = hwilib_read_bytes }, + [XMac1] = { + .pos[0] = {.blk_type = BLK_XIB, .offset = 0xfc, .len = 6}, + .get_field = hwilib_read_bytes }, + [XMac1Aux] = { + .pos[0] = {.blk_type = BLK_XIB, .offset = 0x102, .len = 1}, + .get_field = hwilib_read_bytes }, + [XMac2] = { + .pos[0] = {.blk_type = BLK_XIB, .offset = 0x114, .len = 6}, + .get_field = hwilib_read_bytes }, + [XMac2Aux] = { + .pos[0] = {.blk_type = BLK_XIB, .offset = 0x11a, .len = 1}, + .get_field = hwilib_read_bytes }, + [XMac3] = { + .pos[0] = {.blk_type = BLK_XIB, .offset = 0x12c, .len = 6}, + .get_field = hwilib_read_bytes }, + [XMac3Aux] = { + .pos[0] = {.blk_type = BLK_XIB, .offset = 0x132, .len = 1}, + .get_field = hwilib_read_bytes }, + [XMac4] = { + .pos[0] = {.blk_type = BLK_XIB, .offset = 0x144, .len = 6}, + .get_field = hwilib_read_bytes }, + [XMac4Aux] = { + .pos[0] = {.blk_type = BLK_XIB, .offset = 0x14a, .len = 1}, + .get_field = hwilib_read_bytes }, + [XMac5] = { + .pos[0] = {.blk_type = BLK_XIB, .offset = 0x15c, .len = 6}, + .get_field = hwilib_read_bytes }, + [XMac5Aux] = { + .pos[0] = {.blk_type = BLK_XIB, .offset = 0x162, .len = 1}, + .get_field = hwilib_read_bytes }, + [XMac6] = { + .pos[0] = {.blk_type = BLK_XIB, .offset = 0x174, .len = 6}, + .get_field = hwilib_read_bytes }, + [XMac6Aux] = { + .pos[0] = {.blk_type = BLK_XIB, .offset = 0x17a, .len = 1}, + .get_field = hwilib_read_bytes }, + [XMac7] = { + .pos[0] = {.blk_type = BLK_XIB, .offset = 0x18c, .len = 6}, + .get_field = hwilib_read_bytes }, + [XMac7Aux] = { + .pos[0] = {.blk_type = BLK_XIB, .offset = 0x192, .len = 1}, + .get_field = hwilib_read_bytes }, + [XMac8] = { + .pos[0] = {.blk_type = BLK_XIB, .offset = 0x1a4, .len = 6}, + .get_field = hwilib_read_bytes }, + [XMac8Aux] = { + .pos[0] = {.blk_type = BLK_XIB, .offset = 0x1aa, .len = 1}, + .get_field = hwilib_read_bytes }, + [XMac9] = { + .pos[0] = {.blk_type = BLK_XIB, .offset = 0x1bc, .len = 6}, + .get_field = hwilib_read_bytes }, + [XMac9Aux] = { + .pos[0] = {.blk_type = BLK_XIB, .offset = 0x1c2, .len = 1}, + .get_field = hwilib_read_bytes }, + [XMac10] = { + .pos[0] = {.blk_type = BLK_XIB, .offset = 0x1d4, .len = 6}, + .get_field = hwilib_read_bytes }, + [XMac10Aux] = { + .pos[0] = {.blk_type = BLK_XIB, .offset = 0x1da, .len = 1}, + .get_field = hwilib_read_bytes }, + [XMac1Mapping] = { + .pos[0] = {.blk_type = BLK_XIB, .offset = 0xec, .len = 16}, + .get_field = hwilib_read_bytes }, + [XMac2Mapping] = { + .pos[0] = {.blk_type = BLK_XIB, .offset = 0x104, .len = 16}, + .get_field = hwilib_read_bytes }, + [XMac3Mapping] = { + .pos[0] = {.blk_type = BLK_XIB, .offset = 0x11c, .len = 16}, + .get_field = hwilib_read_bytes }, + [XMac4Mapping] = { + .pos[0] = {.blk_type = BLK_XIB, .offset = 0x134, .len = 16}, + .get_field = hwilib_read_bytes }, + [XMac5Mapping] = { + .pos[0] = {.blk_type = BLK_XIB, .offset = 0x14c, .len = 16}, + .get_field = hwilib_read_bytes }, + [XMac6Mapping] = { + .pos[0] = {.blk_type = BLK_XIB, .offset = 0x164, .len = 16}, + .get_field = hwilib_read_bytes }, + [XMac7Mapping] = { + .pos[0] = {.blk_type = BLK_XIB, .offset = 0x17c, .len = 16}, + .get_field = hwilib_read_bytes }, + [XMac8Mapping] = { + .pos[0] = {.blk_type = BLK_XIB, .offset = 0x194, .len = 16}, + .get_field = hwilib_read_bytes }, + [XMac9Mapping] = { + .pos[0] = {.blk_type = BLK_XIB, .offset = 0x1ac, .len = 16}, + .get_field = hwilib_read_bytes }, + [XMac10Mapping] = { + .pos[0] = {.blk_type = BLK_XIB, .offset = 0x1c4, .len = 16}, + .get_field = hwilib_read_bytes }, + [netKind1] = { + .pos[0] = {.blk_type = BLK_XIB, .offset = 0x103, .len = 1}, + .get_field = hwilib_read_bytes }, + [netKind2] = { + .pos[0] = {.blk_type = BLK_XIB, .offset = 0x11b, .len = 1}, + .get_field = hwilib_read_bytes }, + [netKind3] = { + .pos[0] = {.blk_type = BLK_XIB, .offset = 0x133, .len = 1}, + .get_field = hwilib_read_bytes }, + [netKind4] = { + .pos[0] = {.blk_type = BLK_XIB, .offset = 0x14b, .len = 1}, + .get_field = hwilib_read_bytes }, + [netKind5] = { + .pos[0] = {.blk_type = BLK_XIB, .offset = 0x163, .len = 1}, + .get_field = hwilib_read_bytes }, + [netKind6] = { + .pos[0] = {.blk_type = BLK_XIB, .offset = 0x17b, .len = 1}, + .get_field = hwilib_read_bytes }, + [netKind7] = { + .pos[0] = {.blk_type = BLK_XIB, .offset = 0x193, .len = 1}, + .get_field = hwilib_read_bytes }, + [netKind8] = { + .pos[0] = {.blk_type = BLK_XIB, .offset = 0x1ab, .len = 1}, + .get_field = hwilib_read_bytes }, + [netKind9] = { + .pos[0] = {.blk_type = BLK_XIB, .offset = 0x1c3, .len = 1}, + .get_field = hwilib_read_bytes }, + [netKind10] = { + .pos[0] = {.blk_type = BLK_XIB, .offset = 0x1db, .len = 1}, + .get_field = hwilib_read_bytes }, + [T_Warn] = { + .pos[0] = {.blk_type = BLK_XIB, .offset = 0x18, .len = 4}, + .get_field = hwilib_read_bytes }, + [T_Crit] = { + .pos[0] = {.blk_type = BLK_XIB, .offset = 0x1c, .len = 4}, + .get_field = hwilib_read_bytes }, + [FANSamplingTime] = { + .pos[0] = {.blk_type = BLK_XIB, .offset = 0x20, .len = 4}, + .get_field = hwilib_read_bytes }, + [FANSetPoint] = { + .pos[0] = {.blk_type = BLK_XIB, .offset = 0x24, .len = 4}, + .get_field = hwilib_read_bytes }, + [FANKp] = { + .pos[0] = {.blk_type = BLK_XIB, .offset = 0x28, .len = 4}, + .get_field = hwilib_read_bytes }, + [FANKi] = { + .pos[0] = {.blk_type = BLK_XIB, .offset = 0x2c, .len = 4}, + .get_field = hwilib_read_bytes }, + [FANKd] = { + .pos[0] = {.blk_type = BLK_XIB, .offset = 0x30, .len = 4}, + .get_field = hwilib_read_bytes }, + [FANHystVal] = { + .pos[0] = {.blk_type = BLK_XIB, .offset = 0x34, .len = 4}, + .get_field = hwilib_read_bytes }, + [FANHystThreshold] = { + .pos[0] = {.blk_type = BLK_XIB, .offset = 0x38, .len = 4}, + .get_field = hwilib_read_bytes }, + [FANHystCtrl] = { + .pos[0] = {.blk_type = BLK_XIB, .offset = 0x3c, .len = 4}, + .get_field = hwilib_read_bytes }, + [FANMaxSpeed] = { + .pos[0] = {.blk_type = BLK_XIB, .offset = 0x40, .len = 2}, + .get_field = hwilib_read_bytes }, + [FANStartpeed] = { + .pos[0] = {.blk_type = BLK_XIB, .offset = 0x42, .len = 2}, + .get_field = hwilib_read_bytes }, + [FANSensorDelay] = { + .pos[0] = {.blk_type = BLK_XIB, .offset = 0x44, .len = 4}, + .get_field = hwilib_read_bytes }, + [FANSensorNum] = { + .pos[0] = {.blk_type = BLK_XIB, .offset = 0x48, .len = 1}, + .get_field = hwilib_read_bytes }, + [FANSensorSelect] = { + .pos[0] = {.blk_type = BLK_XIB, .offset = 0x49, .len = 1}, + .get_field = hwilib_read_bytes }, + [FANSensorCfg0] = { + .pos[0] = {.blk_type = BLK_XIB, .offset = 0x4c, .len = 20}, + .get_field = hwilib_read_bytes }, + [FANSensorCfg1] = { + .pos[0] = {.blk_type = BLK_XIB, .offset = 0x60, .len = 20}, + .get_field = hwilib_read_bytes }, + [FANSensorCfg2] = { + .pos[0] = {.blk_type = BLK_XIB, .offset = 0x74, .len = 20}, + .get_field = hwilib_read_bytes }, + [FANSensorCfg3] = { + .pos[0] = {.blk_type = BLK_XIB, .offset = 0x88, .len = 20}, + .get_field = hwilib_read_bytes }, + [FANSensorCfg4] = { + .pos[0] = {.blk_type = BLK_XIB, .offset = 0x9c, .len = 20}, + .get_field = hwilib_read_bytes }, + [FANSensorCfg5] = { + .pos[0] = {.blk_type = BLK_XIB, .offset = 0xb0, .len = 20}, + .get_field = hwilib_read_bytes }, + [FANSensorCfg6] = { + .pos[0] = {.blk_type = BLK_XIB, .offset = 0xc4, .len = 20}, + .get_field = hwilib_read_bytes }, + [FANSensorCfg7] = { + .pos[0] = {.blk_type = BLK_XIB, .offset = 0xd8, .len = 20}, + .get_field = hwilib_read_bytes }, + }; /** \brief This functions reads the given field from the first valid hwinfo @@ -181,8 +386,7 @@ static uint32_t hwilib_read_bytes (const struct param_info *param, uint8_t *dst, { uint8_t i = 0, *blk = NULL; uint8_t **blk_ptr = car_get_var_ptr(&all_blocks[0]); - static const uint16_t all_blk_size[MAX_BLOCK_NUM] = - {LEN_HIB, LEN_SIB, LEN_EIB}; + uint16_t *all_blk_size_ptr = car_get_var_ptr(&all_blk_size[0]); if (!param || !dst) return 0; @@ -200,7 +404,7 @@ static uint32_t hwilib_read_bytes (const struct param_info *param, uint8_t *dst, */ if ((!blk) || (param->pos[i].len > maxlen) || (param->pos[i].len + param->pos[i].offset > - all_blk_size[param->pos[i].blk_type])) + all_blk_size_ptr[param->pos[i].blk_type])) return 0; /* We can now copy the wanted data. */ memcpy(dst, (blk + param->pos[i].offset), param->pos[i].len); @@ -248,6 +452,7 @@ enum cb_err hwilib_find_blocks (const char *hwi_filename) uint8_t *ptr = NULL, *base = NULL; uint32_t next_offset = 1; uint8_t **blk_ptr = car_get_var_ptr(&all_blocks[0]); + uint16_t *all_blk_size_ptr = car_get_var_ptr(&all_blk_size[0]); size_t filesize = 0; /* Check for a valid parameter */ @@ -271,6 +476,12 @@ enum cb_err hwilib_find_blocks (const char *hwi_filename) memset(blk_ptr, 0, (MAX_BLOCK_NUM * sizeof (uint8_t *))); /* Check which blocks are available by examining the length field. */ base = ptr; + /* Fill in sizes of all fixed length blocks. */ + all_blk_size_ptr[BLK_HIB] = LEN_HIB; + all_blk_size_ptr[BLK_SIB] = LEN_SIB; + all_blk_size_ptr[BLK_EIB] = LEN_EIB; + /* Length of BLK_XIB is variable and will be filled if block is found */ + all_blk_size_ptr[BLK_XIB] = 0; while(!(strncmp((char *)ptr, BLOCK_MAGIC, LEN_MAGIC_NUM)) && next_offset) { uint16_t len = read16(ptr + LEN_OFFSET); @@ -294,12 +505,19 @@ enum cb_err hwilib_find_blocks (const char *hwi_filename) next_offset = read32(ptr + NEXT_OFFSET_EIB); if (next_offset) ptr = base + next_offset; + } else if (len >= MIN_LEN_XIB) { + blk_ptr[BLK_XIB] = ptr; + next_offset = read32(ptr + NEXT_OFFSET_XIB); + all_blk_size_ptr[BLK_XIB] = len; + if (next_offset) + ptr = base + next_offset; } else { next_offset = 0; } } /* We should have found at least one valid block */ - if (blk_ptr[BLK_HIB] || blk_ptr[BLK_SIB] || blk_ptr[BLK_EIB]) + if (blk_ptr[BLK_HIB] || blk_ptr[BLK_SIB] || blk_ptr[BLK_EIB] || + blk_ptr[BLK_XIB]) return CB_SUCCESS; else return CB_ERR; diff --git a/src/vendorcode/siemens/hwilib/hwilib.h b/src/vendorcode/siemens/hwilib/hwilib.h index c66a99c..d858091 100644 --- a/src/vendorcode/siemens/hwilib/hwilib.h +++ b/src/vendorcode/siemens/hwilib/hwilib.h @@ -24,16 +24,17 @@ typedef enum { HIB_VerID = 0, SIB_VerID, EIB_VerID, + XIB_VerID, HIB_HwRev, SIB_HwRev, UniqueNum, Mac1, - Mac1Aux, Mac2, - Mac2Aux, Mac3, - Mac3Aux, Mac4, + Mac1Aux, + Mac2Aux, + Mac3Aux, Mac4Aux, SPD, FF_FreezeDis, @@ -43,11 +44,76 @@ typedef enum { MacMapping2, MacMapping3, MacMapping4, + RTCType, PF_Color_Depth, PF_DisplType, PF_DisplCon, Edid, - VddRef + VddRef, + T_Warn, + T_Crit, + FANSamplingTime, + FANSetPoint, + FANKp, + FANKi, + FANKd, + FANHystVal, + FANHystThreshold, + FANHystCtrl, + FANMaxSpeed, + FANStartpeed, + FANSensorDelay, + FANSensorNum, + FANSensorSelect, + FANSensorCfg0, + FANSensorCfg1, + FANSensorCfg2, + FANSensorCfg3, + FANSensorCfg4, + FANSensorCfg5, + FANSensorCfg6, + FANSensorCfg7, + XMac1, + XMac2, + XMac3, + XMac4, + XMac5, + XMac6, + XMac7, + XMac8, + XMac9, + XMac10, + XMac1Aux, + XMac2Aux, + XMac3Aux, + XMac4Aux, + XMac5Aux, + XMac6Aux, + XMac7Aux, + XMac8Aux, + XMac9Aux, + XMac10Aux, + XMac1Mapping, + XMac2Mapping, + XMac3Mapping, + XMac4Mapping, + XMac5Mapping, + XMac6Mapping, + XMac7Mapping, + XMac8Mapping, + XMac9Mapping, + XMac10Mapping, + netKind1, + netKind2, + netKind3, + netKind4, + netKind5, + netKind6, + netKind7, + netKind8, + netKind9, + netKind10 + } hwinfo_field_t; /* Define used values in supported fields */

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Patch set updated for coreboot: soc/intel/apollolake: Let CSE know Ring Buffer Protocol is not needed
by Andrey Petrov 29 Jun '16

29 Jun '16

Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15494 -gerrit commit 64a6385b558d4b241573e73523bfa35d9d353a24 Author: Andrey Petrov <andrey.petrov(a)intel.com> Date: Tue Jun 28 17:37:09 2016 -0700 soc/intel/apollolake: Let CSE know Ring Buffer Protocol is not needed On Apollolake CSE can be used to fetch firmware from boot media. However, when this feature is not used, CSE needs to be explicitly notified of it before memory training is complete. This way it can transition to next state. BUG=chrome-os-partner:53876 TEST=CSE can be power-gated during S0iX. Confirmed with LTB. Change-Id: I5141bff350b6c0bb662424b7b709f0787ec5fd28 Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- src/soc/intel/apollolake/romstage.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c index ce28326..049bf4f 100644 --- a/src/soc/intel/apollolake/romstage.c +++ b/src/soc/intel/apollolake/romstage.c @@ -241,6 +241,14 @@ void platform_fsp_memory_init_params_cb(struct FSPM_UPD *mupd) } else printk(BIOS_DEBUG, "MRC cache was not found\n"); } + + /* + * Tell CSE we do not need to use Ring Buffer Protocol (RBP) to fetch + * firmware for us if we are using memory-mapped SPI. This lets CSE + * state machine transition to next boot state, so that it can function + * as designed. + */ + mupd->FspmConfig.SkipCseRbp = IS_ENABLED(CONFIG_SPI_FLASH_MEMORY_MAPPED); } __attribute__ ((weak))

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Patch set updated for coreboot: soc/intel/apollolake: Let CSE know Ring Buffer Protocol is not needed
by Andrey Petrov 29 Jun '16

29 Jun '16

Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15494 -gerrit commit eefdf58733f20dc257130ae88bcd70d369092593 Author: Andrey Petrov <andrey.petrov(a)intel.com> Date: Tue Jun 28 17:37:09 2016 -0700 soc/intel/apollolake: Let CSE know Ring Buffer Protocol is not needed On Apollolake CSE can be used to fetch firmware from boot media. However, when this feature is not used, CSE needs to be explicitly notified of it before memory training is complete. This way it can transition to next state. BUG=chrome-os-partner:53876 TEST=CSE can be power-gated during S0iX. Confirmed with LTB. Change-Id: I5141bff350b6c0bb662424b7b709f0787ec5fd28 Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- src/soc/intel/apollolake/romstage.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c index ce28326..4c27066 100644 --- a/src/soc/intel/apollolake/romstage.c +++ b/src/soc/intel/apollolake/romstage.c @@ -241,6 +241,16 @@ void platform_fsp_memory_init_params_cb(struct FSPM_UPD *mupd) } else printk(BIOS_DEBUG, "MRC cache was not found\n"); } + + /* + * Tell CSE we do not need to use Ring Buffer Protocol (RBP) to fetch + * firmware for us if we are using memory-mapped SPI. This lets CSE + * state machine transition to next boot state, so that it can function + * as designed. + */ +#if IS_ENABLED(CONFIG_SPI_FLASH_MEMORY_MAPPED) + mupd->FspmConfig.SkipCseRbp = 1; +#endif } __attribute__ ((weak))

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Patch merged into coreboot/master: google/reef: set 20K PULLUP on SDCARD DATA/CLK/CMD
by gerrit＠coreboot.org 29 Jun '16

29 Jun '16

the following patch was just integrated into master: commit 7b3512dde3efa3d25d715bb61326ebfc995e9a69 Author: Freddy Paul <freddy.paul(a)intel.com> Date: Fri Jun 24 08:23:43 2016 -0700 google/reef: set 20K PULLUP on SDCARD DATA/CLK/CMD SD card need 20K PULLUP on D0-D3/CLOCK/COMMAND lines. Without this SDCARD will throw data read/write errors. BUG=chrome-os-partner:54676 TEST=Build and boot to OS. Verify SD card is detected and data read/write works well. Change-Id: I90da5b84dc2e488eb38f805322bd7b4dee394e5b Signed-off-by: Freddy Paul <freddy.paul(a)intel.com> Reviewed-on: https://review.coreboot.org/15345 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Tested-by: build bot (Jenkins) See https://review.coreboot.org/15345 for details. -gerrit

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coreboot-gerrit June 2016