coreboot-gerrit June 2016

coreboot-gerrit@coreboot.org

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1491 discussions

Patch set updated for coreboot: fsp_broadwell_de: Enable Super I/O address range decode
by Werner Zeh 29 Jun '16

29 Jun '16

Werner Zeh (werner.zeh(a)siemens.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15495 -gerrit commit 5c55ff11f7a742b4ed6ec8dc6b876a5ee38a3e71 Author: Werner Zeh <werner.zeh(a)siemens.com> Date: Wed Jun 29 07:17:21 2016 +0200 fsp_broadwell_de: Enable Super I/O address range decode If there is an external 16550 like UART, one needs to enable the appropriate address ranges before console_init() is called so that the init sequence can reach the external UART. Otherwise the UART will only start working in ramstage and will produce unreadable characters in romstage due to the lack of initialization. Tested-on: Siemens MC_BDX1 Change-Id: Iafc5b5b6df14916c5ed778928521d4a8f539cf46 Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- src/soc/intel/fsp_broadwell_de/include/soc/lpc.h | 4 +++- src/soc/intel/fsp_broadwell_de/romstage/romstage.c | 3 +++ 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/src/soc/intel/fsp_broadwell_de/include/soc/lpc.h b/src/soc/intel/fsp_broadwell_de/include/soc/lpc.h index 2c02ebd..0408f7f 100644 --- a/src/soc/intel/fsp_broadwell_de/include/soc/lpc.h +++ b/src/soc/intel/fsp_broadwell_de/include/soc/lpc.h @@ -21,6 +21,8 @@ #define REVID 0x08 #define PIRQ_RCR1 0x60 #define PIRQ_RCR2 0x68 +#define LPC_IO_DEC 0x80 +#define LPC_EN 0x82 #define GEN_PMCON_1 0xA0 #define GEN_PMCON_2 0xA2 #define GEN_PMCON_3 0xA4 @@ -83,4 +85,4 @@ #define TCO_TMR_HALT (1 << 11) #define TCO_TMR 0x70 -#endif /* _SOC_LPC_H_ */ \ No newline at end of file +#endif /* _SOC_LPC_H_ */ diff --git a/src/soc/intel/fsp_broadwell_de/romstage/romstage.c b/src/soc/intel/fsp_broadwell_de/romstage/romstage.c index dc883a4..bdfcbc8 100644 --- a/src/soc/intel/fsp_broadwell_de/romstage/romstage.c +++ b/src/soc/intel/fsp_broadwell_de/romstage/romstage.c @@ -48,6 +48,9 @@ static void init_rtc(void) void *asmlinkage main(FSP_INFO_HEADER *fsp_info_header) { post_code(0x40); + /* Enable decoding of I/O locations for Super I/O devices */ + pci_write_config16(PCI_DEV(0x0, LPC_DEV, LPC_FUNC), LPC_IO_DEC, 0x0010); + pci_write_config16(PCI_DEV(0x0, LPC_DEV, LPC_FUNC), LPC_EN, 0x340f); console_init(); init_rtc();

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Patch set updated for coreboot: intel/sandybridge: Use common ACPI S3 recovery
by Kyösti Mälkki 29 Jun '16

29 Jun '16

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15248 -gerrit commit a64b4444a7f53ff94de005affe340dd35c9a4e8b Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Fri Jun 17 22:54:22 2016 +0300 intel/sandybridge: Use common ACPI S3 recovery There is some 20ms delay with ACPI S3 wakeup time due to MTRR setup being done after the backup copy. Change-Id: Ib72ff914f5dfef8611f5f6cf9687495779013b02 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/cpu/intel/model_206ax/cache_as_ram.inc | 21 --------------------- src/northbridge/intel/sandybridge/early_init.c | 10 ++-------- src/northbridge/intel/sandybridge/sandybridge.h | 6 ------ 3 files changed, 2 insertions(+), 35 deletions(-) diff --git a/src/cpu/intel/model_206ax/cache_as_ram.inc b/src/cpu/intel/model_206ax/cache_as_ram.inc index a1f5cc9..e31d42a 100644 --- a/src/cpu/intel/model_206ax/cache_as_ram.inc +++ b/src/cpu/intel/model_206ax/cache_as_ram.inc @@ -281,27 +281,6 @@ before_romstage: /* Invalidate the cache again. */ invd - post_code(0x3c) - -#if CONFIG_HAVE_ACPI_RESUME - movl CBMEM_BOOT_MODE, %eax - cmpl $0x2, %eax // Resume? - jne __acpi_resume_backup_done - - /* copy 1MB - 64K to high tables ram_base to prevent memory corruption - * through stage 2. We could keep stuff like stack and heap in high - * tables memory completely, but that's a wonderful clean up task for - * another day. - */ - cld - movl $CONFIG_RAMBASE, %esi - movl CBMEM_RESUME_BACKUP, %edi - movl $HIGH_MEMORY_SAVE >> 2, %ecx - rep movsl - -__acpi_resume_backup_done: -#endif - post_code(0x3d) __main: diff --git a/src/northbridge/intel/sandybridge/early_init.c b/src/northbridge/intel/sandybridge/early_init.c index 779f29b..a013ec3 100644 --- a/src/northbridge/intel/sandybridge/early_init.c +++ b/src/northbridge/intel/sandybridge/early_init.c @@ -233,15 +233,9 @@ void northbridge_romstage_finalize(int s3resume) * this is not a resume. In that case we just create the cbmem toc. */ - *(u32 *)CBMEM_BOOT_MODE = 0; - *(u32 *)CBMEM_RESUME_BACKUP = 0; - if (s3resume) { - void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME); - if (resume_backup_memory) { - *(u32 *)CBMEM_BOOT_MODE = 2; - *(u32 *)CBMEM_RESUME_BACKUP = (u32)resume_backup_memory; - } + acpi_prepare_for_resume(); + /* Magic for S3 resume */ pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafed00d); } else { diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h index 7b0efd1..af5bd48 100644 --- a/src/northbridge/intel/sandybridge/sandybridge.h +++ b/src/northbridge/intel/sandybridge/sandybridge.h @@ -196,12 +196,6 @@ #define DMIDRCCFG 0xeb4 /* 32bit */ -/* Delegation of resume backup memory so we don't have to - * (slowly) handle backing up OS memory in romstage.c - */ -#define CBMEM_BOOT_MODE 0x610 -#define CBMEM_RESUME_BACKUP 0x614 - #ifndef __ASSEMBLER__ static inline void barrier(void) { asm("" ::: "memory"); }

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Patch set updated for coreboot: AGESA boards: Fix split to romstage and ramstage
by Kyösti Mälkki 29 Jun '16

29 Jun '16

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15344 -gerrit commit 1174caaf4c739ab6593794b80730aa3d00da12b0 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Fri Jun 24 16:37:05 2016 +0300 AGESA boards: Fix split to romstage and ramstage Boards broken with commit: 062ef1c AGESA boards: Split dispatcher to romstage and ramstage Boot failure with asus/f2a85-m witnessed around MemMS3Save() call, message "Save memory S3 data in heap" in verbose agesa logs was replaced by a system reset. Default stubs for MemS3ResumeConstructNBBlock() returned TRUE without initializing the block contents. This would not work for case with multiple NB support built into same firmware. MemMCreateS3NbBlock() then returned with S3NBPtr!=NULL with uninitialized data and MemMContextSave() referenced those as invalid pointers. There is no reason to prevent booting in the case S3 resume data is not passed to ramstage, so remove the ASSERT(). It only affects builds with IDSOPT_IDS_ENABLED=TRUE anyways. Change-Id: I8fd1e308ceab2b6f4b4c90f0f712934c2918d92d Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/vendorcode/amd/agesa/f15tn/Include/OptionMemoryInstall.h | 2 +- src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/mmMemRestore.c | 1 - src/vendorcode/amd/agesa/f16kb/Include/OptionMemoryInstall.h | 2 +- src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/mmMemRestore.c | 1 - 4 files changed, 2 insertions(+), 4 deletions(-) diff --git a/src/vendorcode/amd/agesa/f15tn/Include/OptionMemoryInstall.h b/src/vendorcode/amd/agesa/f15tn/Include/OptionMemoryInstall.h index e1c47ee..0cb25b8 100644 --- a/src/vendorcode/amd/agesa/f15tn/Include/OptionMemoryInstall.h +++ b/src/vendorcode/amd/agesa/f15tn/Include/OptionMemoryInstall.h @@ -124,7 +124,7 @@ BOOLEAN MemFS3DefConstructorRet ( IN UINT8 NodeID ) { - return TRUE; + return FALSE; } #if (OPTION_MEMCTLR_DR == TRUE) diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/mmMemRestore.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/mmMemRestore.c index 244420d..ab1ce1a 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/mmMemRestore.c +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/mmMemRestore.c @@ -319,7 +319,6 @@ MemMS3Save ( if (RefPtr->MemContext.NvStorage == NULL) { // Memory context cannot be saved succesfully - ASSERT (FALSE); return FALSE; } } diff --git a/src/vendorcode/amd/agesa/f16kb/Include/OptionMemoryInstall.h b/src/vendorcode/amd/agesa/f16kb/Include/OptionMemoryInstall.h index 647c370..8269742 100644 --- a/src/vendorcode/amd/agesa/f16kb/Include/OptionMemoryInstall.h +++ b/src/vendorcode/amd/agesa/f16kb/Include/OptionMemoryInstall.h @@ -124,7 +124,7 @@ BOOLEAN MemFS3DefConstructorRet ( IN UINT8 NodeID ) { - return TRUE; + return FALSE; } #if (OPTION_MEMCTLR_TN == TRUE) diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/mmMemRestore.c b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/mmMemRestore.c index 3d80baf..248e98c 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/mmMemRestore.c +++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/mmMemRestore.c @@ -576,7 +576,6 @@ MemMS3Save ( if (RefPtr->MemContext.NvStorage == NULL) { // Memory context cannot be saved succesfully - ASSERT (FALSE); return FALSE; } }

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Patch set updated for coreboot: AMD binaryPI: Use common ACPI S3 recovery
by Kyösti Mälkki 29 Jun '16

29 Jun '16

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15254 -gerrit commit 94fba59891fc8235b8f4193b9f480eb52880de81 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sat Jun 18 17:55:08 2016 +0300 AMD binaryPI: Use common ACPI S3 recovery Note that no binaryPI board has HAVE_ACPI_RESUME. Change-Id: Ic7d87aa81c75374dd1570cef412a3ca245285d58 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/cpu/amd/pi/s3_resume.c | 31 ++++++------------------------- 1 file changed, 6 insertions(+), 25 deletions(-) diff --git a/src/cpu/amd/pi/s3_resume.c b/src/cpu/amd/pi/s3_resume.c index b6d3633..576a208 100644 --- a/src/cpu/amd/pi/s3_resume.c +++ b/src/cpu/amd/pi/s3_resume.c @@ -28,6 +28,7 @@ #include <string.h> #include "Porting.h" #include <northbridge/amd/pi/BiosCallOuts.h> +#include <halt.h> #include "s3_resume.h" /* The size needs to be 4k aligned, which is the sector size of most flashes. */ @@ -134,24 +135,6 @@ void restore_mtrr(void) } #ifdef __PRE_RAM__ -static void *backup_resume(void) -{ - void *resume_backup_memory; - - if (cbmem_recovery(1)) - return NULL; - - resume_backup_memory = cbmem_find(CBMEM_ID_RESUME); - if (((u32) resume_backup_memory == 0) - || ((u32) resume_backup_memory == -1)) { - printk(BIOS_ERR, "Error: resume_backup_memory: %x\n", - (u32) resume_backup_memory); - for (;;) ; - } - - return resume_backup_memory; -} - static void move_stack_high_mem(void) { void *high_stack; @@ -289,13 +272,14 @@ static void set_resume_cache(void) void prepare_for_resume(void) { - printk(BIOS_DEBUG, "Find resume memory location\n"); - void *resume_backup_memory = backup_resume(); + if (cbmem_recovery(1)) { + printk(BIOS_EMERG, "Unable to recover CBMEM\n"); + halt(); + } post_code(0x62); printk(BIOS_DEBUG, "Move CAR stack.\n"); move_stack_high_mem(); - printk(BIOS_DEBUG, "stack moved to: 0x%x\n", (u32) (resume_backup_memory + HIGH_MEMORY_SAVE)); post_code(0x63); disable_cache_as_ram(); @@ -306,9 +290,6 @@ void prepare_for_resume(void) * Copy the system memory that is in the ramstage area to the * reserved area. */ - if (resume_backup_memory) - memcpy(resume_backup_memory, (void *)(CONFIG_RAMBASE), HIGH_MEMORY_SAVE); - - printk(BIOS_DEBUG, "System memory saved. OK to load ramstage.\n"); + acpi_prepare_for_resume(); } #endif

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Patch set updated for coreboot: intel post-car: Consolidate choose_top_of_stack()
by Kyösti Mälkki 29 Jun '16

29 Jun '16

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15463 -gerrit commit ac8d988354b51b00737a7b3913471b89b74ebc50 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Mon Jun 27 14:50:27 2016 +0300 intel post-car: Consolidate choose_top_of_stack() Change-Id: I2c49d68ea9a8f52737b6064bc4fa703bdb1af1df Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/cpu/intel/haswell/romstage.c | 16 +--------- src/drivers/intel/fsp1_1/Kconfig | 4 --- src/drivers/intel/fsp1_1/stack.c | 23 ++------------ src/include/program_loading.h | 6 ++++ src/lib/Makefile.inc | 1 + src/lib/romstage_stack.c | 48 ++++++++++++++++++++++++++++++ src/soc/intel/baytrail/romstage/romstage.c | 16 +--------- src/soc/intel/broadwell/romstage/stack.c | 17 ++--------- 8 files changed, 62 insertions(+), 69 deletions(-) diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c index cde9441..9154316 100644 --- a/src/cpu/intel/haswell/romstage.c +++ b/src/cpu/intel/haswell/romstage.c @@ -65,20 +65,6 @@ static inline u32 *stack_push(u32 *stack, u32 value) return stack; } -/* Romstage needs quite a bit of stack for decompressing images since the lzma - * lib keeps its state on the stack during romstage. */ -#define ROMSTAGE_RAM_STACK_SIZE 0x5000 -static unsigned long choose_top_of_stack(void) -{ - unsigned long stack_top; - - /* cbmem_add() does a find() before add(). */ - stack_top = (unsigned long)cbmem_add(CBMEM_ID_ROMSTAGE_RAM_STACK, - ROMSTAGE_RAM_STACK_SIZE); - stack_top += ROMSTAGE_RAM_STACK_SIZE; - return stack_top; -} - /* setup_romstage_stack_after_car() determines the stack to use after * cache-as-ram is torn down as well as the MTRR settings to use. */ static void *setup_romstage_stack_after_car(void) @@ -90,7 +76,7 @@ static void *setup_romstage_stack_after_car(void) u32 top_of_ram; /* Top of stack needs to be aligned to a 4-byte boundary. */ - top_of_stack = choose_top_of_stack() & ~3; + top_of_stack = romstage_ram_stack_top() & ~3; slot = (void *)top_of_stack; num_mtrrs = 0; diff --git a/src/drivers/intel/fsp1_1/Kconfig b/src/drivers/intel/fsp1_1/Kconfig index 86f6c7b..59b4797 100644 --- a/src/drivers/intel/fsp1_1/Kconfig +++ b/src/drivers/intel/fsp1_1/Kconfig @@ -99,10 +99,6 @@ config GOP_SUPPORT bool "Enable GOP support" default n -config ROMSTAGE_RAM_STACK_SIZE - hex "Size of the romstage RAM stack in bytes" - default 0x5000 - config USE_GENERIC_FSP_CAR_INC bool default n diff --git a/src/drivers/intel/fsp1_1/stack.c b/src/drivers/intel/fsp1_1/stack.c index 65ba235..8d0759a 100644 --- a/src/drivers/intel/fsp1_1/stack.c +++ b/src/drivers/intel/fsp1_1/stack.c @@ -21,23 +21,7 @@ #include <fsp/romstage.h> #include <fsp/stack.h> #include <stdlib.h> - -const unsigned long romstage_ram_stack_size = CONFIG_ROMSTAGE_RAM_STACK_SIZE; - -/* - * Romstage needs quite a bit of stack for decompressing images since the lzma - * lib keeps its state on the stack during romstage. - */ -static unsigned long choose_top_of_stack(void) -{ - unsigned long stack_top; - - /* cbmem_add() does a find() before add(). */ - stack_top = (unsigned long)cbmem_add(CBMEM_ID_ROMSTAGE_RAM_STACK, - romstage_ram_stack_size); - stack_top += romstage_ram_stack_size; - return stack_top; -} +#include <program_loading.h> /* * setup_stack_and_mtrrs() determines the stack to use after @@ -57,7 +41,7 @@ void *setup_stack_and_mtrrs(void) soc_display_mtrrs(); /* Top of stack needs to be aligned to a 8-byte boundary. */ - top_of_stack = choose_top_of_stack(); + top_of_stack = romstage_ram_stack_top(); slot = (void *)top_of_stack; num_mtrrs = 0; max_mtrrs = soc_get_variable_mtrr_count(NULL); @@ -68,8 +52,7 @@ void *setup_stack_and_mtrrs(void) */ mtrr_mask_upper = (1 << ((cpuid_eax(0x80000008) & 0xff) - 32)) - 1; alignment = mmap_region_granularity(); - aligned_ram = ALIGN_DOWN(top_of_stack - romstage_ram_stack_size, - alignment); + aligned_ram = ALIGN_DOWN(romstage_ram_stack_bottom(), alignment); /* * The order for each MTRR is value then base with upper 32-bits of diff --git a/src/include/program_loading.h b/src/include/program_loading.h index 42addb8..4cadab6 100644 --- a/src/include/program_loading.h +++ b/src/include/program_loading.h @@ -170,6 +170,12 @@ void run_ramstage(void); /* Called when the stage cache couldn't load ramstage on resume. */ void ramstage_cache_invalid(void); +/* Determine where stack for ramstage loader is located. */ +enum { ROMSTAGE_STACK_CBMEM, ROMSTAGE_STACK_LOW_MEM }; +uintptr_t romstage_ram_stack_source(size_t size, int src); +uintptr_t romstage_ram_stack_top(void); +uintptr_t romstage_ram_stack_bottom(void); + /*********************** * PAYLOAD LOADING * ***********************/ diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 1028917..0c34b75 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -78,6 +78,7 @@ romstage-$(CONFIG_PRIMITIVE_MEMTEST) += primitive_memtest.c ramstage-$(CONFIG_PRIMITIVE_MEMTEST) += primitive_memtest.c romstage-$(CONFIG_CACHE_AS_RAM) += ramtest.c romstage-$(CONFIG_GENERIC_GPIO_LIB) += gpio.c +romstage-y += romstage_stack.c romstage-y += stack.c ramstage-y += rtc.c diff --git a/src/lib/romstage_stack.c b/src/lib/romstage_stack.c new file mode 100644 index 0000000..97313f5 --- /dev/null +++ b/src/lib/romstage_stack.c @@ -0,0 +1,48 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015-2016 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <program_loading.h> +#include <cbmem.h> + +/* + * Romstage needs quite a bit of stack for decompressing images since the lzma + * lib keeps its state on the stack during romstage. + */ +#define ROMSTAGE_RAM_STACK_SIZE 0x5000 + +uintptr_t romstage_ram_stack_source(size_t size, int src) +{ + /* cbmem_add() does a find() before add(). */ + if (src == ROMSTAGE_STACK_CBMEM) + return (uintptr_t)cbmem_add(CBMEM_ID_ROMSTAGE_RAM_STACK, size); + if (src == ROMSTAGE_STACK_LOW_MEM) + return CONFIG_RAMTOP - size; + return 0; +} + +uintptr_t romstage_ram_stack_bottom(void) +{ + return romstage_ram_stack_source(ROMSTAGE_RAM_STACK_SIZE, + ROMSTAGE_STACK_CBMEM); +} + +uintptr_t romstage_ram_stack_top(void) +{ + uintptr_t stack_top = romstage_ram_stack_source(ROMSTAGE_RAM_STACK_SIZE, + ROMSTAGE_STACK_CBMEM); + stack_top += ROMSTAGE_RAM_STACK_SIZE; + return stack_top; +} diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c index a167c90..d7e8b17 100644 --- a/src/soc/intel/baytrail/romstage/romstage.c +++ b/src/soc/intel/baytrail/romstage/romstage.c @@ -258,20 +258,6 @@ static inline uint32_t *stack_push(u32 *stack, u32 value) return stack; } -/* Romstage needs quite a bit of stack for decompressing images since the lzma - * lib keeps its state on the stack during romstage. */ -static unsigned long choose_top_of_stack(void) -{ - unsigned long stack_top; - const unsigned long romstage_ram_stack_size = 0x5000; - - /* cbmem_add() does a find() before add(). */ - stack_top = (unsigned long)cbmem_add(CBMEM_ID_ROMSTAGE_RAM_STACK, - romstage_ram_stack_size); - stack_top += romstage_ram_stack_size; - return stack_top; -} - /* setup_stack_and_mttrs() determines the stack to use after * cache-as-ram is torn down as well as the MTRR settings to use. */ static void *setup_stack_and_mttrs(void) @@ -283,7 +269,7 @@ static void *setup_stack_and_mttrs(void) uint32_t top_of_ram; /* Top of stack needs to be aligned to a 4-byte boundary. */ - top_of_stack = choose_top_of_stack() & ~3; + top_of_stack = romstage_ram_stack_top() & ~3; slot = (void *)top_of_stack; num_mtrrs = 0; diff --git a/src/soc/intel/broadwell/romstage/stack.c b/src/soc/intel/broadwell/romstage/stack.c index 6c602a8..76307cf 100644 --- a/src/soc/intel/broadwell/romstage/stack.c +++ b/src/soc/intel/broadwell/romstage/stack.c @@ -21,6 +21,7 @@ #include <cbmem.h> #include <cpu/x86/mtrr.h> #include <soc/romstage.h> +#include <program_loading.h> static inline uint32_t *stack_push(u32 *stack, u32 value) { @@ -29,20 +30,6 @@ static inline uint32_t *stack_push(u32 *stack, u32 value) return stack; } -/* Romstage needs quite a bit of stack for decompressing images since the lzma - * lib keeps its state on the stack during romstage. */ -static unsigned long choose_top_of_stack(void) -{ - unsigned long stack_top; - const unsigned long romstage_ram_stack_size = 0x5000; - - /* cbmem_add() does a find() before add(). */ - stack_top = (unsigned long)cbmem_add(CBMEM_ID_ROMSTAGE_RAM_STACK, - romstage_ram_stack_size); - stack_top += romstage_ram_stack_size; - return stack_top; -} - /* setup_stack_and_mttrs() determines the stack to use after * cache-as-ram is torn down as well as the MTRR settings to use. */ void *setup_stack_and_mttrs(void) @@ -54,7 +41,7 @@ void *setup_stack_and_mttrs(void) uint32_t top_of_ram; /* Top of stack needs to be aligned to a 4-byte boundary. */ - top_of_stack = choose_top_of_stack() & ~3; + top_of_stack = romstage_ram_stack_top() & ~3; slot = (void *)top_of_stack; num_mtrrs = 0;

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Patch set updated for coreboot: ACPI S3: Remove HIGH_MEMORY_SAVE where possible
by Kyösti Mälkki 29 Jun '16

29 Jun '16

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15255 -gerrit commit 7ae58f3f0614df067d5fb4ca652bbb5146eba488 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Jun 28 07:38:46 2016 +0300 ACPI S3: Remove HIGH_MEMORY_SAVE where possible Use actual requirements of ramstage size for S3 resume backup in CBMEM. The backup covers complete pages of 4 KiB. AMD k8 and fam10 platforms have not been adapted yet. Change-Id: Ide7ce013f3727c2928cdb00fbcc7e7e84e859ff1 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/Kconfig | 4 ++ src/arch/x86/acpi_s3.c | 115 +++++++++++++++++++++++++----- src/arch/x86/include/arch/acpi.h | 10 +-- src/cpu/amd/car/post_cache_as_ram.c | 9 ++- src/cpu/amd/family_10h-family_15h/Kconfig | 1 + src/cpu/amd/model_fxx/Kconfig | 1 + src/include/cbfs.h | 3 + src/include/program_loading.h | 4 ++ src/lib/cbfs.c | 12 ++++ src/lib/prog_loaders.c | 14 +++- 10 files changed, 144 insertions(+), 29 deletions(-) diff --git a/src/Kconfig b/src/Kconfig index 7043851..b4c3cbe 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -516,6 +516,10 @@ config HAVE_ACPI_RESUME bool default n +config ACPI_HUGE_LOWMEM_BACKUP + bool + default n + config RESUME_PATH_SAME_AS_BOOT bool default y if ARCH_X86 diff --git a/src/arch/x86/acpi_s3.c b/src/arch/x86/acpi_s3.c index 7855a2f..c744eb5 100644 --- a/src/arch/x86/acpi_s3.c +++ b/src/arch/x86/acpi_s3.c @@ -19,8 +19,10 @@ #include <cbmem.h> #include <cpu/cpu.h> #include <timestamp.h> +#include <program_loading.h> #include <romstage_handoff.h> #include <rules.h> +#include <symbols.h> #if ENV_RAMSTAGE @@ -79,30 +81,101 @@ void acpi_fail_wakeup(void) } #endif /* ENV_RAMSTAGE */ -void acpi_prepare_for_resume(void) +struct resume_backup { + uintptr_t cbmem; + uintptr_t lowmem; + size_t size; + int valid; +}; + +#define BACKUP_PAGE_SZ 4096 + +void *acpi_backup_container(uintptr_t base, size_t size) { - if (!HIGH_MEMORY_SAVE) + struct resume_backup *backup_mem; + uintptr_t top, target; + + if (IS_ENABLED(CONFIG_ACPI_HUGE_LOWMEM_BACKUP)) { + base = CONFIG_RAMBASE; + size = HIGH_MEMORY_SAVE; + } + + /* Align backup region to complete pages. */ + top = ALIGN_UP(base + size, BACKUP_PAGE_SZ); + base = ALIGN_DOWN(base, BACKUP_PAGE_SZ); + + /* FIXME: Check previous CBMEM allocation. */ + + /* Allocate storage with struct resume_backup. */ + size = 2*BACKUP_PAGE_SZ + (top - base); + backup_mem = cbmem_add(CBMEM_ID_RESUME, size); + if (backup_mem == NULL) + return NULL; + + /* Force alignment on the container itself.*/ + target = (uintptr_t)backup_mem + sizeof(*backup_mem); + target = ALIGN_UP(target, BACKUP_PAGE_SZ); + + backup_mem->valid = 0; + backup_mem->cbmem = target; + backup_mem->lowmem = base; + backup_mem->size = top - base; + + return (void*)target; +} + +void acpi_backup_validate(void) +{ + struct resume_backup *backup_mem = cbmem_find(CBMEM_ID_RESUME); + if (backup_mem) + backup_mem->valid = 1; +} + +void backup_ramstage_section(uintptr_t base, size_t size) +{ + struct resume_backup *backup_mem = cbmem_find(CBMEM_ID_RESUME); + if (backup_mem == NULL) + return; + + /* Check that the backup is not done twice. */ + if (backup_mem->valid) return; + /* We are called from ramstage loader, do not rely on previously + * loaded ramstage for location. */ + if (size) + acpi_backup_container(base, size); + /* Back up the OS-controlled memory where ramstage will be loaded. */ - void *src = (void *)CONFIG_RAMBASE; - void *dest = cbmem_find(CBMEM_ID_RESUME); - if (dest != NULL) - memcpy(dest, src, HIGH_MEMORY_SAVE); + memcpy((void*)backup_mem->cbmem, (void*)backup_mem->lowmem, backup_mem->size); + backup_mem->valid = 1; +} + +/* Make backup of low-memory region, relying on the base and size + * of the ramstage that was loaded before entry to ACPI S3. + * + * DEPRECATED + */ +void acpi_prepare_for_resume(void) +{ + backup_ramstage_section(0, 0); } +/* Let's prepare the ACPI S3 Resume area now already, so we can rely on + * it being there during reboot time. If this fails, ACPI resume will + * be disabled. We assume that ramstage does not change while in suspend, + * so base and size of the currently running ramstage are used + * for allocation. + */ void acpi_prepare_resume_backup(void) { if (!acpi_s3_resume_allowed()) return; - /* Let's prepare the ACPI S3 Resume area now already, so we can rely on - * it being there during reboot time. We don't need the pointer, nor - * the result right now. If it fails, ACPI resume will be disabled. - */ + if (IS_ENABLED(CONFIG_RELOCATABLE_RAMSTAGE)) + return; - if (HIGH_MEMORY_SAVE) - cbmem_add(CBMEM_ID_RESUME, HIGH_MEMORY_SAVE); + acpi_backup_container((uintptr_t)_program, _program_size); } #define WAKEUP_BASE 0x600 @@ -115,17 +188,22 @@ extern unsigned int __wakeup_size; static void acpi_jump_to_wakeup(void *vector) { - uintptr_t acpi_backup_memory = 0; + uintptr_t source = 0, target = 0; + size_t size = 0; if (!acpi_s3_resume_allowed()) { printk(BIOS_WARNING, "ACPI: S3 resume not allowed.\n"); return; } - if (HIGH_MEMORY_SAVE) { - acpi_backup_memory = (uintptr_t)cbmem_find(CBMEM_ID_RESUME); - - if (!acpi_backup_memory) { + if (!IS_ENABLED(CONFIG_RELOCATABLE_RAMSTAGE)) { + struct resume_backup *backup_mem = cbmem_find(CBMEM_ID_RESUME); + if (backup_mem && backup_mem->valid) { + backup_mem->valid = 0; + target = backup_mem->lowmem; + source = backup_mem->cbmem; + size = backup_mem->size; + } else { printk(BIOS_WARNING, "ACPI: Backup memory missing. " "No S3 resume.\n"); return; @@ -137,8 +215,7 @@ static void acpi_jump_to_wakeup(void *vector) timestamp_add_now(TS_ACPI_WAKE_JUMP); - acpi_do_wakeup((uintptr_t)vector, acpi_backup_memory, CONFIG_RAMBASE, - HIGH_MEMORY_SAVE); + acpi_do_wakeup((uintptr_t)vector, source, target, size); } void __attribute__((weak)) mainboard_suspend_resume(void) diff --git a/src/arch/x86/include/arch/acpi.h b/src/arch/x86/include/arch/acpi.h index 7434000..2071f93 100644 --- a/src/arch/x86/include/arch/acpi.h +++ b/src/arch/x86/include/arch/acpi.h @@ -24,13 +24,6 @@ #ifndef __ASM_ACPI_H #define __ASM_ACPI_H -#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) && \ - ! IS_ENABLED(CONFIG_RELOCATABLE_RAMSTAGE) -#define HIGH_MEMORY_SAVE (CONFIG_RAMTOP - CONFIG_RAMBASE) -#else -#define HIGH_MEMORY_SAVE 0 -#endif - #ifndef __ASSEMBLER__ #include <stdint.h> #include <rules.h> @@ -623,6 +616,9 @@ static inline int acpi_s3_resume_allowed(void) return IS_ENABLED(CONFIG_HAVE_ACPI_RESUME); } +void *acpi_backup_container(uintptr_t base, size_t size); +void acpi_backup_validate(void); + #if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) extern int acpi_slp_type; diff --git a/src/cpu/amd/car/post_cache_as_ram.c b/src/cpu/amd/car/post_cache_as_ram.c index 15b2642..9e9b10d 100644 --- a/src/cpu/amd/car/post_cache_as_ram.c +++ b/src/cpu/amd/car/post_cache_as_ram.c @@ -31,6 +31,8 @@ #error "You need to set CONFIG_RAMTOP greater than 1M" #endif +#define HIGH_MEMORY_SAVE (CONFIG_RAMTOP - CONFIG_RAMBASE) + #if IS_ENABLED(CONFIG_DEBUG_CAR) #define print_car_debug(format, arg...) printk(BIOS_DEBUG, "%s: " format, __func__, ##arg) #else @@ -69,7 +71,7 @@ static void prepare_romstage_ramstack(int s3resume) print_car_debug("Prepare CAR migration and stack regions..."); if (s3resume) { - void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME); + void *resume_backup_memory = acpi_backup_container(CONFIG_RAMBASE, HIGH_MEMORY_SAVE); if (resume_backup_memory) memcpy_(resume_backup_memory + HIGH_MEMORY_SAVE - backup_top, (void *)(CONFIG_RAMTOP - backup_top), backup_top); @@ -85,7 +87,7 @@ static void prepare_ramstage_region(int s3resume) print_car_debug("Prepare ramstage memory region..."); if (s3resume) { - void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME); + void *resume_backup_memory = acpi_backup_container(CONFIG_RAMBASE, HIGH_MEMORY_SAVE); if (resume_backup_memory) memcpy_(resume_backup_memory, (void *) CONFIG_RAMBASE, HIGH_MEMORY_SAVE - backup_top); @@ -102,6 +104,9 @@ static void prepare_ramstage_region(int s3resume) #endif print_car_debug(" Done\n"); + + if (s3resume) + acpi_backup_validate(); } /* Disable Erratum 343 Workaround, see RevGuide for Fam10h, Pub#41322 Rev 3.33 diff --git a/src/cpu/amd/family_10h-family_15h/Kconfig b/src/cpu/amd/family_10h-family_15h/Kconfig index fda7fc8..30c7dee 100644 --- a/src/cpu/amd/family_10h-family_15h/Kconfig +++ b/src/cpu/amd/family_10h-family_15h/Kconfig @@ -10,6 +10,7 @@ config CPU_AMD_MODEL_10XXX select TSC_SYNC_LFENCE select UDELAY_LAPIC select HAVE_MONOTONIC_TIMER + select ACPI_HUGE_LOWMEM_BACKUP select SUPPORT_CPU_UCODE_IN_CBFS select CPU_MICROCODE_MULTIPLE_FILES if !CPU_MICROCODE_CBFS_NONE diff --git a/src/cpu/amd/model_fxx/Kconfig b/src/cpu/amd/model_fxx/Kconfig index c8bae33..3eb5b94 100644 --- a/src/cpu/amd/model_fxx/Kconfig +++ b/src/cpu/amd/model_fxx/Kconfig @@ -9,6 +9,7 @@ config CPU_AMD_MODEL_FXX select SSE2 select TSC_SYNC_LFENCE select UDELAY_LAPIC + select ACPI_HUGE_LOWMEM_BACKUP select SUPPORT_CPU_UCODE_IN_CBFS if CPU_AMD_MODEL_FXX diff --git a/src/include/cbfs.h b/src/include/cbfs.h index 2d19218..6a9e054 100644 --- a/src/include/cbfs.h +++ b/src/include/cbfs.h @@ -43,6 +43,9 @@ void *cbfs_boot_map_with_leak(const char *name, uint32_t type, size_t *size); size_t cbfs_load_and_decompress(const struct region_device *rdev, size_t offset, size_t in_size, void *buffer, size_t buffer_size, uint32_t compression); +/* Fill base and size of the memory pstage will occupy when loaded. */ +void cbfs_prog_stage_section(struct prog *pstage, uint32_t *base, uint32_t *size); + /* Load stage into memory filling in prog. Return 0 on success. < 0 on error. */ int cbfs_prog_stage_load(struct prog *prog); diff --git a/src/include/program_loading.h b/src/include/program_loading.h index 4cadab6..8da6ada 100644 --- a/src/include/program_loading.h +++ b/src/include/program_loading.h @@ -176,6 +176,10 @@ uintptr_t romstage_ram_stack_source(size_t size, int src); uintptr_t romstage_ram_stack_top(void); uintptr_t romstage_ram_stack_bottom(void); +/* Backup OS memory to CBMEM_ID_RESUME on ACPI S3 resume path, + * if ramstage overwrites low memory. */ +void backup_ramstage_section(uintptr_t base, size_t size); + /*********************** * PAYLOAD LOADING * ***********************/ diff --git a/src/lib/cbfs.c b/src/lib/cbfs.c index aa652c2..c00e6aa 100644 --- a/src/lib/cbfs.c +++ b/src/lib/cbfs.c @@ -166,6 +166,18 @@ void *cbfs_boot_load_stage_by_name(const char *name) return prog_entry(&stage); } +void cbfs_prog_stage_section(struct prog *pstage, uint32_t *base, uint32_t *size) +{ + struct cbfs_stage stage; + const struct region_device *fh = prog_rdev(pstage); + + if (rdev_readat(fh, &stage, 0, sizeof(stage)) != sizeof(stage)) + return; + + *base = stage.load; + *size = stage.memlen; +} + int cbfs_prog_stage_load(struct prog *pstage) { struct cbfs_stage stage; diff --git a/src/lib/prog_loaders.c b/src/lib/prog_loaders.c index ecbc679..d659abe 100644 --- a/src/lib/prog_loaders.c +++ b/src/lib/prog_loaders.c @@ -101,6 +101,18 @@ static int load_relocatable_ramstage(struct prog *ramstage) return rmodule_stage_load(&rmod_ram); } +static int load_nonrelocatable_ramstage(struct prog *ramstage) +{ + if (IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)) { + uint32_t base = 0, size = 0; + cbfs_prog_stage_section(ramstage, &base, &size); + if (size) + backup_ramstage_section(base, size); + } + + return cbfs_prog_stage_load(ramstage); +} + void run_ramstage(void) { struct prog ramstage = @@ -126,7 +138,7 @@ void run_ramstage(void) if (IS_ENABLED(CONFIG_RELOCATABLE_RAMSTAGE)) { if (load_relocatable_ramstage(&ramstage)) goto fail; - } else if (cbfs_prog_stage_load(&ramstage)) + } else if (load_nonrelocatable_ramstage(&ramstage)) goto fail; stage_cache_add(STAGE_RAMSTAGE, &ramstage);

1 0

Patch set updated for coreboot: AGESA: Use common ACPI S3 recovery
by Kyösti Mälkki 29 Jun '16

29 Jun '16

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15253 -gerrit commit 79d1bc11c691e2b70d1f1f1aaad1725a33b2b8d5 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sat Jun 18 16:55:51 2016 +0300 AGESA: Use common ACPI S3 recovery Previous behaviour was to halt() on S3 wakeup in case resume backup memory was missing. In this odd case we now continue to normal boot. Change-Id: I8ce91088c5fa1a2d2abc53b23e423939fe759117 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/cpu/amd/agesa/s3_resume.c | 32 +++++++------------------------- 1 file changed, 7 insertions(+), 25 deletions(-) diff --git a/src/cpu/amd/agesa/s3_resume.c b/src/cpu/amd/agesa/s3_resume.c index 3a60b8d..54e41c1 100644 --- a/src/cpu/amd/agesa/s3_resume.c +++ b/src/cpu/amd/agesa/s3_resume.c @@ -25,29 +25,11 @@ #include <halt.h> #include "s3_resume.h" -static void *backup_resume(void) -{ - void *resume_backup_memory; - - printk(BIOS_DEBUG, "Find resume memory location\n"); - - if (cbmem_recovery(1)) { - printk(BIOS_EMERG, "Unable to recover CBMEM\n"); - halt(); - } - - resume_backup_memory = cbmem_find(CBMEM_ID_RESUME); - if (resume_backup_memory == NULL) { - printk(BIOS_EMERG, "No storage for low-memory backup\n"); - halt(); - } - - return resume_backup_memory; -} - static void move_stack_high_mem(void) { void *high_stack = cbmem_find(CBMEM_ID_ROMSTAGE_RAM_STACK); + if (high_stack == NULL) + halt(); /* TODO: Make the switch with empty stack instead. */ memcpy(high_stack, (void *)BSP_STACK_BASE_ADDR, HIGH_ROMSTAGE_STACK_SIZE); @@ -93,7 +75,10 @@ static void set_resume_cache(void) void prepare_for_resume(void) { - void *resume_backup_memory = backup_resume(); + if (cbmem_recovery(1)) { + printk(BIOS_EMERG, "Unable to recover CBMEM\n"); + halt(); + } post_code(0x62); printk(BIOS_DEBUG, "Move CAR stack.\n"); @@ -108,8 +93,5 @@ void prepare_for_resume(void) * Copy the system memory that is in the ramstage area to the * reserved area. */ - if (resume_backup_memory) - memcpy(resume_backup_memory, (void *)(CONFIG_RAMBASE), HIGH_MEMORY_SAVE); - - printk(BIOS_DEBUG, "System memory saved. OK to load ramstage.\n"); + acpi_prepare_for_resume(); }

1 0

Patch set updated for coreboot: AGESA: Use common romstage ram stack
by Kyösti Mälkki 29 Jun '16

29 Jun '16

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15466 -gerrit commit 7091b7da6478f2360dd92485c38abd5ece618ea5 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Mon Jun 27 16:15:02 2016 +0300 AGESA: Use common romstage ram stack Change-Id: Ie120360fa79aa0f6f6d82606838404bb0b0d9681 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/cpu/amd/agesa/s3_resume.c | 8 +++++--- src/lib/Makefile.inc | 1 + src/northbridge/amd/agesa/oem_s3.c | 4 ++-- 3 files changed, 8 insertions(+), 5 deletions(-) diff --git a/src/cpu/amd/agesa/s3_resume.c b/src/cpu/amd/agesa/s3_resume.c index 54e41c1..c5436ed 100644 --- a/src/cpu/amd/agesa/s3_resume.c +++ b/src/cpu/amd/agesa/s3_resume.c @@ -21,18 +21,20 @@ #include <cpu/amd/mtrr.h> #include <cpu/x86/cache.h> #include <cbmem.h> +#include <program_loading.h> #include <string.h> #include <halt.h> #include "s3_resume.h" static void move_stack_high_mem(void) { - void *high_stack = cbmem_find(CBMEM_ID_ROMSTAGE_RAM_STACK); - if (high_stack == NULL) + uintptr_t high_stack = romstage_ram_stack_source(HIGH_ROMSTAGE_STACK_SIZE, + ROMSTAGE_STACK_CBMEM); + if (!high_stack) halt(); /* TODO: Make the switch with empty stack instead. */ - memcpy(high_stack, (void *)BSP_STACK_BASE_ADDR, HIGH_ROMSTAGE_STACK_SIZE); + memcpy((void*)high_stack, (void *)BSP_STACK_BASE_ADDR, HIGH_ROMSTAGE_STACK_SIZE); /* TODO: We only switch stack on BSP. */ #ifdef __x86_64__ diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 0c34b75..9012321 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -79,6 +79,7 @@ ramstage-$(CONFIG_PRIMITIVE_MEMTEST) += primitive_memtest.c romstage-$(CONFIG_CACHE_AS_RAM) += ramtest.c romstage-$(CONFIG_GENERIC_GPIO_LIB) += gpio.c romstage-y += romstage_stack.c +ramstage-y += romstage_stack.c romstage-y += stack.c ramstage-y += rtc.c diff --git a/src/northbridge/amd/agesa/oem_s3.c b/src/northbridge/amd/agesa/oem_s3.c index 8cce0e7..8708775 100644 --- a/src/northbridge/amd/agesa/oem_s3.c +++ b/src/northbridge/amd/agesa/oem_s3.c @@ -17,6 +17,7 @@ #include <spi_flash.h> #include <string.h> #include <cbmem.h> +#include <program_loading.h> #include <cpu/amd/agesa/s3_resume.h> #include <northbridge/amd/agesa/agesawrapper.h> #include <AGESA.h> @@ -119,8 +120,7 @@ AGESA_STATUS OemS3Save(AMD_S3SAVE_PARAMS *S3SaveParams) u32 MTRRStorageSize = 0; uintptr_t pos, size; - if (HIGH_ROMSTAGE_STACK_SIZE) - cbmem_add(CBMEM_ID_ROMSTAGE_RAM_STACK, HIGH_ROMSTAGE_STACK_SIZE); + romstage_ram_stack_source(HIGH_ROMSTAGE_STACK_SIZE, ROMSTAGE_STACK_CBMEM); /* To be consumed in AmdInitResume. */ get_s3nv_data(S3DataTypeNonVolatile, &pos, &size);

1 0

Patch set updated for coreboot: AMD binaryPI: Split romstage ram stack
by Kyösti Mälkki 29 Jun '16

29 Jun '16

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15467 -gerrit commit aa1037ccf3797fac9b4ef59c1deb13cda593fe4d Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Mon Jun 27 15:25:14 2016 +0300 AMD binaryPI: Split romstage ram stack Change-Id: Ibbff1fdb1af247550815532ef12f078229f12321 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/cpu/amd/pi/heapmanager.c | 10 +++------- src/cpu/amd/pi/s3_resume.c | 9 +++++---- src/cpu/amd/pi/s3_resume.h | 8 ++++++++ 3 files changed, 16 insertions(+), 11 deletions(-) diff --git a/src/cpu/amd/pi/heapmanager.c b/src/cpu/amd/pi/heapmanager.c index c5e4202..d4a79b8 100644 --- a/src/cpu/amd/pi/heapmanager.c +++ b/src/cpu/amd/pi/heapmanager.c @@ -25,13 +25,9 @@ UINT32 GetHeapBase(AMD_CONFIG_PARAMS *StdHeader) { UINT32 heap = BIOS_HEAP_START_ADDRESS; -#if CONFIG_HAVE_ACPI_RESUME - /* Both romstage and ramstage has this S3 detect. */ - if (acpi_get_sleep_type() == 3) - heap = (UINT32) cbmem_find(CBMEM_ID_RESUME_SCRATCH) + - (CONFIG_HIGH_SCRATCH_MEMORY_SIZE - BIOS_HEAP_SIZE); - /* himem_heap_base + high_stack_size */ -#endif + if (acpi_is_wakeup_s3()) + heap = (UINT32) cbmem_find(CBMEM_ID_RESUME_SCRATCH); + return heap; } diff --git a/src/cpu/amd/pi/s3_resume.c b/src/cpu/amd/pi/s3_resume.c index 576a208..830d174 100644 --- a/src/cpu/amd/pi/s3_resume.c +++ b/src/cpu/amd/pi/s3_resume.c @@ -137,11 +137,12 @@ void restore_mtrr(void) #ifdef __PRE_RAM__ static void move_stack_high_mem(void) { - void *high_stack; + void *high_stack = cbmem_find(CBMEM_ID_ROMSTAGE_RAM_STACK); + if (high_stack == NULL) + halt(); - high_stack = cbmem_find(CBMEM_ID_RESUME_SCRATCH); - memcpy(high_stack, (void *)BSP_STACK_BASE_ADDR, - (CONFIG_HIGH_SCRATCH_MEMORY_SIZE - BIOS_HEAP_SIZE)); + /* TODO: Make the switch with empty stack instead. */ + memcpy(high_stack, (void *)BSP_STACK_BASE_ADDR, HIGH_ROMSTAGE_STACK_SIZE); #ifdef __x86_64__ __asm__ diff --git a/src/cpu/amd/pi/s3_resume.h b/src/cpu/amd/pi/s3_resume.h index f952055..3b6ecfa 100644 --- a/src/cpu/amd/pi/s3_resume.h +++ b/src/cpu/amd/pi/s3_resume.h @@ -31,4 +31,12 @@ void OemAgesaSaveMtrr (void); void spi_SaveS3info(u32 pos, u32 size, u8 *buf, u32 len); +#if 1 +/* This covers node 0 only. */ +#define HIGH_ROMSTAGE_STACK_SIZE (0x48000 - BSP_STACK_BASE_ADDR) +#else +/* This covers total of 8 nodes. */ +#define HIGH_ROMSTAGE_STACK_SIZE (0xA0000 - BSP_STACK_BASE_ADDR) +#endif + #endif

1 0

Patch set updated for coreboot: intel post-car: Separate romstage ramstack (WIP)
by Kyösti Mälkki 29 Jun '16

29 Jun '16

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15468 -gerrit commit 304e1d02411e9617b31b34ca92c8b0c9118e5952 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Mon Jun 27 13:24:11 2016 +0300 intel post-car: Separate romstage ramstack (WIP) TODO: Need to fix MTRRs before placing stack high. TODO: Check stack top reference in FSP1_0 TODO: Case LATE_CBMEM_INIT Change-Id: I221e207bcd0031048876f29100a1770a444d435b Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/cpu/intel/car/romstage.c | 20 +++++++++++++++++++- src/drivers/intel/fsp1_0/fsp_util.c | 3 ++- 2 files changed, 21 insertions(+), 2 deletions(-) diff --git a/src/cpu/intel/car/romstage.c b/src/cpu/intel/car/romstage.c index c6df446..215a6a2 100644 --- a/src/cpu/intel/car/romstage.c +++ b/src/cpu/intel/car/romstage.c @@ -1,7 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + #include <cpu/intel/romstage.h> +#include <program_loading.h> void * asmlinkage romstage_main(unsigned long bist) { mainboard_romstage_entry(bist); - return (void*)CONFIG_RAMTOP; + + if (IS_ENABLED(CONFIG_LATE_CBMEM_INIT)) + return (void*)CONFIG_RAMTOP; + + return (void*)romstage_ram_stack_top(); } diff --git a/src/drivers/intel/fsp1_0/fsp_util.c b/src/drivers/intel/fsp1_0/fsp_util.c index a3fef2d..1f12053 100644 --- a/src/drivers/intel/fsp1_0/fsp_util.c +++ b/src/drivers/intel/fsp1_0/fsp_util.c @@ -22,6 +22,7 @@ #include <lib.h> // hexdump #include <ip_checksum.h> #include <timestamp.h> +#include <program_loading.h> #ifndef __PRE_RAM__ /* Globals pointers for FSP structures */ @@ -76,7 +77,7 @@ void __attribute__ ((noreturn)) fsp_early_init (FSP_INFO_HEADER *fsp_ptr) #endif memset((void*)&FspRtBuffer, 0, sizeof(FSP_INIT_RT_BUFFER)); - FspRtBuffer.Common.StackTop = (u32 *)CONFIG_RAMTOP; + FspRtBuffer.Common.StackTop = (u32 *)romstage_ram_stack_top(); FspInitParams.NvsBufferPtr = NULL; #if IS_ENABLED(CONFIG_FSP_USES_UPD)

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coreboot-gerrit June 2016