coreboot-gerrit June 2016

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: quick_ram_check: Remove reference to RAMBASE (WIP)
by Kyösti Mälkki 29 Jun '16

29 Jun '16

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15239 -gerrit commit 10d94c6303aafcd563fc490237e7aa853d609ef6 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Fri Jun 17 23:31:42 2016 +0300 quick_ram_check: Remove reference to RAMBASE (WIP) TODO: Test at address cbmem_top() instead? TODO: lib/ramtest.c builds for arch/x86-only Change-Id: Ieb8f11690fb0e9b287d866be56010bb9adefd21d Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/lib/ramtest.c | 27 ++++++++++++++++----------- 1 file changed, 16 insertions(+), 11 deletions(-) diff --git a/src/lib/ramtest.c b/src/lib/ramtest.c index a29fa25..6d12060 100644 --- a/src/lib/ramtest.c +++ b/src/lib/ramtest.c @@ -181,32 +181,37 @@ int ram_check_noprint_nodie(unsigned long start, unsigned long stop) return failures; } -void quick_ram_check(void) +static void __quick_ram_check(uintptr_t dst) { int fail = 0; u32 backup; - backup = read_phys(CONFIG_RAMBASE); - write_phys(CONFIG_RAMBASE, 0x55555555); + backup = read_phys(dst); + write_phys(dst, 0x55555555); phys_memory_barrier(); - if (read_phys(CONFIG_RAMBASE) != 0x55555555) + if (read_phys(dst) != 0x55555555) fail=1; - write_phys(CONFIG_RAMBASE, 0xaaaaaaaa); + write_phys(dst, 0xaaaaaaaa); phys_memory_barrier(); - if (read_phys(CONFIG_RAMBASE) != 0xaaaaaaaa) + if (read_phys(dst) != 0xaaaaaaaa) fail=1; - write_phys(CONFIG_RAMBASE, 0x00000000); + write_phys(dst, 0x00000000); phys_memory_barrier(); - if (read_phys(CONFIG_RAMBASE) != 0x00000000) + if (read_phys(dst) != 0x00000000) fail=1; - write_phys(CONFIG_RAMBASE, 0xffffffff); + write_phys(dst, 0xffffffff); phys_memory_barrier(); - if (read_phys(CONFIG_RAMBASE) != 0xffffffff) + if (read_phys(dst) != 0xffffffff) fail=1; - write_phys(CONFIG_RAMBASE, backup); + write_phys(dst, backup); if (fail) { post_code(0xea); die("RAM INIT FAILURE!\n"); } phys_memory_barrier(); } + +void quick_ram_check(void) +{ + __quick_ram_check(0x100000); +}

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Patch set updated for coreboot: ACPI S3: Drop early resume backup
by Kyösti Mälkki 29 Jun '16

29 Jun '16

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15477 -gerrit commit b4dd2ccd0733d5a92965352b329b38f98f291349 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Mon Jun 27 13:09:56 2016 +0300 ACPI S3: Drop early resume backup No longer needed as low memory backup is implemented as part of the ramstage loader, after MTRRs are set to write-back cache for better performance. Change-Id: I5f5ad94bae2afef915927b9737c79431b6f75f22 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/x86/acpi_s3.c | 13 +------------ src/arch/x86/include/arch/acpi.h | 2 -- 2 files changed, 1 insertion(+), 14 deletions(-) diff --git a/src/arch/x86/acpi_s3.c b/src/arch/x86/acpi_s3.c index c744eb5..741e5cf 100644 --- a/src/arch/x86/acpi_s3.c +++ b/src/arch/x86/acpi_s3.c @@ -143,24 +143,13 @@ void backup_ramstage_section(uintptr_t base, size_t size) /* We are called from ramstage loader, do not rely on previously * loaded ramstage for location. */ - if (size) - acpi_backup_container(base, size); + acpi_backup_container(base, size); /* Back up the OS-controlled memory where ramstage will be loaded. */ memcpy((void*)backup_mem->cbmem, (void*)backup_mem->lowmem, backup_mem->size); backup_mem->valid = 1; } -/* Make backup of low-memory region, relying on the base and size - * of the ramstage that was loaded before entry to ACPI S3. - * - * DEPRECATED - */ -void acpi_prepare_for_resume(void) -{ - backup_ramstage_section(0, 0); -} - /* Let's prepare the ACPI S3 Resume area now already, so we can rely on * it being there during reboot time. If this fails, ACPI resume will * be disabled. We assume that ramstage does not change while in suspend, diff --git a/src/arch/x86/include/arch/acpi.h b/src/arch/x86/include/arch/acpi.h index f40b9df..6fecd8c 100644 --- a/src/arch/x86/include/arch/acpi.h +++ b/src/arch/x86/include/arch/acpi.h @@ -634,14 +634,12 @@ int acpi_is_wakeup(void); int acpi_is_wakeup_s3(void); int acpi_is_wakeup_s4(void); #endif -void acpi_prepare_for_resume(void); #else #define acpi_slp_type 0 static inline int acpi_is_wakeup(void) { return 0; } static inline int acpi_is_wakeup_s3(void) { return 0; } static inline int acpi_is_wakeup_s4(void) { return 0; } -static inline void acpi_prepare_for_resume(void) { } #endif static inline uintptr_t acpi_align_current(uintptr_t current)

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Patch set updated for coreboot: ACPI S3: Drop ACPI_HUGE_LOWMEM_BACKUP
by Kyösti Mälkki 29 Jun '16

29 Jun '16

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15476 -gerrit commit 3008715dfea64abb9f872abd81a4f10b6359acac Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Jun 28 07:50:48 2016 +0300 ACPI S3: Drop ACPI_HUGE_LOWMEM_BACKUP Change-Id: Ifae41b51b359010ec02269c674936a87bd15623b Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/Kconfig | 4 ---- src/arch/x86/acpi_s3.c | 5 ----- 2 files changed, 9 deletions(-) diff --git a/src/Kconfig b/src/Kconfig index b4c3cbe..7043851 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -516,10 +516,6 @@ config HAVE_ACPI_RESUME bool default n -config ACPI_HUGE_LOWMEM_BACKUP - bool - default n - config RESUME_PATH_SAME_AS_BOOT bool default y if ARCH_X86 diff --git a/src/arch/x86/acpi_s3.c b/src/arch/x86/acpi_s3.c index 741e5cf..b216bc8 100644 --- a/src/arch/x86/acpi_s3.c +++ b/src/arch/x86/acpi_s3.c @@ -95,11 +95,6 @@ void *acpi_backup_container(uintptr_t base, size_t size) struct resume_backup *backup_mem; uintptr_t top, target; - if (IS_ENABLED(CONFIG_ACPI_HUGE_LOWMEM_BACKUP)) { - base = CONFIG_RAMBASE; - size = HIGH_MEMORY_SAVE; - } - /* Align backup region to complete pages. */ top = ALIGN_UP(base + size, BACKUP_PAGE_SZ); base = ALIGN_DOWN(base, BACKUP_PAGE_SZ);

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Patch set updated for coreboot: soc/intel/apollolake: Add GPE routing code
by Shaunak Saha 29 Jun '16

29 Jun '16

Shaunak Saha (shaunak.saha(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15324 -gerrit commit 854215e75ef14fff23b5bbc4fcc885e124e1bd26 Author: Shaunak Saha <shaunak.saha(a)intel.com> Date: Tue Jun 7 02:06:28 2016 -0700 soc/intel/apollolake: Add GPE routing code This patch adds the basic framework for SCI to GPE routing code. BUG = chrome-os-partner:53438 TEST = Toogle pch_sci_l from ec console using gpioset command and see that the sci counter increases in /sys/firmware/acpi/interrupt and also 9 in /proc/interrupts. Change-Id: I3b3198276530bf6513d94e9bea02ab9751212adf Signed-off-by: Shaunak Saha <shaunak.saha(a)intel.com> --- src/soc/intel/apollolake/chip.c | 6 +- src/soc/intel/apollolake/chip.h | 6 ++ src/soc/intel/apollolake/gpio.c | 79 ++++++++++++++++++++++++ src/soc/intel/apollolake/include/soc/gpio.h | 13 ++++ src/soc/intel/apollolake/include/soc/gpio_defs.h | 21 +++++++ src/soc/intel/apollolake/include/soc/pm.h | 8 ++- 6 files changed, 130 insertions(+), 3 deletions(-) diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index af3310e..02875b0 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -33,6 +33,7 @@ #include <soc/pci_devs.h> #include <spi-generic.h> #include <soc/pm.h> +#include <soc/gpio.h> #include "chip.h" @@ -275,7 +276,6 @@ struct chip_operations soc_intel_apollolake_ops = { static void fsp_notify_dummy(void *arg) { - enum fsp_notify_phase ph = (enum fsp_notify_phase) arg; enum fsp_status ret; @@ -285,8 +285,10 @@ static void fsp_notify_dummy(void *arg) fsp_handle_reset(ret); } /* Call END_OF_FIRMWARE Notify after READY_TO_BOOT Notify */ - if (ph == READY_TO_BOOT) + if (ph == READY_TO_BOOT) { + pmc_gpe_init(); fsp_notify_dummy((void *)END_OF_FIRMWARE); + } } BOOT_STATE_INIT_ENTRY(BS_DEV_RESOURCES, BS_ON_EXIT, fsp_notify_dummy, diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h index ef82c53..4446ac5 100644 --- a/src/soc/intel/apollolake/chip.h +++ b/src/soc/intel/apollolake/chip.h @@ -18,6 +18,8 @@ #ifndef _SOC_APOLLOLAKE_CHIP_H_ #define _SOC_APOLLOLAKE_CHIP_H_ +#include <soc/gpio_defs.h> + #define CLKREQ_DISABLED 0xf /* Serial IRQ control. SERIRQ_QUIET is the default (0). */ @@ -79,6 +81,10 @@ struct soc_intel_apollolake_config { /* Integrated Sensor Hub */ uint8_t integrated_sensor_hub_enable; + + uint8_t gpe0_dw1; /* GPE0_63_32 STS/EN */ + uint8_t gpe0_dw2; /* GPE0_95_64 STS/EN */ + uint8_t gpe0_dw3; /* GPE0_127_96 STS/EN */ }; #endif /* _SOC_APOLLOLAKE_CHIP_H_ */ diff --git a/src/soc/intel/apollolake/gpio.c b/src/soc/intel/apollolake/gpio.c index d0ef648..ce32592 100644 --- a/src/soc/intel/apollolake/gpio.c +++ b/src/soc/intel/apollolake/gpio.c @@ -19,6 +19,9 @@ #include <gpio.h> #include <soc/gpio.h> #include <soc/iosf.h> +#include <soc/pm.h> +#include <soc/pci_devs.h> +#include "chip.h" /* This list must be in order, from highest pad numbers, to lowest pad numbers*/ static const struct pad_community { @@ -132,3 +135,79 @@ const char *gpio_acpi_path(gpio_t gpio_num) return NULL; } + +#if ENV_RAMSTAGE + +void pmc_gpe_init(void) +{ + uint32_t gpio_cfg = 0; + uint32_t gpio_cfg_reg; + struct soc_intel_apollolake_config *config; + + struct device *dev = NB_DEV_ROOT; + if (!dev || !dev->chip_info) { + printk(BIOS_ERR, "BUG! Could not find SOC devicetree config\n"); + return; + } + config = dev->chip_info; + + uintptr_t pmc_bar = get_pmc_mmio_bar(); + + const uint32_t gpio_cfg_mask = + (GPE0_DWX_MASK << GPE0_DW1_SHIFT) | + (GPE0_DWX_MASK << GPE0_DW2_SHIFT) | + (GPE0_DWX_MASK << GPE0_DW3_SHIFT); + + /* Route the GPIOs to the GPE0 block. Determine that all values + * are different, and if they aren't use the reset values. + * DW0 is reserved/unused */ + if (config->gpe0_dw1 == config->gpe0_dw2 || + config->gpe0_dw2 == config->gpe0_dw3) { + printk(BIOS_INFO, "PMC: Using default GPE route.\n"); + gpio_cfg = read32((void *)pmc_bar + GPIO_GPE_CFG); + } else { + gpio_cfg |= (uint32_t)config->gpe0_dw1 << GPE0_DW1_SHIFT; + gpio_cfg |= (uint32_t)config->gpe0_dw2 << GPE0_DW2_SHIFT; + gpio_cfg |= (uint32_t)config->gpe0_dw3 << GPE0_DW3_SHIFT; + } + + gpio_cfg_reg = read32((void *)pmc_bar + GPIO_GPE_CFG) & ~gpio_cfg_mask; + gpio_cfg_reg |= gpio_cfg & gpio_cfg_mask; + + write32((void *)pmc_bar + GPIO_GPE_CFG, gpio_cfg_reg); + + /* Set the routes in the GPIO communities as well. */ + gpio_route_gpe(); +} + +void gpio_route_gpe(void) +{ + int i; + uint32_t misccfg_mask; + uint32_t misccfg_value; + uint32_t misccfg_gpe0_dw0; /* ACPI GPE0[31:0] */ + uint32_t misccfg_gpe0_dw1; /* ACPI GPE0[63:32] */ + uint32_t misccfg_gpe0_dw2; /* ACPI GPE0[95:64] */ + + /* Set the group here for community specific MISCCFG register */ + misccfg_gpe0_dw0 = GPP_7; /* GPE0b */ + misccfg_gpe0_dw1 = GPP_0; /* GPE0c */ + misccfg_gpe0_dw2 = GPP_0; /* GPE0d */ + + /* Program GPIO_MISCCFG */ + misccfg_mask = (uint32_t) ~(MISCCFG_GPE0_DW2_MASK | + MISCCFG_GPE0_DW1_MASK | + MISCCFG_GPE0_DW0_MASK); + misccfg_value = (uint32_t)((misccfg_gpe0_dw2 << MISCCFG_GPE0_DW2_SHIFT) + | (misccfg_gpe0_dw1 << MISCCFG_GPE0_DW1_SHIFT) + | (misccfg_gpe0_dw0 << MISCCFG_GPE0_DW0_SHIFT)); + + for (i = 0; i < ARRAY_SIZE(gpio_communities); i++) { + const struct pad_community *comm = &gpio_communities[i]; + + iosf_write(comm->port, GPIO_MISCCFG, ((iosf_read(comm->port, + GPIO_MISCCFG) & misccfg_mask) | misccfg_value)); + } +} + +#endif diff --git a/src/soc/intel/apollolake/include/soc/gpio.h b/src/soc/intel/apollolake/include/soc/gpio.h index c9d32cc..487dd93 100644 --- a/src/soc/intel/apollolake/include/soc/gpio.h +++ b/src/soc/intel/apollolake/include/soc/gpio.h @@ -99,5 +99,18 @@ struct pad_config { void gpio_configure_pad(const struct pad_config *cfg); void gpio_configure_pads(const struct pad_config *cfg, size_t num_pads); +void pmc_gpe_init(void); + +/* + * Set the GPIO groups for the GPE blocks. The gpe0_route is interpreted + * as the packed configuration for GPE0_DW[2:0]. This basically sets the + * MISCCFG register bits: + * dw0 = gpe0_route[11:8] + * dw1 = gpe0_route[15:12] + * dw2 = gpe0_route[19:16]. + */ +void gpio_route_gpe(void); + #endif /* __ACPI__ */ + #endif /* _SOC_APOLLOLAKE_GPIO_H_ */ diff --git a/src/soc/intel/apollolake/include/soc/gpio_defs.h b/src/soc/intel/apollolake/include/soc/gpio_defs.h index 30c4bdb..d0372ea 100644 --- a/src/soc/intel/apollolake/include/soc/gpio_defs.h +++ b/src/soc/intel/apollolake/include/soc/gpio_defs.h @@ -23,6 +23,27 @@ #ifndef _SOC_APOLLOLAKE_GPIO_DEFS_H_ #define _SOC_APOLLOLAKE_GPIO_DEFS_H_ +/* + * There are 8 GPIO groups. GPP_0 -> GPP_8 (Group 3 is not present) + */ +#define GPP_0 0 /* SOUTHWEST GPIO # 0 ~ 31 belong to GROUP0 */ +#define GPP_1 1 /* SOUTHWEST GPIO # 32 ~ 42 belong to GROUP1 */ +#define GPP_2 2 /* WEST GPIO # 0 ~ 25 belong to GROUP2 */ +#define GPP_4 4 /* NORTHWEST GPIO # 0 ~ 17 belong to GROUP4 */ +#define GPP_5 5 /* NORTHWEST GPIO # 32 ~ 63 belong to GROUP5, except # 52 and 60 */ +#define GPP_6 6 /* NORTHWEST GPIO # 64 ~ 76 belong to GROUP6 */ +#define GPP_7 7 /* NORTH GPIO # 0 ~ 31 belong to GROUP7 */ +#define GPP_8 8 /* NORTH GPIO # 32 ~ 61 belong to GROUP8 */ + +#define GPIO_MISCCFG 0x10 /* Miscellaneous Configuration */ + +#define MISCCFG_GPE0_DW0_SHIFT 8 +#define MISCCFG_GPE0_DW0_MASK (0xf << MISCCFG_GPE0_DW0_SHIFT) +#define MISCCFG_GPE0_DW1_SHIFT 12 +#define MISCCFG_GPE0_DW1_MASK (0xf << MISCCFG_GPE0_DW1_SHIFT) +#define MISCCFG_GPE0_DW2_SHIFT 16 +#define MISCCFG_GPE0_DW2_MASK (0xf << MISCCFG_GPE0_DW2_SHIFT) + #define PAD_CFG0_TX_STATE (1 << 0) #define PAD_CFG0_RX_STATE (1 << 1) #define PAD_CFG0_TX_DISABLE (1 << 8) diff --git a/src/soc/intel/apollolake/include/soc/pm.h b/src/soc/intel/apollolake/include/soc/pm.h index 3da7dd0..0f1e36a 100644 --- a/src/soc/intel/apollolake/include/soc/pm.h +++ b/src/soc/intel/apollolake/include/soc/pm.h @@ -129,10 +129,16 @@ # define RPS (1 << 2) #define GEN_PMCON3 0x1028 #define ETR 0x1048 +#define GPIO_GPE_CFG 0x1050 + +#define GPE0_DWX_MASK 0xf +#define GPE0_DW1_SHIFT 4 +#define GPE0_DW2_SHIFT 8 +#define GPE0_DW3_SHIFT 12 + # define CF9_LOCK (1 << 31) # define CF9_GLB_RST (1 << 20) - /* Generic sleep state types */ #define SLEEP_STATE_S0 0 #define SLEEP_STATE_S3 3

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Patch set updated for coreboot: soc/apollolake: Expose a function to read pmc bar
by Shaunak Saha 29 Jun '16

29 Jun '16

Shaunak Saha (shaunak.saha(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15460 -gerrit commit 3f44e0ee5ebea0b6c5b4d4a13f9d295953e46639 Author: Shaunak Saha <shaunak.saha(a)intel.com> Date: Mon Jun 27 23:00:15 2016 -0700 soc/apollolake: Expose a function to read pmc bar This patch exposes a function to read pmc bar. PMC bar is read in function read_pmc_mmio_bar which is defined static in file pmutil.c. This patch exposes that functionality to call it from other files. BUG=chrome-os-partner:53438 TEST= Read the PMC bar value properly from outside pmutil file. Change-Id: I26ee13e6ab95d3a8991c7f8ea4b3856ceb015d10 Signed-off-by: Shaunak Saha <shaunak.saha(a)intel.com> --- src/soc/intel/apollolake/include/soc/pm.h | 1 + src/soc/intel/apollolake/pmutil.c | 5 +++++ 2 files changed, 6 insertions(+) diff --git a/src/soc/intel/apollolake/include/soc/pm.h b/src/soc/intel/apollolake/include/soc/pm.h index 8838d1c..3da7dd0 100644 --- a/src/soc/intel/apollolake/include/soc/pm.h +++ b/src/soc/intel/apollolake/include/soc/pm.h @@ -171,6 +171,7 @@ void disable_pm1_control(uint32_t mask); void enable_gpe(uint32_t mask); void disable_gpe(uint32_t mask); void disable_all_gpe(void); +uintptr_t get_pmc_mmio_bar(void); void global_reset_enable(bool enable); void global_reset_lock(void); diff --git a/src/soc/intel/apollolake/pmutil.c b/src/soc/intel/apollolake/pmutil.c index f8b2fdf..f25adfb 100644 --- a/src/soc/intel/apollolake/pmutil.c +++ b/src/soc/intel/apollolake/pmutil.c @@ -34,6 +34,11 @@ static uintptr_t read_pmc_mmio_bar(void) return bar & ~PCI_BASE_ADDRESS_MEM_ATTR_MASK; } +uintptr_t get_pmc_mmio_bar(void) +{ + return read_pmc_mmio_bar(); +} + static void print_num_status_bits(int num_bits, uint32_t status, const char * const bit_names[]) {

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Patch set updated for coreboot: soc/intel/apollolake: Change PCI macros to match Skylake
by Shaunak Saha 29 Jun '16

29 Jun '16

Shaunak Saha (shaunak.saha(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15483 -gerrit commit 7b6fb5aa71fa8e30140ec1f7dcf195774f707ea5 Author: Andrey Petrov <andrey.petrov(a)intel.com> Date: Tue Jun 28 12:14:33 2016 -0700 soc/intel/apollolake: Change PCI macros to match Skylake Change PCI macros in such a way they can be transparently used across romstage and ramstage. Change-Id: Idc708c1990f2fc1d941bb82efcb0a697524f2eca Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- src/soc/intel/apollolake/chip.c | 35 +++---- src/soc/intel/apollolake/include/soc/pci_devs.h | 124 ++++++++++++++---------- 2 files changed, 92 insertions(+), 67 deletions(-) diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index 821570b..af3310e 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -134,49 +134,49 @@ static void disable_dev(struct device *dev, struct FSP_S_CONFIG *silconfig) { case XDCI_DEVFN: silconfig->UsbOtg = 0; break; - case I2C0_DEVFN: + case LPSS_DEVFN_I2C0: silconfig->I2c0Enable = 0; break; - case I2C1_DEVFN: + case LPSS_DEVFN_I2C1: silconfig->I2c1Enable = 0; break; - case I2C2_DEVFN: + case LPSS_DEVFN_I2C2: silconfig->I2c2Enable = 0; break; - case I2C3_DEVFN: + case LPSS_DEVFN_I2C3: silconfig->I2c3Enable = 0; break; - case I2C4_DEVFN: + case LPSS_DEVFN_I2C4: silconfig->I2c4Enable = 0; break; - case I2C5_DEVFN: + case LPSS_DEVFN_I2C5: silconfig->I2c5Enable = 0; break; - case I2C6_DEVFN: + case LPSS_DEVFN_I2C6: silconfig->I2c6Enable = 0; break; - case I2C7_DEVFN: + case LPSS_DEVFN_I2C7: silconfig->I2c7Enable = 0; break; - case UART0_DEVFN: + case LPSS_DEVFN_UART0: silconfig->Hsuart0Enable = 0; break; - case UART1_DEVFN: + case LPSS_DEVFN_UART1: silconfig->Hsuart1Enable = 0; break; - case UART2_DEVFN: + case LPSS_DEVFN_UART2: silconfig->Hsuart2Enable = 0; break; - case UART3_DEVFN: + case LPSS_DEVFN_UART3: silconfig->Hsuart3Enable = 0; break; - case SPI0_DEVFN: + case LPSS_DEVFN_SPI0: silconfig->Spi0Enable = 0; break; - case SPI1_DEVFN: + case LPSS_DEVFN_SPI1: silconfig->Spi1Enable = 0; break; - case SPI2_DEVFN: + case LPSS_DEVFN_SPI2: silconfig->Spi2Enable = 0; break; case SDCARD_DEVFN: @@ -201,7 +201,7 @@ static void disable_dev(struct device *dev, struct FSP_S_CONFIG *silconfig) { static void parse_devicetree(struct FSP_S_CONFIG *silconfig) { - struct device *dev = dev_find_slot(0, NB_DEVFN); + struct device *dev = NB_DEV_ROOT; if (!dev) { printk(BIOS_ERR, "Could not find root device\n"); @@ -222,7 +222,8 @@ void platform_fsp_silicon_init_params_cb(struct FSPS_UPD *silupd) /* Load VBT before devicetree-specific config. */ silconfig->GraphicsConfigPtr = (uintptr_t)vbt; - struct device *dev = dev_find_slot(NB_BUS, NB_DEVFN); + struct device *dev = NB_DEV_ROOT; + if (!dev || !dev->chip_info) { printk(BIOS_ERR, "BUG! Could not find SOC devicetree config\n"); return; diff --git a/src/soc/intel/apollolake/include/soc/pci_devs.h b/src/soc/intel/apollolake/include/soc/pci_devs.h index fc046d1..88a7a07 100644 --- a/src/soc/intel/apollolake/include/soc/pci_devs.h +++ b/src/soc/intel/apollolake/include/soc/pci_devs.h @@ -17,63 +17,87 @@ #include <rules.h> -#define _LPSS_PCI_DEVFN(slot, func) PCI_DEVFN(LPSS_DEV_SLOT_##slot, func) +#define _LPSS_PCI_DEVFN(slot, func) PCI_DEVFN(LPSS_DEV_SLOT_##slot, func) +#define _PCI_DEVFN(slot, func) PCI_DEVFN(slot, func) #if !defined(__SIMPLE_DEVICE__) #include <device/device.h> #include <device/pci_def.h> -#define _LPSS_PCI_DEV(slot, func) dev_find_slot(0, _LPSS_PCI_DEVFN(slot, func)) +#define _LPSS_PCI_DEV(slot, func) dev_find_slot(0, _LPSS_PCI_DEVFN(slot, func)) +#define _PCI_DEV(slot, func) dev_find_slot(0, PCI_DEVFN(slot, func)) #else #include <arch/io.h> -#define _LPSS_PCI_DEV(slot, func) PCI_DEV(0, LPSS_DEV_SLOT_##slot, func) +#define _LPSS_PCI_DEV(slot, func) PCI_DEV(0, LPSS_DEV_SLOT_##slot, func) +#define _PCI_DEV(slot, func) PCI_DEV(0, slot, func) #endif +#define NB_DEVFN _PCI_DEVFN(0, 0) +#define NB_DEV_ROOT _PCI_DEV(0x0, 0) + +#define P2SB_DEV _PCI_DEV(0xd, 0) +#define PMC_DEV _PCI_DEV(0xd, 1) +#define SPI_DEV _PCI_DEV(0xd, 2) + +#define ISH_DEV _PCI_DEV(0x11, 0) +#define ISH_DEVFN _PCI_DEVFN(0x11, 0) + +#define SATA_DEV _PCI_DEV(0x12, 0) +#define SATA_DEVFN _PCI_DEVFN(0x12, 0) + +#define PCIEA0_DEVFN _PCI_DEVFN(0x13, 0) +#define PCIEA1_DEVFN _PCI_DEVFN(0x13, 1) +#define PCIEA2_DEVFN _PCI_DEVFN(0x13, 2) +#define PCIEA3_DEVFN _PCI_DEVFN(0x13, 3) +#define PCIEB0_DEVFN _PCI_DEVFN(0x14, 0) +#define PCIEB1_DEVFN _PCI_DEVFN(0x14, 1) + +#define XHCI_DEV _PCI_DEV(0x15, 0) +#define XHCI_DEVFN _PCI_DEVFN(0x15, 0) + +#define XDCI_DEV _PCI_DEV(0x15, 1) +#define XDCI_DEVFN _PCI_DEVFN(0x15, 1) + +/* LPSS I2C, 2 devices cover 8 controllers */ +#define LPSS_DEV_SLOT_I2C_D0 0x16 +#define LPSS_DEVFN_I2C0 _LPSS_PCI_DEVFN(I2C_D0, 0) +#define LPSS_DEVFN_I2C1 _LPSS_PCI_DEVFN(I2C_D0, 1) +#define LPSS_DEVFN_I2C2 _LPSS_PCI_DEVFN(I2C_D0, 2) +#define LPSS_DEVFN_I2C3 _LPSS_PCI_DEVFN(I2C_D0, 3) +#define LPSS_DEV_SLOT_I2C_D1 0x17 +#define LPSS_DEVFN_I2C4 _LPSS_PCI_DEVFN(I2C_D1, 0) +#define LPSS_DEVFN_I2C5 _LPSS_PCI_DEVFN(I2C_D1, 1) +#define LPSS_DEVFN_I2C6 _LPSS_PCI_DEVFN(I2C_D1, 2) +#define LPSS_DEVFN_I2C7 _LPSS_PCI_DEVFN(I2C_D1, 3) + /* LPSS UART */ -#define LPSS_DEV_SLOT_UART 0x18 -#define LPSS_DEVFN_UART0 _LPSS_PCI_DEVFN(UART, 0) -#define LPSS_DEVFN_UART1 _LPSS_PCI_DEVFN(UART, 1) -#define LPSS_DEVFN_UART2 _LPSS_PCI_DEVFN(UART, 2) -#define LPSS_DEVFN_UART3 _LPSS_PCI_DEVFN(UART, 3) -#define LPSS_DEV_UART0 _LPSS_PCI_DEV(UART, 0) -#define LPSS_DEV_UART1 _LPSS_PCI_DEV(UART, 1) -#define LPSS_DEV_UART2 _LPSS_PCI_DEV(UART, 2) -#define LPSS_DEV_UART3 _LPSS_PCI_DEV(UART, 3) - -#define NB_BUS 0 -#define NB_DEVFN PCI_DEVFN(0, 0) -#define NB_DEV_ROOT PCI_DEV(NB_BUS, 0x0, 0) -#define P2SB_DEV PCI_DEV(0, 0xd, 0) -#define PMC_DEV PCI_DEV(0, 0xd, 1) -#define SPI_DEV PCI_DEV(0, 0xd, 2) -#define LPC_DEV PCI_DEV(0, 0x1f, 0) - -#define ISH_DEVFN PCI_DEVFN(0x11, 0) -#define SATA_DEVFN PCI_DEVFN(0x12, 0) -#define PCIEA0_DEVFN PCI_DEVFN(0x13, 0) -#define PCIEA1_DEVFN PCI_DEVFN(0x13, 1) -#define PCIEA2_DEVFN PCI_DEVFN(0x13, 2) -#define PCIEA3_DEVFN PCI_DEVFN(0x13, 3) -#define PCIEB0_DEVFN PCI_DEVFN(0x14, 0) -#define PCIEB1_DEVFN PCI_DEVFN(0x14, 1) -#define XHCI_DEVFN PCI_DEVFN(0x15, 0) -#define XDCI_DEVFN PCI_DEVFN(0x15, 1) -#define I2C0_DEVFN PCI_DEVFN(0x16, 0) -#define I2C1_DEVFN PCI_DEVFN(0x16, 1) -#define I2C2_DEVFN PCI_DEVFN(0x16, 2) -#define I2C3_DEVFN PCI_DEVFN(0x16, 3) -#define I2C4_DEVFN PCI_DEVFN(0x17, 0) -#define I2C5_DEVFN PCI_DEVFN(0x17, 1) -#define I2C6_DEVFN PCI_DEVFN(0x17, 2) -#define I2C7_DEVFN PCI_DEVFN(0x17, 3) -#define UART0_DEVFN PCI_DEVFN(0x18, 0) -#define UART1_DEVFN PCI_DEVFN(0x18, 1) -#define UART2_DEVFN PCI_DEVFN(0x18, 2) -#define UART3_DEVFN PCI_DEVFN(0x18, 3) -#define SPI0_DEVFN PCI_DEVFN(0x19, 0) -#define SPI1_DEVFN PCI_DEVFN(0x19, 1) -#define SPI2_DEVFN PCI_DEVFN(0x19, 2) -#define SDCARD_DEVFN PCI_DEVFN(0x1b, 0) -#define EMMC_DEVFN PCI_DEVFN(0x1c, 0) -#define SDIO_DEVFN PCI_DEVFN(0x1e, 0) -#define SMBUS_DEVFN PCI_DEVFN(0x1f, 1) +#define LPSS_DEV_SLOT_UART 0x18 +#define LPSS_DEVFN_UART0 _LPSS_PCI_DEVFN(UART, 0) +#define LPSS_DEVFN_UART1 _LPSS_PCI_DEVFN(UART, 1) +#define LPSS_DEVFN_UART2 _LPSS_PCI_DEVFN(UART, 2) +#define LPSS_DEVFN_UART3 _LPSS_PCI_DEVFN(UART, 3) +#define LPSS_DEV_UART0 _LPSS_PCI_DEV(UART, 0) +#define LPSS_DEV_UART1 _LPSS_PCI_DEV(UART, 1) +#define LPSS_DEV_UART2 _LPSS_PCI_DEV(UART, 2) +#define LPSS_DEV_UART3 _LPSS_PCI_DEV(UART, 3) + +/* LPSS SPI */ +#define LPSS_DEV_SLOT_SPI 0x19 +#define LPSS_DEVFN_SPI0 _LPSS_PCI_DEVFN(SPI, 0) +#define LPSS_DEVFN_SPI1 _LPSS_PCI_DEVFN(SPI, 1) +#define LPSS_DEVFN_SPI2 _LPSS_PCI_DEVFN(SPI, 2) + +#define SDCARD_DEV _PCI_DEV(0x1b, 0) +#define SDCARD_DEVFN _PCI_DEVFN(0x1b, 0) + +#define EMMC_DEV _PCI_DEV(0x1c, 0) +#define EMMC_DEVFN _PCI_DEVFN(0x1c, 0) + +#define SDIO_DEV _PCI_DEV(0x1e, 0) +#define SDIO_DEVFN _PCI_DEVFN(0x1e, 0) + +#define LPC_DEV _PCI_DEV(0x1f, 0) +#define LPC_DEVFN _PCI_DEVFN(0x1f, 0) + +#define SMBUS_DEV _PCI_DEV(0x1f, 1) +#define SMBUS_DEVFN _PCI_DEVFN(0x1f, 1) #endif

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Patch set updated for coreboot: soc/intel/apollolake: Add GPE routing code
by Shaunak Saha 29 Jun '16

29 Jun '16

Shaunak Saha (shaunak.saha(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15324 -gerrit commit cf06f623045f85cd59e17b20037833d19692f318 Author: Shaunak Saha <shaunak.saha(a)intel.com> Date: Tue Jun 7 02:06:28 2016 -0700 soc/intel/apollolake: Add GPE routing code This patch adds the basic framework for SCI to GPE routing code. BUG = chrome-os-partner:53438 TEST = Toogle pch_sci_l from ec console using gpioset command and see that the sci counter increases in /sys/firmware/acpi/interrupt and also 9 in /proc/interrupts. Change-Id: I3b3198276530bf6513d94e9bea02ab9751212adf Signed-off-by: Shaunak Saha <shaunak.saha(a)intel.com> --- src/soc/intel/apollolake/chip.c | 6 +- src/soc/intel/apollolake/chip.h | 7 + src/soc/intel/apollolake/gpio.c | 85 ++++++++ src/soc/intel/apollolake/include/soc/gpio.h | 14 ++ src/soc/intel/apollolake/include/soc/gpio_defs.h | 236 +++++++++++++++++++++++ src/soc/intel/apollolake/include/soc/pm.h | 9 +- 6 files changed, 354 insertions(+), 3 deletions(-) diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index af3310e..eb0333c 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -33,6 +33,7 @@ #include <soc/pci_devs.h> #include <spi-generic.h> #include <soc/pm.h> +#include <soc/gpio.h> #include "chip.h" @@ -275,7 +276,6 @@ struct chip_operations soc_intel_apollolake_ops = { static void fsp_notify_dummy(void *arg) { - enum fsp_notify_phase ph = (enum fsp_notify_phase) arg; enum fsp_status ret; @@ -285,8 +285,10 @@ static void fsp_notify_dummy(void *arg) fsp_handle_reset(ret); } /* Call END_OF_FIRMWARE Notify after READY_TO_BOOT Notify */ - if (ph == READY_TO_BOOT) + if (ph == READY_TO_BOOT){ + pmc_gpe_init(); fsp_notify_dummy((void *)END_OF_FIRMWARE); + } } BOOT_STATE_INIT_ENTRY(BS_DEV_RESOURCES, BS_ON_EXIT, fsp_notify_dummy, diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h index ef82c53..7599d4e 100644 --- a/src/soc/intel/apollolake/chip.h +++ b/src/soc/intel/apollolake/chip.h @@ -18,6 +18,8 @@ #ifndef _SOC_APOLLOLAKE_CHIP_H_ #define _SOC_APOLLOLAKE_CHIP_H_ +#include <soc/gpio_defs.h> + #define CLKREQ_DISABLED 0xf /* Serial IRQ control. SERIRQ_QUIET is the default (0). */ @@ -79,6 +81,11 @@ struct soc_intel_apollolake_config { /* Integrated Sensor Hub */ uint8_t integrated_sensor_hub_enable; + + uint8_t gpe0_dw0; /* GPE0_31_0 STS/EN */ + uint8_t gpe0_dw1; /* GPE0_63_32 STS/EN */ + uint8_t gpe0_dw2; /* GPE0_95_64 STS/EN */ + uint8_t gpe0_dw3; /* GPE0_127_96 STS/EN */ }; #endif /* _SOC_APOLLOLAKE_CHIP_H_ */ diff --git a/src/soc/intel/apollolake/gpio.c b/src/soc/intel/apollolake/gpio.c index d0ef648..0571e51 100644 --- a/src/soc/intel/apollolake/gpio.c +++ b/src/soc/intel/apollolake/gpio.c @@ -19,6 +19,14 @@ #include <gpio.h> #include <soc/gpio.h> #include <soc/iosf.h> +#include <soc/pm.h> +#include <soc/iomap.h> +#include <device/device.h> +#include <device/pci_def.h> +#include <soc/pci_devs.h> +#include <device/pci.h> +#include "chip.h" + /* This list must be in order, from highest pad numbers, to lowest pad numbers*/ static const struct pad_community { @@ -132,3 +140,80 @@ const char *gpio_acpi_path(gpio_t gpio_num) return NULL; } + +#if ENV_RAMSTAGE + +void pmc_gpe_init(void) +{ + uint32_t gpio_cfg = 0; + uint32_t gpio_cfg_reg; + struct soc_intel_apollolake_config *config; + + struct device *dev = dev_find_slot(NB_BUS, NB_DEVFN); + if (!dev || !dev->chip_info) { + printk(BIOS_ERR, "BUG! Could not find SOC devicetree config\n"); + return; + } + config = dev->chip_info; + + uintptr_t pmc_bar = get_pmc_mmio_bar(); + + const uint32_t gpio_cfg_mask = + (GPE0_DWX_MASK << GPE0_DW0_SHIFT) | + (GPE0_DWX_MASK << GPE0_DW1_SHIFT) | + (GPE0_DWX_MASK << GPE0_DW2_SHIFT) | + (GPE0_DWX_MASK << GPE0_DW3_SHIFT); + + /* Route the GPIOs to the GPE0 block. Determine that all values + * are different, and if they aren't use the reset values. + * DW0 is reserved/unused */ + if (config->gpe0_dw1 == config->gpe0_dw2 || + config->gpe0_dw2 == config->gpe0_dw3) { + printk(BIOS_INFO, "PMC: Using default GPE route.\n"); + gpio_cfg = read32((void *)pmc_bar + GPIO_GPE_CFG); + } else { + gpio_cfg |= (uint32_t)config->gpe0_dw1 << GPE0_DW1_SHIFT; + gpio_cfg |= (uint32_t)config->gpe0_dw2 << GPE0_DW2_SHIFT; + gpio_cfg |= (uint32_t)config->gpe0_dw3 << GPE0_DW3_SHIFT; + } + + gpio_cfg_reg = read32((void *)pmc_bar + GPIO_GPE_CFG) & ~gpio_cfg_mask; + gpio_cfg_reg |= gpio_cfg & gpio_cfg_mask; + + write32((void *)pmc_bar + GPIO_GPE_CFG, gpio_cfg_reg); + + /* Set the routes in the GPIO communities as well. */ + gpio_route_gpe(); +} + +void gpio_route_gpe(void) +{ + int i; + uint32_t misccfg_mask; + uint32_t misccfg_value; + uint32_t gpe0_dw0; + uint32_t gpe0_dw1; + uint32_t gpe0_dw2; + + /* Set the group here for community specific MISCCFG register */ + gpe0_dw0 = GPP_7; /* GPE0b */ + gpe0_dw1 = GPP_0; /* GPE0c */ + gpe0_dw2 = GPP_0; /* GPE0d */ + + /*Program GPIO_MISCCFG */ + misccfg_mask = (uint32_t) ~(MISCCFG_GPE0_DW2_MASK | + MISCCFG_GPE0_DW1_MASK | + MISCCFG_GPE0_DW0_MASK); + misccfg_value = (uint32_t)((gpe0_dw2 << MISCCFG_GPE0_DW2_SHIFT) | + (gpe0_dw1 << MISCCFG_GPE0_DW1_SHIFT) | + (gpe0_dw0 << MISCCFG_GPE0_DW0_SHIFT)); + + for (i = 0; i < ARRAY_SIZE(gpio_communities); i++) { + const struct pad_community *comm = &gpio_communities[i]; + + iosf_write( comm->port,GPIO_MISCCFG,((iosf_read( comm->port, + GPIO_MISCCFG)& misccfg_mask) | misccfg_value)); + } +} + +#endif diff --git a/src/soc/intel/apollolake/include/soc/gpio.h b/src/soc/intel/apollolake/include/soc/gpio.h index c9d32cc..9bed198 100644 --- a/src/soc/intel/apollolake/include/soc/gpio.h +++ b/src/soc/intel/apollolake/include/soc/gpio.h @@ -22,6 +22,7 @@ /* __ACPI__ guard is needed to ignore below code in ACPI/ASL compilation */ #ifndef __ACPI__ #include <types.h> +#include <soc/gpio_defs.h> typedef uint32_t gpio_t; @@ -99,5 +100,18 @@ struct pad_config { void gpio_configure_pad(const struct pad_config *cfg); void gpio_configure_pads(const struct pad_config *cfg, size_t num_pads); +void pmc_gpe_init(void); + +/* + * Set the GPIO groups for the GPE blocks. The gpe0_route is interpreted + * as the packed configuration for GPE0_DW[2:0]. This basically sets the + * MISCCFG register bits: + * dw0 = gpe0_route[11:8] + * dw1 = gpe0_route[15:12] + * dw2 = gpe0_route[19:16]. + */ +void gpio_route_gpe(void); + #endif /* __ACPI__ */ + #endif /* _SOC_APOLLOLAKE_GPIO_H_ */ diff --git a/src/soc/intel/apollolake/include/soc/gpio_defs.h b/src/soc/intel/apollolake/include/soc/gpio_defs.h index 30c4bdb..d96ffba 100644 --- a/src/soc/intel/apollolake/include/soc/gpio_defs.h +++ b/src/soc/intel/apollolake/include/soc/gpio_defs.h @@ -23,6 +23,242 @@ #ifndef _SOC_APOLLOLAKE_GPIO_DEFS_H_ #define _SOC_APOLLOLAKE_GPIO_DEFS_H_ +/* + * There are 8 GPIO groups. GPP_0 -> GPP_8 (Group 3 is not present) + */ +#define GPP_0 0 /* SOUTHWEST GPIO # 0 ~ 31 belong to GROUP0 */ +#define GPP_1 1 /* SOUTHWEST GPIO # 32 ~ 42 belong to GROUP1 */ +#define GPP_2 2 /* WEST GPIO # 0 ~ 25 belong to GROUP2 */ +#define GPP_4 4 /* NORTHWEST GPIO # 0 ~ 17 belong to GROUP4 */ +#define GPP_5 5 /* NORTHWEST GPIO # 32 ~ 63 belong to GROUP5, except # 52 and 60 */ +#define GPP_6 6 /* NORTHWEST GPIO # 64 ~ 76 belong to GROUP6 */ +#define GPP_7 7 /* NORTH GPIO # 0 ~ 31 belong to GROUP7 */ +#define GPP_8 8 /* NORTH GPIO # 32 ~ 61 belong to GROUP8 */ + +/* + * GPIOs are ordered monotonically increasing to match ACPI/OS driver. + */ + +/* SOUTHWEST */ +/* Group 0 */ +#define GPP_0_0 0 +#define GPP_0_1 1 +#define GPP_0_2 2 +#define GPP_0_3 3 +#define GPP_0_4 4 +#define GPP_0_5 5 +#define GPP_0_6 6 +#define GPP_0_7 7 +#define GPP_0_8 8 +#define GPP_0_9 9 +#define GPP_0_10 10 +#define GPP_0_11 11 +#define GPP_0_12 12 +#define GPP_0_13 13 +#define GPP_0_14 14 +#define GPP_0_15 15 +#define GPP_0_16 16 +#define GPP_0_17 17 +#define GPP_0_18 18 +#define GPP_0_19 19 +#define GPP_0_20 20 +#define GPP_0_21 21 +#define GPP_0_22 22 +#define GPP_0_23 23 +#define GPP_0_24 24 +#define GPP_0_25 25 +#define GPP_0_26 26 +#define GPP_0_27 27 +#define GPP_0_28 28 +#define GPP_0_29 29 +#define GPP_0_30 30 +#define GPP_0_31 31 + +/* Group 1 */ +#define GPP_1_0 32 +#define GPP_1_1 33 +#define GPP_1_2 34 +#define GPP_1_3 35 +#define GPP_1_4 36 +#define GPP_1_5 37 +#define GPP_1_6 38 +#define GPP_1_7 39 +#define GPP_1_8 40 +#define GPP_1_9 41 +#define GPP_1_10 42 + +/* WEST */ +/* Group 2 */ +#define GPP_2_0 0 +#define GPP_2_1 1 +#define GPP_2_2 2 +#define GPP_2_3 3 +#define GPP_2_4 4 +#define GPP_2_5 5 +#define GPP_2_6 6 +#define GPP_2_7 7 +#define GPP_2_8 8 +#define GPP_2_9 9 +#define GPP_2_10 10 +#define GPP_2_11 11 +#define GPP_2_12 12 +#define GPP_2_13 13 +#define GPP_2_14 14 +#define GPP_2_15 15 +#define GPP_2_16 16 +#define GPP_2_17 17 +#define GPP_2_18 18 +#define GPP_2_19 19 +#define GPP_2_20 20 +#define GPP_2_21 21 +#define GPP_2_22 22 +#define GPP_2_23 23 +#define GPP_2_24 24 +#define GPP_2_25 25 + +/* NORTHWEST */ +/* Group 4 */ +#define GPP_4_0 0 +#define GPP_4_1 1 +#define GPP_4_2 2 +#define GPP_4_3 3 +#define GPP_4_4 4 +#define GPP_4_5 5 +#define GPP_4_6 6 +#define GPP_4_7 7 +#define GPP_4_8 8 +#define GPP_4_9 9 +#define GPP_4_10 10 +#define GPP_4_11 11 +#define GPP_4_12 12 +#define GPP_4_13 13 +#define GPP_4_14 14 +#define GPP_4_15 15 +#define GPP_4_16 16 +#define GPP_4_17 17 + +/* Group 5 */ +#define GPP_5_0 33 +#define GPP_5_1 34 +#define GPP_5_2 35 +#define GPP_5_3 36 +#define GPP_5_4 37 +#define GPP_5_5 38 +#define GPP_5_6 39 +#define GPP_5_7 40 +#define GPP_5_8 41 +#define GPP_5_9 42 +#define GPP_5_10 43 +#define GPP_5_11 44 +#define GPP_5_12 45 +#define GPP_5_13 46 +#define GPP_5_14 47 +#define GPP_5_15 48 +#define GPP_5_16 49 +#define GPP_5_17 50 +#define GPP_5_18 51 +#define GPP_5_19 53 +#define GPP_5_20 54 +#define GPP_5_21 55 +#define GPP_5_22 56 +#define GPP_5_23 57 +#define GPP_5_24 58 +#define GPP_5_25 59 +#define GPP_5_26 61 +#define GPP_5_27 62 +#define GPP_5_28 63 + +/* Group 6 */ +#define GPP_6_0 64 +#define GPP_6_1 65 +#define GPP_6_2 66 +#define GPP_6_3 67 +#define GPP_6_4 68 +#define GPP_6_5 69 +#define GPP_6_6 70 +#define GPP_6_7 71 +#define GPP_6_8 72 +#define GPP_6_9 73 +#define GPP_6_10 74 +#define GPP_6_11 75 +#define GPP_6_12 76 + +/* NORTH */ +/* Group 7 */ +#define GPP_7_0 0 +#define GPP_7_1 1 +#define GPP_7_2 2 +#define GPP_7_3 3 +#define GPP_7_4 4 +#define GPP_7_5 5 +#define GPP_7_6 6 +#define GPP_7_7 7 +#define GPP_7_8 8 +#define GPP_7_9 9 +#define GPP_7_10 10 +#define GPP_7_11 11 +#define GPP_7_12 12 +#define GPP_7_13 13 +#define GPP_7_14 14 +#define GPP_7_15 15 +#define GPP_7_16 16 +#define GPP_7_17 17 +#define GPP_7_18 18 +#define GPP_7_19 19 +#define GPP_7_20 20 +#define GPP_7_21 21 +#define GPP_7_22 22 +#define GPP_7_23 23 +#define GPP_7_24 24 +#define GPP_7_25 25 +#define GPP_7_26 26 +#define GPP_7_27 27 +#define GPP_7_28 28 +#define GPP_7_29 29 +#define GPP_7_30 30 +#define GPP_7_31 31 + +/* Group 8 */ +#define GPP_8_0 32 +#define GPP_8_1 33 +#define GPP_8_2 34 +#define GPP_8_3 35 +#define GPP_8_4 36 +#define GPP_8_5 37 +#define GPP_8_6 38 +#define GPP_8_7 39 +#define GPP_8_8 40 +#define GPP_8_9 41 +#define GPP_8_10 42 +#define GPP_8_11 43 +#define GPP_8_12 44 +#define GPP_8_13 45 +#define GPP_8_14 46 +#define GPP_8_15 47 +#define GPP_8_16 48 +#define GPP_8_17 49 +#define GPP_8_18 50 +#define GPP_8_19 51 +#define GPP_8_20 52 +#define GPP_8_21 53 +#define GPP_8_22 54 +#define GPP_8_23 55 +#define GPP_8_24 56 +#define GPP_8_25 57 +#define GPP_8_26 58 +#define GPP_8_27 59 +#define GPP_8_28 60 +#define GPP_8_29 61 + +#define GPIO_MISCCFG 0x10 ///< Miscellaneous Configuration + +#define MISCCFG_GPE0_DW0_SHIFT 8 +#define MISCCFG_GPE0_DW0_MASK (0xf << MISCCFG_GPE0_DW1_SHIFT) +#define MISCCFG_GPE0_DW1_SHIFT 12 +#define MISCCFG_GPE0_DW1_MASK (0xf << MISCCFG_GPE0_DW1_SHIFT) +#define MISCCFG_GPE0_DW2_SHIFT 16 +#define MISCCFG_GPE0_DW2_MASK (0xf << MISCCFG_GPE0_DW1_SHIFT) + #define PAD_CFG0_TX_STATE (1 << 0) #define PAD_CFG0_RX_STATE (1 << 1) #define PAD_CFG0_TX_DISABLE (1 << 8) diff --git a/src/soc/intel/apollolake/include/soc/pm.h b/src/soc/intel/apollolake/include/soc/pm.h index 3da7dd0..a3ed3b1 100644 --- a/src/soc/intel/apollolake/include/soc/pm.h +++ b/src/soc/intel/apollolake/include/soc/pm.h @@ -128,11 +128,18 @@ #define GEN_PMCON2 0x1024 # define RPS (1 << 2) #define GEN_PMCON3 0x1028 +#define GPIO_GPE_CFG 0x1050 + +#define GPE0_DWX_MASK 0xf +#define GPE0_DW0_SHIFT 0 +#define GPE0_DW1_SHIFT 4 +#define GPE0_DW2_SHIFT 8 +#define GPE0_DW3_SHIFT 12 + #define ETR 0x1048 # define CF9_LOCK (1 << 31) # define CF9_GLB_RST (1 << 20) - /* Generic sleep state types */ #define SLEEP_STATE_S0 0 #define SLEEP_STATE_S3 3

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Patch set updated for coreboot: gigbyte/ga-g41m-es2l: add cmos.layout and cmos.default
by Arthur Heymans 29 Jun '16

29 Jun '16

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15493 -gerrit commit fd61402f018c4572ced31efd6e52093fdcd46a77 Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Sat Jun 18 23:26:46 2016 +0200 gigbyte/ga-g41m-es2l: add cmos.layout and cmos.default This adds a cmos.layout and a cmos.default to ga-g41m-es2l. This allows to set things like baud_rate, debug_level, etc. from cmos. Change-Id: I25df7a1f3a0ce486b96cfe05bda628f604b0baec Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/mainboard/gigabyte/ga-g41m-es2l/Kconfig | 2 + src/mainboard/gigabyte/ga-g41m-es2l/cmos.default | 5 + src/mainboard/gigabyte/ga-g41m-es2l/cmos.layout | 119 +++++++++++++++++++++++ 3 files changed, 126 insertions(+) diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/Kconfig b/src/mainboard/gigabyte/ga-g41m-es2l/Kconfig index 7dec921..6452f4d 100644 --- a/src/mainboard/gigabyte/ga-g41m-es2l/Kconfig +++ b/src/mainboard/gigabyte/ga-g41m-es2l/Kconfig @@ -30,6 +30,8 @@ config BOARD_SPECIFIC_OPTIONS select PCIEXP_CLK_PM select PCIEXP_L1_SUB_STATE select REALTEK_8168_RESET + select HAVE_OPTION_TABLE + select HAVE_CMOS_DEFAULT config MMCONF_BASE_ADDRESS hex diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/cmos.default b/src/mainboard/gigabyte/ga-g41m-es2l/cmos.default new file mode 100644 index 0000000..c20ba94 --- /dev/null +++ b/src/mainboard/gigabyte/ga-g41m-es2l/cmos.default @@ -0,0 +1,5 @@ +boot_option=Fallback +baud_rate=115200 +debug_level=Spew +power_on_after_fail=Enable +nmi=Enable \ No newline at end of file diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/cmos.layout b/src/mainboard/gigabyte/ga-g41m-es2l/cmos.layout new file mode 100644 index 0000000..f92de11 --- /dev/null +++ b/src/mainboard/gigabyte/ga-g41m-es2l/cmos.layout @@ -0,0 +1,119 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2008 coresystems GmbH +## Copyright (C) 2014 Vladimir Serbinenko +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +# ----------------------------------------------------------------- +entries + +# ----------------------------------------------------------------- +# Status Register A +# ----------------------------------------------------------------- +# Status Register B +# ----------------------------------------------------------------- +# Status Register C +#96 4 r 0 status_c_rsvd +#100 1 r 0 uf_flag +#101 1 r 0 af_flag +#102 1 r 0 pf_flag +#103 1 r 0 irqf_flag +# ----------------------------------------------------------------- +# Status Register D +#104 7 r 0 status_d_rsvd +#111 1 r 0 valid_cmos_ram +# ----------------------------------------------------------------- +# Diagnostic Status Register +#112 8 r 0 diag_rsvd1 + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory +#120 264 r 0 unused + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +388 4 r 0 reboot_bits +#390 2 r 0 unused? + +# ----------------------------------------------------------------- +# coreboot config options: console +392 3 e 5 baud_rate +395 4 e 6 debug_level +#399 1 r 0 unused + +# coreboot config options: southbridge +408 1 e 1 nmi +409 2 e 7 power_on_after_fail + +# coreboot config options: cpu +#424 1 e 2 hyper_threading +#425 7 r 0 unused + +# coreboot config options: northbridge +432 4 e 11 gfx_uma_size +#435 549 r 0 unused + + +# coreboot config options: check sums +984 16 h 0 check_sum + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 1 Emergency +6 2 Alert +6 3 Critical +6 4 Error +6 5 Warning +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Disable +7 1 Enable +7 2 Keep +11 0 1M +11 1 4M +11 2 8M +11 3 16M +11 4 32M +11 5 48M +11 6 64M +11 7 128M +11 8 256M +11 9 96M +11 10 160M +11 11 224M +11 12 352M + +# ----------------------------------------------------------------- +checksums + +checksum 392 983 984

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Patch set updated for coreboot: AMD k8 fam10: Delay ACPI S3 backup until ramstage loader
by Kyösti Mälkki 29 Jun '16

29 Jun '16

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15475 -gerrit commit 5d95f3e8d49e2e2c820f7e60c8a7e51253adb137 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Mon Jun 27 12:14:57 2016 +0300 AMD k8 fam10: Delay ACPI S3 backup until ramstage loader Change-Id: I6d5d3e1ccd2dab727c9eba6c6175d47955719b54 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/cpu/amd/car/post_cache_as_ram.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/src/cpu/amd/car/post_cache_as_ram.c b/src/cpu/amd/car/post_cache_as_ram.c index 24182cb..bfdb451 100644 --- a/src/cpu/amd/car/post_cache_as_ram.c +++ b/src/cpu/amd/car/post_cache_as_ram.c @@ -133,9 +133,6 @@ void cache_as_ram_new_stack (void) set_var_mtrr(0, 0x00000000, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK); enable_cache(); - if (acpi_is_wakeup_s3()) - acpi_prepare_for_resume(); - #if IS_ENABLED(CONFIG_HAVE_ROMSTAGE_CONSOLE_SPINLOCK) initialize_romstage_console_lock(); #endif

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Patch set updated for coreboot: Obsoletes RAMBASE and RAMTOP
by Kyösti Mälkki 29 Jun '16

29 Jun '16

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15250 -gerrit commit 92def44888303dad301bf97d81a7977f3eb73199 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sat Jun 18 07:39:31 2016 +0300 Obsoletes RAMBASE and RAMTOP There is no fixed region of RAMBASE..RAMTOP where ramstage gets loaded. Change-Id: Ie90611274fb011759661d5c46c8e35e5cca6533c Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/Kconfig | 2 +- src/arch/x86/Kconfig | 4 ---- src/arch/x86/include/arch/memlayout.h | 4 ---- src/arch/x86/memlayout.ld | 2 +- src/northbridge/amd/agesa/Kconfig | 4 ---- src/northbridge/amd/pi/Kconfig | 4 ---- 6 files changed, 2 insertions(+), 18 deletions(-) diff --git a/src/Kconfig b/src/Kconfig index 7043851..b158d11 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -243,7 +243,7 @@ config RELOCATABLE_MODULES config RELOCATABLE_RAMSTAGE depends on EARLY_CBMEM_INIT - bool "Build the ramstage to be relocatable in 32-bit address space." + bool default n select RELOCATABLE_MODULES help diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig index af73a58..2750459 100644 --- a/src/arch/x86/Kconfig +++ b/src/arch/x86/Kconfig @@ -82,10 +82,6 @@ config SIPI_VECTOR_IN_ROM config RAMBASE hex default 0x100000 - -config RAMTOP - hex - default 0x200000 depends on ARCH_X86 # Traditionally BIOS region on SPI flash boot media was memory mapped right below diff --git a/src/arch/x86/include/arch/memlayout.h b/src/arch/x86/include/arch/memlayout.h index 5f5cba6..840ceb0 100644 --- a/src/arch/x86/include/arch/memlayout.h +++ b/src/arch/x86/include/arch/memlayout.h @@ -24,8 +24,4 @@ #define ARCH_STAGE_HAS_BSS_SECTION 0 #endif -#if !defined(CONFIG_RAMTOP) || !CONFIG_RAMTOP -# error "CONFIG_RAMTOP not configured" -#endif - #endif /* __ARCH_MEMLAYOUT_H */ diff --git a/src/arch/x86/memlayout.ld b/src/arch/x86/memlayout.ld index e6db0b8..a007272 100644 --- a/src/arch/x86/memlayout.ld +++ b/src/arch/x86/memlayout.ld @@ -26,7 +26,7 @@ SECTIONS * conditionalize with macros. */ #if ENV_RAMSTAGE - RAMSTAGE(CONFIG_RAMBASE, CONFIG_RAMTOP - CONFIG_RAMBASE) + RAMSTAGE(CONFIG_RAMBASE, 8M) #elif ENV_ROMSTAGE /* The 1M size is not allocated. It's just for basic size checking. diff --git a/src/northbridge/amd/agesa/Kconfig b/src/northbridge/amd/agesa/Kconfig index d5cff80..37bf3c4 100644 --- a/src/northbridge/amd/agesa/Kconfig +++ b/src/northbridge/amd/agesa/Kconfig @@ -35,8 +35,4 @@ config HEAP_SIZE hex default 0xc0000 -config RAMTOP - hex - default 0x400000 - endif # NORTHBRIDGE_AMD_AGESA diff --git a/src/northbridge/amd/pi/Kconfig b/src/northbridge/amd/pi/Kconfig index cb72416..eea2897 100644 --- a/src/northbridge/amd/pi/Kconfig +++ b/src/northbridge/amd/pi/Kconfig @@ -40,10 +40,6 @@ config HW_MEM_HOLE_SIZE_AUTO_INC bool default n -config RAMTOP - hex - default 0x1000000 - config HEAP_SIZE hex default 0xc0000

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coreboot-gerrit June 2016