Saurabh Satija (saurabh.satija(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15484
-gerrit
commit 614aa6f6835f994c99d752d2c78b20bb229781b1
Author: Saurabh Satija <saurabh.satija(a)intel.com>
Date: Tue Jun 28 12:32:39 2016 -0700
soc/intel/apollolake: Add NHLT blobs configuration settings
Select ACPI_NHLT and add configuration settings for NHLT audio
blobs for Intel Apollolake SoC. These configs are set in mainboard
for including NHLT audio blobs in cbfs. The following audio blobs
configs are added:
NHLT_DMIC_2CH_16B
NHLT_MAX98357
NHLT_DA7219
Change-Id: Ieebf535b584919d6551bde0f2ee691a93eb9e57e
Signed-off-by: Saurabh Satija <saurabh.satija(a)intel.com>
---
src/soc/intel/apollolake/Kconfig | 24 ++++++++++++++++++++++++
1 file changed, 24 insertions(+)
diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig
index 98ce7d8..cad09d3 100644
--- a/src/soc/intel/apollolake/Kconfig
+++ b/src/soc/intel/apollolake/Kconfig
@@ -17,6 +17,9 @@ config CPU_SPECIFIC_OPTIONS
select SMP
select SSE2
select SUPPORT_CPU_UCODE_IN_CBFS
+ # Audio options
+ select ACPI_NHLT
+ select SOC_INTEL_COMMON_NHLT
# Misc options
select C_ENVIRONMENT_BOOTBLOCK
select COLLECT_TIMESTAMPS
@@ -182,4 +185,25 @@ config IFWI_FILE_NAME
help
Name of file to store in the IFWI region.
+config NHLT_DMIC_2CH_16B
+ bool
+ depends on ACPI_NHLT
+ default n
+ help
+ Include DSP firmware settings for 2 channel 16B DMIC array.
+
+config NHLT_MAX98357
+ bool
+ depends on ACPI_NHLT
+ default n
+ help
+ Include DSP firmware settings for Maxim 98357 codec.
+
+config NHLT_DA7219
+ bool
+ depends on ACPI_NHLT
+ default n
+ help
+ Include DSP firmware settings for Dialog 7219 codec.
+
endif
the following patch was just integrated into master:
commit c14a1a940f06546e0135d2c165d1706e2827818e
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Tue Jun 28 15:41:07 2016 -0500
soc/intel/{common,skylake}: provide common NHLT SoC support
The nhlt_soc_serialize() and nhlt_soc_serialize_oem_overrides()
functions should be able to be leveraged on all Intel SoCs
which support NHLT. Therefore provide that functionality and
make skylake use it.
Change-Id: Ib5535cc874f2680ec22554cecaf97b09753cacd0
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-on: https://review.coreboot.org/15490
Reviewed-by: Furquan Shaikh <furquan(a)google.com>
Tested-by: build bot (Jenkins)
See https://review.coreboot.org/15490 for details.
-gerrit
the following patch was just integrated into master:
commit ed114da4370ebee5126e8faf4eb0f1c9b96b32db
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Tue Jun 28 15:36:01 2016 -0500
lib/nhlt: drop nhlt_soc_add_endpoint()
The nhlt_soc_add_endpoint() is no longer used. Drop its declaration.
Change-Id: I3b68471650a43c5faae44bde523abca7ba250a34
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-on: https://review.coreboot.org/15489
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan(a)google.com>
Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net>
See https://review.coreboot.org/15489 for details.
-gerrit
the following patch was just integrated into master:
commit e9657bc8dc6dc94216fcbbc9b83c12b210c32be9
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Tue Jun 28 15:00:30 2016 -0500
soc/intel/skylake: refactor nhlt support
Utilize the new NHLT helper functions by driving the NHLT
endpoints through data descriptors.
Change-Id: I80838214d3615b83d4939ec2d96a4fd7050d5920
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-on: https://review.coreboot.org/15488
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan(a)google.com>
See https://review.coreboot.org/15488 for details.
-gerrit
the following patch was just integrated into master:
commit 5e0a9c7436f77a4e488d77c80fba38cd00b67e67
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Tue Jun 28 15:18:39 2016 -0500
soc/intel/skylake: fix nhlt/ssm4567.c indention
Whitespace fix for improper space usage for indention.
Change-Id: Ia6470bf152c57786d2d7f3d35bbf0609a2ee3ba2
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-on: https://review.coreboot.org/15487
Reviewed-by: Furquan Shaikh <furquan(a)google.com>
Tested-by: build bot (Jenkins)
See https://review.coreboot.org/15487 for details.
-gerrit