coreboot-gerrit June 2016

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: soc/intel/apollolake: Add CQOS CAR implementation
by Andrey Petrov 30 Jun '16

30 Jun '16

Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15455 -gerrit commit 2494d599bcb3b5a26f56badfd3b6da3336c3b809 Author: Andrey Petrov <andrey.petrov(a)intel.com> Date: Mon Jun 27 13:39:34 2016 -0700 soc/intel/apollolake: Add CQOS CAR implementation Add new Cache Quality of Service option that allows to configure cache non-evict mode by manipulating CQOS settings. Also, CQOS allows using cache non-evict mode simultaneously with regular evicting caching. BUG=chrome-os-partner:51959 Change-Id: Ic7f9899918f94a5788b02a4fbd2f5d5ba9aaf91d Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- src/soc/intel/apollolake/Kconfig | 23 ++++++++++++++++++ src/soc/intel/apollolake/bootblock/bootblock.c | 4 ++++ src/soc/intel/apollolake/bootblock/cache_as_ram.S | 26 +++++++++++++++++++- src/soc/intel/apollolake/car.c | 7 ++++++ src/soc/intel/apollolake/exit_car.S | 29 +++++++++++++++++++++-- src/soc/intel/apollolake/include/soc/cpu.h | 12 ++++++++++ 6 files changed, 98 insertions(+), 3 deletions(-) diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index 43249f1..d828f23 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -182,4 +182,27 @@ config IFWI_FILE_NAME help Name of file to store in the IFWI region. +choice + prompt "Cache-as-ram implementation" + default CAR_CQOS + help + This option allows you to select how cache-as-ram (CAR) is set up. + +config CAR_NEM + bool "Non-evict mode" + help + Traditionally, CAR is set up by using Non-Evict mode. This method + does not allow CAR and cache to co-exist, because cache fills are + block in NEM mode. + + +config CAR_CQOS + bool "Cache Quality of Service" + help + Cache Quality of Service allows more fine-grained control of cache + usage. As result, it is possible to set up portion of L2 cache for + CAR and use remainded for actual caching. + +endchoice + endif diff --git a/src/soc/intel/apollolake/bootblock/bootblock.c b/src/soc/intel/apollolake/bootblock/bootblock.c index 8c1ff91..00c280a 100644 --- a/src/soc/intel/apollolake/bootblock/bootblock.c +++ b/src/soc/intel/apollolake/bootblock/bootblock.c @@ -168,5 +168,9 @@ void bootblock_soc_early_init(void) enable_spibar(); +#if IS_ENABLED(CONFIG_CAR_CQOS) + cache_qos_select_mask(1); +#endif + cache_bios_region(); } diff --git a/src/soc/intel/apollolake/bootblock/cache_as_ram.S b/src/soc/intel/apollolake/bootblock/cache_as_ram.S index 8436d51..6f670c6 100644 --- a/src/soc/intel/apollolake/bootblock/cache_as_ram.S +++ b/src/soc/intel/apollolake/bootblock/cache_as_ram.S @@ -103,7 +103,7 @@ clear_var_mtrr: wrmsr mov $MTRR_PHYS_MASK(1), %ecx - mov $~(0x256 * KiB - 1), %eax /* size mask */ + mov $~(256 * KiB - 1), %eax /* size mask */ or $MTRR_PHYS_MASK_VALID, %eax wrmsr #else @@ -124,12 +124,34 @@ clear_var_mtrr: invd mov %eax, %cr0 +#if IS_ENABLED(CONFIG_CAR_NEM) /* Disable cache eviction (setup stage) */ mov $MSR_EVICT_CTL, %ecx rdmsr or $0x1, %eax wrmsr +#endif + +#if IS_ENABLED(CONFIG_CAR_CQOS) +/* Mask can't be set to all zeros */ +#if ((((1 << (CONFIG_DCACHE_RAM_SIZE / CACHE_QOS_SIZE_PER_BIT)) - 1) & 0xff) == 0xff) +#error "calculated class of service mask is all-zeros, which is unsupported by the CPU" +#endif + /* Mask 0 is used for CAR */ + mov $MTRR_L2_QOS_MASK(0), %ecx + rdmsr + /* Calculate how many bits to be used for CAR */ + mov $(1 << ((CONFIG_DCACHE_RAM_SIZE / CACHE_QOS_SIZE_PER_BIT)) - 1), %al + wrmsr + /* Mask 1 is used for evicatable cache */ + mov $MTRR_L2_QOS_MASK(1), %ecx + rdmsr + /* Invert bits that are to be used for cache */ + mov $(1 << ((CONFIG_DCACHE_RAM_SIZE / CACHE_QOS_SIZE_PER_BIT)) - 1), %al + xor $~0, %al + wrmsr +#endif post_code(0x26) /* Clear the cache memory region. This will also fill up the cache */ @@ -140,11 +162,13 @@ clear_var_mtrr: post_code(0x27) +#if IS_ENABLED(CONFIG_CAR_NEM) /* Disable cache eviction (run stage) */ mov $MSR_EVICT_CTL, %ecx rdmsr or $0x2, %eax wrmsr +#endif post_code(0x28) diff --git a/src/soc/intel/apollolake/car.c b/src/soc/intel/apollolake/car.c index 68bcb31..bb96419 100644 --- a/src/soc/intel/apollolake/car.c +++ b/src/soc/intel/apollolake/car.c @@ -56,3 +56,10 @@ void platform_segment_loaded(uintptr_t start, size_t size, int flags) flush_l1d_to_l2(); } + +void cache_qos_select_mask(uint8_t mask) +{ + msr_t msr = rdmsr(MTRR_IA32_PQR_ASSOC); + msr.hi |= mask; + wrmsr(MTRR_IA32_PQR_ASSOC, msr); +} diff --git a/src/soc/intel/apollolake/exit_car.S b/src/soc/intel/apollolake/exit_car.S index 339242b..e5706cf 100644 --- a/src/soc/intel/apollolake/exit_car.S +++ b/src/soc/intel/apollolake/exit_car.S @@ -27,14 +27,38 @@ chipset_teardown_car: */ pop %ebx - /* invalidate cache contents. */ - invd + /* + * Flush all cache lines into the DRAM. Since we are running in the + * very region, disable MTRR first. + */ + /* Disable MTRRs. */ mov $(MTRR_DEF_TYPE_MSR), %ecx rdmsr and $(~(MTRR_DEF_TYPE_EN | MTRR_DEF_TYPE_FIX_EN)), %eax wrmsr +#if IS_ENABLED(CONFIG_CAR_CQOS) + mov $MTRR_L2_QOS_MASK(0), %ecx + rdmsr + mov $~0, %al + wrmsr + + mov $MTRR_L2_QOS_MASK(1), %ecx + rdmsr + mov $~0, %al + wrmsr + + /* reset CLOS selector */ + mov $MTRR_IA32_PQR_ASSOC, %ecx + rdmsr + and $~(1 << 0 | 1 << 1), %edx + wrmsr +#endif + /* invalidate cache contents. */ + invd + +#if IS_ENABLED(CONFIG_CAR_NEM) /* Knock down bit 1 then bit 0 of NEM control not combining steps. */ mov $(MSR_EVICT_CTL), %ecx rdmsr @@ -42,6 +66,7 @@ chipset_teardown_car: wrmsr and $(~(1 << 0)), %eax wrmsr +#endif /* Return to caller. */ jmp *%ebx diff --git a/src/soc/intel/apollolake/include/soc/cpu.h b/src/soc/intel/apollolake/include/soc/cpu.h index 78fc0b0..13a47cd 100644 --- a/src/soc/intel/apollolake/include/soc/cpu.h +++ b/src/soc/intel/apollolake/include/soc/cpu.h @@ -23,6 +23,7 @@ #include <device/device.h> void apollolake_init_cpus(struct device *dev); +void cache_qos_select_mask(uint8_t mask); #endif #define CPUID_APOLLOLAKE_A0 0x506c8 @@ -35,6 +36,17 @@ void apollolake_init_cpus(struct device *dev); #define MSR_EMULATE_PM_TMR 0x121 #define EMULATE_PM_TMR_EN (1 << 16) +#define MTRR_L2_QOS_MASK(reg) (0xd10 + reg) +#define MTRR_IA32_PQR_ASSOC 0xc8f +/* 16 way cache, 8 bits per QOS, 64 byte cache line, 1024 sets */ +#define CACHE_WAYS 16 +#define CACHE_BITS_PER_MASK 8 +#define CACHE_LINE_SIZE 64 +#define CACHE_SETS 1024 +/* Each bit in QOS mask controls this many bytes */ +#define CACHE_QOS_SIZE_PER_BIT ((CACHE_WAYS / CACHE_BITS_PER_MASK) * \ + CACHE_LINE_SIZE * CACHE_SETS) + #define BASE_CLOCK_MHZ 100 /* Common Timer Copy (CTC) frequency - 19.2MHz. */

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Patch set updated for coreboot: WIP: soc/intel/apollolake: Update stage link addresses for 768 KiB cache
by Andrey Petrov 30 Jun '16

30 Jun '16

Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15454 -gerrit commit e23dd41ac43ddc0a872f39ed5a9ec6ae894247a3 Author: Andrey Petrov <andrey.petrov(a)intel.com> Date: Fri Jun 24 18:15:09 2016 -0700 WIP: soc/intel/apollolake: Update stage link addresses for 768 KiB cache Update link addresses for romstage and verstage. Also change build time relocation address for FSP-M to match. Actual addresses are ballpark estimate and need to be validated. BUG=chrome-os-partner:51959 Change-Id: Ia51a341f05b33151ea5fda9f8620408b5a15bc19 Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- src/soc/intel/apollolake/Kconfig | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index f51dbfb..43249f1 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -120,13 +120,13 @@ config X86_TOP4G_BOOTMEDIA_MAP config ROMSTAGE_ADDR hex - default 0xfef3e000 + default 0xfef11000 help The base address (in CAR) where romstage should be linked config VERSTAGE_ADDR hex - default 0xfef60000 + default 0xfef40000 help The base address (in CAR) where verstage should be linked @@ -136,7 +136,7 @@ config CACHE_MRC_SETTINGS config FSP_M_ADDR hex - default 0xfef60000 + default 0xfef40000 help The address FSP-M will be relocated to during build time

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New patch to review for coreboot: util/kconfig: Fix gconfig build
by Jonathan Neuschäfer 30 Jun '16

30 Jun '16

Jonathan Neuschäfer (j.neuschaefer(a)gmx.net) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15505 -gerrit commit fd1c47448404f7e84d8541da75d1e034b9abbff9 Author: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Date: Thu Jun 30 00:32:02 2016 +0200 util/kconfig: Fix gconfig build Change-Id: I4a667c7c15b35618fb9ad536f2be5044b8031ab4 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> --- util/kconfig/gconf.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/util/kconfig/gconf.c b/util/kconfig/gconf.c index d0a35b2..faa1c59 100644 --- a/util/kconfig/gconf.c +++ b/util/kconfig/gconf.c @@ -26,6 +26,8 @@ //#define DEBUG +int kconfig_warnings = 0; + enum { SINGLE_VIEW, SPLIT_VIEW, FULL_VIEW };

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New patch to review for coreboot: soc/intel/apollolake: add initial NHLT support
by Aaron Durbin 30 Jun '16

30 Jun '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15504 -gerrit commit 762944fbcfaca1cd04b4143cb1f3c4baf0a0cae0 Author: Saurabh Satija <saurabh.satija(a)intel.com> Date: Tue Jun 21 14:22:16 2016 -0700 soc/intel/apollolake: add initial NHLT support Provide the initiall NHLT support for the following hardware: 1. 2 channel digital microphone array 2. da7219 headset 3. max98357 speaker amplifiers. The code utilizes the Intel SoC common NHLT support. Change-Id: Ic31e834a08f29c66512a7a63ad7bb35e0374e86a Signed-off-by: Saurabh Satija <saurabh.satija(a)intel.com> Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/soc/intel/apollolake/Kconfig | 24 +++++ src/soc/intel/apollolake/Makefile.inc | 19 ++++ src/soc/intel/apollolake/include/soc/nhlt.h | 43 +++++++++ src/soc/intel/apollolake/nhlt.c | 142 ++++++++++++++++++++++++++++ 4 files changed, 228 insertions(+) diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index 98ce7d8..8e33015 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -17,6 +17,9 @@ config CPU_SPECIFIC_OPTIONS select SMP select SSE2 select SUPPORT_CPU_UCODE_IN_CBFS + # Audio options + select ACPI_NHLT + select SOC_INTEL_COMMON_NHLT # Misc options select C_ENVIRONMENT_BOOTBLOCK select COLLECT_TIMESTAMPS @@ -182,4 +185,25 @@ config IFWI_FILE_NAME help Name of file to store in the IFWI region. +config NHLT_DMIC_2CH_16B + bool + depends on ACPI_NHLT + default n + help + Include DSP firmware settings for 2 channel 16B DMIC array. + +config NHLT_MAX98357 + bool + depends on ACPI_NHLT + default n + help + Include DSP firmware settings for headset codec. + +config NHLT_DA7219 + bool + depends on ACPI_NHLT + default n + help + Include DSP firmware settings for headset codec. + endif diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index 7326f14..030e35c 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -51,6 +51,7 @@ ramstage-y += lpc_lib.c ramstage-y += memmap.c ramstage-y += mmap_boot.c ramstage-y += uart.c +ramstage-y += nhlt.c ramstage-y += northbridge.c ramstage-y += spi.c ramstage-y += tsc_freq.c @@ -104,4 +105,22 @@ files_added:: $(IFWITOOL) $(CBFSTOOL) $(obj)/coreboot.rom write -r $(CONFIG_IFWI_FMAP_NAME) -f $(objcbfs)/ifwi.bin.tmp --fill-upward endif +# DSP firmware settings files. +NHLT_BLOB_PATH = 3rdparty/blobs/soc/intel/apollolake/nhlt-blobs +DMIC_2CH_48KHZ_16B = dmic-2ch-48khz-16b.bin +MAX98357_RENDER = max98357-render-2ch-48khz-24b.bin +DA7219_RENDER_CAPTURE = dialog-2ch-48khz-24b.bin + +cbfs-files-$(CONFIG_NHLT_DMIC_2CH) += $(DMIC_2CH_48KHZ_16B) +$(DMIC_2CH_48KHZ_16B)-file := $(NHLT_BLOB_PATH)/$(DMIC_2CH_48KHZ_16B) +$(DMIC_2CH_48KHZ_16B)-type := raw + +cbfs-files-$(CONFIG_NHLT_MAX98357) += $(MAX98357_RENDER) +$(MAX98357_RENDER)-file := $(NHLT_BLOB_PATH)/$(MAX98357_RENDER) +$(MAX98357_RENDER)-type := raw + +cbfs-files-$(CONFIG_NHLT_DA7219) += $(DA7219_RENDER_CAPTURE) +$(DA7219_RENDER_CAPTURE)-file := $(NHLT_BLOB_PATH)/$(DA7219_RENDER_CAPTURE) +$(DA7219_RENDER_CAPTURE)-type := raw + endif diff --git a/src/soc/intel/apollolake/include/soc/nhlt.h b/src/soc/intel/apollolake/include/soc/nhlt.h new file mode 100644 index 0000000..d49b8cf --- /dev/null +++ b/src/soc/intel/apollolake/include/soc/nhlt.h @@ -0,0 +1,43 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_APOLLOLAKE_NHLT_H_ +#define _SOC_APOLLOLAKE_NHLT_H_ + +#include <nhlt.h> + +#define NHLT_VID 0x8086 +#define NHLT_DID_DMIC 0xae20 +#define NHLT_DID_BT 0xae30 +#define NHLT_DID_SSP 0xae34 + +/* The following link values should be used for the hwlink parameters below. */ +enum { + AUDIO_LINK_SSP0, + AUDIO_LINK_SSP1, + AUDIO_LINK_SSP2, + AUDIO_LINK_SSP3, + AUDIO_LINK_SSP4, + AUDIO_LINK_SSP5, + AUDIO_LINK_DMIC, +}; + +/* Returns < 0 on error, 0 on success. */ +int nhlt_soc_add_dmic_array(struct nhlt *nhlt, int num_channels); +int nhlt_soc_add_max98357(struct nhlt *nhlt, int hwlink); +int nhlt_soc_add_da7219(struct nhlt *nhlt, int hwlink); + +#endif diff --git a/src/soc/intel/apollolake/nhlt.c b/src/soc/intel/apollolake/nhlt.c new file mode 100644 index 0000000..3670a13 --- /dev/null +++ b/src/soc/intel/apollolake/nhlt.c @@ -0,0 +1,142 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <nhlt.h> +#include <soc/nhlt.h> + +static const struct nhlt_format_config dmic_2ch_formats[] = { + /* 48 KHz 16-bits per sample. */ + { + .num_channels = 2, + .sample_freq_khz = 48, + .container_bits_per_sample = 16, + .valid_bits_per_sample = 16, + .settings_file = "dmic-2ch-48khz-16b.bin", + }, +}; + +static const struct nhlt_dmic_array_config dmic_2ch_mic_config = { + .tdm_config = { + .config_type = NHLT_TDM_MIC_ARRAY, + }, + .array_type = NHLT_MIC_ARRAY_2CH_SMALL, +}; + +static const struct nhlt_endp_descriptor dmic_2ch_descriptors[] = { + { + .link = NHLT_LINK_PDM, + .device = NHLT_PDM_DEV, + .direction = NHLT_DIR_CAPTURE, + .vid = NHLT_VID, + .did = NHLT_DID_DMIC, + .cfg = &dmic_2ch_mic_config, + .cfg_size = sizeof(dmic_2ch_mic_config), + .formats = dmic_2ch_formats, + .num_formats = ARRAY_SIZE(dmic_2ch_formats), + }, +}; + +static const struct nhlt_format_config da7219_formats[] = { + /* 48 KHz 24-bits per sample. */ + { + .num_channels = 2, + .sample_freq_khz = 48, + .container_bits_per_sample = 32, + .valid_bits_per_sample = 24, + .settings_file = "dialog-2ch-48khz-24b.bin", + }, +}; + +static const struct nhlt_tdm_config tdm_config = { + .virtual_slot = 0, + .config_type = NHLT_TDM_BASIC, +}; + +static const struct nhlt_endp_descriptor da7219_descriptors[] = { + /* Render Endpoint */ + { + .link = NHLT_LINK_SSP, + .device = NHLT_SSP_DEV_I2S, + .direction = NHLT_DIR_RENDER, + .vid = NHLT_VID, + .did = NHLT_DID_SSP, + .cfg = &tdm_config, + .cfg_size = sizeof(tdm_config), + .formats = da7219_formats, + .num_formats = ARRAY_SIZE(da7219_formats), + }, + /* Capture Endpoint */ + { + .link = NHLT_LINK_SSP, + .device = NHLT_SSP_DEV_I2S, + .direction = NHLT_DIR_CAPTURE, + .vid = NHLT_VID, + .did = NHLT_DID_SSP, + .cfg = &tdm_config, + .cfg_size = sizeof(tdm_config), + .formats = da7219_formats, + .num_formats = ARRAY_SIZE(da7219_formats), + }, +}; + +static const struct nhlt_format_config max98357_formats[] = { + /* 48 KHz 24-bits per sample. */ + { + .num_channels = 2, + .sample_freq_khz = 48, + .container_bits_per_sample = 32, + .valid_bits_per_sample = 24, + .settings_file = "max98357-render-2ch-48khz-24b.bin", + }, +}; + +static const struct nhlt_endp_descriptor max98357_descriptors[] = { + { + .link = NHLT_LINK_SSP, + .device = NHLT_SSP_DEV_I2S, + .direction = NHLT_DIR_RENDER, + .vid = NHLT_VID, + .did = NHLT_DID_SSP, + .formats = max98357_formats, + .num_formats = ARRAY_SIZE(max98357_formats), + }, +}; + +int nhlt_soc_add_dmic_array(struct nhlt *nhlt, int num_channels) +{ + if (num_channels != 2) { + printk(BIOS_ERR, "APL only supports 2CH DMIC array.\n"); + return -1; + } + + return nhlt_add_endpoints(nhlt, dmic_2ch_descriptors, + ARRAY_SIZE(dmic_2ch_descriptors)); +} + +int nhlt_soc_add_da7219(struct nhlt *nhlt, int hwlink) +{ + /* Virtual bus id of SSP links are the hardware port ids proper. */ + return nhlt_add_ssp_endpoints(nhlt, hwlink, da7219_descriptors, + ARRAY_SIZE(da7219_descriptors)); +} + +int nhlt_soc_add_max98357(struct nhlt *nhlt, int hwlink) +{ + /* Virtual bus id of SSP links are the hardware port ids proper. */ + return nhlt_add_ssp_endpoints(nhlt, hwlink, max98357_descriptors, + ARRAY_SIZE(max98357_descriptors)); +}

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New patch to review for coreboot: soc/intel/common: use nvs.h include for nhlt code
by Aaron Durbin 30 Jun '16

30 Jun '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15503 -gerrit commit d1ff194ba382e58b03acdc86e51fefd076324cc7 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Jun 29 17:28:02 2016 -0500 soc/intel/common: use nvs.h include for nhlt code The nvs.h header is the one which defines global_nvs_t proper. Don't rely on an indirect inclusion. Change-Id: I89d6a73f65e408c73f068b4a35b5efd361a6e5d3 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/soc/intel/common/nhlt.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/soc/intel/common/nhlt.c b/src/soc/intel/common/nhlt.c index d498152..03a4b4f 100644 --- a/src/soc/intel/common/nhlt.c +++ b/src/soc/intel/common/nhlt.c @@ -15,7 +15,7 @@ #include <cbmem.h> #include <nhlt.h> -#include <soc/acpi.h> +#include <soc/nvs.h> uintptr_t nhlt_soc_serialize(struct nhlt *nhlt, uintptr_t acpi_addr) {

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New patch to review for coreboot: soc/intel/apollolake: typedef global_nvs_t for consistency
by Aaron Durbin 30 Jun '16

30 Jun '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15502 -gerrit commit ffc500fce2a6b83e8e58641bb0d9e0197da4becd Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Jun 29 17:26:33 2016 -0500 soc/intel/apollolake: typedef global_nvs_t for consistency Every other platform has global_nvs_t as a typedef. For some reason apollolake didn't bother following current conventions. Fix this omission to allow for better code sharing and consistency. Change-Id: Id596eed517737759a64ce803c89ea2a05cbe2cce Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/soc/intel/apollolake/include/soc/nvs.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/soc/intel/apollolake/include/soc/nvs.h b/src/soc/intel/apollolake/include/soc/nvs.h index 3e4f432..bff949e 100644 --- a/src/soc/intel/apollolake/include/soc/nvs.h +++ b/src/soc/intel/apollolake/include/soc/nvs.h @@ -26,7 +26,7 @@ #include <vendorcode/google/chromeos/gnvs.h> -struct global_nvs_t { +typedef struct global_nvs_t { /* Miscellaneous */ uint8_t pcnt; /* 0x00 - Processor Count */ uint8_t ppcm; /* 0x01 - Max PPC State */ @@ -42,6 +42,6 @@ struct global_nvs_t { /* ChromeOS specific (0x100 - 0xfff) */ chromeos_acpi_t chromeos; -} __attribute__((packed)); +} __attribute__((packed)) global_nvs_t; #endif /* _SOC_APOLLOLAKE_NVS_H_ */

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Patch set updated for coreboot: mainboard/intel/amenia: add NHLT support
by Aaron Durbin 30 Jun '16

30 Jun '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15024 -gerrit commit 392dfa8488f9185bb79eb16a9786e120bb556ab5 Author: Saurabh Satija <saurabh.satija(a)intel.com> Date: Thu May 26 16:08:45 2016 -0700 mainboard/intel/amenia: add NHLT support Add ACPI NHLT table generation that the current hardware supports as well select the hardware used on the board. Amenia has support for two audio codecs, Dialog for headsets and Maxim for speakers. Change-Id: Iaba9ec81ffb4f128f2e4413dec5174d9ecb856c9 Signed-off-by: Saurabh Satija <saurabh.satija(a)intel.com> --- src/mainboard/intel/amenia/Kconfig | 6 +++++ src/mainboard/intel/amenia/dsdt.asl | 11 ++++---- src/mainboard/intel/amenia/mainboard.c | 48 ++++++++++++++++++++++++++++++++-- 3 files changed, 58 insertions(+), 7 deletions(-) diff --git a/src/mainboard/intel/amenia/Kconfig b/src/mainboard/intel/amenia/Kconfig index 6fc5e35..b3ef17b 100644 --- a/src/mainboard/intel/amenia/Kconfig +++ b/src/mainboard/intel/amenia/Kconfig @@ -44,4 +44,10 @@ config MAX_CPUS int default 8 +config INCLUDE_NHLT_BLOBS + bool "Include blobs for audio." + select NHLT_DMIC_2CH_16B + select NHLT_DA7219 + select NHLT_MAX98357 + endif # BOARD_INTEL_AMENIA diff --git a/src/mainboard/intel/amenia/dsdt.asl b/src/mainboard/intel/amenia/dsdt.asl index 4a64f87..46404ed 100644 --- a/src/mainboard/intel/amenia/dsdt.asl +++ b/src/mainboard/intel/amenia/dsdt.asl @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Intel Corp. + * Copyright (C) 2016 Intel Corp. * (Written by Lance Zhao <lijian.zhao(a)intel.com> for Intel Corp.) * * This program is free software; you can redistribute it and/or modify @@ -33,15 +33,16 @@ DefinitionBlock( Scope (\_SB) { Device (PCI0) { - #include <soc/intel/apollolake/acpi/northbridge.asl> - #include <soc/intel/apollolake/acpi/southbridge.asl> + #include <soc/intel/apollolake/acpi/northbridge.asl> + #include <soc/intel/apollolake/acpi/southbridge.asl> + #include <soc/intel/apollolake/acpi/pch_hda.asl> } } /* Mainboard Specific devices */ #include "acpi/mainboard.asl" - /* Chipset specific sleep states */ - #include <soc/intel/apollolake/acpi/sleepstates.asl> + /* Chipset specific sleep states */ + #include <soc/intel/apollolake/acpi/sleepstates.asl> #include "acpi/superio.asl" } diff --git a/src/mainboard/intel/amenia/mainboard.c b/src/mainboard/intel/amenia/mainboard.c index 8d10b28..6ec5b98 100644 --- a/src/mainboard/intel/amenia/mainboard.c +++ b/src/mainboard/intel/amenia/mainboard.c @@ -15,9 +15,10 @@ * GNU General Public License for more details. */ +#include <arch/acpi.h> +#include <console/console.h> #include <device/device.h> -#include <soc/gpio.h> -#include <soc/pci_devs.h> +#include <soc/nhlt.h> #include "ec.h" #include "gpio.h" @@ -27,6 +28,49 @@ static void mainboard_init(void *chip_info) mainboard_ec_init(); } +static unsigned long mainboard_write_acpi_tables( + device_t device, unsigned long current, acpi_rsdp_t *rsdp) +{ + uintptr_t start_addr; + uintptr_t end_addr; + struct nhlt *nhlt; + + start_addr = current; + + nhlt = nhlt_init(); + + if (nhlt == NULL) + return start_addr; + + /* 2 Channel DMIC array. */ + if (!nhlt_soc_add_dmic_array(nhlt, 2)) + printk(BIOS_ERR, "Added 2CH DMIC array.\n"); + + /* Dialog for Headset codec. + * Headset codec is bi-directional but uses the same configuration + * settings for render and capture endpoints. + */ + if (!nhlt_soc_add_da7219(nhlt, AUDIO_LINK_SSP1)) + printk(BIOS_ERR, "Added Dialog_7219 codec.\n"); + + /* MAXIM Smart Amps for left and right speakers. */ + if (!nhlt_soc_add_max98357(nhlt, AUDIO_LINK_SSP5)) + printk(BIOS_ERR, "Added Maxim_98357 codec.\n"); + + end_addr = nhlt_soc_serialize(nhlt, start_addr); + + if (end_addr != start_addr) + acpi_add_table(rsdp, (void *)start_addr); + + return end_addr; +} + +static void mainboard_enable(device_t dev) +{ + dev->ops->write_acpi_tables = mainboard_write_acpi_tables; +} + struct chip_operations mainboard_ops = { .init = mainboard_init, + .enable_dev = mainboard_enable, };

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Patch merged into coreboot/master: soc/intel/apollolake: fix space indention in pm.h
by gerrit＠coreboot.org 30 Jun '16

30 Jun '16

the following patch was just integrated into master: commit c4c83839675c74854a3fbd548f5757968ec1c6fe Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Jun 29 16:17:02 2016 -0500 soc/intel/apollolake: fix space indention in pm.h More spaces missed in review. Change-Id: I842da05ca6ad4f2c13d2d42433e41da57ccf7f96 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://review.coreboot.org/15500 Reviewed-by: Furquan Shaikh <furquan(a)google.com> Tested-by: build bot (Jenkins) See https://review.coreboot.org/15500 for details. -gerrit

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New patch to review for coreboot: soc/intel/apollalake: Make global_nvs_t a user defined type
by Saurabh Satija 30 Jun '16

30 Jun '16

Saurabh Satija (saurabh.satija(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15501 -gerrit commit 0af885c8ea94aaa56c90d4b21d66be4804a43f94 Author: Saurabh Satija <saurabh.satija(a)intel.com> Date: Tue Jun 28 20:33:44 2016 -0700 soc/intel/apollalake: Make global_nvs_t a user defined type In order to use nhlt_soc_serialize() and nhlt_soc_serialize_oem_overrides() defined in soc/intel/common/ nhlt.c. These functions are common for all Intel SoCs and use global_nvs_t as a user-defined type. Change-Id: I4016cdc6a873d26f9fca243084c66e69e0e66a74 Signed-off-by: Saurabh Satija <saurabh.satija(a)intel.com> --- src/soc/intel/apollolake/include/soc/nvs.h | 4 ++-- src/soc/intel/common/nhlt.c | 1 + 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/src/soc/intel/apollolake/include/soc/nvs.h b/src/soc/intel/apollolake/include/soc/nvs.h index 3e4f432..bff949e 100644 --- a/src/soc/intel/apollolake/include/soc/nvs.h +++ b/src/soc/intel/apollolake/include/soc/nvs.h @@ -26,7 +26,7 @@ #include <vendorcode/google/chromeos/gnvs.h> -struct global_nvs_t { +typedef struct global_nvs_t { /* Miscellaneous */ uint8_t pcnt; /* 0x00 - Processor Count */ uint8_t ppcm; /* 0x01 - Max PPC State */ @@ -42,6 +42,6 @@ struct global_nvs_t { /* ChromeOS specific (0x100 - 0xfff) */ chromeos_acpi_t chromeos; -} __attribute__((packed)); +} __attribute__((packed)) global_nvs_t; #endif /* _SOC_APOLLOLAKE_NVS_H_ */ diff --git a/src/soc/intel/common/nhlt.c b/src/soc/intel/common/nhlt.c index d498152..0ee9424 100644 --- a/src/soc/intel/common/nhlt.c +++ b/src/soc/intel/common/nhlt.c @@ -16,6 +16,7 @@ #include <cbmem.h> #include <nhlt.h> #include <soc/acpi.h> +#include <soc/nvs.h> uintptr_t nhlt_soc_serialize(struct nhlt *nhlt, uintptr_t acpi_addr) {

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Patch set updated for coreboot: mainboard/intel/amenia: Use common NHLT
by Saurabh Satija 30 Jun '16

30 Jun '16

Saurabh Satija (saurabh.satija(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15024 -gerrit commit e85ea40c1b7bdc52a8098ae907ed81d313306bc1 Author: Saurabh Satija <saurabh.satija(a)intel.com> Date: Thu May 26 16:08:45 2016 -0700 mainboard/intel/amenia: Use common NHLT Add ACPI NHLT table generation that the current hardware supports. Amenia has support for two audio codecs, Dialog for headsets and Maxim for speakers. Change-Id: Iaba9ec81ffb4f128f2e4413dec5174d9ecb856c9 Signed-off-by: Saurabh Satija <saurabh.satija(a)intel.com> --- src/mainboard/intel/amenia/dsdt.asl | 11 ++++---- src/mainboard/intel/amenia/mainboard.c | 49 ++++++++++++++++++++++++++++++++++ 2 files changed, 55 insertions(+), 5 deletions(-) diff --git a/src/mainboard/intel/amenia/dsdt.asl b/src/mainboard/intel/amenia/dsdt.asl index 4a64f87..46404ed 100644 --- a/src/mainboard/intel/amenia/dsdt.asl +++ b/src/mainboard/intel/amenia/dsdt.asl @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Intel Corp. + * Copyright (C) 2016 Intel Corp. * (Written by Lance Zhao <lijian.zhao(a)intel.com> for Intel Corp.) * * This program is free software; you can redistribute it and/or modify @@ -33,15 +33,16 @@ DefinitionBlock( Scope (\_SB) { Device (PCI0) { - #include <soc/intel/apollolake/acpi/northbridge.asl> - #include <soc/intel/apollolake/acpi/southbridge.asl> + #include <soc/intel/apollolake/acpi/northbridge.asl> + #include <soc/intel/apollolake/acpi/southbridge.asl> + #include <soc/intel/apollolake/acpi/pch_hda.asl> } } /* Mainboard Specific devices */ #include "acpi/mainboard.asl" - /* Chipset specific sleep states */ - #include <soc/intel/apollolake/acpi/sleepstates.asl> + /* Chipset specific sleep states */ + #include <soc/intel/apollolake/acpi/sleepstates.asl> #include "acpi/superio.asl" } diff --git a/src/mainboard/intel/amenia/mainboard.c b/src/mainboard/intel/amenia/mainboard.c index 8d10b28..5576c63 100644 --- a/src/mainboard/intel/amenia/mainboard.c +++ b/src/mainboard/intel/amenia/mainboard.c @@ -16,8 +16,14 @@ */ #include <device/device.h> +#include <arch/acpi.h> +#include <console/console.h> +#include <nhlt.h> #include <soc/gpio.h> +#include <soc/nhlt.h> #include <soc/pci_devs.h> +#include <stdlib.h> +#include <string.h> #include "ec.h" #include "gpio.h" @@ -27,6 +33,49 @@ static void mainboard_init(void *chip_info) mainboard_ec_init(); } +static unsigned long mainboard_write_acpi_tables( + device_t device, unsigned long current, acpi_rsdp_t *rsdp) +{ + uintptr_t start_addr; + uintptr_t end_addr; + struct nhlt *nhlt; + + start_addr = current; + + nhlt = nhlt_init(); + + if (nhlt == NULL) + return start_addr; + + /* 2 Channel DMIC array. */ + if (!nhlt_soc_add_dmic_array(nhlt, 2)) + printk(BIOS_ERR, "Added 2CH DMIC array.\n"); + + /* Dialog for Headset codec. + * Headset codec is bi-directional but uses the same configuration + * settings for render and capture endpoints. + */ + if (!nhlt_soc_add_da7219(nhlt, AUDIO_LINK_SSP1)) + printk(BIOS_ERR, "Added Dialog_7219 codec.\n"); + + /* MAXIM Smart Amps for left and right speakers. */ + if (!nhlt_soc_add_max98357(nhlt, AUDIO_LINK_SSP5)) + printk(BIOS_ERR, "Added Maxim_98357 codec.\n"); + + end_addr = nhlt_soc_serialize(nhlt, start_addr); + + if (end_addr != start_addr) + acpi_add_table(rsdp, (void *)start_addr); + + return end_addr; +} + +static void mainboard_enable(device_t dev) +{ + dev->ops->write_acpi_tables = mainboard_write_acpi_tables; +} + struct chip_operations mainboard_ops = { .init = mainboard_init, + .enable_dev = mainboard_enable, };

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coreboot-gerrit June 2016