coreboot-gerrit June 2016

coreboot-gerrit@coreboot.org

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1491 discussions

Patch merged into coreboot/master: nvramcui: Update Makefile
by gerrit＠coreboot.org 29 Jun '16

29 Jun '16

the following patch was just integrated into master: commit 9d8b2ffb4978e4d87f85d6b7b92433594d95b0aa Author: Martin Roth <martinroth(a)google.com> Date: Sat Apr 23 17:19:41 2016 -0600 nvramcui: Update Makefile - Add all, clean and distclean to .PHONY - Rebuild nvramcui.elf when the makefile changes. - Update libpayload target to $(LIBPAYLOAD_DIR) target - these are the same thing, but by using the variable it makes it more obvious. - Remove .config.old as well as .config when running distclean. - Add CFLAGS to the LPGCC command line: -- Enable all warnings, set warnings as errors. -- Optimize for size -- Enable '-ffreestanding -nostdinc -nostdlib' to keep from building in system functions and to fix the warning: libpayload.h: warning: conflicting types for built-in function 'log2' static inline int log2(u32 x) { return sizeof(x) * 8 - clz(x) - 1; } Change-Id: Icc6c70b259cd7c22dc960cdb732927f9c0c93ee8 Signed-off-by: Martin Roth <martinroth(a)google.com> Reviewed-on: https://review.coreboot.org/14482 Tested-by: build bot (Jenkins) Reviewed-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See https://review.coreboot.org/14482 for details. -gerrit

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Patch set updated for coreboot: soc/apollolake: Allow enable/disable of LPSS S0ix from devicetree
by Hannah Williams 29 Jun '16

29 Jun '16

Hannah Williams (hannah.williams(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15055 -gerrit commit ae6dad1b8a9af2c5668eca6b76c96f968a3c31de Author: Saurabh Satija <saurabh.satija(a)intel.com> Date: Tue May 3 15:15:31 2016 -0700 soc/apollolake: Allow enable/disable of LPSS S0ix from devicetree Change-Id: Ib7aa1d1b32adcb541a155b8ba2ee011cb5bcf784 Signed-off-by: Saurabh Satija <saurabh.satija(a)intel.com> Signed-off-by: Hannah Williams <hannah.williams(a)intel.com> --- src/soc/intel/apollolake/chip.c | 2 ++ src/soc/intel/apollolake/chip.h | 3 +++ 2 files changed, 5 insertions(+) diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index 044ef91..edf4a56 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -255,6 +255,8 @@ void platform_fsp_silicon_init_params_cb(struct FSPS_UPD *silupd) silconfig->IshEnable = cfg->integrated_sensor_hub_enable; + silconfig->LPSS_S0ixEnable = cfg->lpss_s0ix_enable; + /* Disable setting of EISS bit in FSP. */ silconfig->SpiEiss = 0; } diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h index ef82c53..0cde7d7 100644 --- a/src/soc/intel/apollolake/chip.h +++ b/src/soc/intel/apollolake/chip.h @@ -79,6 +79,9 @@ struct soc_intel_apollolake_config { /* Integrated Sensor Hub */ uint8_t integrated_sensor_hub_enable; + + /* Configure LPSS S0ix Enable */ + uint8_t lpss_s0ix_enable; }; #endif /* _SOC_APOLLOLAKE_CHIP_H_ */

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Patch set updated for coreboot: amd/olivehillplus: Fix PCIe lane number comments.
by Derek Waldner 29 Jun '16

29 Jun '16

Derek Waldner (derek.waldner.os(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15095 -gerrit commit e3e548d784fad27a04f92863bf5ddaa85089be1f Author: Derek Waldner <derek.waldner.os(a)gmail.com> Date: Mon Jun 6 13:54:26 2016 -0500 amd/olivehillplus: Fix PCIe lane number comments. Correct the GPP PCIe lane number comments so that they match the code. Change-Id: If27c6a55ebedb0927dd9e8c7c9a833194e129a25 Signed-off-by: Derek Waldner <derek.waldner.os(a)gmail.com> --- src/mainboard/amd/olivehillplus/OemCustomize.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/src/mainboard/amd/olivehillplus/OemCustomize.c b/src/mainboard/amd/olivehillplus/OemCustomize.c index 06a8f3d..ac60c42 100644 --- a/src/mainboard/amd/olivehillplus/OemCustomize.c +++ b/src/mainboard/amd/olivehillplus/OemCustomize.c @@ -18,6 +18,7 @@ #define FILECODE PROC_GNB_PCIE_FAMILY_0X15_F15PCIECOMPLEXCONFIG_FILECODE static const PCIe_PORT_DESCRIPTOR PortList [] = { + /* Initialize Port descriptor (PCIe port, Lane 3, PCI Device 2, Function 5) */ { 0, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 3, 3), @@ -27,7 +28,7 @@ static const PCIe_PORT_DESCRIPTOR PortList [] = { PcieGenMaxSupported, AspmDisabled, 0x01, 0) }, - /* Initialize Port descriptor (PCIe port, Lanes 1, PCI Device Number 2, ...) */ + /* Initialize Port descriptor (PCIe port, Lane 2, PCI Device 2, Function 4) */ { 0, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 2, 2), @@ -37,7 +38,7 @@ static const PCIe_PORT_DESCRIPTOR PortList [] = { PcieGenMaxSupported, AspmDisabled, 0x02, 0) }, - /* Initialize Port descriptor (PCIe port, Lanes 2, PCI Device Number 2, ...) */ + /* Initialize Port descriptor (PCIe port, Lane 1, PCI Device 2, Function 3) */ { 0, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 1, 1), @@ -47,7 +48,7 @@ static const PCIe_PORT_DESCRIPTOR PortList [] = { PcieGenMaxSupported, AspmDisabled, 0x03, 0) }, - /* Initialize Port descriptor (PCIe port, Lanes 3, PCI Device Number 2, ...) */ + /* Initialize Port descriptor (PCIe port, Lane 0, PCI Device 2, Function 2) */ { 0, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 0), @@ -57,7 +58,7 @@ static const PCIe_PORT_DESCRIPTOR PortList [] = { PcieGenMaxSupported, AspmDisabled, 0x04, 0) }, - /* Initialize Port descriptor (PCIe port, Lanes 4-7, PCI Device Number 4, ...) */ + /* Initialize Port descriptor (PCIe port, Lanes 4-7, PCI Device 2, Function 1) */ { DESCRIPTOR_TERMINATE_LIST, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 7),

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Patch set updated for coreboot: soc/apollolake: Allow enable\disable of LPSS S0ix from devicetree
by Martin Roth 29 Jun '16

29 Jun '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15055 -gerrit commit 6a978d4a12b0b3b7149789cda8ed88aef16b2359 Author: Saurabh Satija <saurabh.satija(a)intel.com> Date: Tue May 3 15:15:31 2016 -0700 soc/apollolake: Allow enable\disable of LPSS S0ix from devicetree Change-Id: Ib7aa1d1b32adcb541a155b8ba2ee011cb5bcf784 Signed-off-by: Saurabh Satija <saurabh.satija(a)intel.com> Signed-off-by: Hannah Williams <hannah.williams(a)intel.com> --- src/soc/intel/apollolake/chip.c | 2 ++ src/soc/intel/apollolake/chip.h | 3 +++ 2 files changed, 5 insertions(+) diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index 044ef91..edf4a56 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -255,6 +255,8 @@ void platform_fsp_silicon_init_params_cb(struct FSPS_UPD *silupd) silconfig->IshEnable = cfg->integrated_sensor_hub_enable; + silconfig->LPSS_S0ixEnable = cfg->lpss_s0ix_enable; + /* Disable setting of EISS bit in FSP. */ silconfig->SpiEiss = 0; } diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h index ef82c53..0cde7d7 100644 --- a/src/soc/intel/apollolake/chip.h +++ b/src/soc/intel/apollolake/chip.h @@ -79,6 +79,9 @@ struct soc_intel_apollolake_config { /* Integrated Sensor Hub */ uint8_t integrated_sensor_hub_enable; + + /* Configure LPSS S0ix Enable */ + uint8_t lpss_s0ix_enable; }; #endif /* _SOC_APOLLOLAKE_CHIP_H_ */

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Patch merged into coreboot/master: soc/intel/apollolake: Update Upd header files for FSP Label 143_10
by gerrit＠coreboot.org 29 Jun '16

29 Jun '16

the following patch was just integrated into master: commit ba3d626cfbc5b0ba4dcbdf756a3abf5e61afa210 Author: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Date: Fri Jun 24 10:41:39 2016 -0700 soc/intel/apollolake: Update Upd header files for FSP Label 143_10 New UPDs added to header files as well as many comment fixes. Memory infor is now defined in FspmUpd.h and added ability to skip CSE RBP for coreboot. Removes some UPDs that are no longer available from source. BUG=chrome-os-partner:54677 BRANCH=none TEST=built and tested with FSP 143_10 version Change-Id: I7e1f531ebbe343b45151a265ac715ae74aeffcad Signed-off-by: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Reviewed-on: https://review.coreboot.org/15459 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See https://review.coreboot.org/15459 for details. -gerrit

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Patch merged into coreboot/master: rebase.sh: Update to current cros branch
by gerrit＠coreboot.org 29 Jun '16

29 Jun '16

the following patch was just integrated into master: commit deed18627dd0ab7f31176ff2c148e62a481daf48 Author: Martin Roth <martinroth(a)google.com> Date: Wed Jun 22 15:49:42 2016 -0600 rebase.sh: Update to current cros branch Change-Id: I04add4e6fc957cb9a0cdefe79ec9e97e3cebdf8e Signed-off-by: Martin Roth <martinroth(a)google.com> Reviewed-on: https://review.coreboot.org/15322 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See https://review.coreboot.org/15322 for details. -gerrit

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Patch set updated for coreboot: AMD k8 fam10: Delay ACPI S3 backup until ramstage loader
by Kyösti Mälkki 29 Jun '16

29 Jun '16

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15475 -gerrit commit 3c10c7b6af22dafc4aa257d9e75a12fd41457d04 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Mon Jun 27 12:14:57 2016 +0300 AMD k8 fam10: Delay ACPI S3 backup until ramstage loader Change-Id: I6d5d3e1ccd2dab727c9eba6c6175d47955719b54 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/cpu/amd/car/post_cache_as_ram.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/src/cpu/amd/car/post_cache_as_ram.c b/src/cpu/amd/car/post_cache_as_ram.c index 86076b7..e207a65 100644 --- a/src/cpu/amd/car/post_cache_as_ram.c +++ b/src/cpu/amd/car/post_cache_as_ram.c @@ -135,9 +135,6 @@ void cache_as_ram_new_stack (void) set_var_mtrr(0, 0x00000000, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK); enable_cache(); - if (acpi_is_wakeup_s3()) - acpi_prepare_for_resume(); - #if IS_ENABLED(CONFIG_HAVE_ROMSTAGE_CONSOLE_SPINLOCK) initialize_romstage_console_lock(); #endif

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Patch set updated for coreboot: Obsoletes RAMBASE and RAMTOP
by Kyösti Mälkki 29 Jun '16

29 Jun '16

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15250 -gerrit commit 52a82f1c539fab147dea31e70c207d7f481771dd Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sat Jun 18 07:39:31 2016 +0300 Obsoletes RAMBASE and RAMTOP There is no fixed region of RAMBASE..RAMTOP where ramstage gets loaded. Change-Id: Ie90611274fb011759661d5c46c8e35e5cca6533c Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/Kconfig | 2 +- src/arch/x86/Kconfig | 4 ---- src/arch/x86/include/arch/memlayout.h | 4 ---- src/arch/x86/memlayout.ld | 2 +- src/northbridge/amd/agesa/Kconfig | 4 ---- src/northbridge/amd/pi/Kconfig | 4 ---- 6 files changed, 2 insertions(+), 18 deletions(-) diff --git a/src/Kconfig b/src/Kconfig index 7043851..b158d11 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -243,7 +243,7 @@ config RELOCATABLE_MODULES config RELOCATABLE_RAMSTAGE depends on EARLY_CBMEM_INIT - bool "Build the ramstage to be relocatable in 32-bit address space." + bool default n select RELOCATABLE_MODULES help diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig index af73a58..2750459 100644 --- a/src/arch/x86/Kconfig +++ b/src/arch/x86/Kconfig @@ -82,10 +82,6 @@ config SIPI_VECTOR_IN_ROM config RAMBASE hex default 0x100000 - -config RAMTOP - hex - default 0x200000 depends on ARCH_X86 # Traditionally BIOS region on SPI flash boot media was memory mapped right below diff --git a/src/arch/x86/include/arch/memlayout.h b/src/arch/x86/include/arch/memlayout.h index 5f5cba6..840ceb0 100644 --- a/src/arch/x86/include/arch/memlayout.h +++ b/src/arch/x86/include/arch/memlayout.h @@ -24,8 +24,4 @@ #define ARCH_STAGE_HAS_BSS_SECTION 0 #endif -#if !defined(CONFIG_RAMTOP) || !CONFIG_RAMTOP -# error "CONFIG_RAMTOP not configured" -#endif - #endif /* __ARCH_MEMLAYOUT_H */ diff --git a/src/arch/x86/memlayout.ld b/src/arch/x86/memlayout.ld index e6db0b8..a007272 100644 --- a/src/arch/x86/memlayout.ld +++ b/src/arch/x86/memlayout.ld @@ -26,7 +26,7 @@ SECTIONS * conditionalize with macros. */ #if ENV_RAMSTAGE - RAMSTAGE(CONFIG_RAMBASE, CONFIG_RAMTOP - CONFIG_RAMBASE) + RAMSTAGE(CONFIG_RAMBASE, 8M) #elif ENV_ROMSTAGE /* The 1M size is not allocated. It's just for basic size checking. diff --git a/src/northbridge/amd/agesa/Kconfig b/src/northbridge/amd/agesa/Kconfig index d5cff80..37bf3c4 100644 --- a/src/northbridge/amd/agesa/Kconfig +++ b/src/northbridge/amd/agesa/Kconfig @@ -35,8 +35,4 @@ config HEAP_SIZE hex default 0xc0000 -config RAMTOP - hex - default 0x400000 - endif # NORTHBRIDGE_AMD_AGESA diff --git a/src/northbridge/amd/pi/Kconfig b/src/northbridge/amd/pi/Kconfig index cb72416..eea2897 100644 --- a/src/northbridge/amd/pi/Kconfig +++ b/src/northbridge/amd/pi/Kconfig @@ -40,10 +40,6 @@ config HW_MEM_HOLE_SIZE_AUTO_INC bool default n -config RAMTOP - hex - default 0x1000000 - config HEAP_SIZE hex default 0xc0000

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Patch set updated for coreboot: AMD k8 fam10: Use common ACPI S3 recovery
by Kyösti Mälkki 29 Jun '16

29 Jun '16

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15474 -gerrit commit dcfd9ecb4d10ce634debe42b6c9c502a2b363a9b Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Mon Jun 27 12:53:00 2016 +0300 AMD k8 fam10: Use common ACPI S3 recovery Change-Id: I62bbba8cfe515b3cae413582ff8d062a20e6741b Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/cpu/amd/car/post_cache_as_ram.c | 43 +++++++------------------------ src/cpu/amd/family_10h-family_15h/Kconfig | 1 - src/cpu/amd/model_fxx/Kconfig | 1 - 3 files changed, 9 insertions(+), 36 deletions(-) diff --git a/src/cpu/amd/car/post_cache_as_ram.c b/src/cpu/amd/car/post_cache_as_ram.c index ff094ee..86076b7 100644 --- a/src/cpu/amd/car/post_cache_as_ram.c +++ b/src/cpu/amd/car/post_cache_as_ram.c @@ -45,12 +45,6 @@ static void memcpy_(void *d, const void *s, size_t len) memcpy(d, s, len); } -static void memset_(void *d, int val, size_t len) -{ - print_car_debug(" Fill [%08x-%08x] ...", (uint32_t) d, (uint32_t) (d + len - 1)); - memset(d, val, len); -} - static int memcmp_(void *d, const void *s, size_t len) { print_car_debug(" Compare [%08x-%08x] with [%08x - %08x] ...", @@ -58,33 +52,6 @@ static int memcmp_(void *d, const void *s, size_t len) return memcmp(d, s, len); } -static void prepare_ramstage_region(int s3resume) -{ - print_car_debug("Prepare ramstage memory region..."); - - if (s3resume) { - void *resume_backup_memory = acpi_backup_container(CONFIG_RAMBASE, HIGH_MEMORY_SAVE); - if (resume_backup_memory) - memcpy_(resume_backup_memory, (void *) CONFIG_RAMBASE, - HIGH_MEMORY_SAVE); - memset_((void*) CONFIG_RAMBASE, 0, HIGH_MEMORY_SAVE); - } else { - memset_((void*)0, 0, CONFIG_RAMTOP); - } - -#if IS_ENABLED(CONFIG_HAVE_ROMSTAGE_CONSOLE_SPINLOCK) - initialize_romstage_console_lock(); -#endif -#if IS_ENABLED(CONFIG_HAVE_ROMSTAGE_NVRAM_CBFS_SPINLOCK) - initialize_romstage_nvram_cbfs_lock(); -#endif - - print_car_debug(" Done\n"); - - if (s3resume) - acpi_backup_validate(); -} - /* Disable Erratum 343 Workaround, see RevGuide for Fam10h, Pub#41322 Rev 3.33 * and RevGuide for Fam12h, Pub#44739 Rev 3.10 */ @@ -168,7 +135,15 @@ void cache_as_ram_new_stack (void) set_var_mtrr(0, 0x00000000, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK); enable_cache(); - prepare_ramstage_region(acpi_is_wakeup_s3()); + if (acpi_is_wakeup_s3()) + acpi_prepare_for_resume(); + +#if IS_ENABLED(CONFIG_HAVE_ROMSTAGE_CONSOLE_SPINLOCK) + initialize_romstage_console_lock(); +#endif +#if IS_ENABLED(CONFIG_HAVE_ROMSTAGE_NVRAM_CBFS_SPINLOCK) + initialize_romstage_nvram_cbfs_lock(); +#endif set_sysinfo_in_ram(1); // So other core0 could start to train mem diff --git a/src/cpu/amd/family_10h-family_15h/Kconfig b/src/cpu/amd/family_10h-family_15h/Kconfig index 30c7dee..fda7fc8 100644 --- a/src/cpu/amd/family_10h-family_15h/Kconfig +++ b/src/cpu/amd/family_10h-family_15h/Kconfig @@ -10,7 +10,6 @@ config CPU_AMD_MODEL_10XXX select TSC_SYNC_LFENCE select UDELAY_LAPIC select HAVE_MONOTONIC_TIMER - select ACPI_HUGE_LOWMEM_BACKUP select SUPPORT_CPU_UCODE_IN_CBFS select CPU_MICROCODE_MULTIPLE_FILES if !CPU_MICROCODE_CBFS_NONE diff --git a/src/cpu/amd/model_fxx/Kconfig b/src/cpu/amd/model_fxx/Kconfig index 3eb5b94..c8bae33 100644 --- a/src/cpu/amd/model_fxx/Kconfig +++ b/src/cpu/amd/model_fxx/Kconfig @@ -9,7 +9,6 @@ config CPU_AMD_MODEL_FXX select SSE2 select TSC_SYNC_LFENCE select UDELAY_LAPIC - select ACPI_HUGE_LOWMEM_BACKUP select SUPPORT_CPU_UCODE_IN_CBFS if CPU_AMD_MODEL_FXX

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Patch set updated for coreboot: AMD k8 fam10: Separate romstage ramstack (WIP)
by Kyösti Mälkki 29 Jun '16

29 Jun '16

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15473 -gerrit commit c5d35028a499c77f311f2d8f7eff9ffd4eebe4f4 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Mon Jun 27 19:45:19 2016 +0300 AMD k8 fam10: Separate romstage ramstack (WIP) Romstage ram stack was placed below RAMTOP. This is vulnerable location as a large ramstage could overwrite it. Location also prevents optimizing S3 resume path since all low memory between RAMBASE..RAMTOP has to be backed to CBMEM. When possible, place ram stack high. Change-Id: I4106e91ed3256aca5d0d115d4aa7e46b75b27eec Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/cpu/amd/car/post_cache_as_ram.c | 39 +++++++++++-------------------------- 1 file changed, 11 insertions(+), 28 deletions(-) diff --git a/src/cpu/amd/car/post_cache_as_ram.c b/src/cpu/amd/car/post_cache_as_ram.c index 1951084..ff094ee 100644 --- a/src/cpu/amd/car/post_cache_as_ram.c +++ b/src/cpu/amd/car/post_cache_as_ram.c @@ -23,6 +23,7 @@ #include <cpu/amd/mtrr.h> #include <cpu/amd/car.h> #include <arch/acpi.h> +#include <program_loading.h> #include <romstage_handoff.h> #include "cbmem.h" #include "cpu/amd/car/disable_cache_as_ram.c" @@ -37,12 +38,6 @@ #define print_car_debug(format, arg...) #endif -static size_t backup_size(void) -{ - size_t car_size = car_data_size(); - return ALIGN(car_size + 1024, 1024); -} - static void memcpy_(void *d, const void *s, size_t len) { print_car_debug(" Copy [%08x-%08x] to [%08x - %08x] ...", @@ -63,35 +58,18 @@ static int memcmp_(void *d, const void *s, size_t len) return memcmp(d, s, len); } -static void prepare_romstage_ramstack(int s3resume) -{ - size_t backup_top = backup_size(); - print_car_debug("Prepare CAR migration and stack regions..."); - - if (s3resume) { - void *resume_backup_memory = acpi_backup_container(CONFIG_RAMBASE, HIGH_MEMORY_SAVE); - if (resume_backup_memory) - memcpy_(resume_backup_memory + HIGH_MEMORY_SAVE - backup_top, - (void *)(CONFIG_RAMTOP - backup_top), backup_top); - } - memset_((void *)(CONFIG_RAMTOP - backup_top), 0, backup_top); - - print_car_debug(" Done\n"); -} - static void prepare_ramstage_region(int s3resume) { - size_t backup_top = backup_size(); print_car_debug("Prepare ramstage memory region..."); if (s3resume) { void *resume_backup_memory = acpi_backup_container(CONFIG_RAMBASE, HIGH_MEMORY_SAVE); if (resume_backup_memory) memcpy_(resume_backup_memory, (void *) CONFIG_RAMBASE, - HIGH_MEMORY_SAVE - backup_top); - memset_((void*) CONFIG_RAMBASE, 0, HIGH_MEMORY_SAVE - backup_top); + HIGH_MEMORY_SAVE); + memset_((void*) CONFIG_RAMBASE, 0, HIGH_MEMORY_SAVE); } else { - memset_((void*)0, 0, CONFIG_RAMTOP - backup_top); + memset_((void*)0, 0, CONFIG_RAMTOP); } #if IS_ENABLED(CONFIG_HAVE_ROMSTAGE_CONSOLE_SPINLOCK) @@ -121,6 +99,8 @@ static void vErrata343(void) wrmsr(BU_CFG2_MSR, msr); } +#define ROMSTAGE_RAM_STACK_SIZE 0x5000 + void post_cache_as_ram(void) { uint32_t family = amd_fam1x_cpu_family(); @@ -138,7 +118,10 @@ void post_cache_as_ram(void) if (IS_ENABLED(CONFIG_EARLY_CBMEM_INIT) || s3resume) cbmem_recovery(s3resume); - prepare_romstage_ramstack(s3resume); + /* FIXME: CBMEM stack is not wb-cacheable yet. */ + uintptr_t ramtop = romstage_ram_stack_source(ROMSTAGE_RAM_STACK_SIZE, + s3resume ? ROMSTAGE_STACK_CBMEM : ROMSTAGE_STACK_LOW_MEM); + ramtop += ROMSTAGE_RAM_STACK_SIZE; if (IS_ENABLED(CONFIG_EARLY_CBMEM_INIT)) { struct romstage_handoff *handoff; @@ -156,7 +139,7 @@ void post_cache_as_ram(void) } size_t car_size = car_data_size(); - void *migrated_car = (void *)(CONFIG_RAMTOP - car_size); + void *migrated_car = (void *)(ramtop - car_size); print_car_debug("Copying data from cache to RAM..."); memcpy_(migrated_car, _car_relocatable_data_start, car_size);

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coreboot-gerrit June 2016