coreboot-gerrit June 2016

coreboot-gerrit@coreboot.org

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1491 discussions

Patch set updated for coreboot: vbnv: Do not initialize vbnv_copy in vbnv layer
by Furquan Shaikh 30 Jun '16

30 Jun '16

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15498 -gerrit commit db5d309a1032366e870c684af6016f7e851b5f4c Author: Furquan Shaikh <furquan(a)google.com> Date: Wed Jun 29 11:26:27 2016 -0700 vbnv: Do not initialize vbnv_copy in vbnv layer If read_vbnv finds that the vbnv_copy is not valid, it initializes it with the correct HEADER_SIGNATURE and other attributes. However, the vbnv copy is checked for validity and initialized at the vboot layer as well. Since, vboot is the owner of this data, it should be the one initializing it. Thus, if read_vbnv sees that the data is not valid, simply reset it to all 0s and let vboot layer take care of it. This also removes the need for additional checks to ensure that the dirty vbnv copy is properly updated on storage. Change-Id: I6101ac41f31f720a6e357c9c56e571d62e0f2f47 Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- src/vendorcode/google/chromeos/vbnv.c | 15 +++------------ src/vendorcode/google/chromeos/vbnv.h | 7 +------ src/vendorcode/google/chromeos/vboot2/vboot_logic.c | 8 ++------ 3 files changed, 6 insertions(+), 24 deletions(-) diff --git a/src/vendorcode/google/chromeos/vbnv.c b/src/vendorcode/google/chromeos/vbnv.c index baccb23..9fd97a0 100644 --- a/src/vendorcode/google/chromeos/vbnv.c +++ b/src/vendorcode/google/chromeos/vbnv.c @@ -59,14 +59,9 @@ static uint8_t crc8_vbnv(const uint8_t *data, int len) return (uint8_t) (crc >> 8); } -/* Reset header and CRC to defaults. */ static void reset_vbnv(uint8_t *vbnv_copy) { memset(vbnv_copy, 0, VBNV_BLOCK_SIZE); - vbnv_copy[HEADER_OFFSET] = HEADER_SIGNATURE | - HEADER_FIRMWARE_SETTINGS_RESET | - HEADER_KERNEL_SETTINGS_RESET; - vbnv_copy[CRC_OFFSET] = crc8_vbnv(vbnv_copy, CRC_OFFSET); } /* Read VBNV data into cache. */ @@ -88,9 +83,8 @@ int verify_vbnv(uint8_t *vbnv_copy) /* * Read VBNV data from configured storage backend. * If VBNV verification fails, reset the vbnv copy. - * Returns 1 if write-back of vbnv copy is required. Else, returns 0. */ -int read_vbnv(uint8_t *vbnv_copy) +void read_vbnv(uint8_t *vbnv_copy) { if (IS_ENABLED(CONFIG_CHROMEOS_VBNV_CMOS)) read_vbnv_cmos(vbnv_copy); @@ -100,11 +94,8 @@ int read_vbnv(uint8_t *vbnv_copy) read_vbnv_flash(vbnv_copy); /* Check data for consistency */ - if (verify_vbnv(vbnv_copy)) - return 0; - - reset_vbnv(vbnv_copy); - return 1; + if (!verify_vbnv(vbnv_copy)) + reset_vbnv(vbnv_copy); } /* diff --git a/src/vendorcode/google/chromeos/vbnv.h b/src/vendorcode/google/chromeos/vbnv.h index a66d687..5d21cc8 100644 --- a/src/vendorcode/google/chromeos/vbnv.h +++ b/src/vendorcode/google/chromeos/vbnv.h @@ -19,12 +19,7 @@ #include <types.h> /* Generic functions */ -/* - * Return value for read_vbnv: - * 1 = write-back of vbnv copy is required. - * 0 = otherwise - */ -int read_vbnv(uint8_t *vbnv_copy); +void read_vbnv(uint8_t *vbnv_copy); void save_vbnv(const uint8_t *vbnv_copy); int verify_vbnv(uint8_t *vbnv_copy); int get_recovery_mode_from_vbnv(void); diff --git a/src/vendorcode/google/chromeos/vboot2/vboot_logic.c b/src/vendorcode/google/chromeos/vboot2/vboot_logic.c index 116c949..4c799c9 100644 --- a/src/vendorcode/google/chromeos/vboot2/vboot_logic.c +++ b/src/vendorcode/google/chromeos/vboot2/vboot_logic.c @@ -301,12 +301,8 @@ void verstage_main(void) /* Set up context and work buffer */ vb2_init_work_context(&ctx); - /* - * Read nvdata from a non-volatile storage and mark data as changed - * if instructed. - */ - if (read_vbnv(ctx.nvdata)) - ctx.flags |= VB2_CONTEXT_NVDATA_CHANGED; + /* Read nvdata from a non-volatile storage. */ + read_vbnv(ctx.nvdata); /* Set S3 resume flag if vboot should behave differently when selecting * which slot to boot. This is only relevant to vboot if the platform

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New patch to review for coreboot: [WIP] spike-riscv: Register RAM resource at 0x80000000
by Jonathan Neuschäfer 30 Jun '16

30 Jun '16

Jonathan Neuschäfer (j.neuschaefer(a)gmx.net) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15511 -gerrit commit 133d824e3f523cd68bcb630117a53de8a61f673d Author: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Date: Wed Jun 29 21:59:32 2016 +0200 [WIP] spike-riscv: Register RAM resource at 0x80000000 Without this patch, the CBFS loader won't load segments into the RAM. Change-Id: If05c8edb51f9fe2f7af84178826f93b193cfd8a9 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> --- src/mainboard/emulation/spike-riscv/mainboard.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/src/mainboard/emulation/spike-riscv/mainboard.c b/src/mainboard/emulation/spike-riscv/mainboard.c index 111e9b1..5a481f3 100644 --- a/src/mainboard/emulation/spike-riscv/mainboard.c +++ b/src/mainboard/emulation/spike-riscv/mainboard.c @@ -19,13 +19,22 @@ static void mainboard_enable(device_t dev) { + /* + * Size of the emulated system RAM. On hardware, this would be external + * DDR memory. + * + * TODO: Get this size from the hardware-supplied configuration string. + */ + const size_t ram_size = 1*GiB; if (!dev) { printk(BIOS_EMERG, "No dev0; die\n"); while (1); } - ram_resource(dev, 0, 2048, 32768); + /* TODO: move to src/arch/riscv? */ + ram_resource(dev, 0, 0x80000000/KiB, ram_size/KiB); + cbmem_recovery(0); }

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New patch to review for coreboot: [WIP] arch/riscv: Make SBI support optional
by Jonathan Neuschäfer 30 Jun '16

30 Jun '16

Jonathan Neuschäfer (j.neuschaefer(a)gmx.net) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15510 -gerrit commit 757eb21bfb5850a536f3dce201fe5917cd622c7e Author: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Date: Thu Jun 30 04:05:08 2016 +0200 [WIP] arch/riscv: Make SBI support optional I'm posting this patch early so I can link to it from the wiki. Change-Id: I5cbfc90afd3febab33835935f08005136a3f47e9 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> --- src/arch/riscv/boot.c | 4 ++++ src/arch/riscv/virtual_memory.c | 1 + 2 files changed, 5 insertions(+) diff --git a/src/arch/riscv/boot.c b/src/arch/riscv/boot.c index 96526bf..e2d7d14 100644 --- a/src/arch/riscv/boot.c +++ b/src/arch/riscv/boot.c @@ -22,6 +22,7 @@ void arch_prog_run(struct prog *prog) { void (*doit)(void *) = prog_entry(prog); +#if IS_ENABLED(CONFIG_RISCV_SBI) if (ENV_RAMSTAGE && prog_type(prog) == PROG_PAYLOAD) { initVirtualMemory(); write_csr(mepc, doit); @@ -29,6 +30,9 @@ void arch_prog_run(struct prog *prog) } else { doit(prog_entry_arg(prog)); } +#else + doit(prog_entry_arg(prog)); +#endif } int arch_supports_bounce_buffer(void) diff --git a/src/arch/riscv/virtual_memory.c b/src/arch/riscv/virtual_memory.c index 64ea2b1..dce0887 100644 --- a/src/arch/riscv/virtual_memory.c +++ b/src/arch/riscv/virtual_memory.c @@ -101,6 +101,7 @@ void init_vm(uintptr_t virtMemStart, uintptr_t physMemStart, uintptr_t pageTable void initVirtualMemory(void) { printk(BIOS_DEBUG, "Initializing virtual memory...\n"); + return; uintptr_t physicalStart = 0x1000000; // TODO: Figure out how to grab this from cbfs uintptr_t virtualStart = 0xffffffff81000000; uintptr_t pageTableStart = 0x1400000;

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Patch set updated for coreboot: mainboard/intel/amenia: add NHLT support
by Aaron Durbin 30 Jun '16

30 Jun '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15024 -gerrit commit 9a21c39bbf9a5048185d8d33941af1ff00b064c4 Author: Saurabh Satija <saurabh.satija(a)intel.com> Date: Thu May 26 16:08:45 2016 -0700 mainboard/intel/amenia: add NHLT support Add ACPI NHLT table generation that the current hardware supports as well select the hardware used on the board. Amenia has support for two audio codecs, Dialog for headsets and Maxim for speakers. Change-Id: Iaba9ec81ffb4f128f2e4413dec5174d9ecb856c9 Signed-off-by: Saurabh Satija <saurabh.satija(a)intel.com> --- src/mainboard/intel/amenia/Kconfig | 6 +++++ src/mainboard/intel/amenia/dsdt.asl | 11 ++++---- src/mainboard/intel/amenia/mainboard.c | 48 ++++++++++++++++++++++++++++++++-- 3 files changed, 58 insertions(+), 7 deletions(-) diff --git a/src/mainboard/intel/amenia/Kconfig b/src/mainboard/intel/amenia/Kconfig index 6fc5e35..b3ef17b 100644 --- a/src/mainboard/intel/amenia/Kconfig +++ b/src/mainboard/intel/amenia/Kconfig @@ -44,4 +44,10 @@ config MAX_CPUS int default 8 +config INCLUDE_NHLT_BLOBS + bool "Include blobs for audio." + select NHLT_DMIC_2CH_16B + select NHLT_DA7219 + select NHLT_MAX98357 + endif # BOARD_INTEL_AMENIA diff --git a/src/mainboard/intel/amenia/dsdt.asl b/src/mainboard/intel/amenia/dsdt.asl index 4a64f87..46404ed 100644 --- a/src/mainboard/intel/amenia/dsdt.asl +++ b/src/mainboard/intel/amenia/dsdt.asl @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Intel Corp. + * Copyright (C) 2016 Intel Corp. * (Written by Lance Zhao <lijian.zhao(a)intel.com> for Intel Corp.) * * This program is free software; you can redistribute it and/or modify @@ -33,15 +33,16 @@ DefinitionBlock( Scope (\_SB) { Device (PCI0) { - #include <soc/intel/apollolake/acpi/northbridge.asl> - #include <soc/intel/apollolake/acpi/southbridge.asl> + #include <soc/intel/apollolake/acpi/northbridge.asl> + #include <soc/intel/apollolake/acpi/southbridge.asl> + #include <soc/intel/apollolake/acpi/pch_hda.asl> } } /* Mainboard Specific devices */ #include "acpi/mainboard.asl" - /* Chipset specific sleep states */ - #include <soc/intel/apollolake/acpi/sleepstates.asl> + /* Chipset specific sleep states */ + #include <soc/intel/apollolake/acpi/sleepstates.asl> #include "acpi/superio.asl" } diff --git a/src/mainboard/intel/amenia/mainboard.c b/src/mainboard/intel/amenia/mainboard.c index 8d10b28..6ec5b98 100644 --- a/src/mainboard/intel/amenia/mainboard.c +++ b/src/mainboard/intel/amenia/mainboard.c @@ -15,9 +15,10 @@ * GNU General Public License for more details. */ +#include <arch/acpi.h> +#include <console/console.h> #include <device/device.h> -#include <soc/gpio.h> -#include <soc/pci_devs.h> +#include <soc/nhlt.h> #include "ec.h" #include "gpio.h" @@ -27,6 +28,49 @@ static void mainboard_init(void *chip_info) mainboard_ec_init(); } +static unsigned long mainboard_write_acpi_tables( + device_t device, unsigned long current, acpi_rsdp_t *rsdp) +{ + uintptr_t start_addr; + uintptr_t end_addr; + struct nhlt *nhlt; + + start_addr = current; + + nhlt = nhlt_init(); + + if (nhlt == NULL) + return start_addr; + + /* 2 Channel DMIC array. */ + if (!nhlt_soc_add_dmic_array(nhlt, 2)) + printk(BIOS_ERR, "Added 2CH DMIC array.\n"); + + /* Dialog for Headset codec. + * Headset codec is bi-directional but uses the same configuration + * settings for render and capture endpoints. + */ + if (!nhlt_soc_add_da7219(nhlt, AUDIO_LINK_SSP1)) + printk(BIOS_ERR, "Added Dialog_7219 codec.\n"); + + /* MAXIM Smart Amps for left and right speakers. */ + if (!nhlt_soc_add_max98357(nhlt, AUDIO_LINK_SSP5)) + printk(BIOS_ERR, "Added Maxim_98357 codec.\n"); + + end_addr = nhlt_soc_serialize(nhlt, start_addr); + + if (end_addr != start_addr) + acpi_add_table(rsdp, (void *)start_addr); + + return end_addr; +} + +static void mainboard_enable(device_t dev) +{ + dev->ops->write_acpi_tables = mainboard_write_acpi_tables; +} + struct chip_operations mainboard_ops = { .init = mainboard_init, + .enable_dev = mainboard_enable, };

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Patch set updated for coreboot: soc/intel/apollolake: add initial NHLT support
by Aaron Durbin 30 Jun '16

30 Jun '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15504 -gerrit commit 7a02f6b50e5941ebe802233f1dd1e9e46304b314 Author: Saurabh Satija <saurabh.satija(a)intel.com> Date: Tue Jun 21 14:22:16 2016 -0700 soc/intel/apollolake: add initial NHLT support Provide the initial NHLT support for the following hardware: 1. 2 channel digital microphone array 2. da7219 headset 3. max98357 speaker amplifiers. The code utilizes the Intel SoC common NHLT support. Change-Id: Ic31e834a08f29c66512a7a63ad7bb35e0374e86a Signed-off-by: Saurabh Satija <saurabh.satija(a)intel.com> Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/soc/intel/apollolake/Kconfig | 24 +++++ src/soc/intel/apollolake/Makefile.inc | 19 ++++ src/soc/intel/apollolake/include/soc/nhlt.h | 43 +++++++++ src/soc/intel/apollolake/nhlt.c | 142 ++++++++++++++++++++++++++++ 4 files changed, 228 insertions(+) diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index 98ce7d8..8e33015 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -17,6 +17,9 @@ config CPU_SPECIFIC_OPTIONS select SMP select SSE2 select SUPPORT_CPU_UCODE_IN_CBFS + # Audio options + select ACPI_NHLT + select SOC_INTEL_COMMON_NHLT # Misc options select C_ENVIRONMENT_BOOTBLOCK select COLLECT_TIMESTAMPS @@ -182,4 +185,25 @@ config IFWI_FILE_NAME help Name of file to store in the IFWI region. +config NHLT_DMIC_2CH_16B + bool + depends on ACPI_NHLT + default n + help + Include DSP firmware settings for 2 channel 16B DMIC array. + +config NHLT_MAX98357 + bool + depends on ACPI_NHLT + default n + help + Include DSP firmware settings for headset codec. + +config NHLT_DA7219 + bool + depends on ACPI_NHLT + default n + help + Include DSP firmware settings for headset codec. + endif diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index 7326f14..030e35c 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -51,6 +51,7 @@ ramstage-y += lpc_lib.c ramstage-y += memmap.c ramstage-y += mmap_boot.c ramstage-y += uart.c +ramstage-y += nhlt.c ramstage-y += northbridge.c ramstage-y += spi.c ramstage-y += tsc_freq.c @@ -104,4 +105,22 @@ files_added:: $(IFWITOOL) $(CBFSTOOL) $(obj)/coreboot.rom write -r $(CONFIG_IFWI_FMAP_NAME) -f $(objcbfs)/ifwi.bin.tmp --fill-upward endif +# DSP firmware settings files. +NHLT_BLOB_PATH = 3rdparty/blobs/soc/intel/apollolake/nhlt-blobs +DMIC_2CH_48KHZ_16B = dmic-2ch-48khz-16b.bin +MAX98357_RENDER = max98357-render-2ch-48khz-24b.bin +DA7219_RENDER_CAPTURE = dialog-2ch-48khz-24b.bin + +cbfs-files-$(CONFIG_NHLT_DMIC_2CH) += $(DMIC_2CH_48KHZ_16B) +$(DMIC_2CH_48KHZ_16B)-file := $(NHLT_BLOB_PATH)/$(DMIC_2CH_48KHZ_16B) +$(DMIC_2CH_48KHZ_16B)-type := raw + +cbfs-files-$(CONFIG_NHLT_MAX98357) += $(MAX98357_RENDER) +$(MAX98357_RENDER)-file := $(NHLT_BLOB_PATH)/$(MAX98357_RENDER) +$(MAX98357_RENDER)-type := raw + +cbfs-files-$(CONFIG_NHLT_DA7219) += $(DA7219_RENDER_CAPTURE) +$(DA7219_RENDER_CAPTURE)-file := $(NHLT_BLOB_PATH)/$(DA7219_RENDER_CAPTURE) +$(DA7219_RENDER_CAPTURE)-type := raw + endif diff --git a/src/soc/intel/apollolake/include/soc/nhlt.h b/src/soc/intel/apollolake/include/soc/nhlt.h new file mode 100644 index 0000000..d49b8cf --- /dev/null +++ b/src/soc/intel/apollolake/include/soc/nhlt.h @@ -0,0 +1,43 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_APOLLOLAKE_NHLT_H_ +#define _SOC_APOLLOLAKE_NHLT_H_ + +#include <nhlt.h> + +#define NHLT_VID 0x8086 +#define NHLT_DID_DMIC 0xae20 +#define NHLT_DID_BT 0xae30 +#define NHLT_DID_SSP 0xae34 + +/* The following link values should be used for the hwlink parameters below. */ +enum { + AUDIO_LINK_SSP0, + AUDIO_LINK_SSP1, + AUDIO_LINK_SSP2, + AUDIO_LINK_SSP3, + AUDIO_LINK_SSP4, + AUDIO_LINK_SSP5, + AUDIO_LINK_DMIC, +}; + +/* Returns < 0 on error, 0 on success. */ +int nhlt_soc_add_dmic_array(struct nhlt *nhlt, int num_channels); +int nhlt_soc_add_max98357(struct nhlt *nhlt, int hwlink); +int nhlt_soc_add_da7219(struct nhlt *nhlt, int hwlink); + +#endif diff --git a/src/soc/intel/apollolake/nhlt.c b/src/soc/intel/apollolake/nhlt.c new file mode 100644 index 0000000..3670a13 --- /dev/null +++ b/src/soc/intel/apollolake/nhlt.c @@ -0,0 +1,142 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <nhlt.h> +#include <soc/nhlt.h> + +static const struct nhlt_format_config dmic_2ch_formats[] = { + /* 48 KHz 16-bits per sample. */ + { + .num_channels = 2, + .sample_freq_khz = 48, + .container_bits_per_sample = 16, + .valid_bits_per_sample = 16, + .settings_file = "dmic-2ch-48khz-16b.bin", + }, +}; + +static const struct nhlt_dmic_array_config dmic_2ch_mic_config = { + .tdm_config = { + .config_type = NHLT_TDM_MIC_ARRAY, + }, + .array_type = NHLT_MIC_ARRAY_2CH_SMALL, +}; + +static const struct nhlt_endp_descriptor dmic_2ch_descriptors[] = { + { + .link = NHLT_LINK_PDM, + .device = NHLT_PDM_DEV, + .direction = NHLT_DIR_CAPTURE, + .vid = NHLT_VID, + .did = NHLT_DID_DMIC, + .cfg = &dmic_2ch_mic_config, + .cfg_size = sizeof(dmic_2ch_mic_config), + .formats = dmic_2ch_formats, + .num_formats = ARRAY_SIZE(dmic_2ch_formats), + }, +}; + +static const struct nhlt_format_config da7219_formats[] = { + /* 48 KHz 24-bits per sample. */ + { + .num_channels = 2, + .sample_freq_khz = 48, + .container_bits_per_sample = 32, + .valid_bits_per_sample = 24, + .settings_file = "dialog-2ch-48khz-24b.bin", + }, +}; + +static const struct nhlt_tdm_config tdm_config = { + .virtual_slot = 0, + .config_type = NHLT_TDM_BASIC, +}; + +static const struct nhlt_endp_descriptor da7219_descriptors[] = { + /* Render Endpoint */ + { + .link = NHLT_LINK_SSP, + .device = NHLT_SSP_DEV_I2S, + .direction = NHLT_DIR_RENDER, + .vid = NHLT_VID, + .did = NHLT_DID_SSP, + .cfg = &tdm_config, + .cfg_size = sizeof(tdm_config), + .formats = da7219_formats, + .num_formats = ARRAY_SIZE(da7219_formats), + }, + /* Capture Endpoint */ + { + .link = NHLT_LINK_SSP, + .device = NHLT_SSP_DEV_I2S, + .direction = NHLT_DIR_CAPTURE, + .vid = NHLT_VID, + .did = NHLT_DID_SSP, + .cfg = &tdm_config, + .cfg_size = sizeof(tdm_config), + .formats = da7219_formats, + .num_formats = ARRAY_SIZE(da7219_formats), + }, +}; + +static const struct nhlt_format_config max98357_formats[] = { + /* 48 KHz 24-bits per sample. */ + { + .num_channels = 2, + .sample_freq_khz = 48, + .container_bits_per_sample = 32, + .valid_bits_per_sample = 24, + .settings_file = "max98357-render-2ch-48khz-24b.bin", + }, +}; + +static const struct nhlt_endp_descriptor max98357_descriptors[] = { + { + .link = NHLT_LINK_SSP, + .device = NHLT_SSP_DEV_I2S, + .direction = NHLT_DIR_RENDER, + .vid = NHLT_VID, + .did = NHLT_DID_SSP, + .formats = max98357_formats, + .num_formats = ARRAY_SIZE(max98357_formats), + }, +}; + +int nhlt_soc_add_dmic_array(struct nhlt *nhlt, int num_channels) +{ + if (num_channels != 2) { + printk(BIOS_ERR, "APL only supports 2CH DMIC array.\n"); + return -1; + } + + return nhlt_add_endpoints(nhlt, dmic_2ch_descriptors, + ARRAY_SIZE(dmic_2ch_descriptors)); +} + +int nhlt_soc_add_da7219(struct nhlt *nhlt, int hwlink) +{ + /* Virtual bus id of SSP links are the hardware port ids proper. */ + return nhlt_add_ssp_endpoints(nhlt, hwlink, da7219_descriptors, + ARRAY_SIZE(da7219_descriptors)); +} + +int nhlt_soc_add_max98357(struct nhlt *nhlt, int hwlink) +{ + /* Virtual bus id of SSP links are the hardware port ids proper. */ + return nhlt_add_ssp_endpoints(nhlt, hwlink, max98357_descriptors, + ARRAY_SIZE(max98357_descriptors)); +}

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New patch to review for coreboot: marvell/mvmap2315: add BootROM driver
by hakim giydan 30 Jun '16

30 Jun '16

hakim giydan (hgiydan(a)marvell.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15509 -gerrit commit 380bc6655255277a15fb4de50c445c93e6a27e18 Author: Hakim Giydan <hgiydan(a)marvell.com> Date: Wed Jun 29 18:53:06 2016 -0700 marvell/mvmap2315: add BootROM driver this driver is SD & EMMC driver using BootROM callback. we are using BootROM callbacks to save LCM memory space and reduce romstage size. Change-Id: Iaeff9f01dbfad7f313aa237e8c71c36c4ed1e06f Signed-off-by: Hakim Giydan <hgiydan(a)marvell.com> --- src/soc/marvell/mvmap2315/Makefile.inc | 2 + src/soc/marvell/mvmap2315/bootrom.c | 188 ++++++++++ src/soc/marvell/mvmap2315/gic.c | 19 +- src/soc/marvell/mvmap2315/include/soc/addressmap.h | 14 +- src/soc/marvell/mvmap2315/include/soc/bdb.h | 245 ++++++++++++ src/soc/marvell/mvmap2315/include/soc/bootrom.h | 125 +++++++ src/soc/marvell/mvmap2315/include/soc/clock.h | 5 +- src/soc/marvell/mvmap2315/include/soc/gic.h | 412 +++++++++++++++++++++ src/soc/marvell/mvmap2315/romstage.c | 13 + 9 files changed, 1017 insertions(+), 6 deletions(-) diff --git a/src/soc/marvell/mvmap2315/Makefile.inc b/src/soc/marvell/mvmap2315/Makefile.inc index 994c745..ebb0515 100644 --- a/src/soc/marvell/mvmap2315/Makefile.inc +++ b/src/soc/marvell/mvmap2315/Makefile.inc @@ -27,8 +27,10 @@ ramstage-y += stage_entry.S ramstage-y += uart.c romstage-y += assert.c +romstage-y += bootrom.c romstage-y += cbmem.c romstage-y += clock.c +romstage-y += gic.c romstage-y += media.c romstage-y += monotonic_timer.c romstage-y += pinconfig.c diff --git a/src/soc/marvell/mvmap2315/bootrom.c b/src/soc/marvell/mvmap2315/bootrom.c new file mode 100644 index 0000000..3873051 --- /dev/null +++ b/src/soc/marvell/mvmap2315/bootrom.c @@ -0,0 +1,188 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Marvell, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <console/console.h> +#include <soc/addressmap.h> +#include <soc/bdb.h> +#include <soc/bootrom.h> +#include <soc/clock.h> +#include <reset.h> +#include <string.h> + +struct bootrom_ops bootrom_callbacks = { + .security_init = (security_init_F) MVMAP2315_BM_CB_SECURITY_INIT, + .sha_msg_digest = (sha_msg_digest_F) MVMAP2315_BM_CB_SHA_MSG_DIGEST, + .media_init = (media_init_F) MVMAP2315_BM_CB_MEDIA_INIT, + .media_read = (media_read_F) MVMAP2315_BM_CB_MEDIA_READ, + .media_write = (media_write_F) MVMAP2315_BM_CB_MEDIA_WRITE, + .media_shutdown = (media_shutdown_F) MVMAP2315_BM_CB_MEDIA_SHUTDOWN, +}; + +void set_bdb_pointers(u8 *start_addr, struct bdb_pointer *bdb_in) +{ + bdb_in->bdb_h + = (struct bdb_header *)start_addr; + + bdb_in->bdb_k + = (struct bdb_key *)(start_addr + + (bdb_in->bdb_h->struct_size)); + + bdb_in->bdb_oem_0 + = (u8 *)((u32)(bdb_in->bdb_k) + + (bdb_in->bdb_k->struct_size)); + + bdb_in->sub_k + = (struct bdb_key *)((u32)(bdb_in->bdb_oem_0) + + (bdb_in->bdb_h->oem_area_0_size)); + + bdb_in->bdb_h_s + = (struct bdb_sig *)((u32)(bdb_in->bdb_oem_0) + + (bdb_in->bdb_h->signed_size)); + + bdb_in->bdb_d + = (struct bdb_data *)((u32)(bdb_in->bdb_h_s) + + (bdb_in->bdb_h_s->struct_size)); + + bdb_in->oem_1 + = (u8 *)((u32)(bdb_in->bdb_d) + + (bdb_in->bdb_d->struct_size)); + + bdb_in->bdb_hash + = (struct bdb_hash *)((u32)(bdb_in->oem_1) + + (bdb_in->bdb_d->oem_area_1_size)); + + bdb_in->bdb_s + = (struct bdb_sig *)((u32)(bdb_in->bdb_d) + + (bdb_in->bdb_d->signed_size)); +} + +static struct bdb_hash *find_bdb_image(struct bdb_pointer *bdb_info, + u8 image_type) +{ + u8 i; + + if (bdb_info) { + for (i = 0; i < bdb_info->bdb_d->num_hashes; i++) { + if (bdb_info->bdb_hash[i].type == image_type) + return &bdb_info->bdb_hash[i]; + } + } + + return NULL; +} + +static void image_failure(void) +{ + /* TODO: implement image_filaure function to choose between + * image B, or recovery + * for now just reset the system + */ + hard_reset(); +} + +static void set_image_parameters(struct media_params *flash_read_info, + struct bdb_hash *image_info) +{ + (*flash_read_info).flash_offset + = (u32)(image_info->offset); + (*flash_read_info).local_buffer + = (u32)(image_info->load_address); + (*flash_read_info).size = image_info->size; + (*flash_read_info).image_id = 0x0; + (*flash_read_info).partition_num = (u32)image_info->partition; +} + +void load_and_validate_image(struct bdb_pointer *bdb_info, u8 image_type) +{ + struct bdb_hash *image_info; + u32 reg; + u32 rc; + struct media_params flash_read_info; + u8 image_digest[32]; + u32 media_type; + + /* TODO: use bootrom callback pointer + * register to find the location of media_type + */ + media_type = read32((void *)MVMAP2315_BRM_CBS_MEDIA_TYPE); + + reg = read32(&mvmap2315_apmu_clk->apaonclk_sdmmc_clkgenconfig); + reg &= ~MVMAP2315_SDMMC_CLK_RSTN; + write32(&mvmap2315_apmu_clk->apaonclk_sdmmc_clkgenconfig, reg); + + reg = read32(&mvmap2315_apmu_clk->apaonclk_sdmmc_clkgenconfig); + reg |= MVMAP2315_SDMMC_CLK_RSTN; + write32(&mvmap2315_apmu_clk->apaonclk_sdmmc_clkgenconfig, reg); + + image_info = find_bdb_image(bdb_info, image_type); + + if (!image_info) { + printk(BIOS_INFO, "Unable to find image type %d in BDB.\n", + image_type); + printk(BIOS_INFO, "Resetting system!!\n"); + image_failure(); + } + + set_image_parameters(&flash_read_info, image_info); + + rc = bootrom_callbacks.media_init(media_type, 0, 200); + + if (rc) { + printk(BIOS_INFO, "media_init callback failed with rc=%x.\n", + rc); + printk(BIOS_INFO, "Resetting system!!\n"); + + image_failure(); + } + + rc = bootrom_callbacks.media_read(media_type, 0, &flash_read_info); + if (rc) { + printk(BIOS_INFO, "media_read callback failed with rc=%x.\n", + rc); + printk(BIOS_INFO, "Resetting system!!\n"); + + image_failure(); + } + + rc = bootrom_callbacks.media_shutdown(media_type, 0, &flash_read_info); + if (rc) { + printk(BIOS_INFO, "WARNING: media_shutdown callback "); + printk(BIOS_INFO, "failed with rc=%x.\n", rc); + } + + rc = bootrom_callbacks.security_init(0x0); + if (rc) { + printk(BIOS_INFO, "WARNING: security_init callback "); + printk(BIOS_INFO, "failed with rc=%x.\n", rc); + } + + rc = bootrom_callbacks.sha_msg_digest( + ((u8 *)(flash_read_info.local_buffer)), + image_info->size, &image_digest[0], 32); + if (rc) { + printk(BIOS_INFO, "sha_msg_digest callback failed with rc=%x.\n", + rc); + printk(BIOS_INFO, "Resetting system!!\n"); + + image_failure(); + } + if (memcmp(&image_digest[0], &image_info->digest[0], 32)) { + printk(BIOS_INFO, "image hash doesn't match BDB expected"); + printk(BIOS_INFO, "value.\nResetting system!!\n"); + + image_failure(); + } +} diff --git a/src/soc/marvell/mvmap2315/gic.c b/src/soc/marvell/mvmap2315/gic.c index 9d0f9a6..ef5fa79 100644 --- a/src/soc/marvell/mvmap2315/gic.c +++ b/src/soc/marvell/mvmap2315/gic.c @@ -14,17 +14,32 @@ * GNU General Public License for more details. */ +#include <arch/io.h> #include <soc/addressmap.h> +#include <soc/gic.h> #include <gic.h> /* Return a pointer to the base of the GIC distributor mmio region. */ void *gicd_base(void) { - return (void *)MVMAP2315_GICD_BASE; + return (void *)MVMAP2315_AP_GICD_BASE; } /* Return a pointer to the base of the GIC cpu mmio region. */ void *gicc_base(void) { - return (void *)MVMAP2315_GICC_BASE; + return (void *)MVMAP2315_AP_GICC_BASE; +} + +void enable_bcm_gic(void) +{ + u32 reg; + + reg = read32(&mvmap2315_bcm_gicc->ctrl); + reg |= (MVMAP2315_BCM_GICC_EN0 & MVMAP2315_BCM_GICD_FIQ_EN); + write32(&mvmap2315_bcm_gicc->ctrl, reg); + + reg = read32(&mvmap2315_bcm_gicd->ctrl); + reg |= MVMAP2315_BCM_GICD_EN0; + write32(&mvmap2315_bcm_gicd->ctrl, reg); } diff --git a/src/soc/marvell/mvmap2315/include/soc/addressmap.h b/src/soc/marvell/mvmap2315/include/soc/addressmap.h index 242c5c2..9d20a75 100644 --- a/src/soc/marvell/mvmap2315/include/soc/addressmap.h +++ b/src/soc/marvell/mvmap2315/include/soc/addressmap.h @@ -22,15 +22,25 @@ enum { MVMAP2315_RAM_BASE = 0x00000000, MVMAP2315_CBFS_BASE = 0x00400000, + MVMAP2315_BDB_LCM_BASE = 0xE0000000, + MVMAP2315_BRM_CBS_MEDIA_TYPE = 0xE0002004, + MVMAP2315_BCM_GICD_BASE = 0xE0111000, + MVMAP2315_BCM_GICC_BASE = 0xE0112000, MVMAP2315_MAIN_PLL_BASE = 0xE0125000, MVMAP2315_APMU_CLK_BASE = 0xE0125400, MVMAP2315_GENTIMER_BASE = 0xE0137000, MVMAP2315_PADWRAP_BASE = 0xE0140000, MVMAP2315_TIMER0_BASE = 0xE1020000, MVMAP2315_MPMU_CLK_BASE = 0xEF000800, - MVMAP2315_GICD_BASE = 0xF0401000, - MVMAP2315_GICC_BASE = 0xF0402000, + MVMAP2315_AP_GICD_BASE = 0xF0401000, + MVMAP2315_AP_GICC_BASE = 0xF0402000, MVMAP2315_FLASH_BASE = 0xFE000000, + MVMAP2315_BM_CB_SECURITY_INIT = 0xFFE00040, + MVMAP2315_BM_CB_SHA_MSG_DIGEST = 0xFFE00044, + MVMAP2315_BM_CB_MEDIA_INIT = 0xFFE00084, + MVMAP2315_BM_CB_MEDIA_READ = 0xFFE00088, + MVMAP2315_BM_CB_MEDIA_WRITE = 0xFFE0008C, + MVMAP2315_BM_CB_MEDIA_SHUTDOWN = 0xFFE00098, }; #endif /* __SOC_MARVELL_MVMAP2315_ADDRESS_MAP_H__ */ diff --git a/src/soc/marvell/mvmap2315/include/soc/bdb.h b/src/soc/marvell/mvmap2315/include/soc/bdb.h new file mode 100644 index 0000000..42b94f1 --- /dev/null +++ b/src/soc/marvell/mvmap2315/include/soc/bdb.h @@ -0,0 +1,245 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Marvell, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __SOC_MARVELL_MVMAP2315_BDB_H__ +#define __SOC_MARVELL_MVMAP2315_BDB_H__ + +#include <stdint.h> +#include <stdlib.h> + +/* bdb_image_type */ +enum { + BDB_RESERVED = 0, + SP_RW_FIRMWARE = 1, + AP_RW_FIRMWARE = 2, + MCU_FIRMWARE = 3, + APMU_FIRMWARE = 4, + WTM_RW_FIRMWARE = 5, + KERNEL_IMAGE = 128, + KERNEL_COMMAND_LINE = 129, + SIXTEEN_BIT_VMLINUX_HEADER = 130 +}; + +#pragma pack(push, 1) +struct bdb_header { + /* Magic number to identify struct = BDB_HEADER_MAGIC. */ + u32 struct_magic; + + /* Structure version = BDB_HEADER_VERSION{MAJOR,MINOR} */ + u8 struct_major_version; + u8 struct_minor_version; + + /* Size of structure in bytes */ + u16 struct_size; + + /* Recommended address in SP SRAM to load BDB. Set to -1 to use + * default address. + */ + u64 bdb_load_address; + + /* Size of the entire BDB in bytes */ + u32 bdb_size; + + /* Number of bytes following the BDB key which are signed by the BDB + * header signature. + */ + u32 signed_size; + + /* Size of OEM area 0 in bytes, or 0 if not present */ + u32 oem_area_0_size; + + /* Reserved; set 0 */ + u8 reserved0[8]; +}; + +#pragma pack(pop) + +#pragma pack(push, 1) +struct bdb_key { + /* Magic number to identify struct = BDB_KEY_MAGIC. */ + u32 struct_magic; + + /* Structure version = BDB_KEY_VERSION{MAJOR,MINOR} */ + u8 struct_major_version; + u8 struct_minor_version; + + /* Size of structure in bytes, including variable-length key data */ + u16 struct_size; + + /* Hash algorithm (enum bdb_hash_alg) */ + u8 hash_alg; + + /* Signature algorithm (enum bdb_sig_alg) */ + u8 sig_alg; + + /* Reserved; set 0 */ + u8 reserved0[2]; + + /* Key version */ + u32 key_version; + + /* Description; null-terminated ASCII */ + char description[128]; + + /* + * Key data. Variable-length; size is struct_size - + * offset_of(bdb_key, key_data). + */ + u8 key_data[]; +}; + +#pragma pack(pop) + +#pragma pack(push, 1) +struct bdb_sig { + /* Magic number to identify struct = BDB_SIG_MAGIC. */ + u32 struct_magic; + + /* Structure version = BDB_SIG_VERSION{MAJOR,MINOR} */ + u8 struct_major_version; + u8 struct_minor_version; + + /* Size of structure in bytes, including variable-length signature + * data. + */ + u16 struct_size; + + /* Hash algorithm used for this signature (enum bdb_hash_alg) */ + u8 hash_alg; + + /* Signature algorithm (enum bdb_sig_alg) */ + u8 sig_alg; + + /* Reserved; set 0 */ + u8 reserved0[2]; + + /* Number of bytes of data signed by this signature */ + u32 signed_size; + + /* Description; null-terminated ASCII */ + char description[128]; + + /* Signature data. Variable-length; size is struct_size - + * offset_of(bdb_sig, sig_data). + */ + u8 sig_SOC_MARVELL_MVMAP2315_data[]; +}; + +#pragma pack(pop) + +#pragma pack(push, 1) +struct bdb_data { + /* Magic number to identify struct = BDB_DATA_MAGIC. */ + u32 struct_magic; + + /* Structure version = BDB_DATA_VERSION{MAJOR,MINOR} */ + u8 struct_major_version; + u8 struct_minor_version; + + /* Size of structure in bytes, NOT including hashes which follow. */ + u16 struct_size; + + /* Version of data (RW firmware) contained */ + u32 data_version; + + /* Size of OEM area 1 in bytes, or 0 if not present */ + u32 oem_area_1_size; + + /* Number of hashes which follow */ + u8 num_hashes; + + /* Size of each hash entry in bytes */ + u8 hash_entry_size; + + /* Reserved; set 0 */ + u8 reserved0[2]; + + /* Number of bytes of data signed by the subkey, + * including this header + */ + u32 signed_size; + + /* Reserved; set 0 */ + u8 reserved1[8]; + + /* Description; null-terminated ASCII */ + char description[128]; +}; + +#pragma pack(pop) + +/* Hash entries which follow the structure */ +#pragma pack(push, 1) +struct bdb_hash { + /* Offset of data from start of partition */ + u64 offset; + + /* Size of data in bytes */ + u32 size; + + /* Partition number containing data */ + u8 partition; + + /* Type of data; enum bdb_data_type */ + u8 type; + + /* Reserved; set 0 */ + u8 reserved0[2]; + + /* Address in RAM to load data. -1 means use default. */ + u64 load_address; + + /* SHA-256 hash digest */ + u8 digest[32]; +}; + +#pragma pack(pop) + +struct bdb_pointer { + /* Pointer to BDB header */ + struct bdb_header *bdb_h; + /* Pointer to BDB Key */ + struct bdb_key *bdb_k; + /* Pointer to OEM area 0 */ + u8 *bdb_oem_0; + /* Pointer to subkey */ + struct bdb_key *sub_k; + /* Pointer to BDB Header Signature */ + struct bdb_sig *bdb_h_s; + /* Pointer to BDB Data Structure */ + struct bdb_data *bdb_d; + /* Pointer to OEM Area 1 */ + u8 *oem_1; + /* Pointer to Hashes */ + struct bdb_hash *bdb_hash; + /* Pointer to BDB Data Signature */ + struct bdb_sig *bdb_s; +}; + +/* + * find_bdb_image -- Search for image info in BDB via image type + * + * @pBDB_h: BDB base address + * @image_id image type field of desired image + * + * find_bdb_image will search the boot d block start at pBDB_h + * for a hash image entry with the type image_id. A pointer + * to the hash entry in question is returned if the search is + * successful, otherwise a NULL pointer is returned. + * + */ +void set_bdb_pointers(u8 *start_addr, struct bdb_pointer *bdb_in); + +#endif /* __SOC_MARVELL_MVMAP2315_BDB_H__ */ diff --git a/src/soc/marvell/mvmap2315/include/soc/bootrom.h b/src/soc/marvell/mvmap2315/include/soc/bootrom.h new file mode 100644 index 0000000..3801def --- /dev/null +++ b/src/soc/marvell/mvmap2315/include/soc/bootrom.h @@ -0,0 +1,125 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Marvell, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __SOC_MARVELL_MVMAP2315_BOOTROM_H__ +#define __SOC_MARVELL_MVMAP2315_BOOTROM_H__ + +#include <stdint.h> +#include <stdlib.h> + +#include <soc/bdb.h> + +/* + * struct media_parms - flash read/write info for bootROM callbacks + * + * @flash_offset: offset from flash base address for read/write + * @local_buffer: buffer for read or write data. + * @size: Bytes of data to read/write + * @image_id: not needed, set to 0x0 + * @partition_num: media partition number + * + * parameters passed to flash read and write operations. local_buffer + * is the address of a buffer of at least size bytes. For write operations, + * this buffer should be populated with the data to be written to flash + * before the call to media_write. For read operations, the buffer + * will be populated during the call to media_read. + * + */ +struct media_params { + u32 flash_offset; + u32 local_buffer; + u32 size; + u32 image_id; + u32 partition_num; +}; + +/* + * function pointer type definitions for the bootrom callback functions + * + */ +typedef u32 (*security_init_F)(u32 adv_ver); +typedef u32 (*sha_msg_digest_F)(const u8 *src_msg_in, + u32 src_msg_len, + u8 *msg_digest_out, + u32 digest_len); +typedef u32 (*media_init_F)(u32 media_id, + u32 context, + u32 clock_input_mhz); +typedef u32 (*media_read_F)(u32 media_id, + u32 context, + struct media_params *); +typedef u32 (*media_write_F)(u32 media_id, + u32 context, + struct media_params *); +typedef u32 (*media_shutdown_F)(u32 media_id, + u32 context, + struct media_params *); + +/* + * struct bootrom_ops - bootrom callback functions + * + * @security_init: used to initialize BCM hardware. + * Must be called prior to using the sha_message_digest callback. + * + * @sha_msg_digest: Calculates the digest_len SHA hash of the src_msg_len + * byte image starting at address src_msg_in, and places the result at + * msg_digest_out. + * + * @media_init: Configures a flash media device. + * Call before media_read or media_write. + * + * @media_read: Read data from specified media. + * + * @media_write: Write data to specified media. + * + * @media_shutdown: Shut down flash device. + * + * The MVMAP2315 bootROM provides callback functions to assist SP RW code + * in loading and validating additional images that are specified in the + * validated boot descriptor block. + * + */ +struct bootrom_ops { + security_init_F security_init; + sha_msg_digest_F sha_msg_digest; + media_init_F media_init; + media_read_F media_read; + media_write_F media_write; + media_shutdown_F media_shutdown; +}; + +/* + * load_and_validate_image - find image info in BDB, load to specified address, + * calculate image hash, and compare BDB's expected hash. + * + * @bdb_info bdb_pointer structure populated with pointers to BDB's sections + * @image_type type of image for which to search + * + * load_and_validate_image searches the designated BDB's image hash entries + * for an image of type image_type. If the search is successful, bootrom + * callbacks are used to load the image from the flash offset address specified + * in the BDB entry in question to the memory address specified in that entry, + * and then validate the SHA256 hash of the image against the expected value + * specified in the BDB. If the image load or SHA validation checks fail, + * the function image_failure() is called to set appropriate flags in the + * VB_POWER_CLEAR registers, and the entire SoC is reset so that the bootrom + * can attempt to boot using the alternate BDB/image. If the image load and + * SHA validation passes, the function returns to the calling function. + * + */ +void load_and_validate_image(struct bdb_pointer *bdb_info, + u8 image_type); + +#endif /* __SOC_MARVELL_MVMAP2315_BOOTROM_H__ */ diff --git a/src/soc/marvell/mvmap2315/include/soc/clock.h b/src/soc/marvell/mvmap2315/include/soc/clock.h index 12d32c1..a982198 100644 --- a/src/soc/marvell/mvmap2315/include/soc/clock.h +++ b/src/soc/marvell/mvmap2315/include/soc/clock.h @@ -50,7 +50,7 @@ static struct mvmap2315_gentimer_regs * const mvmap2315_gentimer = (void *)MVMAP2315_GENTIMER_BASE; #define MVMAP2315_PLL_LOCK BIT(0) -#define MVMAP2315_PLL_BYPASS_EN BIT(16) +#define MVMAP2315_PLL_BYPASS_EN BIT(16) struct mvmap2315_main_pll_regs { u32 rst_prediv; @@ -70,7 +70,8 @@ check_member(mvmap2315_main_pll_regs, reserve_out, 0x28); static struct mvmap2315_main_pll_regs * const mvmap2315_pll = (void *)MVMAP2315_MAIN_PLL_BASE; -#define MVMAP2315_UART_CLK_EN BIT(0) +#define MVMAP2315_UART_CLK_EN BIT(1) +#define MVMAP2315_SDMMC_CLK_RSTN BIT(0) struct mvmap2315_apmu_clk_regs { u32 uartfracdivcfg0; u8 _reserved0[0x0c]; diff --git a/src/soc/marvell/mvmap2315/include/soc/gic.h b/src/soc/marvell/mvmap2315/include/soc/gic.h new file mode 100644 index 0000000..520ea51 --- /dev/null +++ b/src/soc/marvell/mvmap2315/include/soc/gic.h @@ -0,0 +1,412 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Marvell, Inc. + * + * This program is free software; + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#ifndef __SOC_MARVELL_MVMAP2315_GIC_H__ +#define __SOC_MARVELL_MVMAP2315_GIC_H__ + +#include <stdint.h> +#include <stdlib.h> +#include <types.h> + +#define MVMAP2315_BCM_GICC_EN0 BIT(0) +#define MVMAP2315_BCM_GICD_FIQ_EN BIT(3) +struct mvmap2315_bcm_gicc_regs { + u32 ctrl; + u32 pmr; + u32 bpr; + u32 iar; + u32 eoir; + u32 rpr; + u32 hppir; + u32 abpr; + u32 aiar; + u32 aeoir; + u32 ahppir; +}; + +check_member(mvmap2315_bcm_gicc_regs, ahppir, 0x28); +static struct mvmap2315_bcm_gicc_regs * const mvmap2315_bcm_gicc + = (void *)MVMAP2315_BCM_GICC_BASE; + +#define MVMAP2315_BCM_GICD_EN0 BIT(0) +struct mvmap2315_bcm_gicd_regs { + u32 ctrl; + u32 typer; + u32 iidr; + u8 _reserved0[0x74]; + u32 igroup0; + u32 igroup1; + u32 igroup2; + u32 igroup3; + u32 igroup4; + u32 igroup5; + u32 igroup6; + u32 igroup7; + u32 igroup8; + u32 igroup9; + u32 igroup10; + u32 igroup11; + u8 _reserved1[0x50]; + u32 isenable0; + u32 isenable1; + u32 isenable2; + u32 isenable3; + u32 isenable4; + u32 isenable5; + u32 isenable6; + u32 isenable7; + u32 isenable8; + u32 isenable9; + u32 isenable10; + u32 isenable11; + u8 _reserved2[0x50]; + u32 icenable0; + u32 icenable1; + u32 icenable2; + u32 icenable3; + u32 icenable4; + u32 icenable5; + u32 icenable6; + u32 icenable7; + u32 icenable8; + u32 icenable9; + u32 icenable10; + u32 icenable11; + u8 _reserved3[0x50]; + u32 ispendr0; + u32 ispendr1; + u32 ispendr2; + u32 ispendr3; + u32 ispendr4; + u32 ispendr5; + u32 ispendr6; + u32 ispendr7; + u32 ispendr8; + u32 ispendr9; + u32 ispendr10; + u32 ispendr11; + u8 _reserved4[0x50]; + u32 icpendr0; + u32 icpendr1; + u32 icpendr2; + u32 icpendr3; + u32 icpendr4; + u32 icpendr5; + u32 icpendr6; + u32 icpendr7; + u32 icpendr8; + u32 icpendr9; + u32 icpendr10; + u32 icpendr11; + u8 _reserved5[0x50]; + u32 isactive0; + u32 isactive1; + u32 isactive2; + u32 isactive3; + u32 isactive4; + u32 isactive5; + u32 isactive6; + u32 isactive7; + u32 isactive8; + u32 isactive9; + u32 isactive10; + u32 isactive11; + u8 _reserved6[0x50]; + u32 icactive0; + u32 icactive1; + u32 icactive2; + u32 icactive3; + u32 icactive4; + u32 icactive5; + u32 icactive6; + u32 icactive7; + u32 icactive8; + u32 icactive9; + u32 icactive10; + u32 icactive11; + u8 _reserved7[0x50]; + u32 ipriority0; + u32 ipriority1; + u32 ipriority2; + u32 ipriority3; + u32 ipriority4; + u32 ipriority5; + u32 ipriority6; + u32 ipriority7; + u32 ipriority8; + u32 ipriority9; + u32 ipriority10; + u32 ipriority11; + u32 ipriority12; + u32 ipriority13; + u32 ipriority14; + u32 ipriority15; + u32 ipriority16; + u32 ipriority17; + u32 ipriority18; + u32 ipriority19; + u32 ipriority20; + u32 ipriority21; + u32 ipriority22; + u32 ipriority23; + u32 ipriority24; + u32 ipriority25; + u32 ipriority26; + u32 ipriority27; + u32 ipriority28; + u32 ipriority29; + u32 ipriority30; + u32 ipriority31; + u32 ipriority32; + u32 ipriority33; + u32 ipriority34; + u32 ipriority35; + u32 ipriority36; + u32 ipriority37; + u32 ipriority38; + u32 ipriority39; + u32 ipriority40; + u32 ipriority41; + u32 ipriority42; + u32 ipriority43; + u32 ipriority44; + u32 ipriority45; + u32 ipriority46; + u32 ipriority47; + u32 ipriority48; + u32 ipriority49; + u32 ipriority50; + u32 ipriority51; + u32 ipriority52; + u32 ipriority53; + u32 ipriority54; + u32 ipriority55; + u32 ipriority56; + u32 ipriority57; + u32 ipriority58; + u32 ipriority59; + u32 ipriority60; + u32 ipriority61; + u32 ipriority62; + u32 ipriority63; + u32 ipriority64; + u32 ipriority65; + u32 ipriority66; + u32 ipriority67; + u32 ipriority68; + u32 ipriority69; + u32 ipriority70; + u32 ipriority71; + u32 ipriority72; + u32 ipriority73; + u32 ipriority74; + u32 ipriority75; + u32 ipriority76; + u32 ipriority77; + u32 ipriority78; + u32 ipriority79; + u32 ipriority80; + u32 ipriority81; + u32 ipriority82; + u32 ipriority83; + u32 ipriority84; + u32 ipriority85; + u32 ipriority86; + u32 ipriority87; + u32 ipriority88; + u32 ipriority89; + u32 ipriority90; + u32 ipriority91; + u32 ipriority92; + u32 ipriority93; + u32 ipriority94; + u32 ipriority95; + u8 _reserved8[0x280]; + u32 itargets0; + u32 itargets1; + u32 itargets2; + u32 itargets3; + u32 itargets4; + u32 itargets5; + u32 itargets6; + u32 itargets7; + u32 itargets8; + u32 itargets9; + u32 itargets10; + u32 itargets11; + u32 itargets12; + u32 itargets13; + u32 itargets14; + u32 itargets15; + u32 itargets16; + u32 itargets17; + u32 itargets18; + u32 itargets19; + u32 itargets20; + u32 itargets21; + u32 itargets22; + u32 itargets23; + u32 itargets24; + u32 itargets25; + u32 itargets26; + u32 itargets27; + u32 itargets28; + u32 itargets29; + u32 itargets30; + u32 itargets31; + u32 itargets32; + u32 itargets33; + u32 itargets34; + u32 itargets35; + u32 itargets36; + u32 itargets37; + u32 itargets38; + u32 itargets39; + u32 itargets40; + u32 itargets41; + u32 itargets42; + u32 itargets43; + u32 itargets44; + u32 itargets45; + u32 itargets46; + u32 itargets47; + u32 itargets48; + u32 itargets49; + u32 itargets50; + u32 itargets51; + u32 itargets52; + u32 itargets53; + u32 itargets54; + u32 itargets55; + u32 itargets56; + u32 itargets57; + u32 itargets58; + u32 itargets59; + u32 itargets60; + u32 itargets61; + u32 itargets62; + u32 itargets63; + u32 itargets64; + u32 itargets65; + u32 itargets66; + u32 itargets67; + u32 itargets68; + u32 itargets69; + u32 itargets70; + u32 itargets71; + u32 itargets72; + u32 itargets73; + u32 itargets74; + u32 itargets75; + u32 itargets76; + u32 itargets77; + u32 itargets78; + u32 itargets79; + u32 itargets80; + u32 itargets81; + u32 itargets82; + u32 itargets83; + u32 itargets84; + u32 itargets85; + u32 itargets86; + u32 itargets87; + u32 itargets88; + u32 itargets89; + u32 itargets90; + u32 itargets91; + u32 itargets92; + u32 itargets93; + u32 itargets94; + u32 itargets95; + u8 _reserved9[0x280]; + u32 icfg0; + u32 icfg1; + u32 icfg2; + u32 icfg3; + u32 icfg4; + u32 icfg5; + u32 icfg6; + u32 icfg7; + u32 icfg8; + u32 icfg9; + u32 icfg10; + u32 icfg11; + u32 icfg12; + u32 icfg13; + u32 icfg14; + u32 icfg15; + u32 icfg16; + u32 icfg17; + u32 icfg18; + u32 icfg19; + u32 icfg20; + u32 icfg21; + u32 icfg22; + u32 icfg23; + u8 _reserved10[0xa0]; + u32 ppisr; + u32 spisr0; + u32 spisr1; + u32 spisr2; + u32 spisr3; + u32 spisr4; + u32 spisr5; + u32 spisr6; + u32 spisr7; + u32 spisr8; + u32 spisr9; + u32 spisr10; + u8 _reserved11[0xd0]; + u32 nsacr0; + u32 nsacr1; + u32 nsacr2; + u32 nsacr3; + u32 nsacr4; + u32 nsacr5; + u32 nsacr6; + u32 nsacr7; + u32 nsacr8; + u32 nsacr9; + u32 nsacr10; + u32 nsacr11; + u32 nsacr12; + u32 nsacr13; + u32 nsacr14; + u32 nsacr15; + u32 nsacr16; + u32 nsacr17; + u32 nsacr18; + u32 nsacr19; + u32 nsacr20; + u32 nsacr21; + u8 _reserved12[0xa8]; + u32 sgir; + u8 _reserved13[0x0c]; + u32 cpendsgir0; + u32 cpendsgir1; + u32 cpendsgir2; + u32 cpendsgir3; + u32 spendsgir0; + u32 spendsgir1; + u32 spendsgir2; + u32 spendsgir3; +}; + +check_member(mvmap2315_bcm_gicd_regs, spendsgir3, 0xF2C); +static struct mvmap2315_bcm_gicd_regs * const mvmap2315_bcm_gicd + = (void *)MVMAP2315_BCM_GICD_BASE; + +void enable_bcm_gic(void); + +#endif /* __SOC_MARVELL_MVMAP2315_GIC_H__ */ diff --git a/src/soc/marvell/mvmap2315/romstage.c b/src/soc/marvell/mvmap2315/romstage.c index 6752461..bc9172e 100644 --- a/src/soc/marvell/mvmap2315/romstage.c +++ b/src/soc/marvell/mvmap2315/romstage.c @@ -16,8 +16,12 @@ #include <console/console.h> #include <console/uart.h> #include <program_loading.h> +#include <soc/addressmap.h> #include <soc/assert.h> +#include <soc/bdb.h> +#include <soc/bootrom.h> #include <soc/clock.h> +#include <soc/gic.h> #include <soc/monotonic_timer.h> #include <soc/power.h> #include <soc/romstage.h> @@ -30,10 +34,14 @@ */ void main(void) { + struct bdb_pointer bdb_info; u32 boot_path; configure_main_clk_pll(); + /* enabling BCM GIC for Bootrom callbacks */ + enable_bcm_gic(); + timestamp_init(0); asm volatile ("bl cpu_enable_icache" : : : "r0", "r1"); @@ -50,6 +58,11 @@ void main(void) timestamp_add_now(TS_START_ROMSTAGE); + set_bdb_pointers((u8 *)MVMAP2315_BDB_LCM_BASE, &bdb_info); + + printk(BIOS_INFO, "loading and validating APMU FIRMWARE\n"); + load_and_validate_image(&bdb_info, APMU_FIRMWARE); + boot_path = get_boot_path(); switch (boot_path) {

1 0

New patch to review for coreboot: marvell/mvmap2315: add uart & pinconfig drivers
by hakim giydan 30 Jun '16

30 Jun '16

hakim giydan (hgiydan(a)marvell.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15508 -gerrit commit 1a9aa6e1c95ecec8071d93fd25c9e8cf0e59697c Author: Hakim Giydan <hgiydan(a)marvell.com> Date: Wed Jun 29 18:52:21 2016 -0700 marvell/mvmap2315: add uart & pinconfig drivers the pinconfig driver is for emulation only, the real driver comes later. Change-Id: I89dee1bbf8b68460897f64bf673b328533e70cd4 Signed-off-by: Hakim Giydan <hgiydan(a)marvell.com> --- src/mainboard/marvell/rotor/Makefile.inc | 1 + src/mainboard/marvell/rotor/romstage.c | 63 ++++++++++++++ src/soc/marvell/mvmap2315/Kconfig | 5 ++ src/soc/marvell/mvmap2315/Makefile.inc | 2 + src/soc/marvell/mvmap2315/include/soc/addressmap.h | 1 + src/soc/marvell/mvmap2315/include/soc/pinconfig.h | 68 +++++++++++++++ src/soc/marvell/mvmap2315/include/soc/romstage.h | 23 +++++ src/soc/marvell/mvmap2315/include/soc/uart.h | 49 +++++++++++ src/soc/marvell/mvmap2315/pinconfig.c | 64 ++++++++++++++ src/soc/marvell/mvmap2315/romstage.c | 15 +++- src/soc/marvell/mvmap2315/uart.c | 97 ++++++++++++++++++++-- 11 files changed, 380 insertions(+), 8 deletions(-) diff --git a/src/mainboard/marvell/rotor/Makefile.inc b/src/mainboard/marvell/rotor/Makefile.inc index cb318e5..9c8b8b9 100644 --- a/src/mainboard/marvell/rotor/Makefile.inc +++ b/src/mainboard/marvell/rotor/Makefile.inc @@ -20,4 +20,5 @@ ramstage-$(CONFIG_CHROMEOS) += chromeos.c romstage-y += memlayout.ld romstage-y += reset.c +romstage-y += romstage.c romstage-$(CONFIG_CHROMEOS) += chromeos.c diff --git a/src/mainboard/marvell/rotor/romstage.c b/src/mainboard/marvell/rotor/romstage.c new file mode 100644 index 0000000..3d9f12a --- /dev/null +++ b/src/mainboard/marvell/rotor/romstage.c @@ -0,0 +1,63 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Marvell, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "arch/io.h" +#include "soc/clock.h" +#include "soc/pinconfig.h" +#include "soc/romstage.h" + +static const struct mvmap2315_pinconfig serial_1_pin_cfg[] = { + { 165, 1 }, /* APB:UART2_TXD */ + { 166, 1 } /* APB:UART2_RXD */ +}; + +static const struct mvmap2315_pinconfig serial_2_pin_cfg[] = { + { 176, 1 }, /* APB:UART2_TXD */ + { 177, 1 } /* APB:UART2_RXD */ +}; + +static void initpinconfig(void) +{ + /* Minimal IOs needed for initial startup */ + setpinconfigiogroup(serial_1_pin_cfg, + (sizeof(serial_1_pin_cfg) / + sizeof(struct mvmap2315_pinconfig))); + setpinconfigiogroup(serial_2_pin_cfg, + (sizeof(serial_2_pin_cfg) / + sizeof(struct mvmap2315_pinconfig))); +} + +void romstage_mainboard_early_init(void) +{ + u32 reg; + + /* + * enable APB/UART0 & APB/UART1 clock, but note that in emulation, + * even though this configuration implies that we are selecting + * the reference clock for uart clock source, the top level emulation + * scripts re-route that clock source to a 160690Hz clock in order to + * get a rate that works for 9600 baud uart output + */ + + reg = read32(&mvmap2315_apmu_clk->uartclk0_clkgenconfig); + reg |= MVMAP2315_UART_CLK_EN; + write32(&mvmap2315_apmu_clk->uartclk0_clkgenconfig, reg); + + reg = read32(&mvmap2315_apmu_clk->uartclk1_clkgenconfig); + reg |= MVMAP2315_UART_CLK_EN; + write32(&mvmap2315_apmu_clk->uartclk1_clkgenconfig, reg); + + initpinconfig(); +} diff --git a/src/soc/marvell/mvmap2315/Kconfig b/src/soc/marvell/mvmap2315/Kconfig index cfa622e..b110392 100644 --- a/src/soc/marvell/mvmap2315/Kconfig +++ b/src/soc/marvell/mvmap2315/Kconfig @@ -34,4 +34,9 @@ if SOC_MARVELL_MVMAP2315 config EMULATION bool default n + +config CONSOLE_SERIAL_MVMAP2315_UART_ADDRESS + hex + depends on CONSOLE_SERIAL + default 0xE1060000 endif diff --git a/src/soc/marvell/mvmap2315/Makefile.inc b/src/soc/marvell/mvmap2315/Makefile.inc index d80453a..994c745 100644 --- a/src/soc/marvell/mvmap2315/Makefile.inc +++ b/src/soc/marvell/mvmap2315/Makefile.inc @@ -20,6 +20,7 @@ ramstage-y += gic.c ramstage-y += media.c ramstage-y += mmu_operations.c ramstage-y += monotonic_timer.c +ramstage-y += pinconfig.c ramstage-y += ramstage.c ramstage-y += soc.c ramstage-y += stage_entry.S @@ -30,6 +31,7 @@ romstage-y += cbmem.c romstage-y += clock.c romstage-y += media.c romstage-y += monotonic_timer.c +romstage-y += pinconfig.c romstage-y += power.c romstage-y += romstage_asm.S romstage-y += romstage.c diff --git a/src/soc/marvell/mvmap2315/include/soc/addressmap.h b/src/soc/marvell/mvmap2315/include/soc/addressmap.h index 6cf5db2..242c5c2 100644 --- a/src/soc/marvell/mvmap2315/include/soc/addressmap.h +++ b/src/soc/marvell/mvmap2315/include/soc/addressmap.h @@ -25,6 +25,7 @@ enum { MVMAP2315_MAIN_PLL_BASE = 0xE0125000, MVMAP2315_APMU_CLK_BASE = 0xE0125400, MVMAP2315_GENTIMER_BASE = 0xE0137000, + MVMAP2315_PADWRAP_BASE = 0xE0140000, MVMAP2315_TIMER0_BASE = 0xE1020000, MVMAP2315_MPMU_CLK_BASE = 0xEF000800, MVMAP2315_GICD_BASE = 0xF0401000, diff --git a/src/soc/marvell/mvmap2315/include/soc/pinconfig.h b/src/soc/marvell/mvmap2315/include/soc/pinconfig.h new file mode 100644 index 0000000..047145de --- /dev/null +++ b/src/soc/marvell/mvmap2315/include/soc/pinconfig.h @@ -0,0 +1,68 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Marvell, Inc. + * + * This program is free software; + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __PINCONFIG_H__ +#define __PINCONFIG_H__ + +#include <stdint.h> +#include <stdlib.h> +#include <types.h> + +#include <soc/addressmap.h> + +#define MVMAP2315_PADWRAP_FUNC_SEL (BIT(0) | BIT(1) | BIT(2)) +#define MVMAP2315_PADWRAP_PU_EN BIT(14) +#define MVMAP2315_PADWRAP_PD_EN BIT(13) +struct mvmap2315_padwrap_regs { + u32 io_pad_piocfg[72]; + u8 _reserved0[0xee0]; + u32 pc_pwrdwn_g29_pwrdn; + u32 pc_v18en_lvl_g29; + u32 vdd3p3_1p8_g29_reg_pwrdn; + u32 pc_pwrdwn_g30_pwrdn; + u32 pc_v18en_lvl_g30; + u32 vdd3p3_1p8_g30_reg_pwrdn; + u32 pc_pwrdwn_g31_pwrdn; + u32 pc_v18en_lvl_g31; + u32 vdd3p3_1p8_g31_reg_pwrdn; + u32 pc_pwrdwn_g32_pwrdn; + u32 pc_v18en_lvl_g32; + u32 vdd3p3_1p8_g32_reg_pwrdn; + u32 pc_pwrdwn_g33_pwrdn; + u32 pc_v18en_lvl_g33; + u32 vdd3p3_1p8_g33_reg_pwrdn; +}; + +check_member(mvmap2315_padwrap_regs, vdd3p3_1p8_g33_reg_pwrdn, 0x1038); +static struct mvmap2315_padwrap_regs * const mvmap2315_padwrap + = (void *)MVMAP2315_PADWRAP_BASE; + +struct mvmap2315_pinconfig { + u32 pad; + u32 function; + u32 pull_down_enable; + u32 pull_up_enable; + u32 pull_select; + + /* Add other pin config here if necessary + * (e.g., pullup, slew, etc) + */ +}; + +check_member(mvmap2315_pinconfig, pull_select, 0x10); +void setpinconfigiogroup(const struct mvmap2315_pinconfig *io_grp_pin_cfg, + int num_pins); + +#endif /* __PINCONFIG_H__ */ diff --git a/src/soc/marvell/mvmap2315/include/soc/romstage.h b/src/soc/marvell/mvmap2315/include/soc/romstage.h new file mode 100644 index 0000000..af9f891 --- /dev/null +++ b/src/soc/marvell/mvmap2315/include/soc/romstage.h @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Marvell, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#ifndef __SOC_MARVELL_MVMAP2315_ROMSTAGE_H__ +#define __SOC_MARVELL_MVMAP2315_ROMSTAGE_H__ + +#include <stdint.h> +#include <stdlib.h> + +void romstage_mainboard_early_init(void); + +#endif /* __SOC_MARVELL_MVMAP2315_ROMSTAGE_H__ */ diff --git a/src/soc/marvell/mvmap2315/include/soc/uart.h b/src/soc/marvell/mvmap2315/include/soc/uart.h new file mode 100644 index 0000000..569a5aa --- /dev/null +++ b/src/soc/marvell/mvmap2315/include/soc/uart.h @@ -0,0 +1,49 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Marvell, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __SOC_MARVELL_MVMAP2315_UART_H__ +#define __SOC_MARVELL_MVMAP2315_UART_H__ + +#include <stdint.h> +#include <stdlib.h> + +#define BAUDRATE 9600 +#define BUSSPD 1 + +extern u32 uart_num; + +struct mvmap2315_uart_regs { + union { + u32 thr; + u32 rbr; + u32 dll; + }; + union { + u32 ier; + u32 dlm; + }; + union { + u32 iir; + u32 fcr; + }; + u32 lcr; + u32 mcr; + u32 lsr; + u32 msr; +}; + +check_member(mvmap2315_uart_regs, msr, 0x18); + +#endif /* __SOC_MARVELL_MVMAP2315_UART_H__ */ diff --git a/src/soc/marvell/mvmap2315/pinconfig.c b/src/soc/marvell/mvmap2315/pinconfig.c new file mode 100644 index 0000000..19e7ca1 --- /dev/null +++ b/src/soc/marvell/mvmap2315/pinconfig.c @@ -0,0 +1,64 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Marvell, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "arch/io.h" +#include <soc/pinconfig.h> + +static void setpinconfig(const struct mvmap2315_pinconfig *pinconfig) +{ + u32 reg; + u32 pad_num; + + if (!pinconfig) + return; + + /* pads < 160 are part of the MCU domain and not handled here */ + if (pinconfig->pad < 160) + return; + + pad_num = pinconfig->pad - 160; + + reg = read32(&mvmap2315_padwrap->io_pad_piocfg[pad_num]); + reg |= (pinconfig->function & MVMAP2315_PADWRAP_FUNC_SEL); + write32(&mvmap2315_padwrap->io_pad_piocfg[pad_num], reg); + + if (pinconfig->pull_select) { + reg = read32(&mvmap2315_padwrap->io_pad_piocfg[pad_num]); + + if (pinconfig->pull_up_enable) + reg |= MVMAP2315_PADWRAP_PU_EN; + else + reg &= ~MVMAP2315_PADWRAP_PU_EN; + + if (pinconfig->pull_down_enable) + reg |= MVMAP2315_PADWRAP_PD_EN; + else + reg &= ~MVMAP2315_PADWRAP_PD_EN; + + write32(&mvmap2315_padwrap->io_pad_piocfg[pad_num], reg); + } +} + +void setpinconfigiogroup(const struct mvmap2315_pinconfig *io_grp_pin_cfg, + int num_pins) +{ + int i; + + if (!io_grp_pin_cfg || !num_pins) + return; + + for (i = 0; i < num_pins; i++, io_grp_pin_cfg++) + setpinconfig(io_grp_pin_cfg); +} diff --git a/src/soc/marvell/mvmap2315/romstage.c b/src/soc/marvell/mvmap2315/romstage.c index 8924d01..6752461 100644 --- a/src/soc/marvell/mvmap2315/romstage.c +++ b/src/soc/marvell/mvmap2315/romstage.c @@ -13,11 +13,15 @@ * GNU General Public License for more details. */ +#include <console/console.h> +#include <console/uart.h> #include <program_loading.h> #include <soc/assert.h> #include <soc/clock.h> #include <soc/monotonic_timer.h> #include <soc/power.h> +#include <soc/romstage.h> +#include <soc/uart.h> #include <timestamp.h> /* @@ -34,8 +38,14 @@ void main(void) asm volatile ("bl cpu_enable_icache" : : : "r0", "r1"); + romstage_mainboard_early_init(); + + uart_num = CONFIG_UART_FOR_CONSOLE; + console_init(); + asm volatile ("bl cpu_init" : : : "r0"); + printk(BIOS_INFO, "Starting monotonic timer.\n"); start_monotonic_timer(); timestamp_add_now(TS_START_ROMSTAGE); @@ -63,7 +73,9 @@ void main(void) static void romstage_continue(void) { - /* TODO: R4 Functionality to be added */ + uart_num = 1; + uart_init(uart_num); + printk(BIOS_INFO, "TODO: R4 Functionality to be added\n"); while (1) ; } @@ -73,6 +85,7 @@ void platform_prog_run(struct prog *prog) if (!prog_entry(prog)) __assert("ramstage entrypoint not found", __FILE__, __LINE__); + printk(BIOS_INFO, "powering AP core 0.\n"); start_ap_cores(prog_entry(prog)); romstage_continue(); } diff --git a/src/soc/marvell/mvmap2315/uart.c b/src/soc/marvell/mvmap2315/uart.c index a486ee4..fc986d8 100644 --- a/src/soc/marvell/mvmap2315/uart.c +++ b/src/soc/marvell/mvmap2315/uart.c @@ -14,33 +14,116 @@ * GNU General Public License for more details. */ -#include <console/uart.h> +#include <arch/io.h> +#include <assert.h> #include <boot/coreboot_tables.h> +#include <console/console.h> +#include <console/uart.h> +#include <drivers/uart/uart8250reg.h> +#include <soc/uart.h> + +u32 uart_num; + +static void mvmap2315_uart_tx_flush(struct mvmap2315_uart_regs *uart_ptr) +{ + while (!(read8(&uart_ptr->lsr) & UART8250_LSR_TEMT)) + ; +} + +static void mvmap2315_uart_init(struct mvmap2315_uart_regs *uart_ptr) +{ + const u8 line_config = UART8250_LCR_WLS_8; + u16 divisor = divisor = ((BUSSPD * 6250) + + (BAUDRATE / 2)) / BAUDRATE; + + mvmap2315_uart_tx_flush(uart_ptr); + /* Disable interrupts. */ + write8(&uart_ptr->ier, 0); + /* Enable access to divisor latches. */ + write8(&uart_ptr->lcr, UART8250_LCR_DLAB); + /* Set the divisor. */ + write8(&uart_ptr->dll, divisor & 0xff); + write8(&uart_ptr->dlm, (divisor >> 8) & 0xff); + /* Hide divisor latches and program line config. */ + write8(&uart_ptr->lcr, line_config); + /* Enable FIFOs, and clear receive and transmit. */ + write8(&uart_ptr->fcr, + UART8250_FCR_FIFO_EN | + UART8250_FCR_CLEAR_RCVR | + UART8250_FCR_CLEAR_XMIT); +} + +static void mvmap2315_uart_tx_byte(struct mvmap2315_uart_regs *uart_ptr, + unsigned char data) +{ + while (!(read8(&uart_ptr->lsr) & UART8250_LSR_THRE)) + ; + write8(&uart_ptr->thr, data); +} + +static int mvmap2315_uart_tst_byte(struct mvmap2315_uart_regs *uart_ptr) +{ + return (read8(&uart_ptr->lsr) & UART8250_LSR_DR) + == UART8250_LSR_DR; +} + +static unsigned char mvmap2315_uart_rx_byte( + struct mvmap2315_uart_regs *uart_ptr) +{ + if (!mvmap2315_uart_tst_byte(uart_ptr)) + return 0; + return read8(&uart_ptr->rbr); +} + +uintptr_t uart_platform_base(int idx) +{ + /* Default to UART 0 */ + unsigned int base = CONFIG_CONSOLE_SERIAL_MVMAP2315_UART_ADDRESS; + + assert((uart_num >= 0) && (uart_num < 2)); + base += uart_num * 0x1000; + return base; +} void uart_init(int idx) { - /*TODO: implement uart_init */ + struct mvmap2315_uart_regs *uart_ptr = uart_platform_baseptr(idx); + + mvmap2315_uart_init(uart_ptr); } void uart_tx_byte(int idx, unsigned char data) { - /*TODO: implement uart_tx_byte */ + struct mvmap2315_uart_regs *uart_ptr = uart_platform_baseptr(idx); + + mvmap2315_uart_tx_byte(uart_ptr, data); } void uart_tx_flush(int idx) { - /*TODO: implement uart_tx_flush */ + struct mvmap2315_uart_regs *uart_ptr = uart_platform_baseptr(idx); + + mvmap2315_uart_tx_flush(uart_ptr); } unsigned char uart_rx_byte(int idx) { - /*TODO: implement uart_rx_byte */ - return 0; + struct mvmap2315_uart_regs *uart_ptr = uart_platform_baseptr(idx); + + return mvmap2315_uart_rx_byte(uart_ptr); } #if ENV_RAMSTAGE void uart_fill_lb(void *data) { - /*TODO: implement uart_fill_lb */ + struct lb_serial serial; + + serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED; + serial.baseaddr = uart_platform_base(CONFIG_UART_FOR_CONSOLE); + serial.baud = default_baudrate(); + serial.regwidth = 4; + lb_add_serial(&serial, data); + + lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data); } #endif

1 0

New patch to review for coreboot: marvell/rotor: add support for the Marvell rotor mainboard
by hakim giydan 30 Jun '16

30 Jun '16

hakim giydan (hgiydan(a)marvell.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15507 -gerrit commit 5f81551c6f677e6354467ba6085e4d899b6e7d3e Author: Hakim Giydan <hgiydan(a)marvell.com> Date: Wed Jun 29 18:51:32 2016 -0700 marvell/rotor: add support for the Marvell rotor mainboard Change-Id: I1f97b6f159a0ac36c96636066332ba355c056186 Signed-off-by: Hakim Giydan <hgiydan(a)marvell.com> --- src/mainboard/marvell/Kconfig | 31 +++++++++++++++++++ src/mainboard/marvell/Kconfig.name | 2 ++ src/mainboard/marvell/rotor/Kconfig | 46 ++++++++++++++++++++++++++++ src/mainboard/marvell/rotor/Kconfig.name | 2 ++ src/mainboard/marvell/rotor/Makefile.inc | 23 ++++++++++++++ src/mainboard/marvell/rotor/board_info.txt | 3 ++ src/mainboard/marvell/rotor/chromeos.c | 46 ++++++++++++++++++++++++++++ src/mainboard/marvell/rotor/chromeos.fmd | 27 ++++++++++++++++ src/mainboard/marvell/rotor/devicetree.cb | 18 +++++++++++ src/mainboard/marvell/rotor/mainboard.c | 49 ++++++++++++++++++++++++++++++ src/mainboard/marvell/rotor/memlayout.ld | 16 ++++++++++ src/mainboard/marvell/rotor/reset.c | 32 +++++++++++++++++++ 12 files changed, 295 insertions(+) diff --git a/src/mainboard/marvell/Kconfig b/src/mainboard/marvell/Kconfig new file mode 100644 index 0000000..779f2e4 --- /dev/null +++ b/src/mainboard/marvell/Kconfig @@ -0,0 +1,31 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2016 Marvell, Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +if VENDOR_MARVELL + +choice + prompt "Mainboard model" + +source "src/mainboard/marvell/*/Kconfig.name" + +endchoice + +source "src/mainboard/marvell/*/Kconfig" + +config MAINBOARD_VENDOR + string "Mainboard Vendor" + default "Marvell" + +endif # VENDOR_MARVELL diff --git a/src/mainboard/marvell/Kconfig.name b/src/mainboard/marvell/Kconfig.name new file mode 100644 index 0000000..40c0245 --- /dev/null +++ b/src/mainboard/marvell/Kconfig.name @@ -0,0 +1,2 @@ +config VENDOR_MARVELL + bool "Marvell" diff --git a/src/mainboard/marvell/rotor/Kconfig b/src/mainboard/marvell/rotor/Kconfig new file mode 100644 index 0000000..631fc0e --- /dev/null +++ b/src/mainboard/marvell/rotor/Kconfig @@ -0,0 +1,46 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2016 Marvell, Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +if BOARD_MARVELL_ROTOR + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select SOC_MARVELL_MVMAP2315 + select MAINBOARD_HAS_CHROMEOS + select BOARD_ROMSIZE_KB_4096 + select VBOOT2_MOCK_SECDATA + +config MAINBOARD_DIR + string + default marvell/rotor + +config MAINBOARD_PART_NUMBER + string + default "rotor" + +config GBB_HWID + string + depends on CHROMEOS + default "ROTOR TEST 1234" + +config RAMTOP + hex + default 0x73000000 + +config RAMBASE + hex + default 0x400000 + +endif # BOARD_MARVELL_ROTOR diff --git a/src/mainboard/marvell/rotor/Kconfig.name b/src/mainboard/marvell/rotor/Kconfig.name new file mode 100644 index 0000000..ee6a263 --- /dev/null +++ b/src/mainboard/marvell/rotor/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_MARVELL_ROTOR + bool "Rotor" diff --git a/src/mainboard/marvell/rotor/Makefile.inc b/src/mainboard/marvell/rotor/Makefile.inc new file mode 100644 index 0000000..cb318e5 --- /dev/null +++ b/src/mainboard/marvell/rotor/Makefile.inc @@ -0,0 +1,23 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2016 Marvell, Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +ramstage-y += mainboard.c +ramstage-y += memlayout.ld +ramstage-y += reset.c +ramstage-$(CONFIG_CHROMEOS) += chromeos.c + +romstage-y += memlayout.ld +romstage-y += reset.c +romstage-$(CONFIG_CHROMEOS) += chromeos.c diff --git a/src/mainboard/marvell/rotor/board_info.txt b/src/mainboard/marvell/rotor/board_info.txt new file mode 100644 index 0000000..27011b2 --- /dev/null +++ b/src/mainboard/marvell/rotor/board_info.txt @@ -0,0 +1,3 @@ +Category: laptop +ROM protocol: parallel flash +Flashrom support: y diff --git a/src/mainboard/marvell/rotor/chromeos.c b/src/mainboard/marvell/rotor/chromeos.c new file mode 100644 index 0000000..b394fbe --- /dev/null +++ b/src/mainboard/marvell/rotor/chromeos.c @@ -0,0 +1,46 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2016 Marvell, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <boot/coreboot_tables.h> +#include <bootmode.h> +#include <console/console.h> + + /* TODO: impelemnt the following functions if needed */ + +void fill_lb_gpios(struct lb_gpios *gpios) +{ + int count = 0; + + gpios->size = sizeof(*gpios) + (count * sizeof(struct lb_gpio)); + gpios->count = count; + + printk(BIOS_ERR, "Added %d GPIOS size %d\n", count, gpios->size); +} + +int get_developer_mode_switch(void) +{ + return 1; +} + +int get_recovery_mode_switch(void) +{ + return 0; +} + +int get_write_protect_state(void) +{ + return 0; +} diff --git a/src/mainboard/marvell/rotor/chromeos.fmd b/src/mainboard/marvell/rotor/chromeos.fmd new file mode 100644 index 0000000..f4a2819 --- /dev/null +++ b/src/mainboard/marvell/rotor/chromeos.fmd @@ -0,0 +1,27 @@ +FLASH@0x0 0x400000 { + WP_RO@0x0 0x200000 { + RO_SECTION@0x0 0x1f0000 { + BOOTBLOCK@0 128K + COREBOOT(CBFS)@0x20000 0xe0000 + FMAP@0x100000 0x1000 + GBB@0x101000 0xeef00 + RO_FRID@0x1eff00 0x100 + } + RO_VPD@0x1f0000 0x10000 + } + RW_SECTION_A@0x200000 0x78000 { + VBLOCK_A@0x0 0x2000 + FW_MAIN_A(CBFS)@0x2000 0x75f00 + RW_FWID_A@0x77f00 0x100 + } + RW_SHARED@0x278000 0x4000 { + SHARED_DATA@0x0 0x4000 + } + RW_ELOG@0x27c000 0x4000 + RW_SECTION_B@0x280000 0x78000 { + VBLOCK_B@0x0 0x2000 + FW_MAIN_B(CBFS)@0x2000 0x75f00 + RW_FWID_B@0x77f00 0x100 + } + RW_VPD@0x2f8000 0x8000 +} diff --git a/src/mainboard/marvell/rotor/devicetree.cb b/src/mainboard/marvell/rotor/devicetree.cb new file mode 100644 index 0000000..e2eccf0 --- /dev/null +++ b/src/mainboard/marvell/rotor/devicetree.cb @@ -0,0 +1,18 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2016 Marvell, Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +chip soc/marvell/mvmap2315 + device cpu_cluster 0 on end +end diff --git a/src/mainboard/marvell/rotor/mainboard.c b/src/mainboard/marvell/rotor/mainboard.c new file mode 100644 index 0000000..27ba153 --- /dev/null +++ b/src/mainboard/marvell/rotor/mainboard.c @@ -0,0 +1,49 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2016 Marvell, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/device.h> + +static void setup_pinmux(void) +{ + /* TODO: setup pins as per miniloader configuration + * Possibly move this function to romstage.c if pinmuxing is handled + * during romstage rather than ramstage. + */ +} + +static void setup_kernel_info(void) +{ + /* TODO: Setup required information for Linux kernel, if anything */ +} + +static void mainboard_init(device_t dev) +{ + /*TODO: add ramstage initialization code here */ + + setup_pinmux(); + + setup_kernel_info(); +} + +static void mainboard_enable(device_t dev) +{ + dev->ops->init = &mainboard_init; +} + +struct chip_operations mainboard_ops = { + .name = "rotor", + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/marvell/rotor/memlayout.ld b/src/mainboard/marvell/rotor/memlayout.ld new file mode 100644 index 0000000..05a4496 --- /dev/null +++ b/src/mainboard/marvell/rotor/memlayout.ld @@ -0,0 +1,16 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Marvell, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <soc/memlayout.ld> diff --git a/src/mainboard/marvell/rotor/reset.c b/src/mainboard/marvell/rotor/reset.c new file mode 100644 index 0000000..3f8d5e7 --- /dev/null +++ b/src/mainboard/marvell/rotor/reset.c @@ -0,0 +1,32 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Marvell, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <reset.h> +#include <soc/addressmap.h> +#include <soc/clock.h> + +void hard_reset(void) +{ + u32 reg; + + reg = read32(&mvmap2315_mpmu_clk->resetmcu); + reg &= ~MVMAP2315_MCU_RST_EN; + write32(&mvmap2315_mpmu_clk->resetmcu, reg); + + reg = read32(&mvmap2315_mpmu_clk->resetap); + reg &= ~MVMAP2315_AP_RST_EN; + write32(&mvmap2315_mpmu_clk->resetap, reg); +}

1 0

New patch to review for coreboot: marvell/mvmap2315: add a stub implementation of the mvmap2315 SOC.
by hakim giydan 30 Jun '16

30 Jun '16

hakim giydan (hgiydan(a)marvell.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15506 -gerrit commit dc2ce56a1ada53533d45ef8553391240029b541e Author: Hakim Giydan <hgiydan(a)marvell.com> Date: Wed Jun 29 18:50:41 2016 -0700 marvell/mvmap2315: add a stub implementation of the mvmap2315 SOC. Most things still need to be filled in, but this will allow us to build boards which use this SOC. Change-Id: I8cc3e99df915bb289a2f3539db103cd6be90a0b2 Signed-off-by: Hakim Giydan <hgiydan(a)marvell.com> --- src/soc/marvell/mvmap2315/Kconfig | 37 +++ src/soc/marvell/mvmap2315/Makefile.inc | 53 +++ src/soc/marvell/mvmap2315/assert.c | 42 +++ src/soc/marvell/mvmap2315/bootblock.stub | 20 ++ src/soc/marvell/mvmap2315/cbmem.c | 25 ++ src/soc/marvell/mvmap2315/clock.c | 50 +++ src/soc/marvell/mvmap2315/gic.c | 30 ++ src/soc/marvell/mvmap2315/include/soc/addressmap.h | 35 ++ src/soc/marvell/mvmap2315/include/soc/assert.h | 31 ++ src/soc/marvell/mvmap2315/include/soc/clock.h | 358 +++++++++++++++++++++ src/soc/marvell/mvmap2315/include/soc/memlayout.ld | 66 ++++ .../marvell/mvmap2315/include/soc/mmu_operations.h | 27 ++ .../mvmap2315/include/soc/monotonic_timer.h | 50 +++ src/soc/marvell/mvmap2315/include/soc/power.h | 33 ++ src/soc/marvell/mvmap2315/include/soc/ramstage.h | 23 ++ src/soc/marvell/mvmap2315/media.c | 26 ++ src/soc/marvell/mvmap2315/mmu_operations.c | 46 +++ src/soc/marvell/mvmap2315/monotonic_timer.c | 63 ++++ src/soc/marvell/mvmap2315/power.c | 41 +++ src/soc/marvell/mvmap2315/ramstage.c | 34 ++ src/soc/marvell/mvmap2315/romstage.c | 78 +++++ src/soc/marvell/mvmap2315/romstage_asm.S | 66 ++++ src/soc/marvell/mvmap2315/soc.c | 46 +++ src/soc/marvell/mvmap2315/stage_entry.S | 26 ++ src/soc/marvell/mvmap2315/uart.c | 46 +++ 25 files changed, 1352 insertions(+) diff --git a/src/soc/marvell/mvmap2315/Kconfig b/src/soc/marvell/mvmap2315/Kconfig new file mode 100644 index 0000000..cfa622e --- /dev/null +++ b/src/soc/marvell/mvmap2315/Kconfig @@ -0,0 +1,37 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2016 Marvell, Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +config SOC_MARVELL_MVMAP2315 + bool + default n + select ARM_LPAE + select ARCH_BOOTBLOCK_ARMV7 + select ARCH_RAMSTAGE_ARMV8_64 + select ARCH_ROMSTAGE_ARMV7_R + select ARCH_VERSTAGE_ARMV7_R + select GENERIC_UDELAY + select GIC + select HAVE_HARD_RESET + select HAVE_MONOTONIC_TIMER + select HAVE_UART_SPECIAL + select UNCOMPRESSED_RAMSTAGE + select VBOOT_DYNAMIC_WORK_BUFFER + +if SOC_MARVELL_MVMAP2315 + +config EMULATION + bool + default n +endif diff --git a/src/soc/marvell/mvmap2315/Makefile.inc b/src/soc/marvell/mvmap2315/Makefile.inc new file mode 100644 index 0000000..d80453a --- /dev/null +++ b/src/soc/marvell/mvmap2315/Makefile.inc @@ -0,0 +1,53 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2016 Marvell, Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +ramstage-y += assert.c +ramstage-y += cbmem.c +ramstage-y += clock.c +ramstage-y += gic.c +ramstage-y += media.c +ramstage-y += mmu_operations.c +ramstage-y += monotonic_timer.c +ramstage-y += ramstage.c +ramstage-y += soc.c +ramstage-y += stage_entry.S +ramstage-y += uart.c + +romstage-y += assert.c +romstage-y += cbmem.c +romstage-y += clock.c +romstage-y += media.c +romstage-y += monotonic_timer.c +romstage-y += power.c +romstage-y += romstage_asm.S +romstage-y += romstage.c +romstage-y += uart.c + +CPPFLAGS_common += -Isrc/soc/marvell/mvmap2315/include/ + +all: $(objcbfs)/bootblock.bin $(objcbfs)/romstage.bin + +## Replacing bootblock.bin with bootblock.stub since bootROM load and +## jump to romstage code directly. +## it is necessary to create a bootblock.stub file, or the final coreboot +## make stage will fail when it can't find bootblock.bin. + +$(objcbfs)/bootblock.bin: src/soc/marvell/mvmap2315/bootblock.stub + cat src/soc/marvell/mvmap2315/bootblock.stub > $(objcbfs)/bootblock.bin + +## generating romtage.bin since it is required to create the BDB + +$(objcbfs)/romstage.bin: $(objcbfs)/romstage.elf + $(OBJCOPY_romstage) -O binary $(objcbfs)/romstage.elf $(objcbfs)/romstage.bin diff --git a/src/soc/marvell/mvmap2315/assert.c b/src/soc/marvell/mvmap2315/assert.c new file mode 100644 index 0000000..f4c498c --- /dev/null +++ b/src/soc/marvell/mvmap2315/assert.c @@ -0,0 +1,42 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Marvell, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdint.h> +#include <stddef.h> + +#include <console/console.h> +#include <soc/assert.h> +#include <stddef.h> + +/*Trivial __assert_func */ +static void __assert_func(const char *file, int line, + const char *func, + const char *failedexpr) +{ +#ifdef CONFIG_CONSOLE_SERIAL_UART + printk(BIOS_ERR, "\n\nASSERT!!\n\n"); + printk(BIOS_ERR, "%s:%d - %s - %s\n", file, line, func, failedexpr); +#endif + + /* Purposely empty */ + while (1) + ; +} + +/* Minimal __assert() */ +void __assert(const char *failedexpr, const char *file, int line) +{ + __assert_func(file, line, NULL, failedexpr); +} diff --git a/src/soc/marvell/mvmap2315/bootblock.stub b/src/soc/marvell/mvmap2315/bootblock.stub new file mode 100644 index 0000000..0793599 --- /dev/null +++ b/src/soc/marvell/mvmap2315/bootblock.stub @@ -0,0 +1,20 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Marvell, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +/* This is a dummy file to replace bootblock.bin in the final coreboot + * image since bootblobk is been bypassed and the system is jumping + * directory to romstage from bootROM + */ diff --git a/src/soc/marvell/mvmap2315/cbmem.c b/src/soc/marvell/mvmap2315/cbmem.c new file mode 100644 index 0000000..a78c2ca --- /dev/null +++ b/src/soc/marvell/mvmap2315/cbmem.c @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * Copyright (C) 2016 Marvell, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdint.h> +#include <stddef.h> + +#include <cbmem.h> + +void *cbmem_top(void) +{ + return (void *)CONFIG_RAMTOP; +} diff --git a/src/soc/marvell/mvmap2315/clock.c b/src/soc/marvell/mvmap2315/clock.c new file mode 100644 index 0000000..f3e17cc --- /dev/null +++ b/src/soc/marvell/mvmap2315/clock.c @@ -0,0 +1,50 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Marvell, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/clock.h> +#include <arch/io.h> +#include <soc/clock.h> + +void clock_init_arm_generic_timer(void) +{ + u32 freq = MVMAP2315_CLK_M_KHZ * 1000; + u32 reg; + + set_cntfrq(freq); + + reg = read32(&mvmap2315_gentimer->cntfid0); + reg = freq; + write32(&mvmap2315_gentimer->cntfid0, reg); + + reg = read32(&mvmap2315_gentimer->cntcr); + reg |= MVMAP2315_GENTIMER_EN; + write32(&mvmap2315_gentimer->cntcr, reg); +} + +void configure_main_clk_pll(void) +{ + u32 reg; + + /* pick up speed as soon as possible */ + while (!(read32(&mvmap2315_pll->lock_status) + & MVMAP2315_PLL_LOCK)) + ; + + write32(&mvmap2315_apmu_clk->apaonclk_clkgenconfig, 1); + + reg = read32(&mvmap2315_pll->fixed_mode_ssc_mode); + reg &= ~MVMAP2315_PLL_BYPASS_EN; + write32(&mvmap2315_pll->fixed_mode_ssc_mode, reg); +} diff --git a/src/soc/marvell/mvmap2315/gic.c b/src/soc/marvell/mvmap2315/gic.c new file mode 100644 index 0000000..9d0f9a6 --- /dev/null +++ b/src/soc/marvell/mvmap2315/gic.c @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * Copyright (C) 2016 Marvell, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <soc/addressmap.h> +#include <gic.h> + +/* Return a pointer to the base of the GIC distributor mmio region. */ +void *gicd_base(void) +{ + return (void *)MVMAP2315_GICD_BASE; +} + +/* Return a pointer to the base of the GIC cpu mmio region. */ +void *gicc_base(void) +{ + return (void *)MVMAP2315_GICC_BASE; +} diff --git a/src/soc/marvell/mvmap2315/include/soc/addressmap.h b/src/soc/marvell/mvmap2315/include/soc/addressmap.h new file mode 100644 index 0000000..6cf5db2 --- /dev/null +++ b/src/soc/marvell/mvmap2315/include/soc/addressmap.h @@ -0,0 +1,35 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Marvell, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __SOC_MARVELL_MVMAP2315_ADDRESS_MAP_H__ +#define __SOC_MARVELL_MVMAP2315_ADDRESS_MAP_H__ + +#include <stdint.h> +#include <stdlib.h> + +enum { + MVMAP2315_RAM_BASE = 0x00000000, + MVMAP2315_CBFS_BASE = 0x00400000, + MVMAP2315_MAIN_PLL_BASE = 0xE0125000, + MVMAP2315_APMU_CLK_BASE = 0xE0125400, + MVMAP2315_GENTIMER_BASE = 0xE0137000, + MVMAP2315_TIMER0_BASE = 0xE1020000, + MVMAP2315_MPMU_CLK_BASE = 0xEF000800, + MVMAP2315_GICD_BASE = 0xF0401000, + MVMAP2315_GICC_BASE = 0xF0402000, + MVMAP2315_FLASH_BASE = 0xFE000000, +}; + +#endif /* __SOC_MARVELL_MVMAP2315_ADDRESS_MAP_H__ */ diff --git a/src/soc/marvell/mvmap2315/include/soc/assert.h b/src/soc/marvell/mvmap2315/include/soc/assert.h new file mode 100644 index 0000000..760e39b --- /dev/null +++ b/src/soc/marvell/mvmap2315/include/soc/assert.h @@ -0,0 +1,31 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Marvell, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __SOC_MARVELL_MVMAP2315_ASSERT_H__ +#define __SOC_MARVELL_MVMAP2315_ASSERT_H__ + +#include <stdint.h> +#include <stdlib.h> + +void __assert(const char *failedexpr, const char *file, int line); + +#define assert(x) \ + do { \ + if (!(x)) \ + __assert("assertion failed", \ + __FILE__, __LINE__); \ + } while (0) + +#endif /* __SOC_MARVELL_MVMAP2315_ASSERT_H__ */ diff --git a/src/soc/marvell/mvmap2315/include/soc/clock.h b/src/soc/marvell/mvmap2315/include/soc/clock.h new file mode 100644 index 0000000..12d32c1 --- /dev/null +++ b/src/soc/marvell/mvmap2315/include/soc/clock.h @@ -0,0 +1,358 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Marvell, Inc. + * + * This program is free software; + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __SOC_MARVELL_MVMAP2315_CLOCK_H__ +#define __SOC_MARVELL_MVMAP2315_CLOCK_H__ + +#include <stdint.h> +#include <stdlib.h> +#include <types.h> + +#include <soc/addressmap.h> + +#define MVMAP2315_CLK_M_KHZ 25000 +#define MVMAP2315_GENTIMER_EN BIT(0) + +struct mvmap2315_gentimer_regs { + u32 cntcr; + u32 cntsr; + u32 cntcvl; + u32 cntcvu; + u8 _reserved0[0x10]; + u32 cntfid0; + u8 _reserved1[0xfac]; + u32 pidr4; + u8 _reserved2[0x0c]; + u32 pidr0; + u32 pidr1; + u32 pidr2; + u32 pidr3; + u32 cidr0; + u32 cidr1; + u32 cidr2; + u32 cidr3; +}; + +check_member(mvmap2315_gentimer_regs, cidr3, 0xFFC); +static struct mvmap2315_gentimer_regs * const mvmap2315_gentimer + = (void *)MVMAP2315_GENTIMER_BASE; + +#define MVMAP2315_PLL_LOCK BIT(0) +#define MVMAP2315_PLL_BYPASS_EN BIT(16) + +struct mvmap2315_main_pll_regs { + u32 rst_prediv; + u32 mult_postdiv; + u32 kvco; + u32 misc; + u32 feedback_mode_deskew; + u32 offset_mode; + u32 fixed_mode_ssc_mode; + u32 ssc_freq_ssc_range; + u32 clk_ctrl_marvell_test; + u32 lock_status; + u32 reserve_out; +}; + +check_member(mvmap2315_main_pll_regs, reserve_out, 0x28); +static struct mvmap2315_main_pll_regs * const mvmap2315_pll + = (void *)MVMAP2315_MAIN_PLL_BASE; + +#define MVMAP2315_UART_CLK_EN BIT(0) +struct mvmap2315_apmu_clk_regs { + u32 uartfracdivcfg0; + u8 _reserved0[0x0c]; + u32 uartfracdivcfg1; + u8 _reserved1[0x0c]; + u32 r4clkstatus; + u8 _reserved2[0x5c]; + u32 busclk2x_a2_clkgenconfig; + u32 busclk2x_a2_clkgenstatus; + u8 _reserved3[0x08]; + u32 busclk_mcix2_clkgenconfig; + u32 busclk_mcix2_clkgenstatus; + u32 busclk_mcix2_phyreset_clkgenconfig; + u32 busclk_mcix2_phyreset_clkgenstatus; + u32 busclk_mcix10_clkgenconfig; + u32 busclk_mcix10_clkgenstatus; + u32 busclk_mcix1_phyreset0_clkgenconfig; + u32 busclk_mcix1_phyreset0_clkgenstatus; + u32 busclk_mcix11_clkgenconfig; + u32 busclk_mcix11_clkgenstatus; + u32 busclk_mcix1_phyreset1_clkgenconfig; + u32 busclk_mcix1_phyreset1_clkgenstatus; + u32 busclk_mcix12_clkgenconfig; + u32 busclk_mcix12_clkgenstatus; + u32 busclk_mcix1_phyreset2_clkgenconfig; + u32 busclk_mcix1_phyreset2_clkgenstatus; + u32 busclk_mcix13_clkgenconfig; + u32 busclk_mcix13_clkgenstatus; + u32 busclk_mcix1_phyreset3_clkgenconfig; + u32 busclk_mcix1_phyreset3_clkgenstatus; + u8 _reserved4[0x10]; + u32 busclk_aes_clkgenconfig; + u32 busclk_aes_clkgenstatus; + u32 busclk_apaonbus_hs_clkgenconfig; + u32 busclk_apaonbus_hs_clkgenstatus; + u32 busclk_a2_clkgenconfig; + u32 busclk_a2_clkgenstatus; + u8 _reserved5[0x78]; + u32 apaonclk_clkgenconfig; + u32 apaonclk_clkgenstatus; + u32 apaonclk_apmucpu_clkgenconfig; + u32 apaonclk_apmucpu_clkgenstatus; + u32 apaonclk_sdmmc_clkgenconfig; + u32 apaonclk_sdmmc_clkgenstatus; + u8 _reserved6[0x08]; + u32 apaonclk_m2m_clkgenconfig; + u32 apaonclk_m2m_clkgenstatus; + u32 apaonclk_apb_clkgenconfig; + u32 apaonclk_apb_clkgenstatus; + u8 _reserved7[0x50]; + u32 bistclk_clkgenconfig; + u32 bistclk_clkgenstatus; + u32 bistclk_a2reset_clkgenconfig; + u32 bistclk_a2reset_clkgenstatus; + u32 bistclk_apcpureset_clkgenconfig; + u32 bistclk_apcpureset_clkgenstatus; + u32 bistclk_coresightreset_clkgenconfig; + u32 bistclk_coresightreset_clkgenstatus; + u32 bistclk_mcflcreset_clkgenconfig; + u32 bistclk_mcflcreset_clkgenstatus; + u8 _reserved8[0x08]; + u32 bistclk_gpu3dreset_clkgenconfig; + u32 bistclk_gpu3dreset_clkgenstatus; + u32 bistclk_gpu3dcorereset0_clkgenconfig; + u32 bistclk_gpu3dcorereset0_clkgenstatus; + u32 bistclk_gpu3dcorereset1_clkgenconfig; + u32 bistclk_gpu3dcorereset1_clkgenstatus; + u32 bistclk_gpu3dcorereset2_clkgenconfig; + u32 bistclk_gpu3dcorereset2_clkgenstatus; + u32 bistclk_gpu3dcorereset3_clkgenconfig; + u32 bistclk_gpu3dcorereset3_clkgenstatus; + u32 bistclk_gpu2dreset_clkgenconfig; + u32 bistclk_gpu2dreset_clkgenstatus; + u32 bistclk_zramreset_clkgenconfig; + u32 bistclk_zramreset_clkgenstatus; + u32 bistclk_vpuencreset_clkgenconfig; + u32 bistclk_vpuencreset_clkgenstatus; + u32 bistclk_vpudecreset_clkgenconfig; + u32 bistclk_vpudecreset_clkgenstatus; + u32 bistclk_displayreset_clkgenconfig; + u32 bistclk_displayreset_clkgenstatus; + u32 bistclk_edisplayreset_clkgenconfig; + u32 bistclk_edisplayreset_clkgenstatus; + u8 _reserved9[0x78]; + u32 sdmmcbaseclk_clkgenconfig; + u32 sdmmcbaseclk_clkgenstatus; + u8 _reserved10[0x08]; + u32 cfgclk_a2_clkgenconfig; + u32 cfgclk_a2_clkgenstatus; + u8 _reserved11[0x08]; + u32 uartclk0_clkgenconfig; + u32 uartclk0_clkgenstatus; + u8 _reserved12[0x08]; + u32 uartclk1_clkgenconfig; + u32 uartclk1_clkgenstatus; + u8 _reserved13[0x08]; + u32 sspclk0_clkgenconfig; + u32 sspclk0_clkgenstatus; + u8 _reserved14[0x08]; + u32 sspclk1_clkgenconfig; + u32 sspclk1_clkgenstatus; + u8 _reserved15[0x08]; + u32 i2cclk0_clkgenconfig; + u32 i2cclk0_clkgenstatus; + u8 _reserved16[0x08]; + u32 i2cclk1_clkgenconfig; + u32 i2cclk1_clkgenstatus; + u8 _reserved17[0x08]; + u32 i2cclk2_clkgenconfig; + u32 i2cclk2_clkgenstatus; + u8 _reserved18[0x08]; + u32 i2cclk3_clkgenconfig; + u32 i2cclk3_clkgenstatus; + u8 _reserved19[0x08]; + u32 i2cclk4_clkgenconfig; + u32 i2cclk4_clkgenstatus; +}; + +check_member(mvmap2315_apmu_clk_regs, i2cclk4_clkgenstatus, 0x3A4); +static struct mvmap2315_apmu_clk_regs * const mvmap2315_apmu_clk + = (void *)MVMAP2315_APMU_CLK_BASE; + +#define MVMAP2315_AP_RST_EN BIT(0) +#define MVMAP2315_MCU_RST_EN BIT(0) +struct mvmap2315_mpmu_clk_regs { + u32 resetap; + u32 resetmcu; + u32 resetstatus; + u8 _reserved0[4]; + u32 apaudiopllselect; + u8 _reserved1[0x0c]; + u32 sspa_asrc_rx_clk0; + u32 sspa_asrc_rx_clk1; + u32 sspa_asrc_rx_clk2; + u32 sspa_asrc_tx_clk0; + u32 sspa_asrc_tx_clk1; + u32 sspa_asrc_tx_clk2; + u32 dmic_asrc_clk; + u8 _reserved2[4]; + u32 uartfracdivcfg0; + u8 _reserved3[0x0c]; + u32 uartfracdivcfg1; + u8 _reserved4[0xcc]; + u32 clk32k_clkgenconfig; + u32 clk32k_clkgenstatus; + u8 _reserved5[0x08]; + u32 cpudbgclk_clkgenconfig; + u32 cpudbgclk_clkgenstatus; + u8 _reserved6[0x08]; + u32 m4clk_bist_clkgenconfig; + u32 m4clk_bist_clkgenstatus; + u8 _reserved7[0x08]; + u32 bspiclk_clkgenconfig; + u32 bspiclk_clkgenstatus; + u8 _reserved8[0x08]; + u32 dmicclk_clkgenconfig; + u32 dmicclk_clkgenstatus; + u8 _reserved9[0x48]; + u32 sspaclk0_clkgenconfig; + u32 sspaclk0_clkgenstatus; + u32 sspaclk1_clkgenconfig; + u32 sspaclk1_clkgenstatus; + u32 sspaclk2_clkgenconfig; + u32 sspaclk2_clkgenstatus; + u8 _reserved10[0x38]; + u32 mcuclk_clkgenconfig; + u32 mcuclk_clkgenstatus; + u8 _reserved11[0x08]; + u32 mcuclk_cdma_clkgenconfig; + u32 mcuclk_cdma_clkgenstatus; + u8 _reserved12[0x08]; + u32 mcuclk_bspi_clkgenconfig; + u32 mcuclk_bspi_clkgenstatus; + u8 _reserved13[0x08]; + u32 mcuclk_owi_clkgenconfig; + u32 mcuclk_owi_clkgenstatus; + u8 _reserved14[0x08]; + u32 mcuclk_uart0_clkgenconfig; + u32 mcuclk_uart0_clkgenstatus; + u8 _reserved15[0x08]; + u32 mcuclk_uart1_clkgenconfig; + u32 mcuclk_uart1_clkgenstatus; + u8 _reserved16[0x08]; + u32 mcuclk_ssp0_clkgenconfig; + u32 mcuclk_ssp0_clkgenstatus; + u8 _reserved17[0x08]; + u32 mcuclk_ssp1_clkgenconfig; + u32 mcuclk_ssp1_clkgenstatus; + u8 _reserved18[0x08]; + u32 mcuclk_sspa0_clkgenconfig; + u32 mcuclk_sspa0_clkgenstatus; + u8 _reserved19[0x08]; + u32 mcuclk_sspa1_clkgenconfig; + u32 mcuclk_sspa1_clkgenstatus; + u8 _reserved20[0x08]; + u32 mcuclk_sspa2_clkgenconfig; + u32 mcuclk_sspa2_clkgenstatus; + u8 _reserved21[0x08]; + u32 mcuclk_dmic0_clkgenconfig; + u32 mcuclk_dmic0_clkgenstatus; + u8 _reserved22[0x08]; + u32 mcuclk_dmic1_clkgenconfig; + u32 mcuclk_dmic1_clkgenstatus; + u8 _reserved23[0x08]; + u32 mcuclk_dmic2_clkgenconfig; + u32 mcuclk_dmic2_clkgenstatus; + u8 _reserved24[0x08]; + u32 mcuclk_dmic3_clkgenconfig; + u32 mcuclk_dmic3_clkgenstatus; + u8 _reserved25[0x18]; + u32 dmic_dclk0_clkgenconfig; + u32 dmic_dclk0_clkgenstatus; + u8 _reserved26[0x08]; + u32 dmic_dclk1_clkgenconfig; + u32 dmic_dclk1_clkgenstatus; + u8 _reserved27[0x08]; + u32 dmic_dclk2_clkgenconfig; + u32 dmic_dclk2_clkgenstatus; + u8 _reserved28[0x08]; + u32 dmic_dclk3_clkgenconfig; + u32 dmic_dclk3_clkgenstatus; + u8 _reserved29[0x08]; + u32 dmic_engdetclk_clkgenconfig; + u32 dmic_engdetclk_clkgenstatus; + u8 _reserved30[0x38]; + u32 refclk_clkgenconfig; + u32 refclk_clkgenstatus; + u8 _reserved31[0x08]; + u32 refclk_ssp0_clkgenconfig; + u32 refclk_ssp0_clkgenstatus; + u8 _reserved32[0x08]; + u32 refclk_ssp1_clkgenconfig; + u32 refclk_ssp1_clkgenstatus; + u8 _reserved33[0x08]; + u32 refclk_uart0_clkgenconfig; + u32 refclk_uart0_clkgenstatus; + u8 _reserved34[0x08]; + u32 refclk_uart1_clkgenconfig; + u32 refclk_uart1_clkgenstatus; + u8 _reserved35[0x08]; + u32 refclk_i2c0_clkgenconfig; + u32 refclk_i2c0_clkgenstatus; + u8 _reserved36[0x08]; + u32 refclk_i2c1_clkgenconfig; + u32 refclk_i2c1_clkgenstatus; + u8 _reserved37[0x08]; + u32 refclk_i2c2_clkgenconfig; + u32 refclk_i2c2_clkgenstatus; + u8 _reserved38[0x08]; + u32 refclk_i2c3_clkgenconfig; + u32 refclk_i2c3_clkgenstatus; + u8 _reserved39[0x08]; + u32 refclk_i2c4_clkgenconfig; + u32 refclk_i2c4_clkgenstatus; + u8 _reserved40[0x08]; + u32 refclk_i2c5_clkgenconfig; + u32 refclk_i2c5_clkgenstatus; + u8 _reserved41[0x08]; + u32 refclk_sspa0_clkgenconfig; + u32 refclk_sspa0_clkgenstatus; + u8 _reserved42[0x08]; + u32 refclk_sspa1_clkgenconfig; + u32 refclk_sspa1_clkgenstatus; + u8 _reserved43[0x08]; + u32 refclk_sspa2_clkgenconfig; + u32 refclk_sspa2_clkgenstatus; + u8 _reserved44[0x08]; + u32 tsenclk_clkgenconfig; + u32 tsenclk_clkgenstatus; + u8 _reserved45[0x08]; + u32 ap_tsenclk_clkgenconfig; + u32 ap_tsenclk_clkgenstatus; + u8 _reserved46[0x08]; + u32 sspa_mclk_clkgenconfig; + u32 sspa_mclk_clkgenstatus; +}; + +check_member(mvmap2315_mpmu_clk_regs, sspa_mclk_clkgenstatus, 0x484); +static struct mvmap2315_mpmu_clk_regs * const mvmap2315_mpmu_clk + = (void *)MVMAP2315_MPMU_CLK_BASE; + +void clock_init_arm_generic_timer(void); +void configure_main_clk_pll(void); + +#endif /* __SOC_MARVELL_MVMAP2315_CLOCK_H__ */ diff --git a/src/soc/marvell/mvmap2315/include/soc/memlayout.ld b/src/soc/marvell/mvmap2315/include/soc/memlayout.ld new file mode 100644 index 0000000..665e4f5 --- /dev/null +++ b/src/soc/marvell/mvmap2315/include/soc/memlayout.ld @@ -0,0 +1,66 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Marvell, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <memlayout.h> +#include <arch/header.ld> + +SECTIONS +{ + DRAM_START(0x00000000) + +#if ENV_RAMSTAGE + TIMESTAMP(0x00060010, 128K) + STACK(0x00080010, 8K) +#endif + + VBOOT2_WORK(0x00082010, 16K) + VERSTAGE(0x1A0000, 128K) + POSTRAM_CBFS_CACHE(0x1C0000, 256K) + RAMSTAGE(0x00200000, 640K) + TTB(0x00300000, 1024K) + + SRAM_START(0xE0000000) + + /* The bootblock code won't actually be used, but the make process + * will fail if we don't provide a link address for it. Using LCM + * memory that is actually assigned to the bootROM so we don't + * use any LCM memory needed by coreboot code that will actually + * run. + */ + BOOTBLOCK(0xE0000000, 16K) + + /* The first 40K of LCM memory is reserved for the validated BDB + * as well as for bootROM usage when it is executing callbacks. + */ + + /* ROMSTAGE will be placed starting at the start of the second + * 32K segment in LCM. The Romstage code must not exceed 80KB, + * or it will encroach into LCM space reserved for APMU firmware + */ + ROMSTAGE(0xE0008000, 80K) + PRERAM_CBFS_CACHE(0xE001C000, 256) + PRERAM_CBMEM_CONSOLE(0xE001C100, 8K) + +#if ENV_ROMSTAGE + STACK(0xE001E100, 2K) + TIMESTAMP(0xE001E900, 1K) +#endif + + /* the folowing 2.5K are reserved for FIQ stack use + * memory address higher than 0xE001F700 + */ + + SRAM_END(0xE0020000) +} diff --git a/src/soc/marvell/mvmap2315/include/soc/mmu_operations.h b/src/soc/marvell/mvmap2315/include/soc/mmu_operations.h new file mode 100644 index 0000000..8c51367 --- /dev/null +++ b/src/soc/marvell/mvmap2315/include/soc/mmu_operations.h @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Marvell, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __SOC_MARVELL_MVMAP2315_MMU_OPERATIONS_H__ +#define __SOC_MARVELL_MVMAP2315_MMU_OPERATIONS_H__ + +#include <stdint.h> +#include <stdlib.h> + +#define MVMAP2315_DEVICE_SIZE 0x7E000000 +#define MVMAP2315_FLASH_SIZE 0x02000000 + +void mvmap2315_mmu_init(void); + +#endif /*__SOC_MARVELL_MVMAP2315_MMU_OPERATIONS_H__*/ diff --git a/src/soc/marvell/mvmap2315/include/soc/monotonic_timer.h b/src/soc/marvell/mvmap2315/include/soc/monotonic_timer.h new file mode 100644 index 0000000..79c477b --- /dev/null +++ b/src/soc/marvell/mvmap2315/include/soc/monotonic_timer.h @@ -0,0 +1,50 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Marvell, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __SOC_MARVELL_MVMAP2315_MONOTONIC_TIMER_H__ +#define __SOC_MARVELL_MVMAP2315_MONOTONIC_TIMER_H__ + +#include <stdint.h> +#include <stdlib.h> +#include <types.h> + +#include <soc/addressmap.h> + +#define MVMAP2315_TIMER_T1CR_TE BIT(0) +#define MVMAP2315_TIMER_T1CR_TM BIT(1) +#define MVMAP2315_TIMER_T1CR_TIM BIT(2) +#define MVMAP2315_TIMER_T1CR_TPWM BIT(3) + +struct mvmap2315_timer_regs { + u32 t1lc; + u32 t1cv; + u32 t1cr; + u32 t1eoi; + u32 t1is; + u8 _reserved0[0x8c]; + u32 tis; + u32 teoi; + u32 tris; + u32 tcv; + u32 t1lc2; +}; + +check_member(mvmap2315_timer_regs, t1lc2, 0xB0); +static struct mvmap2315_timer_regs * const mvmap2315_timer0 + = (void *)MVMAP2315_TIMER0_BASE; + +void start_monotonic_timer(void); + +#endif /* __SOC_MARVELL_MVMAP2315_MONOTONIC_TIMER_H__ */ diff --git a/src/soc/marvell/mvmap2315/include/soc/power.h b/src/soc/marvell/mvmap2315/include/soc/power.h new file mode 100644 index 0000000..308f657 --- /dev/null +++ b/src/soc/marvell/mvmap2315/include/soc/power.h @@ -0,0 +1,33 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Marvell, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#ifndef __SOC_MARVELL_MVMAP2315_POWER_H__ +#define __SOC_MARVELL_MVMAP2315_POWER_H__ + +#include <stdint.h> +#include <stdlib.h> + +enum boot_paths { + NO_BOOT = 0, + CHARGING_SCREEN = 1, + FULL_BOOT = 2 +}; + +void no_boot(void); +void full_boot(void); +void charging_screen(void); +void start_ap_cores(void *entry); +u32 get_boot_path(void); + +#endif /* __SOC_MARVELL_MVMAP2315_POWER_H__ */ diff --git a/src/soc/marvell/mvmap2315/include/soc/ramstage.h b/src/soc/marvell/mvmap2315/include/soc/ramstage.h new file mode 100644 index 0000000..61608cf --- /dev/null +++ b/src/soc/marvell/mvmap2315/include/soc/ramstage.h @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Marvell, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#ifndef __SOC_MARVELL_MVMAP2315_RAMSTAGE_H__ +#define __SOC_MARVELL_MVMAP2315_RAMSTAGE_H__ + +#include <stdint.h> +#include <stdlib.h> + +void ramstage_entry(void); + +#endif /* __SOC_MARVELL_MVMAP2315_RAMSTAGE_H__ */ diff --git a/src/soc/marvell/mvmap2315/media.c b/src/soc/marvell/mvmap2315/media.c new file mode 100644 index 0000000..cafc85d --- /dev/null +++ b/src/soc/marvell/mvmap2315/media.c @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Marvell, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <boot_device.h> +#include <soc/addressmap.h> +#include <symbols.h> + +static struct mem_region_device mdev = + MEM_REGION_DEV_INIT((void *)MVMAP2315_CBFS_BASE, CONFIG_ROM_SIZE); + +const struct region_device *boot_device_ro(void) +{ + return &mdev.rdev; +} diff --git a/src/soc/marvell/mvmap2315/mmu_operations.c b/src/soc/marvell/mvmap2315/mmu_operations.c new file mode 100644 index 0000000..105dd72 --- /dev/null +++ b/src/soc/marvell/mvmap2315/mmu_operations.c @@ -0,0 +1,46 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Google Inc. + * Copyright (C) 2016 Marvell, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/cpu.h> +#include <device/device.h> +#include <memrange.h> +#include <arch/mmu.h> +#include <soc/addressmap.h> +#include <soc/mmu_operations.h> + +static void mvmap2315_mmu_config(void) +{ + const unsigned long ram_mem = MA_MEM | MA_NS | MA_RW; + const unsigned long dev_mem = MA_DEV | MA_S | MA_RW; + const unsigned long flash_mem = MA_MEM | MA_S | MA_RW; + + mmu_config_range((void *)MVMAP2315_RAM_BASE, (2UL * GiB), ram_mem); + + mmu_config_range((void *)(2UL * GiB), + MVMAP2315_DEVICE_SIZE, dev_mem); + + mmu_config_range((void *)MVMAP2315_FLASH_BASE, + MVMAP2315_FLASH_SIZE, flash_mem); +} + +void mvmap2315_mmu_init(void) +{ + mmu_init(); + + mvmap2315_mmu_config(); + + mmu_enable(); +} diff --git a/src/soc/marvell/mvmap2315/monotonic_timer.c b/src/soc/marvell/mvmap2315/monotonic_timer.c new file mode 100644 index 0000000..2316798 --- /dev/null +++ b/src/soc/marvell/mvmap2315/monotonic_timer.c @@ -0,0 +1,63 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Marvell, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <soc/monotonic_timer.h> +#include <timer.h> + +void start_monotonic_timer(void) +{ + u32 reg; + + reg = read32(&mvmap2315_timer0->t1cr); + + /* disable timer */ + reg &= ~MVMAP2315_TIMER_T1CR_TE; + /* set to free-running mode (loads max value at timer expiration) */ + reg &= ~MVMAP2315_TIMER_T1CR_TM; + /* mask interrupt (not currently used) */ + reg |= MVMAP2315_TIMER_T1CR_TIM; + /* disable PWM output */ + reg &= ~MVMAP2315_TIMER_T1CR_TPWM; + + write32(&mvmap2315_timer0->t1cr, reg); + + /* perform dummy read to clear all active interrupts */ + reg = read32(&mvmap2315_timer0->t1eoi); + + /* must provide an initial load count even in free-running mode */ + reg = read32(&mvmap2315_timer0->t1lc); + reg = 0xFFFFFFFF; + write32(&mvmap2315_timer0->t1lc, reg); + + /* enable timer */ + reg = read32(&mvmap2315_timer0->t1cr); + reg |= MVMAP2315_TIMER_T1CR_TE; + write32(&mvmap2315_timer0->t1cr, reg); + + /* busy wait until timer count is non-zero */ + while (!read32(&mvmap2315_timer0->t1cv)) + ; +} + +void timer_monotonic_get(struct mono_time *mt) +{ + u32 reg; + + /* invert count to change from down to up count */ + reg = ~read32(&mvmap2315_timer0->t1cv); + + mt->microseconds = (long)(reg / 13); +} diff --git a/src/soc/marvell/mvmap2315/power.c b/src/soc/marvell/mvmap2315/power.c new file mode 100644 index 0000000..578fb51 --- /dev/null +++ b/src/soc/marvell/mvmap2315/power.c @@ -0,0 +1,41 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Marvell, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <soc/power.h> + +void start_ap_cores(void *entry) +{ + /*TODO: start_ap_cores */ +} + +void no_boot(void) +{ + /*TODO: impelement no_boot */ +} + +void charging_screen(void) +{ + /*TODO: impelement charging_screen */ +} + +void full_boot(void) +{ + /*TODO: impelement full_boot */ +} + +u32 get_boot_path(void) +{ + return FULL_BOOT; +} diff --git a/src/soc/marvell/mvmap2315/ramstage.c b/src/soc/marvell/mvmap2315/ramstage.c new file mode 100644 index 0000000..bd830c8 --- /dev/null +++ b/src/soc/marvell/mvmap2315/ramstage.c @@ -0,0 +1,34 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * Copyright (C) 2016 Marvell, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/stages.h> +#include <console/console.h> +#include <gic.h> +#include <soc/clock.h> +#include <soc/mmu_operations.h> +#include <soc/ramstage.h> + +void ramstage_entry(void) +{ + gic_init(); + + mvmap2315_mmu_init(); + + clock_init_arm_generic_timer(); + + /* Jump to boot state machine in common code. */ + main(); +} diff --git a/src/soc/marvell/mvmap2315/romstage.c b/src/soc/marvell/mvmap2315/romstage.c new file mode 100644 index 0000000..8924d01 --- /dev/null +++ b/src/soc/marvell/mvmap2315/romstage.c @@ -0,0 +1,78 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Marvell, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <program_loading.h> +#include <soc/assert.h> +#include <soc/clock.h> +#include <soc/monotonic_timer.h> +#include <soc/power.h> +#include <timestamp.h> + +/* + * main -- romstage main code. + * + */ +void main(void) +{ + u32 boot_path; + + configure_main_clk_pll(); + + timestamp_init(0); + + asm volatile ("bl cpu_enable_icache" : : : "r0", "r1"); + + asm volatile ("bl cpu_init" : : : "r0"); + + start_monotonic_timer(); + + timestamp_add_now(TS_START_ROMSTAGE); + + boot_path = get_boot_path(); + + switch (boot_path) { + case NO_BOOT: + no_boot(); + break; + + case CHARGING_SCREEN: + charging_screen(); + break; + + case FULL_BOOT: + full_boot(); + break; + } + + timestamp_add_now(TS_END_ROMSTAGE); + + run_ramstage(); +} + +static void romstage_continue(void) +{ + /* TODO: R4 Functionality to be added */ + while (1) + ; +} + +void platform_prog_run(struct prog *prog) +{ + if (!prog_entry(prog)) + __assert("ramstage entrypoint not found", __FILE__, __LINE__); + + start_ap_cores(prog_entry(prog)); + romstage_continue(); +} diff --git a/src/soc/marvell/mvmap2315/romstage_asm.S b/src/soc/marvell/mvmap2315/romstage_asm.S new file mode 100644 index 0000000..3fac9a5 --- /dev/null +++ b/src/soc/marvell/mvmap2315/romstage_asm.S @@ -0,0 +1,66 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * Copyright (C) 2016 Marvell, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/asm.h> + +# .balign 16 + +.arm +ENTRY(stage_entry) + blx _thumb_start +ENDPROC(stage_entry) + +.thumb +ENTRY(_thumb_start) + + ldr sp, =_estack + ldr r0, =_stack + ldr r1, =_estack + ldr r2, =0xdeadbeef +init_stack_loop: + str r2, [r0] + add r0, #4 + cmp r0, r1 + bne init_stack_loop + nop + + /* First arg: start of memory block */ + ldr a1, =_bss + + /* Second arg: fill value */ + mov a2, #0 + ldr a3, =_ebss + + /* Third arg: length of block */ + sub a3, a3, a1 + bl memset + + /* initializing FIQ stack */ + mrs r0, CPSR + mov r1, r0 + bic r1, r1, #0x40 + orr r0, r0, #0x51 + and r0, r0, #0xFFFFFFF1 + msr CPSR_c, r0 + ldr sp, =0xE001F700 + orr r0, r0, #0x10 + and r0, r0, #0xFFFFFFB0 + msr CPSR_cf, r1 + + /* call the code to authenticate this */ + bl main + /* should never return from this */ +ENDPROC(_thumb_start) diff --git a/src/soc/marvell/mvmap2315/soc.c b/src/soc/marvell/mvmap2315/soc.c new file mode 100644 index 0000000..a206e7b --- /dev/null +++ b/src/soc/marvell/mvmap2315/soc.c @@ -0,0 +1,46 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Google Inc. + * Copyright (C) 2016 Marvell, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/cpu.h> +#include <device/device.h> + +static void soc_enable(device_t dev) +{ + /* Provide RAM resource for use by coreboot. Memory area needs to + * inclue load address for the payload. note that base and size are + * in Kbytes, so actual base and size are 0x10000000. + */ + + ram_resource(dev, 0, 0x0, CONFIG_RAMTOP / 1024); +} + +static struct device_operations soc_ops = { + .read_resources = DEVICE_NOOP, + .set_resources = DEVICE_NOOP, + .enable_resources = soc_enable, + .init = DEVICE_NOOP, + .scan_bus = NULL, +}; + +static void enable_mvmap2315_dev(device_t dev) +{ + dev->ops = &soc_ops; +} + +struct chip_operations soc_marvell_mvmap2315_ops = { + CHIP_NAME("SOC Marvell MVMAP2315") + .enable_dev = enable_mvmap2315_dev, +}; diff --git a/src/soc/marvell/mvmap2315/stage_entry.S b/src/soc/marvell/mvmap2315/stage_entry.S new file mode 100644 index 0000000..1bdf2d6 --- /dev/null +++ b/src/soc/marvell/mvmap2315/stage_entry.S @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Google Inc. + * Copyright (C) 2016 Marvell, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/asm.h> + +ENTRY(stage_entry) + + /* Initialize PSTATE, SCTLR and caches to clean state, set up stack. */ + bl arm64_init_cpu + + /* Jump to Tegra-specific C entry point. */ + bl ramstage_entry +ENDPROC(stage_entry) diff --git a/src/soc/marvell/mvmap2315/uart.c b/src/soc/marvell/mvmap2315/uart.c new file mode 100644 index 0000000..a486ee4 --- /dev/null +++ b/src/soc/marvell/mvmap2315/uart.c @@ -0,0 +1,46 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Google Inc. + * Copyright (C) 2016 Marvell, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/uart.h> +#include <boot/coreboot_tables.h> + +void uart_init(int idx) +{ + /*TODO: implement uart_init */ +} + +void uart_tx_byte(int idx, unsigned char data) +{ + /*TODO: implement uart_tx_byte */ +} + +void uart_tx_flush(int idx) +{ + /*TODO: implement uart_tx_flush */ +} + +unsigned char uart_rx_byte(int idx) +{ + /*TODO: implement uart_rx_byte */ + return 0; +} + +#if ENV_RAMSTAGE +void uart_fill_lb(void *data) +{ + /*TODO: implement uart_fill_lb */ +} +#endif

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Patch set updated for coreboot: WIP: soc/intel/apollolake: Change default CAR size to 768 KiB
by Andrey Petrov 30 Jun '16

30 Jun '16

Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15453 -gerrit commit c01491d37ceda5922d5c309cc57624ecf7a1697a Author: Andrey Petrov <andrey.petrov(a)intel.com> Date: Mon Jun 27 15:21:26 2016 -0700 WIP: soc/intel/apollolake: Change default CAR size to 768 KiB As whole 1024 KiB is not used, it is possible to shrink CAR size to 768 KiB. Since 768 KiB is not power of two, 2 MTRRs are used to setup it. This is part of preparation for CQOS enabling. BUG=chrome-os-partner:51959 Change-Id: I56326a1790df202a0e428e092dd90286c58763c5 Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- src/soc/intel/apollolake/Kconfig | 2 +- src/soc/intel/apollolake/bootblock/cache_as_ram.S | 27 +++++++++++++++++++++++ 2 files changed, 28 insertions(+), 1 deletion(-) diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index 98ce7d8..f51dbfb 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -77,7 +77,7 @@ config DCACHE_RAM_BASE config DCACHE_RAM_SIZE hex "Length in bytes of cache-as-RAM" - default 0x100000 + default 0xc0000 help The size of the cache-as-ram region required during bootblock and/or romstage. diff --git a/src/soc/intel/apollolake/bootblock/cache_as_ram.S b/src/soc/intel/apollolake/bootblock/cache_as_ram.S index 8647206..8436d51 100644 --- a/src/soc/intel/apollolake/bootblock/cache_as_ram.S +++ b/src/soc/intel/apollolake/bootblock/cache_as_ram.S @@ -17,6 +17,7 @@ */ #include <device/pci_def.h> +#include <commonlib/helpers.h> #include <cpu/x86/mtrr.h> #include <cpu/x86/cache.h> #include <cpu/x86/cr.h> @@ -70,6 +71,7 @@ clear_var_mtrr: post_code(0x24) +#if ((CONFIG_DCACHE_RAM_SIZE & (CONFIG_DCACHE_RAM_SIZE - 1)) == 0) /* Configure CAR region as write-back (WB) */ mov $MTRR_PHYS_BASE(0), %ecx mov $CONFIG_DCACHE_RAM_BASE, %eax @@ -82,6 +84,31 @@ clear_var_mtrr: mov $~(CONFIG_DCACHE_RAM_SIZE - 1), %eax /* size mask */ or $MTRR_PHYS_MASK_VALID, %eax wrmsr +#elif (CONFIG_DCACHE_RAM_SIZE == 768 * KiB) /* 768 KiB */ + mov $MTRR_PHYS_BASE(0), %ecx + mov $CONFIG_DCACHE_RAM_BASE, %eax + or $MTRR_TYPE_WRBACK, %eax + xor %edx,%edx + wrmsr + + mov $MTRR_PHYS_MASK(0), %ecx + mov $~(512 * KiB - 1), %eax /* size mask */ + or $MTRR_PHYS_MASK_VALID, %eax + wrmsr + + mov $MTRR_PHYS_BASE(1), %ecx + mov $(CONFIG_DCACHE_RAM_BASE + 512 * KiB), %eax + or $MTRR_TYPE_WRBACK, %eax + xor %edx,%edx + wrmsr + + mov $MTRR_PHYS_MASK(1), %ecx + mov $~(0x256 * KiB - 1), %eax /* size mask */ + or $MTRR_PHYS_MASK_VALID, %eax + wrmsr +#else +#error "CONFIG_DCACHE_RAM_SIZE is not power of 2 and no matching mtrr set up code" +#endif post_code(0x25)

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coreboot-gerrit June 2016