coreboot-gerrit June 2016

coreboot-gerrit@coreboot.org

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1491 discussions

New patch to review for coreboot: marvell/mvmap2315: add watchdog timer driver
by hakim giydan 30 Jun '16

30 Jun '16

hakim giydan (hgiydan(a)marvell.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15519 -gerrit commit 57b1095dd3d362563356ca6f1816913585e25494 Author: Hakim Giydan <hgiydan(a)marvell.com> Date: Thu Jun 30 09:02:38 2016 -0700 marvell/mvmap2315: add watchdog timer driver Change-Id: Ie9c9297f321c838f86e5536aab29f67a0eeb053d Signed-off-by: Hakim Giydan <hgiydan(a)marvell.com> --- src/soc/marvell/mvmap2315/Makefile.inc | 1 + src/soc/marvell/mvmap2315/include/soc/addressmap.h | 1 + src/soc/marvell/mvmap2315/include/soc/watchdog.h | 54 ++++++++++++++++ src/soc/marvell/mvmap2315/romstage.c | 16 ++++- src/soc/marvell/mvmap2315/watchdog.c | 74 ++++++++++++++++++++++ 5 files changed, 144 insertions(+), 2 deletions(-) diff --git a/src/soc/marvell/mvmap2315/Makefile.inc b/src/soc/marvell/mvmap2315/Makefile.inc index a408049..ca32b76 100644 --- a/src/soc/marvell/mvmap2315/Makefile.inc +++ b/src/soc/marvell/mvmap2315/Makefile.inc @@ -39,6 +39,7 @@ romstage-y += power.c romstage-y += romstage_asm.S romstage-y += romstage.c romstage-y += uart.c +romstage-y += watchdog.c CPPFLAGS_common += -Isrc/soc/marvell/mvmap2315/include/ diff --git a/src/soc/marvell/mvmap2315/include/soc/addressmap.h b/src/soc/marvell/mvmap2315/include/soc/addressmap.h index 1303cc8..0de4222 100644 --- a/src/soc/marvell/mvmap2315/include/soc/addressmap.h +++ b/src/soc/marvell/mvmap2315/include/soc/addressmap.h @@ -34,6 +34,7 @@ enum { MVMAP2315_GENTIMER_BASE = 0xE0137000, MVMAP2315_CPU_BASE = 0xE013F200, MVMAP2315_PADWRAP_BASE = 0xE0140000, + MVMAP2315_WDT0_BASE = 0XE1010000, MVMAP2315_TIMER0_BASE = 0xE1020000, MVMAP2315_MPMU_CLK_BASE = 0xEF000800, MVMAP2315_AP_GICD_BASE = 0xF0401000, diff --git a/src/soc/marvell/mvmap2315/include/soc/watchdog.h b/src/soc/marvell/mvmap2315/include/soc/watchdog.h new file mode 100644 index 0000000..6756585 --- /dev/null +++ b/src/soc/marvell/mvmap2315/include/soc/watchdog.h @@ -0,0 +1,54 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Marvell, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#ifndef __WATCHDOG_H__ +#define __WATCHDOG_H__ + +#include <stdint.h> +#include <stdlib.h> +#include <types.h> + +#include <soc/addressmap.h> + +#define MVMAP2315_WDT_CR_RPL_SHIFT 2 +#define MVMAP2315_WDT_CR_RMOD BIT(1) +#define MVMAP2315_WDT_CR_EN BIT(0) +#define MVMAP2315_WDT_TORR_TOP_SHIFT 0 +#define MVMAP2315_WDT_CRR_SHIFT 0 +struct mvmap2315_wdt_regs { + u32 wdt_cr; + u32 wdt_torr; + u32 wdt_ccvr; + u32 wdt_crr; + u32 wdt_stat; + u32 wdt_eoi; + u8 _reserved0[0xcc]; + u32 wdt_comp_params_5; + u32 wdt_comp_params_4; + u32 wdt_comp_params_3; + u32 wdt_comp_params_2; + u32 wdt_comp_params_1; + u32 wdt_comp_version; + u32 wdt_comp_type; +}; + +check_member(mvmap2315_wdt_regs, wdt_comp_type, 0xfc); +static struct mvmap2315_wdt_regs * const mvmap2315_wdt0 + = (void *)MVMAP2315_WDT0_BASE; + +void enable_sp_watchdog(u32 timeout_value); +void reset_sp_watchdog(u32 timeout_value); +int should_reset_sp_watchdog(void); + +#endif /* __WATCHDOG_H__ */ diff --git a/src/soc/marvell/mvmap2315/romstage.c b/src/soc/marvell/mvmap2315/romstage.c index f4c64d2..0e32020 100644 --- a/src/soc/marvell/mvmap2315/romstage.c +++ b/src/soc/marvell/mvmap2315/romstage.c @@ -28,6 +28,7 @@ #include <soc/power.h> #include <soc/romstage.h> #include <soc/uart.h> +#include <soc/watchdog.h> #include <timestamp.h> /* @@ -58,10 +59,13 @@ void main(void) printk(BIOS_INFO, "Starting monotonic timer.\n"); start_monotonic_timer(); + enable_sp_watchdog(0); timestamp_add_now(TS_START_ROMSTAGE); set_bdb_pointers((u8 *)MVMAP2315_BDB_LCM_BASE, &bdb_info); + reset_sp_watchdog(1); + printk(BIOS_INFO, "loading and validating APMU FIRMWARE\n"); load_and_validate_image(&bdb_info, APMU_FIRMWARE); @@ -72,6 +76,8 @@ void main(void) apmu_start(4, 5); + reset_sp_watchdog(1); + if (!(read32((void *)MVMAP2315_LOWPWR_REG) & MVMAP2315_LOWPWR_FLAG)) { printk(BIOS_INFO, "loading and validating MCU FIRMWARE\n"); load_and_validate_image(&bdb_info, MCU_FIRMWARE); @@ -97,10 +103,14 @@ void main(void) break; } + reset_sp_watchdog(1); + apmu_declare_s0(); timestamp_add_now(TS_END_ROMSTAGE); + reset_sp_watchdog(1); + run_ramstage(); } @@ -109,8 +119,10 @@ static void romstage_continue(void) uart_num = 1; uart_init(uart_num); printk(BIOS_INFO, "TODO: R4 Functionality to be added\n"); - while (1) - ; + while (1) { + if (!should_reset_sp_watchdog()) + reset_sp_watchdog(1); + } } void platform_prog_run(struct prog *prog) diff --git a/src/soc/marvell/mvmap2315/watchdog.c b/src/soc/marvell/mvmap2315/watchdog.c new file mode 100644 index 0000000..72f987e --- /dev/null +++ b/src/soc/marvell/mvmap2315/watchdog.c @@ -0,0 +1,74 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Marvell, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <console/console.h> +#include <soc/watchdog.h> + +void enable_sp_watchdog(u32 timeout_value) +{ + u32 reg; + + reg = read32(&mvmap2315_wdt0->wdt_cr); + + /* setting watchdog Reset pulse length to the highest value + * (256 Pclk cycles) + */ + reg |= 7 << MVMAP2315_WDT_CR_RPL_SHIFT; + + /* setting the watchdog timer to generate a system reset */ + reg &= ~MVMAP2315_WDT_CR_RMOD; + + /* enabling the watchdog timer */ + reg = read32(&mvmap2315_wdt0->wdt_cr); + reg |= MVMAP2315_WDT_CR_EN; + write32(&mvmap2315_wdt0->wdt_cr, reg); + + /* setting watchdog Timeout Range Register */ + reg = timeout_value << MVMAP2315_WDT_TORR_TOP_SHIFT; + write32(&mvmap2315_wdt0->wdt_torr, reg); + + /* resetting the timer */ + reg = 0x76 << MVMAP2315_WDT_CRR_SHIFT; + write32(&mvmap2315_wdt0->wdt_crr, reg); +} + +void reset_sp_watchdog(u32 timeout_value) +{ + u32 reg; + + /* setting watchdog Timeout Range Register */ + reg = timeout_value << MVMAP2315_WDT_TORR_TOP_SHIFT; + write32(&mvmap2315_wdt0->wdt_torr, reg); + + if (read32(&mvmap2315_wdt0->wdt_cr) & MVMAP2315_WDT_CR_EN) { + /* resetting the timer */ + reg = 0x76 << MVMAP2315_WDT_CRR_SHIFT; + write32(&mvmap2315_wdt0->wdt_crr, reg); + } else { + /* enabling the watchdog timer */ + reg = read32(&mvmap2315_wdt0->wdt_cr); + reg |= MVMAP2315_WDT_CR_EN; + write32(&mvmap2315_wdt0->wdt_cr, reg); + } +} + +int should_reset_sp_watchdog(void) +{ + if (read32(&mvmap2315_wdt0->wdt_ccvr) <= 0x1000) + return 0; + + return 1; +}

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Patch set updated for coreboot: spike-riscv: Look for the CBFS in RAM
by Jonathan Neuschäfer 30 Jun '16

30 Jun '16

Jonathan Neuschäfer (j.neuschaefer(a)gmx.net) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15285 -gerrit commit f4492225dc2309fe63811f02486b2fd6daffe40a Author: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Date: Wed Jun 29 21:59:30 2016 +0200 spike-riscv: Look for the CBFS in RAM Change-Id: I98927a70adc45d9aca916bd985932b94287921de Signed-off-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> --- src/arch/riscv/Makefile.inc | 3 --- src/arch/riscv/rom_media.c | 26 -------------------- src/mainboard/emulation/spike-riscv/Makefile.inc | 3 +++ src/mainboard/emulation/spike-riscv/rom_media.c | 30 ++++++++++++++++++++++++ 4 files changed, 33 insertions(+), 29 deletions(-) diff --git a/src/arch/riscv/Makefile.inc b/src/arch/riscv/Makefile.inc index 243fa53..c1c62ef 100644 --- a/src/arch/riscv/Makefile.inc +++ b/src/arch/riscv/Makefile.inc @@ -33,7 +33,6 @@ bootblock-y += trap_util.S bootblock-y += trap_handler.c bootblock-y += virtual_memory.c bootblock-y += boot.c -bootblock-y += rom_media.c bootblock-y += misc.c bootblock-y += \ $(top)/src/lib/memchr.c \ @@ -60,7 +59,6 @@ ifeq ($(CONFIG_ARCH_ROMSTAGE_RISCV),y) romstage-y += boot.c romstage-y += stages.c -romstage-y += rom_media.c romstage-y += misc.c romstage-y += \ $(top)/src/lib/memchr.c \ @@ -90,7 +88,6 @@ ifeq ($(CONFIG_ARCH_RAMSTAGE_RISCV),y) ramstage-y = ramstage-y += trap_handler.c ramstage-y += virtual_memory.c -ramstage-y += rom_media.c ramstage-y += stages.c ramstage-y += misc.c ramstage-y += boot.c diff --git a/src/arch/riscv/rom_media.c b/src/arch/riscv/rom_media.c deleted file mode 100644 index c171307..0000000 --- a/src/arch/riscv/rom_media.c +++ /dev/null @@ -1,26 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2015 Google Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ -#include <boot_device.h> - -/* This assumes that the CBFS resides at 0x0, which is true for the default - * configuration. */ -static const struct mem_region_device boot_dev = - MEM_REGION_DEV_RO_INIT(NULL, CONFIG_ROM_SIZE); - -const struct region_device *boot_device_ro(void) -{ - return &boot_dev.rdev; -} diff --git a/src/mainboard/emulation/spike-riscv/Makefile.inc b/src/mainboard/emulation/spike-riscv/Makefile.inc index dff4758..91c1369 100644 --- a/src/mainboard/emulation/spike-riscv/Makefile.inc +++ b/src/mainboard/emulation/spike-riscv/Makefile.inc @@ -15,11 +15,14 @@ bootblock-y += bootblock.c bootblock-y += uart.c bootblock-y += spike_util.c +bootblock-y += rom_media.c romstage-y += romstage.c romstage-y += uart.c romstage-y += spike_util.c +romstage-y += rom_media.c ramstage-y += uart.c ramstage-y += spike_util.c +ramstage-y += rom_media.c bootblock-y += memlayout.ld romstage-y += memlayout.ld diff --git a/src/mainboard/emulation/spike-riscv/rom_media.c b/src/mainboard/emulation/spike-riscv/rom_media.c new file mode 100644 index 0000000..10952a3 --- /dev/null +++ b/src/mainboard/emulation/spike-riscv/rom_media.c @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 Google Inc. + * Copyright 2016 Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include <boot_device.h> + +/* + * 0x80000000 is this start of RAM. We currently need to load coreboot.rom into + * RAM on SPIKE, because SPIKE doesn't support loading custom code into the + * boot ROM. + */ +static const struct mem_region_device boot_dev = + MEM_REGION_DEV_RO_INIT(0x80000000, CONFIG_ROM_SIZE); + +const struct region_device *boot_device_ro(void) +{ + return &boot_dev.rdev; +}

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Patch set updated for coreboot: util/riscvtools: Provide a tohost symbol so Spike doesn't hang
by Jonathan Neuschäfer 30 Jun '16

30 Jun '16

Jonathan Neuschäfer (j.neuschaefer(a)gmx.net) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15288 -gerrit commit 7200f2f21f88359598c54992cf30fbc80d42c5d1 Author: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Date: Wed Jun 29 21:59:31 2016 +0200 util/riscvtools: Provide a tohost symbol so Spike doesn't hang See https://github.com/riscv/riscv-isa-sim/issues/54 for more information. Change-Id: I8cda8dc07866d395eb3ce5d94df8232840fa8b82 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> --- util/riscvtools/spike-elf.ld | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/util/riscvtools/spike-elf.ld b/util/riscvtools/spike-elf.ld index 341a16f..44114f7 100644 --- a/util/riscvtools/spike-elf.ld +++ b/util/riscvtools/spike-elf.ld @@ -8,4 +8,8 @@ SECTIONS .data : { *(.data) } + + tohost = .; + . = . + 8; + fromhost = .; }

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Patch set updated for coreboot: util/kconfig: Fix gconfig build
by Jonathan Neuschäfer 30 Jun '16

30 Jun '16

Jonathan Neuschäfer (j.neuschaefer(a)gmx.net) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15505 -gerrit commit 1fc08f2dae7acd22e5e54e97ead4434d12579ea6 Author: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Date: Thu Jun 30 00:32:02 2016 +0200 util/kconfig: Fix gconfig build This linker error was the problem: build/util/kconfig/zconf.tab.o: In function `conf_read_simple': /home/jn/dev/coreboot/util/kconfig/confdata.c:413: undefined reference to `kconfig_warnings' /home/jn/dev/coreboot/util/kconfig/confdata.c:413: undefined reference to `kconfig_warnings' build/util/kconfig/zconf.tab.o: In function `sym_calc_value': /home/jn/dev/coreboot/util/kconfig/symbol.c:388: undefined reference to `kconfig_warnings' /home/jn/dev/coreboot/util/kconfig/symbol.c:388: undefined reference to `kconfig_warnings' collect2: error: ld returned 1 exit status /home/jn/dev/coreboot/util/kconfig/Makefile:339: recipe for target 'build/util/kconfig/gconf' failed make: *** [build/util/kconfig/gconf] Error 1 Change-Id: I4a667c7c15b35618fb9ad536f2be5044b8031ab4 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> --- util/kconfig/gconf.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/util/kconfig/gconf.c b/util/kconfig/gconf.c index d0a35b2..faa1c59 100644 --- a/util/kconfig/gconf.c +++ b/util/kconfig/gconf.c @@ -26,6 +26,8 @@ //#define DEBUG +int kconfig_warnings = 0; + enum { SINGLE_VIEW, SPLIT_VIEW, FULL_VIEW };

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Patch set updated for coreboot: spike-riscv: Remove HTIF related code
by Jonathan Neuschäfer 30 Jun '16

30 Jun '16

Jonathan Neuschäfer (j.neuschaefer(a)gmx.net) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15289 -gerrit commit 0dc81dda1518ddc24f5d799264a0fa42a77a93bb Author: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Date: Wed Jun 29 21:59:31 2016 +0200 spike-riscv: Remove HTIF related code The HTIF is deprecated and the newest RISC-V binutils don't know the mtohost/mfromhost CSRs anymore. The SBI implementation still needs to be restructured. Change-Id: I13f01e45b714f1bd919e27b84aff8db772504b1f Signed-off-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> --- src/mainboard/emulation/spike-riscv/spike_util.c | 110 ++--------------------- 1 file changed, 7 insertions(+), 103 deletions(-) diff --git a/src/mainboard/emulation/spike-riscv/spike_util.c b/src/mainboard/emulation/spike-riscv/spike_util.c index fca7d56..358cb44 100644 --- a/src/mainboard/emulation/spike-riscv/spike_util.c +++ b/src/mainboard/emulation/spike-riscv/spike_util.c @@ -55,14 +55,7 @@ uintptr_t mcall_query_memory(uintptr_t id, memory_block_info *p) uintptr_t mcall_send_ipi(uintptr_t recipient) { - //if (recipient >= num_harts) - //return -1; - - if (atomic_swap(&OTHER_HLS(recipient)->ipi_pending, 1) == 0) { - mb(); - write_csr(send_ipi, recipient); - } - + die("mcall_send_ipi is currently not implemented"); return 0; } @@ -79,50 +72,26 @@ uintptr_t mcall_clear_ipi(void) uintptr_t mcall_shutdown(void) { - while (1) write_csr(mtohost, 1); + die("mcall_shutdown is currently not implemented"); return 0; } uintptr_t mcall_set_timer(unsigned long long when) { - write_csr(mtimecmp, when); - clear_csr(mip, MIP_STIP); - set_csr(mie, MIP_MTIP); + die("mcall_set_timer is currently not implemented"); return 0; } uintptr_t mcall_dev_req(sbi_device_message *m) { - if ((m->dev > 0xFFU) | (m->cmd > 0xFFU) | (m->data > 0x0000FFFFFFFFFFFFU)) return -EINVAL; - - while (swap_csr(mtohost, TOHOST_CMD(m->dev, m->cmd, m->data)) != 0); - - m->sbi_private_data = (uintptr_t)HLS()->device_request_queue_head; - HLS()->device_request_queue_head = m; - HLS()->device_request_queue_size++; - + die("mcall_dev_req is currently not implemented"); return 0; } uintptr_t mcall_dev_resp(void) { - htif_interrupt(0, 0); - - sbi_device_message* m = HLS()->device_response_queue_head; - if (m) { - //printm("resp %p\n", m); - sbi_device_message* next = (void*)atomic_read(&m->sbi_private_data); - HLS()->device_response_queue_head = next; - if (!next) { - HLS()->device_response_queue_tail = 0; - - // only clear SSIP if no other events are pending - clear_csr(mip, MIP_SSIP); - mb(); - if (HLS()->ipi_pending) set_csr(mip, MIP_SSIP); - } - } - return (uintptr_t)m; + die("mcall_dev_resp is currently not implemented"); + return 0; } uintptr_t mcall_hart_id(void) @@ -136,74 +105,9 @@ void hls_init(uint32_t hart_id) HLS()->hart_id = hart_id; } -uintptr_t htif_interrupt(uintptr_t mcause, uintptr_t* regs) { - uintptr_t fromhost = swap_csr(mfromhost, 0); - if (!fromhost) - return 0; - - uintptr_t dev = FROMHOST_DEV(fromhost); - uintptr_t cmd = FROMHOST_CMD(fromhost); - uintptr_t data = FROMHOST_DATA(fromhost); - - sbi_device_message* m = HLS()->device_request_queue_head; - sbi_device_message* prev = 0x0; - unsigned long i, n; - for (i = 0, n = HLS()->device_request_queue_size; i < n; i++) { - /* - if (!supervisor_paddr_valid(m, sizeof(*m)) - && EXTRACT_FIELD(read_csr(mstatus), MSTATUS_PRV1) != PRV_M) - panic("htif: page fault"); - */ - - sbi_device_message* next = (void*)m->sbi_private_data; - if (m->dev == dev && m->cmd == cmd) { - m->data = data; - - // dequeue from request queue - if (prev) - prev->sbi_private_data = (uintptr_t)next; - else - HLS()->device_request_queue_head = next; - HLS()->device_request_queue_size = n-1; - m->sbi_private_data = 0; - - // enqueue to response queue - if (HLS()->device_response_queue_tail) - { - HLS()->device_response_queue_tail->sbi_private_data = (uintptr_t)m; - } - else - { - HLS()->device_response_queue_head = m; - } - HLS()->device_response_queue_tail = m; - - // signal software interrupt - set_csr(mip, MIP_SSIP); - return 0; - } - - prev = m; - m = (void*)atomic_read(&m->sbi_private_data); - } - //HLT(); - return 0; - //panic("htif: no record"); -} - uintptr_t mcall_console_putchar(uint8_t ch) { - while (swap_csr(mtohost, TOHOST_CMD(1, 1, ch)) != 0); - while (1) { - uintptr_t fromhost = read_csr(mfromhost); - if (FROMHOST_DEV(fromhost) != 1 || FROMHOST_CMD(fromhost) != 1) { - if (fromhost) - htif_interrupt(0, 0); - continue; - } - write_csr(mfromhost, 0); - break; - } + do_putchar(ch); return 0; }

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Patch set updated for coreboot: Exynos7: Bootblock: Update header with size in blocks
by Stefan Reinauer 30 Jun '16

30 Jun '16

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14903 -gerrit commit 3197375e21ef9cc81ffee08c4012532d253981c0 Author: Akshay Saraswat <akshay.s(a)samsung.com> Date: Fri Sep 5 16:18:01 2014 +0530 Exynos7: Bootblock: Update header with size in blocks BL1 may not always ask for bootblock binary's size in number of bytes rather it may find reading size in number of blocks easier sometimes. Modify the header populating script to mention bootblock size in number of blocks instead of number of bytes whenever asked. BUG=None BRANCH=None TEST=Compiled and booted coreboot over Jazz mainboard with this series Change-Id: Ic8895d7142c70a92a658cba56367231d36908b61 Signed-off-by: Alim Akhtar <alim.akhtar(a)samsung.com> Signed-off-by: Akshay Saraswat <akshay.s(a)samsung.com> --- util/exynos/variable_cksum.py | 43 ++++++++++++++++++++++++++++++++++++------- 1 file changed, 36 insertions(+), 7 deletions(-) diff --git a/util/exynos/variable_cksum.py b/util/exynos/variable_cksum.py index 9725261..4db4f98 100755 --- a/util/exynos/variable_cksum.py +++ b/util/exynos/variable_cksum.py @@ -29,7 +29,7 @@ This utility computes and fills Exynos ROM checksum (for BL1 or BL2). (Algorithm from U-Boot: tools/mkexynosspl.c) -Input: IN OUT +Input: IN OUT <size_in_blocks> Output: @@ -39,21 +39,50 @@ Output: import struct import sys +import argparse -def main(argv): - if len(argv) != 3: - exit('usage: %s IN OUT' % argv[0]) +# Get the number of bytes needed to make _data_ 512 byte alinged +def alignpos(pos, alignbytes): + mask = alignbytes - 1 + return (pos + mask) & ~mask + +def parseargs(): + """Parses arguments and returns results""" + parser = argparse.ArgumentParser() + parser.add_argument("IN", type=str, help="Input file") + parser.add_argument("OUT", type=str, help="Output file") + + parser.add_argument("--blocks", action='store_true', help="Use block as size") + parser.add_argument("--bsize", type=int, help="Size of block to use, default=512", default=512) + + return parser.parse_args() + +def main(): + + args = parseargs() + + in_name = args.IN + out_name = args.OUT - in_name, out_name = argv[1:3] header_format = "<IIII" with open(in_name, "rb") as in_file, open(out_name, "wb") as out_file: data = in_file.read() + size = struct.calcsize(header_format) + len(data) + + if args.blocks: + block_size = args.bsize + if ((size % block_size) != 0): + data = data + (alignpos(size, block_size) - size) * '\0' + count = len(data) + else: + size = (size / block_size) + header = struct.pack(header_format, - struct.calcsize(header_format) + len(data), + size, sum(map(ord, data)), 0, 0) out_file.write(header + data) if __name__ == '__main__': - main(sys.argv) + main()

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New patch to review for coreboot: marvell/mvmap2315: add apmu driver
by hakim giydan 30 Jun '16

30 Jun '16

hakim giydan (hgiydan(a)marvell.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15518 -gerrit commit a06929dd247c59286074ce3c454813a5bd3442f2 Author: Hakim Giydan <hgiydan(a)marvell.com> Date: Wed Jun 29 18:55:45 2016 -0700 marvell/mvmap2315: add apmu driver this driver send and receive command from/to APMU to enable/disable individual power rails. Change-Id: I5ae07849f8432bece8a0ae9066a3f786e6e8d2fe Signed-off-by: Hakim Giydan <hgiydan(a)marvell.com> --- src/soc/marvell/mvmap2315/Makefile.inc | 1 + src/soc/marvell/mvmap2315/apmu.c | 149 +++++++ src/soc/marvell/mvmap2315/include/soc/addressmap.h | 4 + src/soc/marvell/mvmap2315/include/soc/apmu.h | 288 ++++++++++++ src/soc/marvell/mvmap2315/include/soc/clock.h | 2 + src/soc/marvell/mvmap2315/include/soc/power.h | 171 +++++++- src/soc/marvell/mvmap2315/include/soc/pwr_types.h | 487 +++++++++++++++++++++ src/soc/marvell/mvmap2315/power.c | 89 +++- src/soc/marvell/mvmap2315/romstage.c | 20 + 9 files changed, 1205 insertions(+), 6 deletions(-) diff --git a/src/soc/marvell/mvmap2315/Makefile.inc b/src/soc/marvell/mvmap2315/Makefile.inc index ebb0515..a408049 100644 --- a/src/soc/marvell/mvmap2315/Makefile.inc +++ b/src/soc/marvell/mvmap2315/Makefile.inc @@ -26,6 +26,7 @@ ramstage-y += soc.c ramstage-y += stage_entry.S ramstage-y += uart.c +romstage-y += apmu.c romstage-y += assert.c romstage-y += bootrom.c romstage-y += cbmem.c diff --git a/src/soc/marvell/mvmap2315/apmu.c b/src/soc/marvell/mvmap2315/apmu.c new file mode 100644 index 0000000..ce9c85c --- /dev/null +++ b/src/soc/marvell/mvmap2315/apmu.c @@ -0,0 +1,149 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Marvell, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <console/console.h> +#include <soc/apmu.h> +#include <soc/clock.h> + +static int apmu_blocking_cmd(u32 cmd) +{ + u32 reg; + u32 completed_cmd; + u32 success = 0; + u32 timeout_count = 0; + + printk(BIOS_INFO, "Sending cmd: %x.\n", cmd); + + /* Send a sync command with interrupt when complete */ + reg = read32(&mvmap2315_apmu_pwrctl->pwrcmdfifo); + reg = (cmd | MVMAP2315_APMU_PWRCMDFIFO_DONEIRQ); + write32(&mvmap2315_apmu_pwrctl->pwrcmdfifo, cmd); + + while (!(read32(&mvmap2315_apmu_pwrctl->intstatus) & + (MVMAP2315_APMU_ISTCLR_DONE | + MVMAP2315_APMU_ISTCLR_ERROR)) && + (timeout_count < 0x5000)) + timeout_count++; + + if (timeout_count >= 0x5000) { + printk(BIOS_INFO, "Timeout: %d.\n", timeout_count); + return -2; + } + + if (read32(&mvmap2315_apmu_pwrctl->intstatus) & + MVMAP2315_APMU_ISTCLR_DONE) { + completed_cmd = read32(&mvmap2315_apmu_pwrctl->doneirq); + + reg = read32(&mvmap2315_apmu_pwrctl->intstatusclear); + reg = MVMAP2315_APMU_ISTCLR_DONE; + write32(&mvmap2315_apmu_pwrctl->intstatusclear, reg); + + printk(BIOS_INFO, "Completed cmd: %x.\n", completed_cmd); + success = 1; + } else if (read32(&mvmap2315_apmu_pwrctl->intstatus) & + MVMAP2315_APMU_ISTCLR_ERROR) { + completed_cmd = read32(&mvmap2315_apmu_pwrctl->errorirq); + + reg = read32(&mvmap2315_apmu_pwrctl->intstatusclear); + reg = MVMAP2315_APMU_ISTCLR_ERROR; + write32(&mvmap2315_apmu_pwrctl->intstatusclear, reg); + printk(BIOS_INFO, "Error cmd: %x.\n", completed_cmd); + } + + if (success) + return 0; + + return -1; +} + +int apmu_start(u32 first_lcm_bank, u32 last_lcm_bank) +{ + u32 reg; + + printk(BIOS_INFO, "APMU LCM start bank: %d.\n", first_lcm_bank); + printk(BIOS_INFO, "end bank: %d.\n", last_lcm_bank); + + /* Dedicate the specified LCM area to the APMU */ + reg = (last_lcm_bank << MVMAP2315_LCM_END_BANK) + | (first_lcm_bank << MVMAP2315_LCM_START_BANK) + | MVMAP2315_LCM_DIRACCESS_EN; + write32(&mvmap2315_lcm_regs->lcm_access, reg); + + printk(BIOS_INFO, "Release APMU...\r\n"); + + /* Take the APMU out of reset and let it start running */ + reg = read32(&mvmap2315_apmu_clk->apaonclk_apmucpu_clkgenconfig); + reg |= MVMAP2315_APMU_CLK_EN; + write32(&mvmap2315_apmu_clk->apaonclk_apmucpu_clkgenconfig, reg); + + reg = read32(&mvmap2315_apmu_clk->apaonclk_apmucpu_clkgenconfig); + reg |= MVMAP2315_APMU_CLK_RSTN; + write32(&mvmap2315_apmu_clk->apaonclk_apmucpu_clkgenconfig, reg); + + return 0; +} + +int apmu_set_device_state(u32 device, u32 new_state) +{ + u32 pwr_cmd; + + pwr_cmd = MVMAP2315_APMU_PWRCMDFIFO_DONEIRQ; + pwr_cmd |= (2 << MVMAP2315_APMU_PWRCMDFIFO_OPCODE_SHIFT); + pwr_cmd |= (new_state << MVMAP2315_APMU_PWRCMDFIFO_STATE_SHIFT); + pwr_cmd |= (device << MVMAP2315_APMU_PWRCMDFIFO_OBJECT_SHIFT); + + return apmu_blocking_cmd(pwr_cmd); +} + +int apmu_set_pll_state(u32 device, u32 new_state, u32 frequency) +{ + u32 pwr_cmd = 0; + + pwr_cmd = MVMAP2315_APMU_PWRCMDFIFO_DONEIRQ; + pwr_cmd |= (2 << MVMAP2315_APMU_PWRCMDFIFO_OPCODE_SHIFT); + pwr_cmd |= (frequency << MVMAP2315_APMU_PWRCMDFIFO_TARGFREQ_SHIFT); + pwr_cmd |= (new_state << MVMAP2315_APMU_PWRCMDFIFO_STATE_SHIFT); + pwr_cmd |= (device << MVMAP2315_APMU_PWRCMDFIFO_OBJECT_SHIFT); + + return apmu_blocking_cmd(pwr_cmd); +} + +int apmu_set_clock_state(u32 clock, u32 new_state, u32 divider, u32 source) +{ + u32 pwr_cmd = 0; + u32 arg = 0; + + pwr_cmd = MVMAP2315_APMU_PWRCMDFIFO_DONEIRQ; + pwr_cmd |= (1 << MVMAP2315_APMU_PWRCMDFIFO_OPCODE_SHIFT); + + arg = (new_state << 25) | (divider << 12) | + (source << 8) | (clock); + + pwr_cmd |= (arg << MVMAP2315_APMU_PWRCMDFIFO_ARGUMENT_SHIFT); + + return apmu_blocking_cmd(pwr_cmd); +} + +int apmu_declare_s0(void) +{ + u32 pwr_cmd = 0; + + pwr_cmd = MVMAP2315_APMU_PWRCMDFIFO_DONEIRQ; + pwr_cmd |= (0XF << MVMAP2315_APMU_PWRCMDFIFO_OPCODE_SHIFT); + pwr_cmd |= (0X14 << MVMAP2315_APMU_PWRCMDFIFO_ARGUMENT_SHIFT); + + return apmu_blocking_cmd(pwr_cmd); +} diff --git a/src/soc/marvell/mvmap2315/include/soc/addressmap.h b/src/soc/marvell/mvmap2315/include/soc/addressmap.h index 9d20a75..1303cc8 100644 --- a/src/soc/marvell/mvmap2315/include/soc/addressmap.h +++ b/src/soc/marvell/mvmap2315/include/soc/addressmap.h @@ -23,12 +23,16 @@ enum { MVMAP2315_RAM_BASE = 0x00000000, MVMAP2315_CBFS_BASE = 0x00400000, MVMAP2315_BDB_LCM_BASE = 0xE0000000, + MVMAP2315_LOWPWR_REG = 0xE0002000, MVMAP2315_BRM_CBS_MEDIA_TYPE = 0xE0002004, MVMAP2315_BCM_GICD_BASE = 0xE0111000, MVMAP2315_BCM_GICC_BASE = 0xE0112000, MVMAP2315_MAIN_PLL_BASE = 0xE0125000, MVMAP2315_APMU_CLK_BASE = 0xE0125400, + MVMAP2315_APMU_PWRCTL_BASE = 0xE012C000, + MVMAP2315_LCM_REGS_BASE = 0xE0130000, MVMAP2315_GENTIMER_BASE = 0xE0137000, + MVMAP2315_CPU_BASE = 0xE013F200, MVMAP2315_PADWRAP_BASE = 0xE0140000, MVMAP2315_TIMER0_BASE = 0xE1020000, MVMAP2315_MPMU_CLK_BASE = 0xEF000800, diff --git a/src/soc/marvell/mvmap2315/include/soc/apmu.h b/src/soc/marvell/mvmap2315/include/soc/apmu.h new file mode 100644 index 0000000..e8ede68 --- /dev/null +++ b/src/soc/marvell/mvmap2315/include/soc/apmu.h @@ -0,0 +1,288 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Marvell, Inc. + * + * This program is free software; + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#ifndef __SOC_MARVELL_MVMAP2315_APMU_H__ +#define __SOC_MARVELL_MVMAP2315_APMU_H__ + +#include <stdint.h> +#include <stdlib.h> +#include <types.h> + +#include <soc/addressmap.h> + +#define MVMAP2315_APMU_PWRCMDFIFO_DONEIRQ BIT(27) +#define MVMAP2315_APMU_ISTCLR_DONE BIT(30) +#define MVMAP2315_APMU_ISTCLR_ERROR BIT(31) +#define MVMAP2315_APMU_PWRCMDFIFO_OPCODE_SHIFT 28 +#define MVMAP2315_APMU_PWRCMDFIFO_STATE_SHIFT 8 +#define MVMAP2315_APMU_PWRCMDFIFO_OBJECT_SHIFT 0 +#define MVMAP2315_APMU_PWRCMDFIFO_TARGFREQ_SHIFT 12 +#define MVMAP2315_APMU_PWRCMDFIFO_ARGUMENT_SHIFT 0 +struct mvmap2315_apmu_pwrctl_regs { + u32 pwrcmdfifo; + u32 pwrcmdfifostatus; + u8 _reserved0[0x08]; + u32 intstatusset; + u32 intstatusclear; + u32 intstatus; + u8 _reserved1[0x04]; + u32 doneirq; + u32 errorirq; + u32 scratch0; + u32 scratch1; + u8 _reserved2[0x10]; + u32 pmp_spci_rx_int_status; + u32 pmp_spci_rx_int_set; + u32 pmp_spci_rx_int_clear; + u8 _reserved3[0x04]; + u32 pmp_spci_tx_int_status; + u32 pmp_spci_tx_int_set; + u32 pmp_spci_tx_int_clear; + u8 _reserved4[0xa4]; + u32 global_pwrstate; + u8 _reserved5[0x0c]; + u32 a72core0_pwrstate; + u8 _reserved6[0x0c]; + u32 a72core1_pwrstate; + u8 _reserved7[0x0c]; + u32 a72core2_pwrstate; + u8 _reserved8[0x0c]; + u32 a72core3_pwrstate; + u8 _reserved9[0x0c]; + u32 a72l2_pwrstate; + u8 _reserved10[0x0c]; + u32 a2fab_pwrstate; + u8 _reserved11[0x0c]; + u32 mc_pwrstate; + u8 _reserved12[0x0c]; + u32 mc_phy0_pwrstate; + u8 _reserved13[0x0c]; + u32 mc_phy1_pwrstate; + u8 _reserved14[0x0c]; + u32 mc_phy2_pwrstate; + u8 _reserved15[0x0c]; + u32 mc_phy3_pwrstate; + u8 _reserved16[0x0c]; + u32 mcflc_pwrstate; + u8 _reserved17[0x0c]; + u32 mcflc_phy0_pwrstate; + u8 _reserved18[0x0c]; + u32 mcflc_phy1_pwrstate; + u8 _reserved19[0x0c]; + u32 mcflc_phy2_pwrstate; + u8 _reserved20[0x0c]; + u32 mcflc_phy3_pwrstate; + u8 _reserved21[0x0c]; + u32 gpu3dcore0_pwrstate; + u8 _reserved22[0x0c]; + u32 gpu3dcore1_pwrstate; + u8 _reserved23[0x0c]; + u32 gpu3dcore2_pwrstate; + u8 _reserved24[0x0c]; + u32 gpu3dcore3_pwrstate; + u8 _reserved25[0x0c]; + u32 gpu3dl2_pwrstate; + u8 _reserved26[0x0c]; + u32 smmu_pwrstate; + u8 _reserved27[0x0c]; + u32 vpudec_pwrstate; + u8 _reserved28[0x0c]; + u32 jpeg_pwrstate; + u8 _reserved29[0x0c]; + u32 decoder_pwrstate; + u8 _reserved30[0x0c]; + u32 vpuenc_pwrstate; + u8 _reserved31[0x0c]; + u32 vp8_pwrstate; + u8 _reserved32[0x0c]; + u32 vp9_pwrstate; + u8 _reserved33[0x0c]; + u32 zram_pwrstate; + u8 _reserved34[0x0c]; + u32 gpu2d_pwrstate; + u8 _reserved35[0x0c]; + u32 edisplay_pwrstate; + u8 _reserved36[0x0c]; + u32 edp_phy_pwrstate; + u8 _reserved37[0x0c]; + u32 dsi_phy0_pwrstate; + u8 _reserved38[0x0c]; + u32 dsi_phy1_pwrstate; + u8 _reserved39[0x0c]; + u32 display_pwrstate; + u8 _reserved40[0x0c]; + u32 mci_x40_pwrstate; + u8 _reserved41[0x0c]; + u32 mci_x4_phy0_pwrstate; + u8 _reserved42[0x0c]; + u32 mci_x41_pwrstate; + u8 _reserved43[0x0c]; + u32 mci_x4_phy1_pwrstate; + u8 _reserved44[0x0c]; + u32 mci_x42_pwrstate; + u8 _reserved45[0x0c]; + u32 mci_x4_phy2_pwrstate; + u8 _reserved46[0x0c]; + u32 mci_x2_pwrstate; + u8 _reserved47[0x0c]; + u32 mci_x2_phy_pwrstate; + u8 _reserved48[0x0c]; + u32 mci_x10_pwrstate; + u8 _reserved49[0x0c]; + u32 mci_x1_phy0_pwrstate; + u8 _reserved50[0x0c]; + u32 mci_x11_pwrstate; + u8 _reserved51[0x0c]; + u32 mci_x1_phy1_pwrstate; + u8 _reserved52[0x0c]; + u32 mci_x12_pwrstate; + u8 _reserved53[0x0c]; + u32 mci_x1_phy2_pwrstate; + u8 _reserved54[0x0c]; + u32 mci_x13_pwrstate; + u8 _reserved55[0x0c]; + u32 mci_x1_phy3_pwrstate; + u8 _reserved56[0x2c]; + u32 sdmmc_pwrstate; + u8 _reserved57[0x0c]; + u32 emmc_phy_pwrstate; + u8 _reserved58[0x0c]; + u32 sdio_phy0_pwrstate; + u8 _reserved59[0x0c]; + u32 sdio_phy1_pwrstate; + u8 _reserved60[0x0c]; + u32 aes256_pwrstate; + u8 _reserved61[0x0c]; + u32 ap_axi_pwrstate; + u8 _reserved62[0x1c]; + u32 ap_uart0_pwrstate; + u8 _reserved63[0x0c]; + u32 ap_uart1_pwrstate; + u8 _reserved64[0x0c]; + u32 ap_ssp0_pwrstate; + u8 _reserved65[0x0c]; + u32 ap_ssp1_pwrstate; + u8 _reserved66[0x0c]; + u32 ap_i2c0_pwrstate; + u8 _reserved67[0x0c]; + u32 ap_i2c1_pwrstate; + u8 _reserved68[0x0c]; + u32 ap_i2c2_pwrstate; + u8 _reserved69[0x0c]; + u32 ap_i2c3_pwrstate; + u8 _reserved70[0x0c]; + u32 ap_i2c4_pwrstate; + u8 _reserved71[0x0c]; + u32 ap_lcm_pwrstate; + u8 _reserved72[0x0c]; + u32 ap_m2m_pwrstate; + u8 _reserved73[0x0c]; + u32 ap_apb_pwrstate; + u8 _reserved74[0x0c]; + u32 bcm_r4_pwrstate; + u8 _reserved75[0x0c]; + u32 apmu_m4_pwrstate; + u8 _reserved76[0x0c]; + u32 ap_gic_pwrstate; + u8 _reserved77[0x4c]; + u32 cpu_pll_pwrstate; + u8 _reserved78[0x0c]; + u32 mc_pll_pwrstate; + u8 _reserved79[0x0c]; + u32 mcflc_pll_pwrstate; + u8 _reserved80[0x0c]; + u32 a2_pll_pwrstate; + u8 _reserved81[0x0c]; + u32 main_pll_pwrstate; + u8 _reserved82[0x0c]; + u32 gpu_pll0_pwrstate; + u8 _reserved83[0x0c]; + u32 gpu_pll1_pwrstate; + u8 _reserved84[0x0c]; + u32 mipi_pll_pwrstate; + u8 _reserved85[0x0c]; + u32 display_pll_pwrstate; + u8 _reserved86[0x0c]; + u32 avs_vmain_pwrstate; + u8 _reserved87[0x0c]; + u32 avs_vcpu_pwrstate; + u8 _reserved88[0x0c]; + u32 avs_vgpu_pwrstate; + u8 _reserved89[0x0c]; + u32 ap_tsene_pwrstate; + u8 _reserved90[0x0c]; + u32 rng_pwrstate; + u8 _reserved91[0x3c]; + u32 padgroup29_pwrstate; + u8 _reserved92[0x0c]; + u32 padgroup30_pwrstate; + u8 _reserved93[0x0c]; + u32 padgroup31_pwrstate; + u8 _reserved94[0x0c]; + u32 padgroup32_pwrstate; + u8 _reserved95[0x0c]; + u32 padgroup33_pwrstate; +}; + +check_member(mvmap2315_apmu_pwrctl_regs, padgroup33_pwrstate, 0x750); +static struct mvmap2315_apmu_pwrctl_regs * const mvmap2315_apmu_pwrctl + = (void *)MVMAP2315_APMU_PWRCTL_BASE; + +#define MVMAP2315_LCM_DIRACCESS_EN BIT(0) +#define MVMAP2315_LCM_START_BANK BIT(2) +#define MVMAP2315_LCM_END_BANK BIT(3) +struct mvmap2315_lcm_regs { + u32 lcm_scfg; + u32 lcm_access; + u8 _reserved0[0x08]; + u32 lcm_ctrl_bank_mstr_id_wr0; + u32 lcm_ctrl_bank_mstr_id_wr1; + u32 lcm_ctrl_bank_mstr_id_wr2; + u32 lcm_ctrl_bank_mstr_id_wr3; + u32 lcm_ctrl_bank_mstr_id_wr4; + u32 lcm_ctrl_bank_mstr_id_wr5; + u8 _reserved1[0x28]; + u32 lcm_ctrl_bank_mask_id_wr0; + u32 lcm_ctrl_bank_mask_id_wr1; + u32 lcm_ctrl_bank_mask_id_wr2; + u32 lcm_ctrl_bank_mask_id_wr3; + u32 lcm_ctrl_bank_mask_id_wr4; + u32 lcm_ctrl_bank_mask_id_wr5; + u8 _reserved2[0x28]; + u32 lcm_ctrl_bank_mstr_id_rd0; + u32 lcm_ctrl_bank_mstr_id_rd1; + u32 lcm_ctrl_bank_mstr_id_rd2; + u32 lcm_ctrl_bank_mstr_id_rd3; + u32 lcm_ctrl_bank_mstr_id_rd4; + u32 lcm_ctrl_bank_mstr_id_rd5; + u8 _reserved3[0x28]; + u32 lcm_ctrl_bank_mask_id_rd0; + u32 lcm_ctrl_bank_mask_id_rd1; + u32 lcm_ctrl_bank_mask_id_rd2; + u32 lcm_ctrl_bank_mask_id_rd3; + u32 lcm_ctrl_bank_mask_id_rd4; + u32 lcm_ctrl_bank_mask_id_rd5; +}; + +check_member(mvmap2315_lcm_regs, lcm_ctrl_bank_mask_id_rd5, 0xe4); +static struct mvmap2315_lcm_regs * const mvmap2315_lcm_regs + = (void *)MVMAP2315_LCM_REGS_BASE; + +int apmu_start(u32 first_lcm_bank, u32 last_lcm_bank); +int apmu_set_device_state(u32 device, u32 new_state); +int apmu_set_pll_state(u32 device, u32 new_state, u32 frequency); +int apmu_set_clock_state(u32 clock, u32 new_state, u32 divider, u32 source); +int apmu_declare_s0(void); + +#endif /* __SOC_MARVELL_MVMAP2315_APMU_H__ */ diff --git a/src/soc/marvell/mvmap2315/include/soc/clock.h b/src/soc/marvell/mvmap2315/include/soc/clock.h index a982198..7fd15b1 100644 --- a/src/soc/marvell/mvmap2315/include/soc/clock.h +++ b/src/soc/marvell/mvmap2315/include/soc/clock.h @@ -72,6 +72,8 @@ static struct mvmap2315_main_pll_regs * const mvmap2315_pll #define MVMAP2315_UART_CLK_EN BIT(1) #define MVMAP2315_SDMMC_CLK_RSTN BIT(0) +#define MVMAP2315_APMU_CLK_EN BIT(1) +#define MVMAP2315_APMU_CLK_RSTN BIT(0) struct mvmap2315_apmu_clk_regs { u32 uartfracdivcfg0; u8 _reserved0[0x0c]; diff --git a/src/soc/marvell/mvmap2315/include/soc/power.h b/src/soc/marvell/mvmap2315/include/soc/power.h index 308f657..154a3c0 100644 --- a/src/soc/marvell/mvmap2315/include/soc/power.h +++ b/src/soc/marvell/mvmap2315/include/soc/power.h @@ -3,12 +3,12 @@ * * Copyright (C) 2016 Marvell, Inc. * - * This program is free software; you can redistribute it and/or modify + * This program is free software; * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. + * the Free Software Foundation; * * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of + * but WITHOUT ANY WARRANTY; * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ @@ -17,8 +17,170 @@ #include <stdint.h> #include <stdlib.h> +#include <types.h> -enum boot_paths { +#include <soc/addressmap.h> + +#define MVMAP2315_LOWPWR_FLAG BIT(4) + +#define MVMAP2315_APGENCFG_SYSBARDISABLE BIT(1) +#define MVMAP2315_APGENCFG_BROADCASTINNER BIT(2) +#define MVMAP2315_APGENCFG_BROADCASTOUTER BIT(3) +#define MVMAP2315_APGENCFG_BROADCASTCACHEMAINT BIT(4) +#define MVMAP2315_APGENCFG_BROADCASTCACHEMAINTPOU BIT(5) +#define MVMAP2315_APCORECFG0_AA64NAA32 BIT(4) +struct mvmap2315_cpu_regs { + u32 fuse00; + u32 fuse01; + u32 fuse02; + u32 fuse03; + u32 fuse04; + u32 fuse05; + u32 fuse06; + u32 fuse07; + u32 fuse10; + u32 fuse11; + u32 fuse12; + u32 fuse13; + u32 fuse14; + u32 fuse15; + u32 fuse16; + u32 fuse17; + u8 _reserved0[0x20]; + u32 fuse20; + u32 fuse21; + u32 fuse22; + u32 fuse23; + u32 fuse24; + u32 fuse25; + u32 fuse26; + u32 fuse27; + u32 fuse30; + u32 fuse31; + u32 fuse32; + u32 fuse33; + u32 fuse34; + u32 fuse35; + u32 fuse36; + u32 fuse37; + u32 fuse40; + u32 fuse41; + u32 fuse42; + u32 fuse43; + u32 fuse44; + u32 fuse45; + u32 fuse46; + u32 fuse47; + u32 fuse50; + u32 fuse51; + u32 fuse52; + u32 fuse53; + u32 fuse54; + u32 fuse55; + u32 fuse56; + u32 fuse57; + u32 fuse60; + u32 fuse61; + u32 fuse62; + u32 fuse63; + u32 fuse64; + u32 fuse65; + u32 fuse66; + u32 fuse67; + u32 fuse70; + u32 fuse71; + u32 fuse72; + u32 fuse73; + u32 fuse74; + u32 fuse75; + u32 fuse76; + u32 fuse77; + u32 fuse80; + u32 fuse81; + u32 fuse82; + u32 fuse83; + u32 fuse84; + u32 fuse85; + u32 fuse86; + u32 fuse87; + u32 fuse90; + u32 fuse91; + u32 fuse92; + u32 fuse93; + u32 fuse94; + u32 fuse95; + u32 fuse96; + u32 fuse97; + u32 fuse100; + u32 fuse101; + u32 fuse102; + u32 fuse103; + u32 fuse104; + u32 fuse105; + u32 fuse106; + u32 fuse107; + u32 fuse110; + u32 fuse111; + u32 fuse112; + u32 fuse113; + u32 fuse114; + u32 fuse115; + u32 fuse116; + u32 fuse117; + u32 fuse120; + u32 fuse121; + u32 fuse122; + u32 fuse123; + u32 fuse124; + u32 fuse125; + u32 fuse126; + u32 fuse127; + u32 fuse130; + u32 fuse131; + u32 fuse132; + u32 fuse133; + u32 fuse134; + u32 fuse135; + u32 fuse136; + u32 fuse137; + u32 fuse140; + u32 fuse141; + u32 fuse142; + u32 fuse143; + u32 fuse144; + u32 fuse145; + u32 fuse146; + u32 fuse147; + u32 fuse150; + u32 fuse151; + u32 fuse152; + u32 fuse153; + u32 fuse154; + u32 fuse155; + u32 fuse156; + u32 fuse157; + u32 apgencfg; + u32 apcorecfg0; + u32 apcorecfg1; + u32 apcorecfg2; + u32 apcorecfg3; + u32 rvbaraddr_low0; + u32 rvbaraddr_low1; + u32 rvbaraddr_low2; + u32 rvbaraddr_low3; + u8 _reserved1[0x10]; + u32 rvbaraddr_high0; + u32 rvbaraddr_high1; + u32 rvbaraddr_high2; + u32 rvbaraddr_high3; + u32 highvecremap; +}; + +check_member(mvmap2315_cpu_regs, highvecremap, 0x264); +static struct mvmap2315_cpu_regs * const mvmap2315_cpu + = (void *)MVMAP2315_CPU_BASE; + +enum boot_options { NO_BOOT = 0, CHARGING_SCREEN = 1, FULL_BOOT = 2 @@ -28,6 +190,7 @@ void no_boot(void); void full_boot(void); void charging_screen(void); void start_ap_cores(void *entry); +void mcu_start(void); u32 get_boot_path(void); #endif /* __SOC_MARVELL_MVMAP2315_POWER_H__ */ diff --git a/src/soc/marvell/mvmap2315/include/soc/pwr_types.h b/src/soc/marvell/mvmap2315/include/soc/pwr_types.h new file mode 100644 index 0000000..04493e6 --- /dev/null +++ b/src/soc/marvell/mvmap2315/include/soc/pwr_types.h @@ -0,0 +1,487 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Marvell, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __SOC_MARVELL_MVMAP2315_ADDRESS_PWR_TYPES_H__ +#define __SOC_MARVELL_MVMAP2315_ADDRESS_PWR_TYPES_H__ + +#include <stdint.h> +#include <stdlib.h> + +enum sleepstatet { + S0 = 0, + S3 = 3, + S5 = 5 +}; + +enum devicestatet { + D0 = 0, + D1 = 1, + D2 = 2, + D3 = 3, + D3WAKEINT = 11 +}; + +enum clockstatet { + NOCHANGE = 0, + GATED = 1, + RUNNING = 2 +}; + +enum clocksscstatet { + SSCOFF = 0, + SSCONDOWN1 = 1, + SSCONDOWN2 = 2, + SSCONDOWN3 = 3 +}; + +enum apllfreqt { + APLL_NOCHANGE = 0, + APLL_589P824 = 1, + APLL_541P9008 = 2, + APLL_451P584 = 3 +}; + +enum clocktypest { + CLKMUX_C = 0, + CLKGEN_C = 1, + CLKGEN_W_CLKGATE_C = 2, + CLKGATE_C = 4, + CLKGATEDIV2_C = 5, + CLKGATEDIV4_C = 6, + CLKGATEDIV8_C = 7, + CLKFRAC_W_CLKGATE_C = 8, + DIV2_C = 9, + DIV4_C = 10, + SSPLL_C = 11, + APLL_C = 12, + REFCLK25M_C = 13, + REFCLK32K_C = 14, + DROCLK_C = 15 +}; + +enum devicetypest { + DIGLOGIC_D = 0, + DIGLOGIC_WSRAM_D = 2, + DIGLOGIC_PI_D = 3, + DIGLOGIC_WSRAM_PI_D = 4, + PHY_D = 5, + SSPLL_D = 6, + APLL_D = 7, + TSENSOR_D = 8, + EFUSE_D = 9, + AVS_D = 10, + ANA_GRP_D = 11, + PADGROUP_D = 12, + MCIREFDRV_D = 13, + TESTTYPE_D = 14 +}; + +enum gaclockst { + CPUCLK = 0, + CPUBUSCLK = 1, + CPUTSCLK = 2, + TRACECLK0 = 3, + MCCLK2X = 4, + MCCLK = 5, + MCFLCCLK2X = 6, + MCFLCCLK = 7, + BUSRINGCLK = 8, + SNOOPCLK = 9, + MCBUSCLK = 10, + MCBUSCLK_A2 = 11, + MCCFGCLK = 12, + MCCFGCLK_A2 = 13, + CPUCFGCLK = 14, + CPUCFGCLK_A2 = 15, + VPUENC_VP8CLK = 16, + VPUENC_VP9CLK = 17, + BUSCLK2X_A2 = 18, + BUSCLK = 19, + BUSCLK_MCIX2_0 = 20, + BUSCLK_MCIX1_0 = 21, + BUSCLK_MCIX1_1 = 22, + BUSCLK_MCIX1_2 = 23, + BUSCLK_MCIX1_3 = 24, + BUSCLK_A2 = 25, + BUSCLK_AES = 26, + BUSCLK_APAONBUS_HS = 27, + ACLK2X_A2 = 28, + ACLK_A2 = 29, + ACLK_VPU = 30, + ACLK_MCIX4_0 = 31, + ACLK_MCIX4_1 = 32, + ACLK_MCIX4_2 = 33, + ACLK_EDISPLAY = 34, + ACLK_DISPLAY = 35, + CFGCLK = 36, + CFGCLK_A2 = 37, + HCLK_A2 = 38, + HCLK_EDISPLAY = 39, + HCLK_DISPLAY = 40, + HCLK_VPU = 41, + APAONCLK = 42, + APAONCLK_APMUCPU = 43, + APAONCLK_SDMMC = 44, + APAONCLK_LCM = 45, + APAONCLK_M2M = 46, + APAONCLK_APB = 47, + BISTCLK = 48, + BCMCPUCLK = 49, + ZRAMCLK = 50, + ZRAMCLK_A2 = 51, + SDMMCBASECLK = 52, + JPEGCLK = 53, + UARTCLKGEN = 54, + UARTCLK_0 = 55, + UARTCLK_1 = 56, + SSPCLK_0 = 57, + SSPCLK_1 = 58, + I2CCLK_0 = 59, + I2CCLK_1 = 60, + I2CCLK_2 = 61, + I2CCLK_3 = 62, + I2CCLK_4 = 63, + GPU2DBUSCLK = 64, + GPU2DBUSCLK_A2 = 65, + GPU2DCFGCLK = 66, + GPU2DCFGCLK_A2 = 67, + GPU2DCORECLK = 68, + GPU3DBUSCORECLK = 69, + GPU3DBUSCORECLK_A2 = 70, + GPU3DCFGCLK = 71, + GPU3DCFGCLK_A2 = 72, + GPU3DSHADERCLK = 73, + VPUDECCLK = 74, + VPUDECM3CLK = 75, + DISPLAYPIPECLK = 76, + EDISPLAYPIPECLK = 77, + EDISPLAYMIPIBITCLK = 78, + EDISPLAYAUXREFCLK = 79, + EDISPLAYAUXCLK = 80, + EDISPLAYPIXELCLK = 81, + DMICCLK = 82, + SSPACLK_0 = 83, + SSPACLK_1 = 84, + SSPACLK_2 = 85, + TSENCLK = 86, + AP_TSENCLK = 87, + CLK32K = 88, + REFCLK = 89, + REFCLK_UARTGEN = 90, + REFCLK_UART0 = 91, + REFCLK_UART1 = 92, + REFCLK_I2C0 = 93, + REFCLK_I2C1 = 94, + REFCLK_I2C2 = 95, + REFCLK_I2C3 = 96, + REFCLK_I2C4 = 97, + REFCLK_I2C5 = 98, + REFCLK_SSP0 = 99, + REFCLK_SSP1 = 100, + REFCLK_SSPA0 = 101, + REFCLK_SSPA1 = 102, + REFCLK_SSPA2 = 103, + MCUCLK = 104, + MCUCLK_CDMA = 105, + MCUCLK_BSPI = 106, + MCUCLK_OWI = 107, + MCUCLK_UART0 = 108, + MCUCLK_UART1 = 109, + MCUCLK_SSP0 = 110, + MCUCLK_SSP1 = 111, + MCUCLK_SSPA0 = 112, + MCUCLK_SSPA1 = 113, + MCUCLK_SSPA2 = 114, + MCUCLK_DMIC0 = 115, + MCUCLK_DMIC1 = 116, + MCUCLK_DMIC2 = 117, + MCUCLK_DMIC3 = 118, + DMIC_DCLK0 = 119, + DMIC_DCLK1 = 120, + DMIC_DCLK2 = 121, + DMIC_DCLK3 = 122, + DMIC_ENGDETCLK = 123, + M4CLK = 124, + M4CLK_LCM0 = 125, + M4CLK_LCM1 = 126, + M4CLK_LCM2 = 127, + CPUDBGCLK = 128, + M4CLK_BIST = 129, + BSPICLK = 130, + CPU_MUXCLK = 131, + DISPLAY_MUXCLK = 132, + CPU_PLL_CLK = 133, + MC_PLL_CLK = 134, + MCFLC_PLL_CLK = 135, + A2_PLL_CLK = 136, + MAIN_PLL_CLK = 137, + GPU_PLL0_CLK = 138, + GPU_PLL1_CLK = 139, + MIPI_PLL_CLK = 140, + DISPLAY_PLL_CLK = 141, + APLL0_CLK = 142, + APLL1_CLK = 143, + REFCLK25M = 144, + REFCLK32K = 145, + DROCLK = 146, + GACLOCKS_END = 147 +}; + +enum gasrcselclockst { + SRCSEL_NO_CHANGE = 0, + SRCSEL_CPU_PLL = 1, + SRCSEL_MC_PLL = 2, + SRCSEL_MCFLC_PLL = 3, + SRCSEL_A2_PLL = 4, + SRCSEL_MAIN_PLL = 5, + SRCSEL_GPU_PLL0 = 6, + SRCSEL_GPU_PLL1 = 7, + SRCSEL_MIPI_PLL = 8, + SRCSEL_DISPLAY_PLL = 9, + SRCSEL_APLL0 = 10, + SRCSEL_APLL1 = 11, + SRCSEL_REFCLK25M = 12, + SRCSEL_REFCLK32K = 13, + SRCSEL_DROCLK = 14, + SRCSEL_SELECT_INVALID = 15 +}; + +enum gadevicest { + APCPU_0 = 0, + APCPU_1 = 1, + APCPU_2 = 2, + APCPU_3 = 3, + APCPU_L2 = 4, + A2 = 5, + MC = 6, + DDRPHY_0 = 7, + DDRPHY_1 = 8, + DDRPHY_2 = 9, + DDRPHY_3 = 10, + MCFLC = 11, + MCFLCPHY_0 = 12, + MCFLCPHY_1 = 13, + MCFLCPHY_2 = 14, + MCFLCPHY_3 = 15, + GPU3D_0 = 16, + GPU3D_1 = 17, + GPU3D_2 = 18, + GPU3D_3 = 19, + GPU3D_L2 = 20, + VPUDEC = 21, + JPEG = 22, + DECODER = 23, + VPUENC = 24, + VP8 = 25, + VP9 = 26, + ZRAM = 27, + GPU2D = 28, + EDISPLAY = 29, + EDP_PHY = 30, + DSI0_PHY = 31, + DSI1_PHY = 32, + DISPLAY = 33, + MCI0 = 34, + MCI0_PHY = 35, + MCI1 = 36, + MCI1_PHY = 37, + MCI2 = 38, + MCI2_PHY = 39, + MCI3 = 40, + MCI3_PHY = 41, + MCI4 = 42, + MCI4_PHY = 43, + MCI5 = 44, + MCI5_PHY = 45, + MCI6 = 46, + MCI6_PHY = 47, + MCI7 = 48, + MCI7_PHY = 49, + SDMMC = 50, + EMMC_PHY = 51, + SDIO1_PHY = 52, + SDIO2_PHY = 53, + AES256 = 54, + AP_AXI_HS = 55, + AP_UART0 = 56, + AP_UART1 = 57, + AP_SSP0 = 58, + AP_SSP1 = 59, + AP_I2C0 = 60, + AP_I2C1 = 61, + AP_I2C2 = 62, + AP_I2C3 = 63, + AP_I2C4 = 64, + AP_M2M = 65, + AP_APB = 66, + AP_GIC = 67, + MCU_BOOTSPI = 68, + MCU_UART0 = 69, + MCU_UART1 = 70, + MCU_SSP0 = 71, + MCU_SSP1 = 72, + MCU_I2C0 = 73, + MCU_I2C1 = 74, + MCU_I2C2 = 75, + MCU_I2C3 = 76, + MCU_I2C4 = 77, + MCU_I2C5 = 78, + MCU_OWI = 79, + MCU_DMIC = 80, + MCU_DMIC0 = 81, + MCU_DMIC1 = 82, + MCU_DMIC2 = 83, + MCU_DMIC3 = 84, + MCU_CDMA = 85, + MCU_SSPA0 = 86, + MCU_SSPA1 = 87, + MCU_SSPA2 = 88, + MCU_LCM0 = 89, + MCU_LCM1 = 90, + MCU_LCM2 = 91, + TRACE_DEBUG = 92, + CPU_PLL = 93, + MC_PLL = 94, + MCFLC_PLL = 95, + A2_PLL = 96, + MAIN_PLL = 97, + GPU_PLL0 = 98, + GPU_PLL1 = 99, + MIPI_PLL = 100, + DISPLAY_PLL = 101, + APLL0 = 102, + APLL1 = 103, + ANA_GRP = 104, + AVS_VMCU = 105, + AVS_VMAIN = 106, + AVS_VCPU = 107, + AVS_VGPU = 108, + AP_TSENE = 109, + MCU_TSENE = 110, + RBIST_EFUSE = 111, + MCICLK0 = 112, + MCICLK1 = 113, + MCICLK2 = 114, + MCICLK3 = 115, + MCICLK4 = 116, + MCICLK5 = 117, + PG4 = 118, + PG18 = 119, + PG19 = 120, + PG20 = 121, + PG21 = 122, + PG22 = 123, + PG23 = 124, + PG24 = 125, + PG25 = 126, + PG26 = 127, + PG27 = 128, + PG29 = 129, + PG30 = 130, + PG31 = 131, + PG32 = 132, + PG33 = 133, + GADEVICES_END = 134 +}; + +enum pmuerrort { + PMUERRORNONE = 0, + PMUERRORGENERAL = 1, + PMUERROROPCODE = 2, + PMUERROROBJECT = 3, + PMUERRORMAX_FREQ = 4, + PMUERRORLIMIT = 5, + PMUERRORUNGATABLE = 6, + PMUERRORFREQ = 7, + PMUERRORCLKSRC = 9, + PMUERRORMAX_DIV = 10, + PMUERRORSHELFMAX = 11, + PMUERRORSTATE = 12 +}; + +enum opcodet { + SYNC = 0, + CHANGECLOCKSTATE = 1, + CHANGEDEVICEPOWERSTATE = 2, + CHANGESOCPOWERSTATE = 3, + SETWAKEUPSOURCE = 4, + EXECUTELIST = 5, + READCLOCKSTATE = 6, + READDEVICEPOWERSTATE = 7 +}; + +enum executelistcmdt { + BUILDLISTSHELF = 0, + ENDOFLIST = 1, + BLOCKLISTUNTILWAKE = 2, + PROCESSLISTSHELF = 3, + PROCESSLISTAPLCM = 4, + PROCESSLISTMCULCM = 5 +}; + +enum wakeupsourcet { + RTCINT1 = 0, + RTCINT2 = 1, + RTC1SINT = 2, + MCUTIMERINT0 = 3, + MCUTIMERINT1 = 4, + MCUTIMERINT2 = 5, + MCUTIMERINT3 = 6, + MCUTIMERINT4 = 7, + MCUTIMERINT5 = 8, + MCUTIMERINT6 = 9, + MCUTIMERINT7 = 10, + APTIMERINT0 = 11, + APTIMERINT1 = 12, + APTIMERINT2 = 13, + APTIMERINT3 = 14, + APTIMERINT4 = 15, + APTIMERINT5 = 16, + APTIMERINT6 = 17, + APTIMERINT7 = 18, + MCUGPIOINT0 = 19, + MCUGPIOINT1 = 20, + MCUGPIOINT2 = 21, + MCUGPIOINT3 = 22, + MCUGPIOINT4 = 23, + MCUGPIOINT5 = 24, + MCUGPIOINT6 = 25, + MCUGPIOINT7 = 26, + APGPIOINT0 = 27, + APGPIOINT1 = 28, + APGPIOINT2 = 29, + APGPIOINT3 = 30, + APGPIOINT4 = 31, + APGPIOINT5 = 32, + APGPIOINT6 = 33, + APGPIOINT7 = 34, + KEYBINT = 35, + ENGDETINT = 36, + MCIREMOTE0 = 37, + MCIREMOTE1 = 38, + MCIREMOTE2 = 39, + MCIREMOTE3 = 40, + MCIREMOTE4 = 41, + MCIREMOTE5 = 42, + MCIREMOTE6 = 43, + MCIREMOTE7 = 44, + EMMCPHY = 45, + SDIOPHY1 = 46, + SDIOPHY2 = 47, + SDMMCWAKEINT = 48, + WAKEINTINVALID = 49 +}; + +#endif /* __SOC_MARVELL_MVMAP2315_ADDRESS_PWR_TYPES_H__ */ diff --git a/src/soc/marvell/mvmap2315/power.c b/src/soc/marvell/mvmap2315/power.c index 578fb51..bf7ffda 100644 --- a/src/soc/marvell/mvmap2315/power.c +++ b/src/soc/marvell/mvmap2315/power.c @@ -13,11 +13,95 @@ * GNU General Public License for more details. */ +#include <arch/io.h> +#include <console/console.h> +#include <soc/apmu.h> +#include <soc/assert.h> +#include <soc/clock.h> #include <soc/power.h> +#include <soc/pwr_types.h> + +static void enable_sys_power(void) +{ + int result = 0; + + /* Start the PLLs */ + result |= apmu_set_pll_state(MAIN_PLL, D0, 2000); + result |= apmu_set_pll_state(CPU_PLL, D0, 2400); + result |= apmu_set_pll_state(MC_PLL, D0, 3200); + result |= apmu_set_pll_state(MCFLC_PLL, D0, 2133); + result |= apmu_set_pll_state(A2_PLL, D0, 1800); + result |= apmu_set_pll_state(GPU_PLL0, D0, 2000); + result |= apmu_set_pll_state(GPU_PLL1, D0, 2400); + result |= apmu_set_pll_state(MIPI_PLL, D0, 2000); + result |= apmu_set_pll_state(DISPLAY_PLL, D0, 1800); + + /* Start the peripheral devices */ + result |= apmu_set_device_state(A2, D0); + result |= apmu_set_device_state(MC, D0); + result |= apmu_set_device_state(SDMMC, D0); + result |= apmu_set_device_state(AES256, D0); + result |= apmu_set_device_state(AP_AXI_HS, D0); + result |= apmu_set_device_state(AP_UART0, D0); + result |= apmu_set_device_state(AP_UART1, D0); + result |= apmu_set_device_state(AP_M2M, D0); + result |= apmu_set_device_state(AP_APB, D0); + result |= apmu_set_device_state(AP_GIC, D0); + + if (result != 0) + __assert("ERRORS DURING POWER-on", __FILE__, __LINE__); +} void start_ap_cores(void *entry) { - /*TODO: start_ap_cores */ + int result = 0; + u32 reg; + + printk(BIOS_INFO, "Writing APGenCfg, initial value is %x.\n", + read32(&mvmap2315_cpu->apgencfg)); + + reg = read32(&mvmap2315_cpu->apgencfg); + + reg |= MVMAP2315_APGENCFG_SYSBARDISABLE; + reg |= MVMAP2315_APGENCFG_BROADCASTINNER; + reg &= ~MVMAP2315_APGENCFG_BROADCASTOUTER; + reg |= MVMAP2315_APGENCFG_BROADCASTCACHEMAINT; + reg |= MVMAP2315_APGENCFG_BROADCASTCACHEMAINTPOU; + + write32(&mvmap2315_cpu->apgencfg, reg); + + printk(BIOS_INFO, "Writes complete, APGenCfg is now %x.\n", + read32(&mvmap2315_cpu->apgencfg)); + + result |= apmu_set_device_state(APCPU_L2, D0); + + reg = read32(&mvmap2315_cpu->apcorecfg0); + reg |= MVMAP2315_APCORECFG0_AA64NAA32; + write32(&mvmap2315_cpu->apcorecfg0, reg); + + write32(&mvmap2315_cpu->rvbaraddr_low0, ((uintptr_t)entry) >> 2); + write32(&mvmap2315_cpu->rvbaraddr_high0, 0); + + result |= apmu_set_device_state(APCPU_0, D0); + + if (result != 0) + __assert("ERRORS DURING POWER-on", __FILE__, __LINE__); +} + +void mcu_start(void) +{ + u32 reg; + + apmu_set_pll_state(APLL0, D0, APLL_589P824); + apmu_set_clock_state(M4CLK, NOCHANGE, 4, SRCSEL_APLL0); + + reg = read32(&mvmap2315_mpmu_clk->resetmcu); + reg &= ~MVMAP2315_MCU_RST_EN; + write32(&mvmap2315_mpmu_clk->resetmcu, reg); + + reg = read32(&mvmap2315_mpmu_clk->resetmcu); + reg |= MVMAP2315_MCU_RST_EN; + write32(&mvmap2315_mpmu_clk->resetmcu, reg); } void no_boot(void) @@ -32,7 +116,8 @@ void charging_screen(void) void full_boot(void) { - /*TODO: impelement full_boot */ + printk(BIOS_INFO, "Powering up the system.\n"); + enable_sys_power(); } u32 get_boot_path(void) diff --git a/src/soc/marvell/mvmap2315/romstage.c b/src/soc/marvell/mvmap2315/romstage.c index bc9172e..f4c64d2 100644 --- a/src/soc/marvell/mvmap2315/romstage.c +++ b/src/soc/marvell/mvmap2315/romstage.c @@ -13,10 +13,12 @@ * GNU General Public License for more details. */ +#include <arch/io.h> #include <console/console.h> #include <console/uart.h> #include <program_loading.h> #include <soc/addressmap.h> +#include <soc/apmu.h> #include <soc/assert.h> #include <soc/bdb.h> #include <soc/bootrom.h> @@ -63,6 +65,22 @@ void main(void) printk(BIOS_INFO, "loading and validating APMU FIRMWARE\n"); load_and_validate_image(&bdb_info, APMU_FIRMWARE); + /* Temporary fix for emulation testing only + * TODO: remove in real silicon + */ + write32(&mvmap2315_apmu_pwrctl->scratch0, 0x900dc0de); + + apmu_start(4, 5); + + if (!(read32((void *)MVMAP2315_LOWPWR_REG) & MVMAP2315_LOWPWR_FLAG)) { + printk(BIOS_INFO, "loading and validating MCU FIRMWARE\n"); + load_and_validate_image(&bdb_info, MCU_FIRMWARE); + mcu_start(); + } else { + printk(BIOS_INFO, "low power restart. skip MCU code load\n"); + printk(BIOS_INFO, "TODO: check MCU Firmware hash\n"); + } + boot_path = get_boot_path(); switch (boot_path) { @@ -79,6 +97,8 @@ void main(void) break; } + apmu_declare_s0(); + timestamp_add_now(TS_END_ROMSTAGE); run_ramstage();

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Patch merged into coreboot/master: soc/apollolake: Expose a function to read pmc bar
by gerrit＠coreboot.org 30 Jun '16

30 Jun '16

the following patch was just integrated into master: commit 9a0c9ac912b4bc4248cdada2889a13e48a06d28d Author: Shaunak Saha <shaunak.saha(a)intel.com> Date: Mon Jun 27 23:00:15 2016 -0700 soc/apollolake: Expose a function to read pmc bar This patch exposes a function to read pmc bar. PMC bar is read in function read_pmc_mmio_bar which is defined static in file pmutil.c. This patch exposes that functionality to call it from other files. BUG=chrome-os-partner:53438 TEST= Read the PMC bar value properly from outside pmutil file. Change-Id: I26ee13e6ab95d3a8991c7f8ea4b3856ceb015d10 Signed-off-by: Shaunak Saha <shaunak.saha(a)intel.com> Reviewed-on: https://review.coreboot.org/15460 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See https://review.coreboot.org/15460 for details. -gerrit

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Patch set updated for coreboot: intel/i210: Change API for function mainboard_get_mac_address()
by Werner Zeh 30 Jun '16

30 Jun '16

Werner Zeh (werner.zeh(a)siemens.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15516 -gerrit commit d12ac269b74c62a0961d6a6ecde3cea8c1f2ce54 Author: Werner Zeh <werner.zeh(a)siemens.com> Date: Wed Jun 29 07:53:47 2016 +0200 intel/i210: Change API for function mainboard_get_mac_address() The function mainboard_get_mac_address() is used to get a MAC address for a given i210 PCI device. Instead of passing pure numbers for PCI bus, device and function pass the device pointer to this function. In this way the function can retrieve the needed values itself as well as have the pointer to the device tree so that PCI path can be evaluated there. Change-Id: I2335d995651baa5e23a0448f5f32310dcd394f9b Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- src/drivers/intel/i210/i210.c | 10 +--------- src/drivers/intel/i210/i210.h | 8 ++++++++ src/mainboard/siemens/mc_tcu3/mainboard.c | 5 ++--- src/vendorcode/siemens/hwilib/hwilib.h | 5 +++-- 4 files changed, 14 insertions(+), 14 deletions(-) diff --git a/src/drivers/intel/i210/i210.c b/src/drivers/intel/i210/i210.c index c5e0c4e..c55eecc 100644 --- a/src/drivers/intel/i210/i210.c +++ b/src/drivers/intel/i210/i210.c @@ -14,20 +14,13 @@ */ #include "i210.h" -#include <device/device.h> #include <console/console.h> #include <device/pci.h> #include <device/pci_ids.h> #include <device/pci_ops.h> #include <string.h> -#include <types.h> #include <delay.h> -/* We need one function we can call to get a MAC address to use */ -/* This function can be coded somewhere else but must exist. */ -extern enum cb_err mainboard_get_mac_address(uint16_t bus, uint8_t devfn, - uint8_t mac[6]); - /* This is a private function to wait for a bit mask in a given register */ /* To avoid endless loops, a time-out is implemented here. */ static int wait_done(uint32_t* reg, uint32_t mask) @@ -202,8 +195,7 @@ static void init(struct device *dev) enum cb_err status; /*Check first whether there is a valid MAC address available */ - status = mainboard_get_mac_address(dev->bus->subordinate, - dev->path.pci.devfn, adr_to_set); + status = mainboard_get_mac_address(dev, adr_to_set); if (status != CB_SUCCESS) { printk(BIOS_ERR, "I210: No valid MAC address found\n"); return; diff --git a/src/drivers/intel/i210/i210.h b/src/drivers/intel/i210/i210.h index b19b584..e3179b7 100644 --- a/src/drivers/intel/i210/i210.h +++ b/src/drivers/intel/i210/i210.h @@ -16,6 +16,9 @@ #ifndef _INTEL_I210_H_ #define _INTEL_I210_H_ +#include <types.h> +#include <device/device.h> + #define I210_PCI_MEM_BAR_OFFSET 0x10 #define I210_REG_EECTRL 0x12010 /* Offset for EEPROM control reg */ #define I210_FLUPD 0x800000 /* Start flash update bit */ @@ -38,4 +41,9 @@ #define I210_CHECKSUM_ERROR 0x00000010 #define I210_FLASH_UPDATE_ERROR 0x00000020 +/* We need one function we can call to get a MAC address to use */ +/* This function can be coded somewhere else but must exist. */ +extern enum cb_err mainboard_get_mac_address(struct device *dev, + uint8_t mac[6]); + #endif /* _INTEL_I210_H_ */ diff --git a/src/mainboard/siemens/mc_tcu3/mainboard.c b/src/mainboard/siemens/mc_tcu3/mainboard.c index 009c34d..9ac6dc0 100644 --- a/src/mainboard/siemens/mc_tcu3/mainboard.c +++ b/src/mainboard/siemens/mc_tcu3/mainboard.c @@ -35,12 +35,11 @@ /** \brief This function will search for a MAC address which can be assigned * to a MACPHY. - * @param pci_bdf Bus, device and function of the given PCI-device + * @param dev pointer to PCI device * @param mac buffer where to store the MAC address * @return cb_err CB_ERR or CB_SUCCESS */ -enum cb_err mainboard_get_mac_address(uint16_t bus, uint8_t devfn, - uint8_t mac[6]) +extern enum cb_err mainboard_get_mac_address(struct device *dev, uint8_t mac[6]) { uint8_t mac_adr[6]; uint32_t i; diff --git a/src/vendorcode/siemens/hwilib/hwilib.h b/src/vendorcode/siemens/hwilib/hwilib.h index d858091..9ccb3fe 100644 --- a/src/vendorcode/siemens/hwilib/hwilib.h +++ b/src/vendorcode/siemens/hwilib/hwilib.h @@ -17,6 +17,7 @@ #define SIEMENS_HWI_LIB_H_ #include <types.h> +#include <device/device.h> /* Declare all supported fields which can be get with hwilib. */ @@ -136,6 +137,6 @@ enum cb_err hwilib_find_blocks (const char *hwi_filename); uint32_t hwilib_get_field (hwinfo_field_t field, uint8_t *data, uint32_t maxlen); /* This functions needs to be implemented for every mainboard that uses i210. */ -enum cb_err mainboard_get_mac_address(uint16_t bus, uint8_t devfn, - uint8_t mac[6]); +extern enum cb_err mainboard_get_mac_address(struct device *dev, + uint8_t mac[6]); #endif /* SIEMENS_HWI_LIB_H_ */

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Patch set updated for coreboot: siemens/mc_bdx1: Set up MAC address for available i210 MACs
by Werner Zeh 30 Jun '16

30 Jun '16

Werner Zeh (werner.zeh(a)siemens.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15517 -gerrit commit ec51d012fed9d7da81e515f77448efe8754c88e5 Author: Werner Zeh <werner.zeh(a)siemens.com> Date: Thu Jun 30 08:21:17 2016 +0200 siemens/mc_bdx1: Set up MAC address for available i210 MACs Enable the usage of DRIVER_INTEL_I210 and provide a function to search for a valid MAC address for all i210 devices using hwilib. Change-Id: Ic0f4f1579364cf5b0111334a05a8a0926785318b Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- src/mainboard/siemens/mc_bdx1/Kconfig | 2 + src/mainboard/siemens/mc_bdx1/mainboard.c | 74 +++++++++++++++++++++++++++++++ 2 files changed, 76 insertions(+) diff --git a/src/mainboard/siemens/mc_bdx1/Kconfig b/src/mainboard/siemens/mc_bdx1/Kconfig index e33b14a..f947f3d 100644 --- a/src/mainboard/siemens/mc_bdx1/Kconfig +++ b/src/mainboard/siemens/mc_bdx1/Kconfig @@ -9,6 +9,8 @@ config BOARD_SPECIFIC_OPTIONS select TSC_MONOTONIC_TIMER select HAVE_FSP_BIN if FSP_PACKAGE_DEFAULT select CBFS_AUTOGEN_ATTRIBUTES + select USE_SIEMENS_HWILIB + select DRIVER_INTEL_I210 config MAINBOARD_DIR string diff --git a/src/mainboard/siemens/mc_bdx1/mainboard.c b/src/mainboard/siemens/mc_bdx1/mainboard.c index 58da036..ccfb471 100644 --- a/src/mainboard/siemens/mc_bdx1/mainboard.c +++ b/src/mainboard/siemens/mc_bdx1/mainboard.c @@ -3,6 +3,7 @@ * * Copyright (C) 2007-2009 coresystems GmbH * Copyright (C) 2011 Google Inc. + * Copyright (C) 2016 Siemens AG * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -29,7 +30,10 @@ #include <arch/io.h> #include <arch/interrupt.h> #include <boot/coreboot_tables.h> +#include <hwilib.h> +#define MAX_PATH_DEPTH 14 +#define MAX_NUM_MAPPINGS 10 /* * mainboard_enable is executed as first thing after enumerate_buses(). * This is the earliest point to add customization. @@ -38,6 +42,76 @@ static void mainboard_enable(device_t dev) { } +/** \brief This function can decide if a given MAC address is valid or not. + * Currently, addresses filled with 0xff or 0x00 are not valid. + * @param mac Buffer to the MAC address to check + * @return 0 if address is not valid, otherwise 1 + */ +static uint8_t is_mac_adr_valid(uint8_t mac[6]) +{ + uint8_t buf[6]; + + memset(buf, 0, sizeof(buf)); + if (!memcmp(buf, mac, sizeof(buf))) + return 0; + memset(buf, 0xff, sizeof(buf)); + if (!memcmp(buf, mac, sizeof(buf))) + return 0; + return 1; +} + /** \brief This function will search for a MAC address which can be assigned + * to a MACPHY. + * @param dev pointer to PCI device + * @param mac buffer where to store the MAC address + * @return cb_err CB_ERR or CB_SUCCESS + */ +extern enum cb_err mainboard_get_mac_address(struct device *dev, uint8_t mac[6]) +{ + struct bus *parent = dev->bus; + uint8_t buf[16], mapping[16], i = 0, chain_len = 0; + + memset(buf, 0, sizeof(buf)); + memset(mapping, 0, sizeof(mapping)); + + /* The first entry in the tree is the device itself. */ + buf[0] = dev->path.pci.devfn; + for (i = 1; i < MAX_PATH_DEPTH && parent->dev->bus->subordinate; i++) { + buf[i] = parent->dev->path.pci.devfn; + parent = parent->dev->bus; + } + if (i == MAX_PATH_DEPTH) { + /* The path is deeper than MAX_PATH_DEPTH devices, error. */ + printk(BIOS_ERR, "Too many bridges for %s\n", dev_path(dev)); + return CB_ERR; + } + chain_len = i; + /* Now construct the mapping based on the device chain starting from */ + /* root bridge device to the device itself. */ + mapping[0] = 1; + mapping[1] = chain_len; + for (i = 1; i <= chain_len; i++) + mapping[i + 3] = buf[chain_len - i]; + + /* Open main hwinfo block */ + if (hwilib_find_blocks("hwinfo.hex") != CB_SUCCESS) + return CB_ERR; + /* Now try to find a valid MAC address in hwinfo for this mapping.*/ + for (i = 0; i < MAX_NUM_MAPPINGS; i++) { + if ((hwilib_get_field(XMac1Mapping + i, buf, 16) == 16) && + !(memcmp(buf, mapping, chain_len + 4))) { + /* There is a matching mapping available, get MAC address. */ + if ((hwilib_get_field(XMac1 + i, mac, 6) == 6) && + (is_mac_adr_valid(mac))) { + return CB_SUCCESS; + } else { + return CB_ERR; + } + } else + continue; + } + /* No MAC address found for */ + return CB_ERR; +} struct chip_operations mainboard_ops = { .enable_dev = mainboard_enable,

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coreboot-gerrit June 2016