coreboot-gerrit May 2016

coreboot-gerrit@coreboot.org

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Patch merged into coreboot/master: nb/intel/x4x: Add DMI/EP init
by gerrit＠coreboot.org 31 May '16

31 May '16

the following patch was just integrated into master: commit a090ae04c285c4086973e826a36fe87dfeb74d9e Author: Damien Zammit <damien(a)zamaudio.com> Date: Sat May 21 01:56:01 2016 +1000 nb/intel/x4x: Add DMI/EP init The values were obtained from vendor bios at runtime. I am not 100% sure of the sequence required to initiate them, but guessed from the gm45 code. There may be some status bytes needed to be polled during the sequence that is missing, but as I don't have bios writer's datasheet it's very hard for me to know. Change-Id: Idd205e0bab5f75e01c6e3a5dc320c08639f52db8 Signed-off-by: Damien Zammit <damien(a)zamaudio.com> Reviewed-on: https://review.coreboot.org/14925 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/14925 for details. -gerrit

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Patch merged into coreboot/master: mb/gigabyte/ga-g41m-es2l: Fix ACPI IRQ settings for SATA
by gerrit＠coreboot.org 31 May '16

31 May '16

the following patch was just integrated into master: commit 2b2f465fcb1afe4960c613b8ca91e868c64592d4 Author: Damien Zammit <damien(a)zamaudio.com> Date: Wed May 11 19:08:33 2016 +1000 mb/gigabyte/ga-g41m-es2l: Fix ACPI IRQ settings for SATA Previously, due to a bug in devicetree and incorrect IRQ settings in ACPI, SATA controller would not initialize any HDDs in the OS, even though it worked in SeaBIOS. The devicetree setting is not needed because SATA must function in "plain" mode on this board, as "combined" mode does not work at all. Change-Id: I0036c4734de00b84cc3d64f38e4b1fd80fd1a25d Signed-off-by: Damien Zammit <damien(a)zamaudio.com> Reviewed-on: https://review.coreboot.org/14776 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/14776 for details. -gerrit

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Patch set updated for coreboot: intel/wifi: Add support for generating SSDT table
by Duncan Laurie 31 May '16

31 May '16

Duncan Laurie (dlaurie(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15019 -gerrit commit bfcbd0b3080e00aa4dab1f504532cee00d678626 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Wed May 11 14:05:07 2016 -0700 intel/wifi: Add support for generating SSDT table Intel WiFi devices that support wake-on-wifi need to declare a Power Resource for this wake pin. Typically this has been done with a static declaration in the DSDT for each mainboard. By adding it to the existing intel/wifi driver it can be done based on a configuration register in the devicetree. Additionally the WiFi regulatory domain can be set in the SSDT directly instead of needing to use NVS to pass the value to the DSDT. Also add device IDs for Wilkins Peak 2 and Stone Peak 2 devices that are found on Chromebooks, and clean up a long line and some comment formatting. This was tested by booting on an HP Chromebook 13 device and comparing that the output in the SSDT matches what used to be in the DSDT. The WRDD value is read from VPD, if present, not from devicetree.cb. devicetree.cb: device pci 1c.0 on chip drivers/intel/wifi register "wake" = "GPE0_DW0_16" device pci 00.0 on end end end SSDT.dsl: Scope (\_SB.PCI0.RP01) { Device (WIFI) { Name (_UID, Zero) Name (_DDN, "Intel WiFi") Name (_ADR, 0x00000000) Name (_PRW, Package () { 16, 3 }) Name (WRDD, Package () { Zero, Package () { 0x00000007, 0x00004150 } }) } } Change-Id: I8b5c916f1a04742507dc1ecc9a20c19d3822b18c Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/drivers/intel/wifi/chip.h | 3 ++ src/drivers/intel/wifi/wifi.c | 88 ++++++++++++++++++++++++++++++++++++------- 2 files changed, 78 insertions(+), 13 deletions(-) diff --git a/src/drivers/intel/wifi/chip.h b/src/drivers/intel/wifi/chip.h new file mode 100644 index 0000000..117d39c --- /dev/null +++ b/src/drivers/intel/wifi/chip.h @@ -0,0 +1,3 @@ +struct drivers_intel_wifi_config { + unsigned wake; /* Wake pin for ACPI _PRW */ +}; diff --git a/src/drivers/intel/wifi/wifi.c b/src/drivers/intel/wifi/wifi.c index 5ae5498..d2def8b 100644 --- a/src/drivers/intel/wifi/wifi.c +++ b/src/drivers/intel/wifi/wifi.c @@ -14,12 +14,16 @@ * GNU General Public License for more details. */ +#include <arch/acpi_device.h> +#include <arch/acpigen.h> #include <console/console.h> #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> #include <smbios.h> #include <string.h> +#include <wrdd.h> +#include "chip.h" static int smbios_write_wifi(struct device *dev, int *handle, unsigned long *current) @@ -32,15 +36,17 @@ static int smbios_write_wifi(struct device *dev, int *handle, char eos[2]; } __attribute__((packed)); - struct smbios_type_intel_wifi *t = (struct smbios_type_intel_wifi *)*current; + struct smbios_type_intel_wifi *t = + (struct smbios_type_intel_wifi *)*current; int len = sizeof(struct smbios_type_intel_wifi); memset(t, 0, sizeof(struct smbios_type_intel_wifi)); t->type = 0x85; t->length = len - 2; t->handle = *handle; - /* Intel wifi driver expects this string to be in the table 0x85 - with PCI IDs enumerated below. + /* + * Intel wifi driver expects this string to be in the table 0x85 + * with PCI IDs enumerated below. */ t->str = smbios_add_string(t->eos, "KHOIHGIUCCHHII"); @@ -50,30 +56,86 @@ static int smbios_write_wifi(struct device *dev, int *handle, return len; } +#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) +static void intel_wifi_fill_ssdt(struct device *dev) +{ + struct drivers_intel_wifi_config *config = dev->chip_info; + const char *path = acpi_device_path(dev->bus->dev); + u32 address; + + if (!path) + return; + + /* Device */ + acpigen_write_scope(path); + acpigen_write_device(acpi_device_name(dev)); + acpigen_write_name_integer("_UID", 0); + acpigen_write_name_string("_DDN", dev->chip_ops->name); + + /* Address */ + address = PCI_SLOT(dev->path.pci.devfn) & 0xffff; + address <<= 16; + address |= PCI_FUNC(dev->path.pci.devfn) & 0xffff; + acpigen_write_name_dword("_ADR", address); + + /* Wake capabilities */ + if (config->wake) + acpigen_write_PRW(config->wake, 3); + + /* Fill regulatory domain structure */ + wifi_regulatory_domain_write_acpi(); + + acpigen_pop_len(); /* Device */ + acpigen_pop_len(); /* Scope */ + + printk(BIOS_INFO, "%s.%s: %s %s\n", path, acpi_device_name(dev), + dev->chip_ops->name, dev_path(dev)); +} + +static const char *intel_wifi_acpi_name(struct device *dev) +{ + return "WIFI"; +} +#endif + static struct pci_operations pci_ops = { .set_subsystem = pci_dev_set_subsystem, }; struct device_operations device_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = pci_dev_init, - .scan_bus = 0, - .enable = 0, - .get_smbios_data = smbios_write_wifi, - .ops_pci = &pci_ops, + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = pci_dev_init, + .get_smbios_data = smbios_write_wifi, + .ops_pci = &pci_ops, +#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) + .acpi_name = &intel_wifi_acpi_name, + .acpi_fill_ssdt_generator = &intel_wifi_fill_ssdt, +#endif }; - static const unsigned short pci_device_ids[] = { 0x0084, 0x0085, 0x0089, 0x008b, 0x008e, 0x0090, 0x0886, 0x0888, 0x0891, 0x0893, 0x0895, 0x088f, 0x4236, 0x4237, 0x4238, 0x4239, 0x423b, 0x423d, - 0 }; + 0x08b1, 0x08b2, /* Wilkins Peak 2 */ + 0x095a, 0x095b, /* Stone Peak 2 */ + 0 +}; static const struct pci_driver pch_intel_wifi __pci_driver = { .ops = &device_ops, .vendor = PCI_VENDOR_ID_INTEL, .devices = pci_device_ids, }; + +static void intel_wifi_enable(struct device *dev) +{ + dev->ops = &device_ops; +} + +struct chip_operations drivers_intel_wifi_ops = { + CHIP_NAME("Intel WiFi") + .enable_dev = &intel_wifi_enable +};

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Patch set updated for coreboot: wrdd: Add function to generate WRDD ACPI object
by Duncan Laurie 31 May '16

31 May '16

Duncan Laurie (dlaurie(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15018 -gerrit commit f04c9463cd8dbd829e313bfbd4d458b68c0a7801 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Wed May 11 13:52:43 2016 -0700 wrdd: Add function to generate WRDD ACPI object Add a function to generate the expected ACPI WRDD object into the SSDT at boot time instead of adding statically to the DSDT at build time. The country identifier is still read out of the Chrome OS VPD if found, otherwise it uses the default regulatory domain constant. This does not yet remove the existing static code, that will happen after the mainboards are converted to use this driver instead. The resulting object looks like: Name (WRDD, Package () { Zero, /* Revision */ Package () { 0x00000007, /* WiFi domain type */ 0x00004150, /* Default country identifier */ } }) Change-Id: I3222eca723c52fe74a004aa7bac7167264249fd1 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/include/wrdd.h | 10 +++++++++- src/lib/wrdd.c | 26 ++++++++++++++++++++++++++ 2 files changed, 35 insertions(+), 1 deletion(-) diff --git a/src/include/wrdd.h b/src/include/wrdd.h index 97fa5dc..8306b2e 100644 --- a/src/include/wrdd.h +++ b/src/include/wrdd.h @@ -18,6 +18,12 @@ #include <stdint.h> +/* WRDD Spec Revision */ +#define WRDD_REVISION 0x0 + +/* Domain type */ +#define WRDD_DOMAIN_TYPE_WIFI 0x7 + /* Default regulatory domain ID */ #define WRDD_DEFAULT_REGULATORY_DOMAIN 0x4150 /* INDONESIA regulatory domain ID */ @@ -26,5 +32,7 @@ /* Retrieve the regulatory domain information */ uint16_t wifi_regulatory_domain(void); -#endif /* _WRDD_H_ */ +/* Write ACPI WRDD Object */ +void wifi_regulatory_domain_write_acpi(void); +#endif /* _WRDD_H_ */ diff --git a/src/lib/wrdd.c b/src/lib/wrdd.c index da082f8..a26722c 100644 --- a/src/lib/wrdd.c +++ b/src/lib/wrdd.c @@ -14,9 +14,35 @@ * GNU General Public License for more details. */ +#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) +#include <arch/acpigen.h> +#endif #include <wrdd.h> uint16_t __attribute__((weak)) wifi_regulatory_domain(void) { return WRDD_DEFAULT_REGULATORY_DOMAIN; } + +#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) +void wifi_regulatory_domain_write_acpi(void) +{ + /* + * Name ("WRDD", Package () { + * 0, // Revision + * Package () { + * 0x00000007, // Domain Type, 7:WiFi + * 0x00000000, // Country Identifier + * } + * }) + */ + acpigen_write_name("WRDD"); + acpigen_write_package(2); + acpigen_write_integer(WRDD_REVISION); + acpigen_write_package(2); + acpigen_write_dword(WRDD_DOMAIN_TYPE_WIFI); + acpigen_write_dword(wifi_regulatory_domain()); + acpigen_pop_len(); + acpigen_pop_len(); +} +#endif

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New patch to review for coreboot: soc/intel/common: Add _OSC method
by Hannah Williams 31 May '16

31 May '16

Hannah Williams (hannah.williams(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15021 -gerrit commit 1e7ed8ab2a3f65b79b1c30795159be3839966e94 Author: Hannah Williams <hannah.williams(a)intel.com> Date: Wed May 18 13:45:20 2016 -0700 soc/intel/common: Add _OSC method Not masking any bits in Operating System Capabilities, which means we support all the capabilities that OS passed in Arg3 Change-Id: Ib87915e18e305db41b52891ac5430201dda64bb5 Signed-off-by: Hannah Williams <hannah.williams(a)intel.com> --- src/soc/intel/common/acpi/osc.asl | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/src/soc/intel/common/acpi/osc.asl b/src/soc/intel/common/acpi/osc.asl new file mode 100644 index 0000000..749efd8 --- /dev/null +++ b/src/soc/intel/common/acpi/osc.asl @@ -0,0 +1,31 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Method (_OSC, 4) +{ + /* Check for proper GUID */ + If (LEqual (Arg0, ToUUID ("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) + { + /* Let OS control everything */ + Return (Arg3) + } + Else + { + /* Unrecognized UUID */ + CreateDWordField (Arg3, 0, CDW1) + Or (CDW1, 4, CDW1) + Return (Arg3) + } +}

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New patch to review for coreboot: intel/fsp2.0: Add END_OF_FIRMWARE in enum fsp_notify_phase
by Hannah Williams 31 May '16

31 May '16

Hannah Williams (hannah.williams(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15020 -gerrit commit b770201dac855f475b4377cc3ba197d4aa35f5a1 Author: Hannah Williams <hannah.williams(a)intel.com> Date: Fri Apr 29 14:40:40 2016 -0700 intel/fsp2.0: Add END_OF_FIRMWARE in enum fsp_notify_phase Change-Id: Ib39e828c6e3145957ecc2dacc1f72de793165514 Signed-off-by: Hannah Williams <hannah.williams(a)intel.com> --- src/drivers/intel/fsp2_0/include/fsp/api.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/drivers/intel/fsp2_0/include/fsp/api.h b/src/drivers/intel/fsp2_0/include/fsp/api.h index d49fc42..a7b9951 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/api.h +++ b/src/drivers/intel/fsp2_0/include/fsp/api.h @@ -47,7 +47,8 @@ enum fsp_boot_mode { enum fsp_notify_phase { AFTER_PCI_ENUM = 0x20, - READY_TO_BOOT = 0x40 + READY_TO_BOOT = 0x40, + END_OF_FIRMWARE = 0xF0 };

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New patch to review for coreboot: intel/wifi: Add support for generating SSDT table
by Duncan Laurie 31 May '16

31 May '16

Duncan Laurie (dlaurie(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15019 -gerrit commit c41106118308a948d9f3a0f7c759f835c40e53ef Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Wed May 11 14:05:07 2016 -0700 intel/wifi: Add support for generating SSDT table Intel WiFi devices that support wake-on-wifi need to declare a Power Resource for this wake pin. Typically this has been done with a static declaration in the DSDT for each mainboard. By adding it to the existing intel/wifi driver it can be done based on a configuration register in the devicetree. Additionally the WiFi regulatory domain can be set in the SSDT directly instead of needing to use NVS to pass the value to the DSDT. Also add device IDs for Wilkins Peak 2 and Stone Peak 2 devices that are found on Chromebooks, and clean up a long line and some comment formatting. This was tested by booting on an HP Chromebook 13 device and comparing that the output in the SSDT matches what used to be in the DSDT. The WRDD value is read from VPD, if present, not from devicetree.cb. devicetree.cb: device pci 1c.0 on chip drivers/intel/wifi register "wake" = "GPE0_DW0_16" device pci 00.0 on end end end SSDT.dsl: Scope (\_SB.PCI0.RP01) { Device (WIFI) { Name (_UID, Zero) Name (_DDN, "Intel WiFi") Name (_ADR, 0x00000000) Name (_PRW, Package () { 16, 3 }) Name (WRDD, Package () { Zero, Package () { 0x00000007, 0x00004150 } }) } } Change-Id: I8b5c916f1a04742507dc1ecc9a20c19d3822b18c Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/drivers/intel/wifi/chip.h | 3 ++ src/drivers/intel/wifi/wifi.c | 88 ++++++++++++++++++++++++++++++++++++------- 2 files changed, 78 insertions(+), 13 deletions(-) diff --git a/src/drivers/intel/wifi/chip.h b/src/drivers/intel/wifi/chip.h new file mode 100644 index 0000000..117d39c --- /dev/null +++ b/src/drivers/intel/wifi/chip.h @@ -0,0 +1,3 @@ +struct drivers_intel_wifi_config { + unsigned wake; /* Wake pin for ACPI _PRW */ +}; diff --git a/src/drivers/intel/wifi/wifi.c b/src/drivers/intel/wifi/wifi.c index 5ae5498..d2def8b 100644 --- a/src/drivers/intel/wifi/wifi.c +++ b/src/drivers/intel/wifi/wifi.c @@ -14,12 +14,16 @@ * GNU General Public License for more details. */ +#include <arch/acpi_device.h> +#include <arch/acpigen.h> #include <console/console.h> #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> #include <smbios.h> #include <string.h> +#include <wrdd.h> +#include "chip.h" static int smbios_write_wifi(struct device *dev, int *handle, unsigned long *current) @@ -32,15 +36,17 @@ static int smbios_write_wifi(struct device *dev, int *handle, char eos[2]; } __attribute__((packed)); - struct smbios_type_intel_wifi *t = (struct smbios_type_intel_wifi *)*current; + struct smbios_type_intel_wifi *t = + (struct smbios_type_intel_wifi *)*current; int len = sizeof(struct smbios_type_intel_wifi); memset(t, 0, sizeof(struct smbios_type_intel_wifi)); t->type = 0x85; t->length = len - 2; t->handle = *handle; - /* Intel wifi driver expects this string to be in the table 0x85 - with PCI IDs enumerated below. + /* + * Intel wifi driver expects this string to be in the table 0x85 + * with PCI IDs enumerated below. */ t->str = smbios_add_string(t->eos, "KHOIHGIUCCHHII"); @@ -50,30 +56,86 @@ static int smbios_write_wifi(struct device *dev, int *handle, return len; } +#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) +static void intel_wifi_fill_ssdt(struct device *dev) +{ + struct drivers_intel_wifi_config *config = dev->chip_info; + const char *path = acpi_device_path(dev->bus->dev); + u32 address; + + if (!path) + return; + + /* Device */ + acpigen_write_scope(path); + acpigen_write_device(acpi_device_name(dev)); + acpigen_write_name_integer("_UID", 0); + acpigen_write_name_string("_DDN", dev->chip_ops->name); + + /* Address */ + address = PCI_SLOT(dev->path.pci.devfn) & 0xffff; + address <<= 16; + address |= PCI_FUNC(dev->path.pci.devfn) & 0xffff; + acpigen_write_name_dword("_ADR", address); + + /* Wake capabilities */ + if (config->wake) + acpigen_write_PRW(config->wake, 3); + + /* Fill regulatory domain structure */ + wifi_regulatory_domain_write_acpi(); + + acpigen_pop_len(); /* Device */ + acpigen_pop_len(); /* Scope */ + + printk(BIOS_INFO, "%s.%s: %s %s\n", path, acpi_device_name(dev), + dev->chip_ops->name, dev_path(dev)); +} + +static const char *intel_wifi_acpi_name(struct device *dev) +{ + return "WIFI"; +} +#endif + static struct pci_operations pci_ops = { .set_subsystem = pci_dev_set_subsystem, }; struct device_operations device_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = pci_dev_init, - .scan_bus = 0, - .enable = 0, - .get_smbios_data = smbios_write_wifi, - .ops_pci = &pci_ops, + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = pci_dev_init, + .get_smbios_data = smbios_write_wifi, + .ops_pci = &pci_ops, +#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) + .acpi_name = &intel_wifi_acpi_name, + .acpi_fill_ssdt_generator = &intel_wifi_fill_ssdt, +#endif }; - static const unsigned short pci_device_ids[] = { 0x0084, 0x0085, 0x0089, 0x008b, 0x008e, 0x0090, 0x0886, 0x0888, 0x0891, 0x0893, 0x0895, 0x088f, 0x4236, 0x4237, 0x4238, 0x4239, 0x423b, 0x423d, - 0 }; + 0x08b1, 0x08b2, /* Wilkins Peak 2 */ + 0x095a, 0x095b, /* Stone Peak 2 */ + 0 +}; static const struct pci_driver pch_intel_wifi __pci_driver = { .ops = &device_ops, .vendor = PCI_VENDOR_ID_INTEL, .devices = pci_device_ids, }; + +static void intel_wifi_enable(struct device *dev) +{ + dev->ops = &device_ops; +} + +struct chip_operations drivers_intel_wifi_ops = { + CHIP_NAME("Intel WiFi") + .enable_dev = &intel_wifi_enable +};

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New patch to review for coreboot: wrdd: Add function to generate WRDD ACPI object
by Duncan Laurie 31 May '16

31 May '16

Duncan Laurie (dlaurie(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15018 -gerrit commit 2e78515d1c7b70aacc31aebd4e19653e8be9c9c9 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Wed May 11 13:52:43 2016 -0700 wrdd: Add function to generate WRDD ACPI object Add a function to generate the expected ACPI WRDD object into the SSDT at boot time instead of adding statically to the DSDT at build time. The country identifier is still read out of the Chrome OS VPD if found, otherwise it uses the default regulatory domain constant. This does not yet remove the existing static code, that will happen after the mainboards are converted to use this driver instead. The resulting object looks like: Name (WRDD, Package () { Zero, /* Revision */ Package () { 0x00000007, /* WiFi domain type */ 0x00004150, /* Default country identifier */ } }) Change-Id: I3222eca723c52fe74a004aa7bac7167264249fd1 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/include/wrdd.h | 10 +++++++++- src/lib/wrdd.c | 22 ++++++++++++++++++++++ 2 files changed, 31 insertions(+), 1 deletion(-) diff --git a/src/include/wrdd.h b/src/include/wrdd.h index 97fa5dc..8306b2e 100644 --- a/src/include/wrdd.h +++ b/src/include/wrdd.h @@ -18,6 +18,12 @@ #include <stdint.h> +/* WRDD Spec Revision */ +#define WRDD_REVISION 0x0 + +/* Domain type */ +#define WRDD_DOMAIN_TYPE_WIFI 0x7 + /* Default regulatory domain ID */ #define WRDD_DEFAULT_REGULATORY_DOMAIN 0x4150 /* INDONESIA regulatory domain ID */ @@ -26,5 +32,7 @@ /* Retrieve the regulatory domain information */ uint16_t wifi_regulatory_domain(void); -#endif /* _WRDD_H_ */ +/* Write ACPI WRDD Object */ +void wifi_regulatory_domain_write_acpi(void); +#endif /* _WRDD_H_ */ diff --git a/src/lib/wrdd.c b/src/lib/wrdd.c index da082f8..874f194 100644 --- a/src/lib/wrdd.c +++ b/src/lib/wrdd.c @@ -14,9 +14,31 @@ * GNU General Public License for more details. */ +#include <arch/acpigen.h> #include <wrdd.h> uint16_t __attribute__((weak)) wifi_regulatory_domain(void) { return WRDD_DEFAULT_REGULATORY_DOMAIN; } + +void wifi_regulatory_domain_write_acpi(void) +{ + /* + * Name ("WRDD", Package () { + * 0, // Revision + * Package () { + * 0x00000007, // Domain Type, 7:WiFi + * 0x00000000, // Country Identifier + * } + * }) + */ + acpigen_write_name("WRDD"); + acpigen_write_package(2); + acpigen_write_integer(WRDD_REVISION); + acpigen_write_package(2); + acpigen_write_dword(WRDD_DOMAIN_TYPE_WIFI); + acpigen_write_dword(wifi_regulatory_domain()); + acpigen_pop_len(); + acpigen_pop_len(); +}

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New patch to review for coreboot: generic: Add a Maxim 98357A codec driver
by Duncan Laurie 31 May '16

31 May '16

Duncan Laurie (dlaurie(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15017 -gerrit commit 9204eb0f591c87b6650ec3d8a5de0f4b0910e0d5 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Wed May 11 11:27:47 2016 -0700 generic: Add a Maxim 98357A codec driver The Maxim Integrated 98357A codec is an I2S slave device that has no control channel for configuration and instead provides a GPIO that is used for channel selection and power down. This means it does not fit into a bus hierarchy easily and is instead represented as a generic device and found with a static bus scan using the devicetree. This driver provides configuration options for passing the "sdmode" GPIO descriptor as well as a second option for "sdmode delay" which can configure the timing of the sdmode toggling in relation to the I2S channel output. In addition an GPIO can be provided to indicate to the driver whether this device is present or not. This can be used for board designs that may have different codec possibilities that are selected by HW strap. Sample usage for this device driver: device pci 1f.3 on chip drivers/generic/max98357a register "sdmode_gpio" = "ACPI_GPIO_OUTPUT(GPP_C6)" register "sdmode_delay" = "100" device generic 0 on end end end Will result in the following code in the SSDT: Scope (\_SB.PCI0.HDAS) { Device (MAXM) { Name (_HID, "MX98357A") Name (_UID, Zero) Name (_DDN, "Maxim Integrated 98357A Amplifier") Method (_STA) { Return (0xF) } Name (_CRS, ResourceTemplate () { GpioIo (Exclusive, PullDefault, 0, 0, IoRestrictionOutputOnly, "\\_SB.PCI0.GPIO", 0, ResourceConsumer) }) Name (_DSD, Package () { ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), Package () { Package () { "maxim,sdmode-gpio", \_SB.PCI0.HDAS.MAXM, 0, 0, 0 } Package () { "maxim,sdmode-delay", 100 } Package () { "sdmode-delay", 100 } } }) } } Change-Id: Ia0bafe49bea9bbe4a3cc0f9f9cdb6f6390da57b5 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/drivers/generic/max98357a/Kconfig | 2 + src/drivers/generic/max98357a/Makefile.inc | 1 + src/drivers/generic/max98357a/chip.h | 13 ++++ src/drivers/generic/max98357a/max98357a.c | 109 +++++++++++++++++++++++++++++ 4 files changed, 125 insertions(+) diff --git a/src/drivers/generic/max98357a/Kconfig b/src/drivers/generic/max98357a/Kconfig new file mode 100644 index 0000000..a7104f1 --- /dev/null +++ b/src/drivers/generic/max98357a/Kconfig @@ -0,0 +1,2 @@ +config DRIVERS_GENERIC_MAX98357A + bool diff --git a/src/drivers/generic/max98357a/Makefile.inc b/src/drivers/generic/max98357a/Makefile.inc new file mode 100644 index 0000000..529e24a --- /dev/null +++ b/src/drivers/generic/max98357a/Makefile.inc @@ -0,0 +1 @@ +ramstage-$(CONFIG_DRIVERS_GENERIC_MAX98357A) += max98357a.c diff --git a/src/drivers/generic/max98357a/chip.h b/src/drivers/generic/max98357a/chip.h new file mode 100644 index 0000000..0abd616 --- /dev/null +++ b/src/drivers/generic/max98357a/chip.h @@ -0,0 +1,13 @@ +#include <arch/acpi_device.h> + +struct drivers_generic_max98357a_config { + /* SDMODE GPIO */ + struct acpi_gpio sdmode_gpio; + + /* SDMODE Delay */ + unsigned sdmode_delay; + + /* GPIO used to indicate if this device is present */ + unsigned device_present_gpio; + unsigned device_present_gpio_invert; +}; diff --git a/src/drivers/generic/max98357a/max98357a.c b/src/drivers/generic/max98357a/max98357a.c new file mode 100644 index 0000000..331df4c --- /dev/null +++ b/src/drivers/generic/max98357a/max98357a.c @@ -0,0 +1,109 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/acpi_device.h> +#include <arch/acpigen.h> +#include <console/console.h> +#include <device/device.h> +#include <device/path.h> +#include <gpio.h> +#include <stdint.h> +#include <string.h> +#include "chip.h" + +#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) + +#define MAX98357A_ACPI_NAME "MAXM" +#define MAX98357A_ACPI_HID "MX98357A" + +static void max98357a_fill_ssdt(struct device *dev) +{ + struct drivers_generic_max98357a_config *config = dev->chip_info; + const char *path = acpi_device_path(dev); + + if (!dev->enabled || !path) + return; + + /* Device */ + acpigen_write_scope(acpi_device_scope(dev)); + acpigen_write_device(acpi_device_name(dev)); + acpigen_write_name_string("_HID", MAX98357A_ACPI_HID); + acpigen_write_name_integer("_UID", 0); + acpigen_write_name_string("_DDN", dev->chip_ops->name); + acpigen_write_STA(ACPI_STATUS_DEVICE_ALL_ON); + + /* Resources */ + acpigen_write_name("_CRS"); + acpigen_write_resourcetemplate_header(); + acpi_device_write_gpio(&config->sdmode_gpio); + acpigen_write_resourcetemplate_footer(); + + /* _DSD for devicetree properties */ + acpi_dp_write_header(); + /* This points to the first pin in the first gpio entry in _CRS */ + acpi_dp_write_gpio("maxim,sdmode-gpio", path, 0, 0, 0); + /* This is the correctly formatted Device Property name */ + acpi_dp_write_integer("maxim,sdmode-delay", config->sdmode_delay); + /* This is used by the chromium kernel but is not upstream */ + acpi_dp_write_integer("sdmode-delay", config->sdmode_delay); + acpi_dp_write_footer(); + + acpigen_pop_len(); /* Device */ + acpigen_pop_len(); /* Scope */ + + printk(BIOS_INFO, "%s: %s\n", path, dev->chip_ops->name); +} + +static const char *max98357a_acpi_name(struct device *dev) +{ + return MAX98357A_ACPI_NAME; +} +#endif + +static struct device_operations max98357a_ops = { + .read_resources = DEVICE_NOOP, + .set_resources = DEVICE_NOOP, + .enable_resources = DEVICE_NOOP, +#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) + .acpi_name = &max98357a_acpi_name, + .acpi_fill_ssdt_generator = &max98357a_fill_ssdt, +#endif +}; + +static void max98357a_enable(struct device *dev) +{ + struct drivers_generic_max98357a_config *config = dev->chip_info; + + /* Check if device is present by reading GPIO */ + if (config->device_present_gpio) { + int present = gpio_get(config->device_present_gpio); + present ^= config->device_present_gpio_invert; + + printk(BIOS_INFO, "%s is %spresent\n", + dev->chip_ops->name, present ? "" : "not "); + + if (!present) { + dev->enabled = 0; + return; + } + } + + dev->ops = &max98357a_ops; +} + +struct chip_operations drivers_generic_max98357a_ops = { + CHIP_NAME("Maxim Integrated 98357A Amplifier") + .enable_dev = &max98357a_enable +};

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New patch to review for coreboot: i2c: Add a generic i2c driver
by Duncan Laurie 31 May '16

31 May '16

Duncan Laurie (dlaurie(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15016 -gerrit commit 83d09e2d4fd92452bf113695fb26c59113a8cde1 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Wed May 11 09:50:59 2016 -0700 i2c: Add a generic i2c driver This adds a generic I2C driver that can be described in the devicetree and used to generate ACPI objects in the SSDT based on the information provided in the config registers. The I2C bus can be configured and the device can provide an interrupt and wake capability to the OS. A configuration option allows for a GPIO to be provided that will be checked to determine if the device is preset on the board before including it in the generated SSDT. The driver is generic enough to be used for basic I2C devices that do not have special configuration needs such as touchpads, touchscreens, sensors, some audio codec/amplifiers, etc. Sample usage for a touchpad device: device pci 15.1 on chip drivers/i2c/generic register "hid" = ""ELAN0000"" register "desc" = "ELAN Touchpad" register "irq" = "IRQ_EDGE_LOW(GPP_B3_IRQ)" register "wake" = "GPE0_DW0_05" device i2c 15.0 on end end end Will result in the following code in the SSDT: Scope (\_SB.PCI0.I2C1) { Device (D015) { Name (_HID, "ELAN0000") Name (_UID, 0) Name (_S0W, 4) Name (_PRW, Package () { 5, 3 }) Method (_STA) { Return (0x0f) } Name (_CRS, ResourceTemplate () { I2cSerialBus (0x15, ControllerInitiated, 400000, AddressingMode7Bit, "\\_S.PCI0.I2C1", 0, ResourceConsumer) Interrupt (ResourceConsumer, Edge, ActiveLow) { 51 } }) } } Change-Id: Ib32055720835b70e91ede5e4028ecd91894d70d5 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/drivers/i2c/generic/Kconfig | 2 + src/drivers/i2c/generic/Makefile.inc | 1 + src/drivers/i2c/generic/chip.h | 15 +++++ src/drivers/i2c/generic/generic.c | 123 +++++++++++++++++++++++++++++++++++ 4 files changed, 141 insertions(+) diff --git a/src/drivers/i2c/generic/Kconfig b/src/drivers/i2c/generic/Kconfig new file mode 100644 index 0000000..a4c0104 --- /dev/null +++ b/src/drivers/i2c/generic/Kconfig @@ -0,0 +1,2 @@ +config DRIVERS_I2C_GENERIC + bool diff --git a/src/drivers/i2c/generic/Makefile.inc b/src/drivers/i2c/generic/Makefile.inc new file mode 100644 index 0000000..86cbc7b --- /dev/null +++ b/src/drivers/i2c/generic/Makefile.inc @@ -0,0 +1 @@ +ramstage-$(CONFIG_DRIVERS_I2C_GENERIC) += generic.c diff --git a/src/drivers/i2c/generic/chip.h b/src/drivers/i2c/generic/chip.h new file mode 100644 index 0000000..7b371c4 --- /dev/null +++ b/src/drivers/i2c/generic/chip.h @@ -0,0 +1,15 @@ +#include <arch/acpi_device.h> + +struct drivers_i2c_generic_config { + const char *hid; /* ACPI _HID (required) */ + const char *name; /* ACPI Device Name */ + const char *desc; /* Device Description */ + unsigned uid; /* ACPI _UID */ + unsigned bus_speed; /* I2C Bus Frequency (default=400kHz) */ + unsigned wake; /* Wake GPE */ + struct acpi_irq irq; /* Interrupt */ + + /* GPIO used to indicate if this device is present */ + unsigned device_present_gpio; + unsigned device_present_gpio_invert; +}; diff --git a/src/drivers/i2c/generic/generic.c b/src/drivers/i2c/generic/generic.c new file mode 100644 index 0000000..a12c273 --- /dev/null +++ b/src/drivers/i2c/generic/generic.c @@ -0,0 +1,123 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/acpi_device.h> +#include <arch/acpigen.h> +#include <console/console.h> +#include <device/i2c.h> +#include <device/device.h> +#include <device/path.h> +#include <gpio.h> +#include <stdint.h> +#include <string.h> +#include "chip.h" + +#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) +static void i2c_generic_fill_ssdt(struct device *dev) +{ + struct drivers_i2c_generic_config *config = dev->chip_info; + const char *scope = acpi_device_scope(dev); + struct acpi_i2c i2c = { + .address = dev->path.i2c.device, + .mode_10bit = dev->path.i2c.mode_10bit, + .speed = config->bus_speed ? : I2C_SPEED_FAST, + .resource = scope, + }; + + if (!dev->enabled || !scope) + return; + + if (!config->hid) { + printk(BIOS_ERR, "%s: ERROR: HID required\n", dev_path(dev)); + return; + } + + /* Device */ + acpigen_write_scope(scope); + acpigen_write_device(acpi_device_name(dev)); + acpigen_write_name_string("_HID", config->hid); + acpigen_write_name_integer("_UID", config->uid); + acpigen_write_name_string("_DDN", config->desc); + acpigen_write_STA(ACPI_STATUS_DEVICE_ALL_ON); + + /* Resources */ + acpigen_write_name("_CRS"); + acpigen_write_resourcetemplate_header(); + acpi_device_write_i2c(&i2c); + acpi_device_write_interrupt(&config->irq); + acpigen_write_resourcetemplate_footer(); + + /* Wake capabilities */ + if (config->wake) { + acpigen_write_name_integer("_S0W", 4); + acpigen_write_PRW(config->wake, 3); + } + + acpigen_pop_len(); /* Device */ + acpigen_pop_len(); /* Scope */ + + printk(BIOS_INFO, "%s: %s at %s\n", acpi_device_path(dev), + config->desc ? : dev->chip_ops->name, dev_path(dev)); +} + +/* Use name specified in config or build one from I2C address */ +static const char *i2c_generic_acpi_name(struct device *dev) +{ + struct drivers_i2c_generic_config *config = dev->chip_info; + static char name[5]; + + if (config->name) + return name; + + snprintf(name, sizeof(name), "D%03X", dev->path.i2c.device); + return name; +} +#endif + +static struct device_operations i2c_generic_ops = { + .read_resources = DEVICE_NOOP, + .set_resources = DEVICE_NOOP, + .enable_resources = DEVICE_NOOP, +#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) + .acpi_name = &i2c_generic_acpi_name, + .acpi_fill_ssdt_generator = &i2c_generic_fill_ssdt, +#endif +}; + +static void i2c_generic_enable(struct device *dev) +{ + struct drivers_i2c_generic_config *config = dev->chip_info; + + /* Check if device is present by reading GPIO */ + if (config->device_present_gpio) { + int present = gpio_get(config->device_present_gpio); + present ^= config->device_present_gpio_invert; + + printk(BIOS_INFO, "%s is %spresent\n", + dev->chip_ops->name, present ? "" : "not "); + + if (!present) { + dev->enabled = 0; + return; + } + } + + dev->ops = &i2c_generic_ops; +} + +struct chip_operations drivers_i2c_generic_ops = { + CHIP_NAME("I2C Device") + .enable_dev = &i2c_generic_enable +};

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coreboot-gerrit May 2016