coreboot-gerrit May 2016

coreboot-gerrit@coreboot.org

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New patch to review for coreboot: apollolake/amenia: Adding NHLA and NHLL, address and length of NHLT table in ACPI
by Saurabh Satija 01 Jun '16

01 Jun '16

Saurabh Satija (saurabh.satija(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15025 -gerrit commit 2f1808d4c16dc0ec3b3b42505ea3070f1de4ee8a Author: Saurabh Satija <saurabh.satija(a)intel.com> Date: Thu Mar 31 15:41:30 2016 -0700 apollolake/amenia: Adding NHLA and NHLL, address and length of NHLT table in ACPI Change-Id: Ic0959a8aae18d54e10e3fcd95bfc98a6b6e0385a Signed-off-by: Saurabh Satija <saurabh.satija(a)intel.com> --- src/mainboard/intel/amenia/dsdt.asl | 3 +++ src/soc/intel/apollolake/acpi/globalnvs.asl | 4 +++- src/soc/intel/apollolake/include/soc/nvs.h | 4 +++- 3 files changed, 9 insertions(+), 2 deletions(-) diff --git a/src/mainboard/intel/amenia/dsdt.asl b/src/mainboard/intel/amenia/dsdt.asl index 19e7360..8147c27 100644 --- a/src/mainboard/intel/amenia/dsdt.asl +++ b/src/mainboard/intel/amenia/dsdt.asl @@ -24,6 +24,9 @@ DefinitionBlock( 0x20110725 // OEM revision ) { + // global NVS and variables + #include <soc/intel/apollolake/acpi/globalnvs.asl> + Scope (\_SB) { Device (PCI0) { diff --git a/src/soc/intel/apollolake/acpi/globalnvs.asl b/src/soc/intel/apollolake/acpi/globalnvs.asl index 2ef5031..3efca51 100644 --- a/src/soc/intel/apollolake/acpi/globalnvs.asl +++ b/src/soc/intel/apollolake/acpi/globalnvs.asl @@ -26,8 +26,10 @@ External (NVSA) OperationRegion (GNVS, SystemMemory, NVSA, 0x1000) Field (GNVS, ByteAcc, NoLock, Preserve) { - /* Nothing here yet, folks */ + /* Miscellaneous */ Offset (0x00), + NHLA, 64, // 0x00 - NHLT Address + NHLL, 32, // 0x08 - NHLT Length /* ChromeOS stuff (0x100 -> 0xfff, size 0xeff) */ Offset (0x100), diff --git a/src/soc/intel/apollolake/include/soc/nvs.h b/src/soc/intel/apollolake/include/soc/nvs.h index 8b3a3af..23e40e8 100644 --- a/src/soc/intel/apollolake/include/soc/nvs.h +++ b/src/soc/intel/apollolake/include/soc/nvs.h @@ -28,7 +28,9 @@ struct global_nvs_t { /* Miscellaneous */ - uint8_t unused[256]; + u64 nhla; /* 0x00 - NHLT Address */ + u32 nhll; /* 0x08 - NHLT Length */ + uint8_t unused[244]; /* ChromeOS specific (0x100 - 0xfff) */ chromeos_acpi_t chromeos;

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New patch to review for coreboot: intel/amenia: Add nhlt support
by Saurabh Satija 01 Jun '16

01 Jun '16

Saurabh Satija (saurabh.satija(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15024 -gerrit commit fbe282380f0f8311804ba09c2c46f07f97937515 Author: Saurabh Satija <saurabh.satija(a)intel.com> Date: Thu May 26 16:08:45 2016 -0700 intel/amenia: Add nhlt support Adding the ACPI NHLT table generation that the current hardware supports. Amenia has support for two audio codecs Nuvoton and Dialog for headphones and Maxim for speakers. Change-Id: Iaba9ec81ffb4f128f2e4413dec5174d9ecb856c9 Signed-off-by: Saurabh Satija <saurabh.satija(a)intel.com> --- src/mainboard/intel/amenia/Kconfig | 8 +++ src/mainboard/intel/amenia/dsdt.asl | 1 + src/mainboard/intel/amenia/mainboard.c | 90 +++++++++++++++++++++++++++++++++- 3 files changed, 98 insertions(+), 1 deletion(-) diff --git a/src/mainboard/intel/amenia/Kconfig b/src/mainboard/intel/amenia/Kconfig index bfc4091..edf9d91 100644 --- a/src/mainboard/intel/amenia/Kconfig +++ b/src/mainboard/intel/amenia/Kconfig @@ -14,6 +14,8 @@ config BOARD_SPECIFIC_OPTIONS select MAINBOARD_HAS_CHROMEOS select SYSTEM_TYPE_LAPTOP select TPM_ON_FAST_SPI + select ACPI_NHLT + select USE_COMMON_AUDIO config CHROMEOS bool @@ -64,4 +66,10 @@ config MAX_CPUS int default 8 +config INCLUDE_AUDIO_BLOBS + bool "Include blobs for audio." + select AUDIO_DMIC_2CH_16B + select AUDIO_SPEAKER + select AUDIO_HEADSET + endif # BOARD_INTEL_AMENIA diff --git a/src/mainboard/intel/amenia/dsdt.asl b/src/mainboard/intel/amenia/dsdt.asl index 19e7360..1be4a9f 100644 --- a/src/mainboard/intel/amenia/dsdt.asl +++ b/src/mainboard/intel/amenia/dsdt.asl @@ -29,6 +29,7 @@ DefinitionBlock( { #include <soc/intel/apollolake/acpi/northbridge.asl> #include <soc/intel/apollolake/acpi/southbridge.asl> + #include <soc/intel/apollolake/acpi/pch.asl } } /* Mainboard Specific devices */ diff --git a/src/mainboard/intel/amenia/mainboard.c b/src/mainboard/intel/amenia/mainboard.c index 22304f8..40a65ff 100644 --- a/src/mainboard/intel/amenia/mainboard.c +++ b/src/mainboard/intel/amenia/mainboard.c @@ -16,8 +16,14 @@ */ #include <device/device.h> +#include <pc80/keyboard.h> #include <soc/gpio.h> #include <soc/pci_devs.h> +#include <drivers/audio.h> +#include <arch/acpi.h> +#include <console/console.h> +#include <stdlib.h> +#include <string.h> #include "ec.h" /* TODO: Move GPIO config to its own file once we get more GPIOs in the list */ @@ -89,7 +95,6 @@ static const struct pad_config amenia_gpios[] = { PAD_CFG_GPO(GPIO_154, 1, DEEP), /* BT_DISABLE_1P8_N */ PAD_CFG_GPI(GPIO_167, NONE, DEEP), /* DB_ID */ - PAD_CFG_NF(GPIO_172, UP_20K, DEEP, NF1), /* SDCARD_CLK */ PAD_CFG_NF(GPIO_173, UP_20K, DEEP, NF1), /* SDCARD_D0 */ PAD_CFG_NF(GPIO_174, UP_20K, DEEP, NF1), /* SDCARD_D1 */ @@ -114,6 +119,9 @@ static const struct pad_config amenia_gpios[] = { PAD_CFG_NF(GPIO_165, UP_20K, DEEP, NF1), /* EMMC0_CMD */ PAD_CFG_NF(GPIO_182, DN_20K, DEEP, NF1), /* EMMC_RCLK */ + PAD_CFG_NF(GPIO_199, UP_20K, DEEP, NF1), /* DDI0_HPD */ + PAD_CFG_NF(GPIO_200, UP_20K, DEEP, NF1), /* DDI1_HPD */ + PAD_CFG_NF(GPIO_203, NATIVE, DEEP, NF1), /* USB2_OC0_3p3_N */ PAD_CFG_NF(GPIO_204, NATIVE, DEEP, NF1), /* USB2_OC2_N */ @@ -129,15 +137,95 @@ static const struct pad_config amenia_gpios[] = { PAD_CFG_NF(GPIO_199, UP_20K, DEEP, NF2), /* HV_DDI1_HPD */ PAD_CFG_NF(GPIO_200, UP_20K, DEEP, NF2), /* HV_DDI0_HPD */ PAD_CFG_NF(PMC_SPI_FS1, NATIVE, DEEP, NF2), /* HV_DDI2_HPD */ +}; + +const struct nhlt_format_config dmic_2ch_cfg[] = { + /* 48 KHz 16-bits per sample. */ + { + .num_channels = 2, + .sample_freq_khz = 48, + .container_bits_per_sample = 16, + .valid_bits_per_sample = 16, + .settings_file = "dmic-2ch-48khz-16b.bin", + }, +}; + +const struct nhlt_format_config headset_cfg[] = { + /* 48 KHz 24-bits per sample. */ + { + .num_channels = 2, + .sample_freq_khz = 48, + .container_bits_per_sample = 32, + .valid_bits_per_sample = 24, + .settings_file = "headset-2ch-48khz-24b.bin", + }, +}; + +struct nhlt_tdm_config headset_tdm_cfg = { + .virtual_slot = 0, + .config_type = NHLT_TDM_BASIC, +}; + +const struct nhlt_format_config speaker_cfg[] = { + /* 48 KHz 24-bits per sample. */ + { + .num_channels = 2, + .sample_freq_khz = 48, + .container_bits_per_sample = 32, + .valid_bits_per_sample = 24, + .settings_file = "max98357-render-2ch-48khz-24b.bin", + }, }; static void mainboard_init(void *chip_info) { gpio_configure_pads(amenia_gpios, ARRAY_SIZE(amenia_gpios)); mainboard_ec_init(); + pc_keyboard_init(NO_AUX_DEVICE); +} + +static unsigned long mainboard_write_acpi_tables( + device_t device, unsigned long current, acpi_rsdp_t *rsdp) +{ + uintptr_t start_addr; + uintptr_t end_addr; + struct nhlt *nhlt; + + start_addr = current; + + nhlt = nhlt_init(); + + if (nhlt == NULL) + return start_addr; + + /* 2 Channel DMIC array. */ + if (nhlt_soc_add_dmic_array(nhlt, dmic_2ch_cfg, ARRAY_SIZE(dmic_2ch_cfg), 2)) + printk(BIOS_ERR, "Couldn't add 2CH DMIC array.\n"); + + /* NAU88l25 and Dialog have Headset codec. */ + if (nhlt_soc_add_headset(nhlt, headset_cfg, ARRAY_SIZE(headset_cfg), &headset_tdm_cfg, AUDIO_LINK_SSP1)) + printk(BIOS_ERR, "Couldn't add headset codec.\n"); + + /* MAXIM Smart Amps for left and right. */ + if (nhlt_soc_add_speaker(nhlt, speaker_cfg, ARRAY_SIZE(speaker_cfg), NULL, AUDIO_LINK_SSP5)) + printk(BIOS_ERR, "Couldn't add speaker codec.\n"); + + end_addr = nhlt_soc_serialize(nhlt, start_addr); + + if (end_addr != start_addr) + acpi_add_table(rsdp, (void *)start_addr); + + return end_addr; +} + +static void mainboard_enable(device_t dev) +{ + dev->ops->write_acpi_tables = (void *) mainboard_write_acpi_tables; } struct chip_operations mainboard_ops = { .init = mainboard_init, + .enable_dev = mainboard_enable, }; +

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New patch to review for coreboot: Add common Audio support for intel platforms
by Saurabh Satija 01 Jun '16

01 Jun '16

Saurabh Satija (saurabh.satija(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15023 -gerrit commit de71a4201202c6cc35d5fedf0b0d7e2dd7278f30 Author: Saurabh Satija <saurabh.satija(a)intel.com> Date: Thu May 26 15:53:41 2016 -0700 Add common Audio support for intel platforms The use of a NHLT table is required to make audio work on the intel SoCs employing the internal DSP. The table describes the audo endpoints (render vs capture) along with their supported formats. These formats are not only dependent on the audio peripheral but also hardware interfaces. As such each format has an associated blob of DSP settings to make the peripheral work. Lastly, each of these settings are provided by Intel and need to be generated for each device's hardware connection plus mode/format it supports. This patch does not include the dsp setting blobs. Change-Id: I3c75d3537288c47d29e8949ca253ea8c5c1a387d Signed-off-by: Saurabh Satija <saurabh.satija(a)intel.com> --- src/drivers/intel/audio/Kconfig | 48 +++++++++++++ src/drivers/intel/audio/Makefile.inc | 43 +++++++++++ src/drivers/intel/audio/dmic.c | 53 ++++++++++++++ src/drivers/intel/audio/headset.c | 60 ++++++++++++++++ src/drivers/intel/audio/include/drivers/audio.h | 59 +++++++++++++++ src/drivers/intel/audio/nhlt.c | 95 +++++++++++++++++++++++++ src/drivers/intel/audio/speaker.c | 40 +++++++++++ 7 files changed, 398 insertions(+) diff --git a/src/drivers/intel/audio/Kconfig b/src/drivers/intel/audio/Kconfig new file mode 100644 index 0000000..fdc494c --- /dev/null +++ b/src/drivers/intel/audio/Kconfig @@ -0,0 +1,48 @@ +config USE_COMMON_AUDIO + bool + default n + help + Build support for drivers audio code, common to intel + platforms that use NHLT. + +config AUDIO_DMIC_2CH_16B + bool + depends on USE_COMMON_AUDIO + default n + help + Include DSP firmware settings for 2 channel 16B DMIC array. + +config AUDIO_DMIC_2CH_32B + bool + depends on USE_COMMON_AUDIO + default n + help + Include DSP firmware settings for 2 channel 32B DMIC array. + +config AUDIO_DMIC_4CH_16B + bool + depends on USE_COMMON_AUDIO + default n + help + Include DSP firmware settings for 4 channel 16B DMIC array. + +config AUDIO_DMIC_4CH_32B + bool + depends on USE_COMMON_AUDIO + default n + help + Include DSP firmware settings for 4 channel 32B DMIC array. + +config AUDIO_HEADSET + bool + depends on USE_COMMON_AUDIO + default n + help + Include DSP firmware settings for headset codec. + +config AUDIO_SPEAKER + bool + depends on USE_COMMON_AUDIO + default n + help + Include DSP firmware settings for speaker amplifier. diff --git a/src/drivers/intel/audio/Makefile.inc b/src/drivers/intel/audio/Makefile.inc new file mode 100644 index 0000000..6bea190 --- /dev/null +++ b/src/drivers/intel/audio/Makefile.inc @@ -0,0 +1,43 @@ +ifeq ($(CONFIG_USE_COMMON_AUDIO),y) +ramstage-y += nhlt.c +ramstage-y += dmic.c +ramstage-y += headset.c +ramstage-y += speaker.c + +# DSP firmware settings files. +NHLT_BLOB_PATH = 3rdparty/blobs/soc/intel/apollolake/nhlt-blobs +DMIC_2CH_48KHZ_16B = dmic-2ch-48khz-16b.bin +DMIC_2CH_48KHZ_32B = dmic-2ch-48khz-32b.bin +DMIC_4CH_48KHZ_16B = dmic-4ch-48khz-16b.bin +DMIC_4CH_48KHZ_32B = dmic-4ch-48khz-32b.bin + +HEADSET = headset-2ch-48khz-24b.bin + +SPEAKER_RENDER = max98357-render-2ch-48khz-24b.bin + +cbfs-files-$(CONFIG_AUDIO_DMIC_2CH_16B) += $(DMIC_2CH_48KHZ_16B) +$(DMIC_2CH_48KHZ_16B)-file := $(NHLT_BLOB_PATH)/$(DMIC_2CH_48KHZ_16B) +$(DMIC_2CH_48KHZ_16B)-type := raw + +cbfs-files-$(CONFIG_AUDIO_DMIC_2CH_32B) += $(DMIC_2CH_48KHZ_32B) +$(DMIC_2CH_48KHZ_32B)-file := $(NHLT_BLOB_PATH)/$(DMIC_2CH_48KHZ_32B) +$(DMIC_2CH_48KHZ_32B)-type := raw + +cbfs-files-$(CONFIG_AUDIO_DMIC_4CH_16B) += $(DMIC_4CH_48KHZ_16B) +$(DMIC_4CH_48KHZ_16B)-file := $(NHLT_BLOB_PATH)/$(DMIC_4CH_48KHZ_16B) +$(DMIC_4CH_48KHZ_16B)-type := raw + +cbfs-files-$(CONFIG_AUDIO_DMIC_4CH_32B) += $(DMIC_4CH_48KHZ_32B) +$(DMIC_4CH_48KHZ_32B)-file := $(NHLT_BLOB_PATH)/$(DMIC_4CH_48KHZ_32B) +$(DMIC_4CH_48KHZ_32B)-type := raw + +cbfs-files-$(CONFIG_AUDIO_HEADSET) += $(HEADSET) +$(HEADSET)-file := $(NHLT_BLOB_PATH)/$(HEADSET) +$(HEADSET)-type := raw + +cbfs-files-$(CONFIG_AUDIO_SPEAKER) += $(SPEAKER_RENDER) +$(SPEAKER_RENDER)-file := $(NHLT_BLOB_PATH)/$(SPEAKER_RENDER) +$(SPEAKER_RENDER)-type := raw +endif + +CPPFLAGS_common += -I$(src)/drivers/intel/audio/include diff --git a/src/drivers/intel/audio/dmic.c b/src/drivers/intel/audio/dmic.c new file mode 100644 index 0000000..fe11d51 --- /dev/null +++ b/src/drivers/intel/audio/dmic.c @@ -0,0 +1,53 @@ + /* + * This file is part of the coreboot project. + * + * Copyright 2016 Google, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <drivers/audio.h> +#include <string.h> + +int nhlt_soc_add_dmic_array(struct nhlt *nhlt, const struct nhlt_format_config *dmic_ch_cfg, int fmt_size, int num_channels) +{ + struct nhlt_endpoint *endp; + struct nhlt_dmic_array_config mic_config; + const struct nhlt_format_config *formats; + + if (num_channels != 2 && num_channels != 4) + return -1; + + endp = nhlt_soc_add_endpoint(nhlt, AUDIO_LINK_DMIC, AUDIO_DEV_DMIC, + NHLT_DIR_CAPTURE); + + if (endp == NULL) + return -1; + + memset(&mic_config, 0, sizeof(mic_config)); + mic_config.tdm_config.config_type = NHLT_TDM_MIC_ARRAY; + + formats = dmic_ch_cfg; + + switch (num_channels) { + case 2: + mic_config.array_type = NHLT_MIC_ARRAY_2CH_SMALL; + break; + case 4: + mic_config.array_type = NHLT_MIC_ARRAY_4CH_L_SHAPED; + break; + } + + if (nhlt_endpoint_append_config(endp, &mic_config, sizeof(mic_config))) + return -1; + + return nhlt_endpoint_add_formats(endp, formats, fmt_size); +} + diff --git a/src/drivers/intel/audio/headset.c b/src/drivers/intel/audio/headset.c new file mode 100644 index 0000000..68acee2 --- /dev/null +++ b/src/drivers/intel/audio/headset.c @@ -0,0 +1,60 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 Google, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <drivers/audio.h> +#include <console/console.h> + +/* The same DSP firmwware settings are used for both the capture and + * render endpoints. */ +int nhlt_soc_add_headset(struct nhlt *nhlt, const struct nhlt_format_config *headset_cfg, int fmt_size, struct nhlt_tdm_config *tdm_config, int hwlink) +{ + struct nhlt_endpoint *endp; + /* The headphone codec has headphones and a mic. Both the capture and + * render endpoints occupy the same virtual slot. */ + const void *fmt_cfg = headset_cfg; + size_t fmt_sz = fmt_size; + + /* Render Endpoint */ + endp = nhlt_soc_add_endpoint(nhlt, hwlink, AUDIO_DEV_I2S, + NHLT_DIR_RENDER); + if (endp == NULL) + return -1; + + if(tdm_config != NULL){ + if (nhlt_endpoint_append_config(endp, tdm_config, 1)) + return -1; + } + + if (nhlt_endpoint_add_formats(endp, fmt_cfg, fmt_sz)) + return -1; + + /* Capture Endpoint */ + endp = nhlt_soc_add_endpoint(nhlt, hwlink, AUDIO_DEV_I2S, + NHLT_DIR_CAPTURE); + if (endp == NULL) + return -1; + + if(tdm_config != NULL){ + if (nhlt_endpoint_append_config(endp, &tdm_config, 1)) + return -1; + } + + if (nhlt_endpoint_add_formats(endp, fmt_cfg, fmt_sz)) + return -1; + + nhlt_next_instance(nhlt, NHLT_LINK_SSP); + + return 0; +} diff --git a/src/drivers/intel/audio/include/drivers/audio.h b/src/drivers/intel/audio/include/drivers/audio.h new file mode 100644 index 0000000..caf1edc --- /dev/null +++ b/src/drivers/intel/audio/include/drivers/audio.h @@ -0,0 +1,59 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 Google, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _DRIVERS_AUDIO_H_ +#define _DRIVERS_AUDIO_H_ + +#include <nhlt.h> + +/* + * Skylake NHLT device and hardware link types. These values are to be used + * with nhlt_soc_add_endpoint(). + */ + +enum { + AUDIO_LINK_SSP0, + AUDIO_LINK_SSP1, + AUDIO_LINK_SSP2, /* Only Bluetooth supported on SSP2. */ + AUDIO_LINK_SSP3, + AUDIO_LINK_SSP4, + AUDIO_LINK_SSP5, + AUDIO_LINK_DMIC, +}; + +enum { + AUDIO_DEV_I2S, + AUDIO_DEV_DMIC, + AUDIO_DEV_BT, +}; + +/* + * Add a dmic array composed of the provided number of channels. + * Returns 0 on success, < 0 on error. + */ +int nhlt_soc_add_dmic_array(struct nhlt *nhlt, const struct nhlt_format_config *dmic_ch_config, int cfg_size, int num_channels); + +/* + * Add headset codec on provided SSP link. Return 0 on succes, < 0 on error. + */ +int nhlt_soc_add_headset(struct nhlt *nhlt, const struct nhlt_format_config *headset_cfg, int cfg_size, struct nhlt_tdm_config *tdm_config, int hwlink); + +/* + * Add speaker amplifier in stereo configuration on provide SSP link. + * Return 0 on success, < 0 on error. + */ +int nhlt_soc_add_speaker(struct nhlt *nhlt, const struct nhlt_format_config *speaker_cfg, int cfg_size, struct nhlt_tdm_config *tdm_config, int hwlink); + +#endif diff --git a/src/drivers/intel/audio/nhlt.c b/src/drivers/intel/audio/nhlt.c new file mode 100644 index 0000000..0f8e6e1 --- /dev/null +++ b/src/drivers/intel/audio/nhlt.c @@ -0,0 +1,95 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 Google, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <cbmem.h> +#include <soc/acpi.h> +#include <drivers/audio.h> + +#define NHLT_VID 0x8086 +#define NHLT_DID_DMIC 0xae20 +#define NHLT_DID_BT 0xae30 +#define NHLT_DID_SSP 0xae34 + +struct nhlt_endpoint *nhlt_soc_add_endpoint(struct nhlt *nhlt, int soc_hwintf, + int soc_devtype, int dir) +{ + int nhlt_link_type; + int nhlt_dev_type; + uint16_t did; + struct nhlt_endpoint *endp; + + /* Check link type and device type. */ + switch (soc_hwintf) { + case AUDIO_LINK_SSP0: + case AUDIO_LINK_SSP1: + case AUDIO_LINK_SSP5: + case AUDIO_LINK_SSP2: + nhlt_link_type = NHLT_LINK_SSP; + break; + case AUDIO_LINK_DMIC: + /* Only DMIC devices on DMIC links. */ + if (soc_devtype != AUDIO_DEV_DMIC) + return NULL; + nhlt_link_type = NHLT_LINK_PDM; + break; + default: + return NULL; + } + + switch (soc_devtype) { + case AUDIO_DEV_I2S: + nhlt_dev_type = NHLT_SSP_DEV_I2S; + did = NHLT_DID_SSP; + break; + case AUDIO_DEV_DMIC: + nhlt_dev_type = NHLT_PDM_DEV; + did = NHLT_DID_DMIC; + break; + case AUDIO_DEV_BT: + nhlt_dev_type = NHLT_SSP_DEV_BT; + did = NHLT_DID_BT; + break; + default: + return NULL; + } + + endp = nhlt_add_endpoint(nhlt, nhlt_link_type, nhlt_dev_type, dir, + NHLT_VID, did); + + if (endp == NULL) + return NULL; + + /* Virtual bus id of SSP links are the hardware port ids proper. */ + if (nhlt_link_type == NHLT_LINK_SSP) + endp->virtual_bus_id = soc_hwintf; + + return endp; +} + +uintptr_t nhlt_soc_serialize(struct nhlt *nhlt, uintptr_t acpi_addr) +{ + struct global_nvs_t *gnvs; + + gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); + + if (gnvs == NULL) + return acpi_addr; + + /* Update NHLT GNVS Data */ + gnvs->nhla = (uintptr_t)acpi_addr; + gnvs->nhll = nhlt_current_size(nhlt); + + return nhlt_serialize(nhlt, acpi_addr); +} diff --git a/src/drivers/intel/audio/speaker.c b/src/drivers/intel/audio/speaker.c new file mode 100644 index 0000000..63dba66 --- /dev/null +++ b/src/drivers/intel/audio/speaker.c @@ -0,0 +1,40 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 Google, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <drivers/audio.h> + +int nhlt_soc_add_speaker(struct nhlt *nhlt, const struct nhlt_format_config *speaker_cfg, int fmt_size, struct nhlt_tdm_config *tdm_config, int hwlink) +{ + struct nhlt_endpoint *endp; + + /* Render Endpoint */ + endp = nhlt_soc_add_endpoint(nhlt, hwlink, AUDIO_DEV_I2S, + NHLT_DIR_RENDER); + + if (endp == NULL) + return -1; + + if(tdm_config != NULL){ + if (nhlt_endpoint_append_config(endp, &tdm_config, 1)) + return -1; + } + + if (nhlt_endpoint_add_formats(endp, speaker_cfg, fmt_size)) + return -1; + + nhlt_next_instance(nhlt, NHLT_LINK_SSP); + + return 0; +}

1 0

Patch set updated for coreboot: WIP: intel/amenia: Add changes for image assembly
by Saurabh Satija 01 Jun '16

01 Jun '16

Saurabh Satija (saurabh.satija(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14897 -gerrit commit 420fe39fa5e66cd456f992305a382d2ca41da580 Author: Bora Guvendik <bora.guvendik(a)intel.com> Date: Wed May 18 14:56:27 2016 -0700 WIP: intel/amenia: Add changes for image assembly Insert bootblock Build base images for different variants Generate fmd files for different variants BUG=chrome-os-partner:51844 BRANCH=none TEST=boots to chrome OS Change-Id: I0e92858486ecf4720b8bcdf64bae97d9476caabc Signed-off-by: Bora Guvendik <bora.guvendik(a)intel.com> --- src/mainboard/intel/amenia/Kconfig | 17 +++++++++++++++-- src/soc/intel/apollolake/Makefile.inc | 5 +++++ 2 files changed, 20 insertions(+), 2 deletions(-) diff --git a/src/mainboard/intel/amenia/Kconfig b/src/mainboard/intel/amenia/Kconfig index ec76119..bfc4091 100644 --- a/src/mainboard/intel/amenia/Kconfig +++ b/src/mainboard/intel/amenia/Kconfig @@ -35,9 +35,22 @@ config FMAP_FILE string default "amenia" -config PREBUILT_SPI_IMAGE +config HAVE_IFD_BIN + default y + +config APOLLOLAKE_A0 + bool + default y + +config IFD_BIN_PATH + string "Path and filename of the descriptor.bin file" + default "3rdparty/blobs/baseboard-reef/reef.bin.orig.a0" if APOLLOLAKE_A0 + default "3rdparty/blobs/baseboard-reef/reef.bin.orig.b0" if !APOLLOLAKE_A0 + +config FMDFILE string - default "amenia.bin.orig.a0" + default "3rdparty/blobs/baseboard-reef/reef.bin.orig.a0.fmd" if APOLLOLAKE_A0 + default "3rdparty/blobs/baseboard-reef/reef.bin.orig.b0.fmd" if !APOLLOLAKE_A0 config IFD_BIOS_END hex diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index 1ea21f6..350a8d2 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -75,4 +75,9 @@ files_added:: $(CBFSTOOL) $(obj)/coreboot.rom write -r $(CONFIG_LBP2_FMAP_NAME) -f $(CONFIG_LBP2_FILE_NAME) --fill-upward endif +build_complete:: + $(CBFSTOOL) $(obj)/coreboot.rom write \ + -r bootblock \ + -f $(objcbfs)/bootblock.bin + endif

1 0

Patch merged into coreboot/master: quark: Enable HSUART0 as console
by gerrit＠coreboot.org 31 May '16

31 May '16

the following patch was just integrated into master: commit bc518d5cab4234a0d0d06a7d3829bbca9e318ba6 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Mon May 30 15:01:06 2016 -0700 quark: Enable HSUART0 as console The use of HSUART0 on galileo requires early initialization of the I2C GPIO expanders to direct the RXD and TXD signals to DIGITAL 0 and 1 on the expansion connector. TEST=None Change-Id: I11195d79e954c1f6bc91eafe257d7ddc1310b2e7 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> Reviewed-on: https://review.coreboot.org/15010 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/15010 for details. -gerrit

1 0

Patch merged into coreboot/master: soc/intel/quark: Move UART init into romstage.c
by gerrit＠coreboot.org 31 May '16

31 May '16

the following patch was just integrated into master: commit ac78db3a53a7653a73409936455d68c754291e9d Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Mon May 30 14:35:15 2016 -0700 soc/intel/quark: Move UART init into romstage.c Move UART initialization into romstage.c and eliminate uart.c. TEST=Build and run on Galileo Gen2 Change-Id: I5f2c9b4c566008000c2201c422a0bba63da64487 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> Reviewed-on: https://review.coreboot.org/15009 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/15009 for details. -gerrit

1 0

Patch merged into coreboot/master: mainboard/intel/quark: Enable reg_access during romstage
by gerrit＠coreboot.org 31 May '16

31 May '16

the following patch was just integrated into master: commit fd91dee42001cd055d5a51c13750c8e1abc0e7e1 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Mon May 30 11:23:49 2016 -0700 mainboard/intel/quark: Enable reg_access during romstage Turn on reg_access during romstage. TEST=Build and run on Galileo Gen2 Change-Id: Iff1616836d6031f43d7741693febefa0bf26b948 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> Reviewed-on: https://review.coreboot.org/15008 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/15008 for details. -gerrit

1 0

Patch merged into coreboot/master: soc/intel/quark: Split I2C out from driver
by gerrit＠coreboot.org 31 May '16

31 May '16

the following patch was just integrated into master: commit a5258cba6fc2b6cf47380581065cc22f06ecccae Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Mon May 30 14:06:25 2016 -0700 soc/intel/quark: Split I2C out from driver Split out the I2C code to allow I2C transactions during early romstage. TEST=Build and run on Galileo Gen2 Change-Id: I87ceb0a8cf660e4337738b3bcde9d4fdeae0159d Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> Reviewed-on: https://review.coreboot.org/15007 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/15007 for details. -gerrit

1 0

Patch set updated for coreboot: soc/intel/quark: Split I2C out from driver
by Leroy P Leahy 31 May '16

31 May '16

Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15007 -gerrit commit b56d6816ac3b13db94fcdde5e6a6a32a53ffa5e6 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Mon May 30 14:06:25 2016 -0700 soc/intel/quark: Split I2C out from driver Split out the I2C code to allow I2C transactions during early romstage. TEST=Build and run on Galileo Gen2 Change-Id: I87ceb0a8cf660e4337738b3bcde9d4fdeae0159d Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/soc/intel/quark/Makefile.inc | 2 + src/soc/intel/quark/gpio_i2c.c | 152 --------------------------------- src/soc/intel/quark/i2c.c | 176 +++++++++++++++++++++++++++++++++++++++ 3 files changed, 178 insertions(+), 152 deletions(-) diff --git a/src/soc/intel/quark/Makefile.inc b/src/soc/intel/quark/Makefile.inc index 08325e7..d747079 100644 --- a/src/soc/intel/quark/Makefile.inc +++ b/src/soc/intel/quark/Makefile.inc @@ -18,6 +18,7 @@ ifeq ($(CONFIG_SOC_INTEL_QUARK),y) subdirs-y += romstage subdirs-y += ../../../cpu/x86/tsc +romstage-y += i2c.c romstage-y += memmap.c romstage-y += reg_access.c romstage-y += tsc_freq.c @@ -27,6 +28,7 @@ ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c ramstage-y += chip.c ramstage-y += ehci.c ramstage-y += gpio_i2c.c +ramstage-y += i2c.c ramstage-y += lpc.c ramstage-y += memmap.c ramstage-y += northcluster.c diff --git a/src/soc/intel/quark/gpio_i2c.c b/src/soc/intel/quark/gpio_i2c.c index d23a905..5580894 100644 --- a/src/soc/intel/quark/gpio_i2c.c +++ b/src/soc/intel/quark/gpio_i2c.c @@ -23,158 +23,6 @@ #include <soc/ramstage.h> #include <soc/reg_access.h> -static void i2c_disable(I2C_REGS *regs) -{ - uint32_t status; - uint32_t timeout; - - /* Disable I2C controller */ - regs->ic_enable = 0; - - /* Wait for the enable bit to clear */ - timeout = 1 * 1000 * 1000; - status = regs->ic_enable_status; - while (status & IC_ENABLE_CONTROLLER) { - udelay(1); - if (--timeout == 0) - die("ERROR - I2C failed to disable!\n"); - status = regs->ic_enable_status; - } - - /* Clear any pending interrupts */ - status = regs->ic_clr_intr; -} - -int platform_i2c_transfer(unsigned bus, struct i2c_seg *segments, int count) -{ - uint8_t *buffer; - int bytes_transferred; - uint8_t chip; - uint32_t cmd; - int length; - int read_length; - I2C_REGS *regs; - uint32_t status; - uint32_t timeout; - - regs = get_i2c_address(); - - /* Disable the I2C controller to get access to the registers */ - i2c_disable(regs); - - /* Set the slave address */ - ASSERT (count > 0); - ASSERT (segments != NULL); - ASSERT (segments->read == 0); - - /* Clear the start and stop detection */ - status = regs->ic_clr_start_det; - status = regs->ic_clr_stop_det; - - /* Set addressing mode to 7-bit and fast mode */ - cmd = regs->ic_con; - cmd &= ~(IC_CON_10B | IC_CON_SPEED); - cmd |= IC_CON_RESTART_EN | IC_CON_7B | IC_CON_SPEED_100_KHz - | IC_CON_MASTER_MODE; - regs->ic_con = cmd; - - /* Set the target chip address */ - chip = segments->chip; - regs->ic_tar = chip; - - /* Enable the I2C controller */ - regs->ic_enable = IC_ENABLE_CONTROLLER; - - /* Clear the interrupts */ - status = regs->ic_clr_rx_under; - status = regs->ic_clr_rx_over; - status = regs->ic_clr_tx_over; - status = regs->ic_clr_tx_abrt; - - /* Process each of the segments */ - bytes_transferred = 0; - read_length = 0; - buffer = NULL; - while (count-- > 0) { - buffer = segments->buf; - length = segments->len; - ASSERT (buffer != NULL); - ASSERT (length >= 1); - ASSERT (segments->chip = chip); - - if (segments->read) { - /* Place read commands into the FIFO */ - read_length = length; - while (length > 0) { - /* Send stop bit after last byte */ - cmd = IC_DATA_CMD_READ; - if ((count == 0) && (length == 1)) - cmd |= IC_DATA_CMD_STOP; - - /* Place read command in transmit FIFO */ - regs->ic_data_cmd = cmd; - length--; - } - } else { - /* Write the data into the FIFO */ - while (length > 0) { - /* End of the transaction? */ - cmd = IC_DATA_CMD_WRITE | *buffer++; - if ((count == 0) && (length == 1)) - cmd |= IC_DATA_CMD_STOP; - - /* Place a data byte into the FIFO */ - regs->ic_data_cmd = cmd; - length--; - bytes_transferred++; - } - } - segments++; - } - - /* Wait for the end of the transaction */ - timeout = 1 * 1000 * 1000; - do { - status = regs->ic_raw_intr_stat; - if (status & IC_INTR_STOP_DET) - break; - if ((status & (IC_INTR_RX_OVER | IC_INTR_RX_UNDER - | IC_INTR_TX_ABRT | IC_INTR_TX_OVER)) - || (timeout == 0)) { - if (timeout == 0) - printk (BIOS_ERR, - "ERROR - I2C stop bit not received!\n"); - if (status & IC_INTR_RX_OVER) - printk (BIOS_ERR, - "ERROR - I2C receive overrun!\n"); - if (status & IC_INTR_RX_UNDER) - printk (BIOS_ERR, - "ERROR - I2C receive underrun!\n"); - if (status & IC_INTR_TX_ABRT) - printk (BIOS_ERR, - "ERROR - I2C transmit abort!\n"); - if (status & IC_INTR_TX_OVER) - printk (BIOS_ERR, - "ERROR - I2C transmit overrun!\n"); - i2c_disable(regs); - return -1; - } - timeout--; - udelay(1); - } while(1); - - /* Finish reading the data bytes */ - while (read_length > 0) { - status = regs->ic_status; - *buffer++ = (UINT8)regs->ic_data_cmd; - read_length--; - bytes_transferred++; - status = regs->ic_status; - } - - return bytes_transferred; -} - __attribute__((weak)) void mainboard_gpio_i2c_init(device_t dev) { /* Initialize any of the GPIOs or I2C devices */ diff --git a/src/soc/intel/quark/i2c.c b/src/soc/intel/quark/i2c.c new file mode 100644 index 0000000..118cbea --- /dev/null +++ b/src/soc/intel/quark/i2c.c @@ -0,0 +1,176 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <delay.h> +#include <device/device.h> +#include <device/i2c.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <soc/i2c.h> +#include <soc/ramstage.h> +#include <soc/reg_access.h> + +static void i2c_disable(I2C_REGS *regs) +{ + uint32_t status; + uint32_t timeout; + + /* Disable I2C controller */ + regs->ic_enable = 0; + + /* Wait for the enable bit to clear */ + timeout = 1 * 1000 * 1000; + status = regs->ic_enable_status; + while (status & IC_ENABLE_CONTROLLER) { + udelay(1); + if (--timeout == 0) + die("ERROR - I2C failed to disable!\n"); + status = regs->ic_enable_status; + } + + /* Clear any pending interrupts */ + status = regs->ic_clr_intr; +} + +int platform_i2c_transfer(unsigned bus, struct i2c_seg *segments, int count) +{ + uint8_t *buffer; + int bytes_transferred; + uint8_t chip; + uint32_t cmd; + int length; + int read_length; + I2C_REGS *regs; + uint32_t status; + uint32_t timeout; + + regs = get_i2c_address(); + + /* Disable the I2C controller to get access to the registers */ + i2c_disable(regs); + + /* Set the slave address */ + ASSERT (count > 0); + ASSERT (segments != NULL); + ASSERT (segments->read == 0); + + /* Clear the start and stop detection */ + status = regs->ic_clr_start_det; + status = regs->ic_clr_stop_det; + + /* Set addressing mode to 7-bit and fast mode */ + cmd = regs->ic_con; + cmd &= ~(IC_CON_10B | IC_CON_SPEED); + cmd |= IC_CON_RESTART_EN | IC_CON_7B | IC_CON_SPEED_100_KHz + | IC_CON_MASTER_MODE; + regs->ic_con = cmd; + + /* Set the target chip address */ + chip = segments->chip; + regs->ic_tar = chip; + + /* Enable the I2C controller */ + regs->ic_enable = IC_ENABLE_CONTROLLER; + + /* Clear the interrupts */ + status = regs->ic_clr_rx_under; + status = regs->ic_clr_rx_over; + status = regs->ic_clr_tx_over; + status = regs->ic_clr_tx_abrt; + + /* Process each of the segments */ + bytes_transferred = 0; + read_length = 0; + buffer = NULL; + while (count-- > 0) { + buffer = segments->buf; + length = segments->len; + ASSERT (buffer != NULL); + ASSERT (length >= 1); + ASSERT (segments->chip = chip); + + if (segments->read) { + /* Place read commands into the FIFO */ + read_length = length; + while (length > 0) { + /* Send stop bit after last byte */ + cmd = IC_DATA_CMD_READ; + if ((count == 0) && (length == 1)) + cmd |= IC_DATA_CMD_STOP; + + /* Place read command in transmit FIFO */ + regs->ic_data_cmd = cmd; + length--; + } + } else { + /* Write the data into the FIFO */ + while (length > 0) { + /* End of the transaction? */ + cmd = IC_DATA_CMD_WRITE | *buffer++; + if ((count == 0) && (length == 1)) + cmd |= IC_DATA_CMD_STOP; + + /* Place a data byte into the FIFO */ + regs->ic_data_cmd = cmd; + length--; + bytes_transferred++; + } + } + segments++; + } + + /* Wait for the end of the transaction */ + timeout = 1 * 1000 * 1000; + do { + status = regs->ic_raw_intr_stat; + if (status & IC_INTR_STOP_DET) + break; + if ((status & (IC_INTR_RX_OVER | IC_INTR_RX_UNDER + | IC_INTR_TX_ABRT | IC_INTR_TX_OVER)) + || (timeout == 0)) { + if (timeout == 0) + printk (BIOS_ERR, + "ERROR - I2C stop bit not received!\n"); + if (status & IC_INTR_RX_OVER) + printk (BIOS_ERR, + "ERROR - I2C receive overrun!\n"); + if (status & IC_INTR_RX_UNDER) + printk (BIOS_ERR, + "ERROR - I2C receive underrun!\n"); + if (status & IC_INTR_TX_ABRT) + printk (BIOS_ERR, + "ERROR - I2C transmit abort!\n"); + if (status & IC_INTR_TX_OVER) + printk (BIOS_ERR, + "ERROR - I2C transmit overrun!\n"); + i2c_disable(regs); + return -1; + } + timeout--; + udelay(1); + } while(1); + + /* Finish reading the data bytes */ + while (read_length > 0) { + status = regs->ic_status; + *buffer++ = (UINT8)regs->ic_data_cmd; + read_length--; + bytes_transferred++; + status = regs->ic_status; + } + + return bytes_transferred; +}

1 0

Patch merged into coreboot/master: soc/intel/quark: Set temporary I2C base address
by gerrit＠coreboot.org 31 May '16

31 May '16

the following patch was just integrated into master: commit 56c99f28501bbb79a9f8b7a1e1bd698788b42f0e Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Mon May 30 14:16:10 2016 -0700 soc/intel/quark: Set temporary I2C base address Set a temporary I2C base address during romstage. TEST=Build and run on Galileo Gen2 Change-Id: I4b427c66a4e7e6d30cc611d4d3c40bb0ea36066d Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> Reviewed-on: https://review.coreboot.org/15006 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/15006 for details. -gerrit

1 0

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