coreboot-gerrit May 2016

coreboot-gerrit@coreboot.org

1 participants
1843 discussions

Patch merged into coreboot/master: mainboard/intel/galileo: Use HSUART1 for console
by gerrit＠coreboot.org 31 May '16

31 May '16

the following patch was just integrated into master: commit ca65bb7b4e9247362e8667d5833119ffffa82321 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Mon May 30 14:02:49 2016 -0700 mainboard/intel/galileo: Use HSUART1 for console Select HSUART1 for console. TEST=Build and run on Galileo Gen2 Change-Id: I4425af4dc8b3730b3fa2108d6cc2941bc22c2cdb Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> Reviewed-on: https://review.coreboot.org/15005 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/15005 for details. -gerrit

1 0

Patch merged into coreboot/master: Documentation/Intel/Board: Add analog switch link
by gerrit＠coreboot.org 31 May '16

31 May '16

the following patch was just integrated into master: commit 2a8cc3064e56eb129bb43c8b9e251f3bba8e6543 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Mon May 30 11:25:22 2016 -0700 Documentation/Intel/Board: Add analog switch link Add link for TI TS5A23159 specification. TEST=None Change-Id: I2756ded963fc7597e4db1fa151bf62630b1108d9 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> Reviewed-on: https://review.coreboot.org/15003 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/15003 for details. -gerrit

1 0

Patch merged into coreboot/master: soc/intel/quark: Conditionally define BIT names
by gerrit＠coreboot.org 31 May '16

31 May '16

the following patch was just integrated into master: commit d5493683eae95e9b89fcea7e126db7c7b1caf60d Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Mon May 30 05:38:57 2016 -0700 soc/intel/quark: Conditionally define BIT names Only define BIT names if they are not already defined. TEST=Build and run on Galileo Gen2 Change-Id: Ief4c4bb7a42a1bb2a7f46f13dc9b8bbb4d233e3c Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> Reviewed-on: https://review.coreboot.org/15002 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/15002 for details. -gerrit

1 0

Patch merged into coreboot/master: mainboard/intel/galileo: Split out enabling FSP1_1
by gerrit＠coreboot.org 31 May '16

31 May '16

the following patch was just integrated into master: commit 5e808cb811d9cfbf38b9d50ba0de4d5129c2b339 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Sat May 28 14:58:57 2016 -0700 mainboard/intel/galileo: Split out enabling FSP1_1 Split out enabling FSP 1.1 support to prepare for enabling FSP 2.0 support. TEST=Build and run on Galileo Gen2. Change-Id: Ic4e814bcf61f9480f98e2d7bc7a1648dec43a07d Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> Reviewed-on: https://review.coreboot.org/15001 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/15001 for details. -gerrit

1 0

Patch merged into coreboot/master: soc/intel/quark: Fix reg_script display
by gerrit＠coreboot.org 31 May '16

31 May '16

the following patch was just integrated into master: commit 6b24dfce742d92f399a943d72cbae26b5d6f90aa Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Sun May 22 16:24:36 2016 -0700 soc/intel/quark: Fix reg_script display Remove extra ": " following reigster type. TEST=Build and run on Galileo Gen2 Change-Id: I57dd40a540d7b5371a6c45174f47a311b83a2aab Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> Reviewed-on: https://review.coreboot.org/14948 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/14948 for details. -gerrit

1 0

Patch merged into coreboot/master: soc/intel/quark: Clear SMI interrupts and wake events
by gerrit＠coreboot.org 31 May '16

31 May '16

the following patch was just integrated into master: commit 7f4b0539808ceea3854ad56cdc6f1cf69595279b Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Sun May 22 11:52:28 2016 -0700 soc/intel/quark: Clear SMI interrupts and wake events Migrate the clearing of the SMI interrupts and wake events from FSP into coreboot. TEST=Build and run on Galileo Gen2 Change-Id: Ia369801da87a16bc00fb2c05475831ebe8a315f8 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> Reviewed-on: https://review.coreboot.org/14945 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/14945 for details. -gerrit

1 0

Patch set updated for coreboot: soc/intel/quark: Clear SMI interrupts and wake events
by Leroy P Leahy 31 May '16

31 May '16

Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14945 -gerrit commit 69bc517c98bc544a3eee8d83ab7dbcd4e5ba58f0 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Sun May 22 11:52:28 2016 -0700 soc/intel/quark: Clear SMI interrupts and wake events Migrate the clearing of the SMI interrupts and wake events from FSP into coreboot. TEST=Build and run on Galileo Gen2 Change-Id: Ia369801da87a16bc00fb2c05475831ebe8a315f8 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/soc/intel/quark/include/soc/iomap.h | 9 ++++--- src/soc/intel/quark/include/soc/reg_access.h | 22 +++++++++++++++++ src/soc/intel/quark/lpc.c | 18 +++++++++++--- src/soc/intel/quark/reg_access.c | 35 ++++++++++++++++++++++++++++ src/soc/intel/quark/romstage/romstage.c | 19 +++++++++++++++ 5 files changed, 97 insertions(+), 6 deletions(-) diff --git a/src/soc/intel/quark/include/soc/iomap.h b/src/soc/intel/quark/include/soc/iomap.h index ce92676..61773d5 100644 --- a/src/soc/intel/quark/include/soc/iomap.h +++ b/src/soc/intel/quark/include/soc/iomap.h @@ -30,10 +30,13 @@ /* * I/O port address space */ -#define ACPI_BASE_ADDRESS 0x1000 -#define ACPI_BASE_SIZE 0x100 +#define GPE0_BASE_ADDRESS 0x2000 +#define GPE0_SIZE 0x40 -#define LEGACY_GPIO_BASE_ADDRESS 0x1080 +#define PM1BLK_BASE_ADDRESS 0x2040 +#define PM1BLK_SIZE 0x10 + +#define LEGACY_GPIO_BASE_ADDRESS 0x2080 #define LEGACY_GPIO_SIZE 0x80 #define IO_ADDRESS_VALID 0x80000000 diff --git a/src/soc/intel/quark/include/soc/reg_access.h b/src/soc/intel/quark/include/soc/reg_access.h index 580400c..e7a8963 100644 --- a/src/soc/intel/quark/include/soc/reg_access.h +++ b/src/soc/intel/quark/include/soc/reg_access.h @@ -35,6 +35,7 @@ enum { GPIO_REGS, PCIE_AFE_REGS, PCIE_RESET, + GPE0_REGS, }; enum { @@ -46,6 +47,27 @@ enum { _REG_SCRIPT_ENCODE_RAW(REG_SCRIPT_COMMAND_##cmd_, SOC_TYPE, \ size_, reg_, mask_, value_, timeout_, reg_set_) +/* GPE0 controller register access macros */ +#define REG_GPE0_ACCESS(cmd_, reg_, mask_, value_, timeout_) \ + SOC_ACCESS(cmd_, reg_, REG_SCRIPT_SIZE_32, mask_, value_, timeout_, \ + GPE0_REGS) +#define REG_GPE0_READ(reg_) \ + REG_GPE0_ACCESS(READ, reg_, 0, 0, 0) +#define REG_GPE0_WRITE(reg_, value_) \ + REG_GPE0_ACCESS(WRITE, reg_, 0, value_, 0) +#define REG_GPE0_AND(reg_, value_) \ + REG_GPE0_RMW(reg_, value_, 0) +#define REG_GPE0_RMW(reg_, mask_, value_) \ + REG_GPE0_ACCESS(RMW, reg_, mask_, value_, 0) +#define REG_GPE0_RXW(reg_, mask_, value_) \ + REG_GPE0_ACCESS(RXW, reg_, mask_, value_, 0) +#define REG_GPE0_OR(reg_, value_) \ + REG_GPE0_RMW(reg_, 0xffffffff, value_) +#define REG_GPE0_POLL(reg_, mask_, value_, timeout_) \ + REG_GPE0_ACCESS(POLL, reg_, mask_, value_, timeout_) +#define REG_GPE0_XOR(reg_, value_) \ + REG_GPE0_RXW(reg_, 0xffffffff, value_) + /* GPIO controller register access macros */ #define REG_GPIO_ACCESS(cmd_, reg_, mask_, value_, timeout_) \ SOC_ACCESS(cmd_, reg_, REG_SCRIPT_SIZE_32, mask_, value_, timeout_, \ diff --git a/src/soc/intel/quark/lpc.c b/src/soc/intel/quark/lpc.c index fbed935..e57b717 100644 --- a/src/soc/intel/quark/lpc.c +++ b/src/soc/intel/quark/lpc.c @@ -30,10 +30,22 @@ static void pmc_read_resources(device_t dev) /* Get the normal PCI resources of this device. */ pci_dev_read_resources(dev); - /* PMBASE */ + /* GPE0 */ res = new_resource(dev, index++); - res->base = ACPI_BASE_ADDRESS; - res->size = ACPI_BASE_SIZE; + res->base = GPE0_BASE_ADDRESS; + res->size = GPE0_SIZE; + res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + + /* PM1BLK */ + res = new_resource(dev, index++); + res->base = PM1BLK_BASE_ADDRESS; + res->size = PM1BLK_SIZE; + res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + + /* Legacy GPIO */ + res = new_resource(dev, index++); + res->base = LEGACY_GPIO_BASE_ADDRESS; + res->size = LEGACY_GPIO_SIZE; res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } diff --git a/src/soc/intel/quark/reg_access.c b/src/soc/intel/quark/reg_access.c index f7820e9..30cc7db 100644 --- a/src/soc/intel/quark/reg_access.c +++ b/src/soc/intel/quark/reg_access.c @@ -19,6 +19,19 @@ #include <soc/pci_devs.h> #include <soc/ramstage.h> +static uint16_t get_gpe0_address(uint32_t reg_address) +{ + uint32_t gpe0_base_address; + + /* Get the GPE0 base address */ + gpe0_base_address = pci_read_config32(LPC_BDF, R_QNC_LPC_GPE0BLK); + ASSERT (gpe0_base_address >= 0x80000000); + gpe0_base_address &= B_QNC_LPC_GPE0BLK_MASK; + + /* Return the GPE0 register address */ + return (uint16_t)(gpe0_base_address + reg_address); +} + static uint32_t *get_gpio_address(uint32_t reg_address) { uint32_t gpio_base_address; @@ -83,6 +96,18 @@ void mea_write(uint32_t reg_address) & QNC_MEA_MASK); } +static uint32_t reg_gpe0_read(uint32_t reg_address) +{ + /* Read the GPE0 register */ + return inl(get_gpe0_address(reg_address)); +} + +static void reg_gpe0_write(uint32_t reg_address, uint32_t value) +{ + /* Write the GPE0 register */ + outl(get_gpe0_address(reg_address), value); +} + static uint32_t reg_gpio_read(uint32_t reg_address) { /* Read the GPIO register */ @@ -190,6 +215,11 @@ static uint64_t reg_read(struct reg_script_context *ctx) ctx->display_features = REG_SCRIPT_DISPLAY_NOTHING; return 0; + case GPE0_REGS: + ctx->display_prefix = "GPE0: "; + value = reg_gpe0_read(step->reg); + break; + case GPIO_REGS: ctx->display_prefix = "GPIO: "; value = reg_gpio_read(step->reg); @@ -234,6 +264,11 @@ static void reg_write(struct reg_script_context *ctx) ctx->display_features = REG_SCRIPT_DISPLAY_NOTHING; return; + case GPE0_REGS: + ctx->display_prefix = "GPE0: "; + reg_gpe0_write(step->reg, (uint32_t)step->value); + break; + case GPIO_REGS: ctx->display_prefix = "GPIO: "; reg_gpio_write(step->reg, (uint32_t)step->value); diff --git a/src/soc/intel/quark/romstage/romstage.c b/src/soc/intel/quark/romstage/romstage.c index 4ed5863..c4f9844 100644 --- a/src/soc/intel/quark/romstage/romstage.c +++ b/src/soc/intel/quark/romstage/romstage.c @@ -30,10 +30,22 @@ #include <soc/romstage.h> #include <soc/reg_access.h> +static const struct reg_script clear_smi_and_wake_events[] = { + /* Clear any SMI or wake events */ + REG_GPE0_READ(R_QNC_GPE0BLK_GPE0S), + REG_GPE0_READ(R_QNC_GPE0BLK_SMIS), + REG_GPE0_OR(R_QNC_GPE0BLK_GPE0S, B_QNC_GPE0BLK_GPE0S_ALL), + REG_GPE0_OR(R_QNC_GPE0BLK_SMIS, B_QNC_GPE0BLK_SMIS_ALL), + REG_SCRIPT_END +}; + static const struct reg_script legacy_gpio_init[] = { /* Temporarily enable the legacy GPIO controller */ REG_PCI_WRITE32(R_QNC_LPC_GBA_BASE, IO_ADDRESS_VALID | LEGACY_GPIO_BASE_ADDRESS), + /* Temporarily enable the GPE controller */ + REG_PCI_WRITE32(R_QNC_LPC_GPE0BLK, IO_ADDRESS_VALID + | GPE0_BASE_ADDRESS), REG_PCI_OR8(PCI_COMMAND, PCI_COMMAND_IO), REG_SCRIPT_END }; @@ -81,6 +93,7 @@ void soc_memory_init_params(struct romstage_params *params, char *pdat_file; size_t pdat_file_len; const struct soc_intel_quark_config *config; + struct chipset_power_state *ps = car_get_var_ptr(&power_state); /* Locate the pdat.bin file */ pdat_file = cbfs_boot_map_with_leak("pdat.bin", CBFS_TYPE_RAW, @@ -104,6 +117,12 @@ void soc_memory_init_params(struct romstage_params *params, /* Display the ROM shadow data */ hexdump((void *)0x000ffff0, 0x10); + + /* Clear SMI and wake events */ + if (ps->prev_sleep_state != 3) { + printk(BIOS_SPEW, "Clearing SMI interrupts and wake events\n"); + reg_script_run_on_dev(LPC_BDF, clear_smi_and_wake_events); + } } void soc_after_ram_init(struct romstage_params *params)

1 0

Patch merged into coreboot/master: soc/intel/quark: Rename pmc.c to lpc.c
by gerrit＠coreboot.org 31 May '16

31 May '16

the following patch was just integrated into master: commit 773ee2bb17344ebad1e99e997ff6700fc6479044 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Sun May 22 15:34:11 2016 -0700 soc/intel/quark: Rename pmc.c to lpc.c Rename the file pmc.c to lpc.c to prepare for further additions. TEST=Build and run on Galileo Gen2 Change-Id: If98825d72878f0601f77bff8c766276dbda8a9ae Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> Reviewed-on: https://review.coreboot.org/14946 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/14946 for details. -gerrit

1 0

Patch merged into coreboot/master: soc/intel/quark: Add PCIe reset support
by gerrit＠coreboot.org 31 May '16

31 May '16

the following patch was just integrated into master: commit 5ef051a53a03d537b6feab4e85edb69835eb6998 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Fri Apr 29 15:16:54 2016 -0700 soc/intel/quark: Add PCIe reset support Migrate PCIe reset from PlatformPciHelperLib in QuarkFspPkg into coreboot. Change-Id: I1c33fa16b0323091e8f9bd503bbfdb8a253a76d4 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> Reviewed-on: https://review.coreboot.org/14944 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/14944 for details. -gerrit

1 0

Patch set updated for coreboot: soc/intel/quark: Add PCIe reset support
by Leroy P Leahy 31 May '16

31 May '16

Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14944 -gerrit commit 459e8aa01ce796f599f47b43e9d6d0f6758e47e5 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Fri Apr 29 15:16:54 2016 -0700 soc/intel/quark: Add PCIe reset support Migrate PCIe reset from PlatformPciHelperLib in QuarkFspPkg into coreboot. Change-Id: I1c33fa16b0323091e8f9bd503bbfdb8a253a76d4 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/mainboard/intel/galileo/gen1.h | 3 + src/mainboard/intel/galileo/gen2.h | 3 + src/mainboard/intel/galileo/gpio.c | 17 +++++ src/soc/intel/quark/include/soc/pci_devs.h | 17 ++++- src/soc/intel/quark/include/soc/reg_access.h | 31 ++++++++ src/soc/intel/quark/include/soc/romstage.h | 1 + src/soc/intel/quark/reg_access.c | 38 +++++++++- src/soc/intel/quark/romstage/Makefile.inc | 1 + src/soc/intel/quark/romstage/pcie.c | 109 +++++++++++++++++++++++++++ src/soc/intel/quark/romstage/romstage.c | 3 + 10 files changed, 219 insertions(+), 4 deletions(-) diff --git a/src/mainboard/intel/galileo/gen1.h b/src/mainboard/intel/galileo/gen1.h index 26335da..e1e8f59 100644 --- a/src/mainboard/intel/galileo/gen1.h +++ b/src/mainboard/intel/galileo/gen1.h @@ -13,6 +13,9 @@ * GNU General Public License for more details. */ +/* PCIe reset pin */ +#define GEN1_PCI_RESET_RESUMEWELL_GPIO 3 + /* Jumper J2 determines the slave address of Cypress I/O GPIO expander */ #define GALILEO_DETERMINE_IOEXP_SLA_RESUMEWELL_GPIO 5 diff --git a/src/mainboard/intel/galileo/gen2.h b/src/mainboard/intel/galileo/gen2.h index 108971b..8eee744 100644 --- a/src/mainboard/intel/galileo/gen2.h +++ b/src/mainboard/intel/galileo/gen2.h @@ -13,6 +13,9 @@ * GNU General Public License for more details. */ +/* PCIe reset pin */ +#define GEN2_PCI_RESET_RESUMEWELL_GPIO 0 + static const struct reg_script gen2_gpio_init[] = { /* Initialize the legacy GPIO controller */ REG_LEG_GPIO_WRITE(R_QNC_GPIO_CGEN_CORE_WELL, 0x03), diff --git a/src/mainboard/intel/galileo/gpio.c b/src/mainboard/intel/galileo/gpio.c index a411c5a..3184381 100644 --- a/src/mainboard/intel/galileo/gpio.c +++ b/src/mainboard/intel/galileo/gpio.c @@ -50,3 +50,20 @@ void mainboard_gpio_init(void) script = gen1_gpio_init; reg_script_run(script); } + +void mainboard_gpio_pcie_reset(uint32_t pin_value) +{ + uint32_t pin_number; + uint32_t value; + + /* Determine the correct PCIe reset pin */ + if (IS_ENABLED(CONFIG_GALILEO_GEN2)) + pin_number = GEN2_PCI_RESET_RESUMEWELL_GPIO; + else + pin_number = GEN1_PCI_RESET_RESUMEWELL_GPIO; + + /* Update the PCIe reset value */ + value = reg_legacy_gpio_read(R_QNC_GPIO_RGLVL_RESUME_WELL); + value = (value & ~(1 << pin_number)) | ((pin_value & 1) << pin_number); + reg_legacy_gpio_write(R_QNC_GPIO_RGLVL_RESUME_WELL, value); +} diff --git a/src/soc/intel/quark/include/soc/pci_devs.h b/src/soc/intel/quark/include/soc/pci_devs.h index 67d8d32..ff9d65f 100644 --- a/src/soc/intel/quark/include/soc/pci_devs.h +++ b/src/soc/intel/quark/include/soc/pci_devs.h @@ -18,9 +18,8 @@ #ifndef _QUARK_PCI_DEVS_H_ #define _QUARK_PCI_DEVS_H_ -#include <arch/io.h> #include <device/pci.h> -#include <soc/QuarkNcSocId.h> +#include <soc/reg_access.h> /* DEVICE 0 (Memory Controller Hub) */ #define MC_BDF PCI_DEV(PCI_BUS_NUMBER_QNC, MC_DEV, MC_FUN) @@ -29,6 +28,8 @@ #define I2CGPIO_DEVID 0x0934 #define HSUART_DEVID 0x0936 #define EHCI_DEVID 0x0939 +#define PCIE_PORT0_DEVID 0x11c3 +#define PCIE_PORT1_DEVID 0x11c4 /* IO Fabric 1 */ #define SIO1_DEV 0x14 @@ -45,6 +46,18 @@ #define I2CGPIO_DEV_FUNC PCI_DEVFN(I2CGPIO_DEV, I2CGPIO_FUNC) #define I2CGPIO_BDF PCI_DEV(PCI_BUS_NUMBER_QNC, I2CGPIO_DEV, I2CGPIO_FUNC) +/* PCIe Ports */ +#define PCIE_DEV 0x17 +#define PCIE_PORT0_DEV PCIE_DEV +#define PCIE_PORT0_FUNC 0 +#define PCIE_PORT0_DEV_FUNC DEV_FUNC(PCIE_DEV, PCIE_PORT0_FUNC) +#define PCIE_PORT0_BDF PCI_DEV(PCI_BUS_NUMBER_QNC, PCIE_DEV, PCIE_PORT0_FUNC) + +#define PCIE_PORT1_DEV PCIE_DEV +#define PCIE_PORT1_FUNC 1 +#define PCIE_PORT1_DEV_FUNC DEV_FUNC(PCIE_DEV,PCIE_PORT1_FUNC) +#define PCIE_PORT1_BDF PCI_DEV(PCI_BUS_NUMBER_QNC, PCIE_DEV, PCIE_PORT1_FUNC) + /* Platform Controller Unit */ #define LPC_DEV PCI_DEVICE_NUMBER_QNC_LPC #define LPC_FUNC PCI_FUNCTION_NUMBER_QNC_LPC diff --git a/src/soc/intel/quark/include/soc/reg_access.h b/src/soc/intel/quark/include/soc/reg_access.h index 66ab7b8..580400c 100644 --- a/src/soc/intel/quark/include/soc/reg_access.h +++ b/src/soc/intel/quark/include/soc/reg_access.h @@ -16,6 +16,9 @@ #ifndef _QUARK_REG_ACCESS_H_ #define _QUARK_REG_ACCESS_H_ +#define __SIMPLE_DEVICE__ + +#include <arch/io.h> #include <delay.h> #include <fsp/util.h> #include <reg_script.h> @@ -30,6 +33,8 @@ enum { MICROSECOND_DELAY, LEG_GPIO_REGS, GPIO_REGS, + PCIE_AFE_REGS, + PCIE_RESET, }; enum { @@ -83,6 +88,31 @@ enum { #define REG_LEG_GPIO_XOR(reg_, value_) \ REG_LEG_GPIO_RXW(reg_, 0xffffffff, value_) +/* PCIE AFE register access macros */ +#define REG_PCIE_AFE_ACCESS(cmd_, reg_, mask_, value_, timeout_) \ + SOC_ACCESS(cmd_, reg_, REG_SCRIPT_SIZE_32, mask_, value_, timeout_, \ + PCIE_AFE_REGS) +#define REG_PCIE_AFE_READ(reg_) \ + REG_PCIE_AFE_ACCESS(READ, reg_, 0, 0, 0) +#define REG_PCIE_AFE_WRITE(reg_, value_) \ + REG_PCIE_AFE_ACCESS(WRITE, reg_, 0, value_, 0) +#define REG_PCIE_AFE_AND(reg_, value_) \ + REG_PCIE_AFE_RMW(reg_, value_, 0) +#define REG_PCIE_AFE_RMW(reg_, mask_, value_) \ + REG_PCIE_AFE_ACCESS(RMW, reg_, mask_, value_, 0) +#define REG_PCIE_AFE_RXW(reg_, mask_, value_) \ + REG_PCIE_AFE_ACCESS(RXW, reg_, mask_, value_, 0) +#define REG_PCIE_AFE_OR(reg_, value_) \ + REG_PCIE_AFE_RMW(reg_, 0xffffffff, value_) +#define REG_PCIE_AFE_POLL(reg_, mask_, value_, timeout_) \ + REG_PCIE_AFE_ACCESS(POLL, reg_, mask_, value_, timeout_) +#define REG_PCIE_AFE_XOR(reg_, value_) \ + REG_PCIE_AFE_RXW(reg_, 0xffffffff, value_) + +/* PCIe reset */ +#define MAINBOARD_PCIE_RESET(pin_value_) \ + SOC_ACCESS(WRITE, 0, REG_SCRIPT_SIZE_32, 1, pin_value_, 0, PCIE_RESET) + /* RMU temperature register access macros */ #define REG_RMU_TEMP_ACCESS(cmd_, reg_, mask_, value_, timeout_) \ SOC_ACCESS(cmd_, reg_, REG_SCRIPT_SIZE_32, mask_, value_, timeout_, \ @@ -152,6 +182,7 @@ enum { void *get_i2c_address(void); void mainboard_gpio_init(void); +void mainboard_gpio_pcie_reset(uint32_t pin_value); void mcr_write(uint8_t opcode, uint8_t port, uint32_t reg_address); uint32_t mdr_read(void); void mdr_write(uint32_t value); diff --git a/src/soc/intel/quark/include/soc/romstage.h b/src/soc/intel/quark/include/soc/romstage.h index c344ada..3a9e7a8 100644 --- a/src/soc/intel/quark/include/soc/romstage.h +++ b/src/soc/intel/quark/include/soc/romstage.h @@ -29,5 +29,6 @@ uint32_t port_reg_read(uint8_t port, uint32_t offset); void port_reg_write(uint8_t port, uint32_t offset, uint32_t value); void report_platform_info(void); int set_base_address_and_enable_uart(u8 bus, u8 dev, u8 func, u32 mmio_base); +void pcie_init(void); #endif /* _QUARK_ROMSTAGE_H_ */ diff --git a/src/soc/intel/quark/reg_access.c b/src/soc/intel/quark/reg_access.c index 4734135..f7820e9 100644 --- a/src/soc/intel/quark/reg_access.c +++ b/src/soc/intel/quark/reg_access.c @@ -15,10 +15,9 @@ #define __SIMPLE_DEVICE__ -#include <arch/io.h> #include <console/console.h> #include <soc/pci_devs.h> -#include <soc/reg_access.h> +#include <soc/ramstage.h> static uint32_t *get_gpio_address(uint32_t reg_address) { @@ -108,6 +107,24 @@ void reg_legacy_gpio_write(uint32_t reg_address, uint32_t value) outl(value, get_legacy_gpio_address(reg_address)); } +static uint32_t reg_pcie_afe_read(uint32_t reg_address) +{ + /* Read the PCIE AFE register */ + mea_write(reg_address); + mcr_write(QUARK_OPCODE_IO_READ, QUARK_SC_PCIE_AFE_SB_PORT_ID, + reg_address); + return mdr_read(); +} + +static void reg_pcie_afe_write(uint32_t reg_address, uint32_t value) +{ + /* Write the PCIE AFE register */ + mea_write(reg_address); + mdr_write(value); + mcr_write(QUARK_OPCODE_IO_WRITE, QUARK_SC_PCIE_AFE_SB_PORT_ID, + reg_address); +} + uint32_t reg_rmu_temp_read(uint32_t reg_address) { /* Read the RMU temperature register */ @@ -181,6 +198,10 @@ static uint64_t reg_read(struct reg_script_context *ctx) case LEG_GPIO_REGS: ctx->display_prefix = "Legacy GPIO: "; value = reg_legacy_gpio_read(step->reg); + + case PCIE_AFE_REGS: + ctx->display_prefix = "PCIe AFE: "; + value = reg_pcie_afe_read(step->reg); break; case RMU_TEMP_REGS: @@ -223,6 +244,19 @@ static void reg_write(struct reg_script_context *ctx) reg_legacy_gpio_write(step->reg, (uint32_t)step->value); break; + case PCIE_AFE_REGS: + ctx->display_prefix = "PCIe AFE: "; + reg_pcie_afe_write(step->reg, (uint32_t)step->value); + break; + + case PCIE_RESET: + if (ctx->display_features) { + ctx->display_prefix = "PCIe reset: "; + ctx->display_features &= ~REG_SCRIPT_DISPLAY_REGISTER; + } + mainboard_gpio_pcie_reset(step->value); + break; + case RMU_TEMP_REGS: ctx->display_prefix = "RMU TEMP"; reg_rmu_temp_write(step->reg, (uint32_t)step->value); diff --git a/src/soc/intel/quark/romstage/Makefile.inc b/src/soc/intel/quark/romstage/Makefile.inc index fc7bd6a..2f29b06 100644 --- a/src/soc/intel/quark/romstage/Makefile.inc +++ b/src/soc/intel/quark/romstage/Makefile.inc @@ -17,6 +17,7 @@ cpu_incs-y += $(src)/soc/intel/quark/romstage/esram_init.inc cpu_incs-y += $(src)/soc/intel/quark/romstage/cache_as_ram.inc romstage-y += mtrr.c +romstage-y += pcie.c romstage-y += report_platform.c romstage-y += romstage.c romstage-$(CONFIG_ENABLE_BUILTIN_HSUART1) += uart.c diff --git a/src/soc/intel/quark/romstage/pcie.c b/src/soc/intel/quark/romstage/pcie.c new file mode 100644 index 0000000..f2adc18 --- /dev/null +++ b/src/soc/intel/quark/romstage/pcie.c @@ -0,0 +1,109 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <delay.h> +#include <device/device.h> +#include <device/pci_ids.h> +#include <soc/pci_devs.h> +#include <soc/reg_access.h> +#include <soc/romstage.h> + +/* Minimum time in microseconds for assertion of PERST# signal */ +#define PCIEXP_PERST_MIN_ASSERT_US 100 + +/* Microsecond delay post issuing common lane reset */ +#define PCIEXP_DELAY_US_POST_CMNRESET_RESET 1 + +/* Microsecond delay to wait for PLL to lock */ +#define PCIEXP_DELAY_US_WAIT_PLL_LOCK 80 + +/* Microsecond delay post issuing sideband interface reset */ +#define PCIEXP_DELAY_US_POST_SBI_RESET 20 + +/* Microsecond delay post deasserting PERST# */ +#define PCIEXP_DELAY_US_POST_PERST_DEASSERT 10 + +const struct reg_script pcie_init_script[] = { + /* Assert PCIe reset# */ + MAINBOARD_PCIE_RESET(0), + + /* PHY Common lane reset */ + REG_SOC_UNIT_OR(QUARK_SCSS_SOC_UNIT_SOCCLKEN_CONFIG, + SOCCLKEN_CONFIG_PHY_I_CMNRESET_L), + + /* Wait post common lane reset */ + TIME_DELAY_USEC(PCIEXP_DELAY_US_POST_CMNRESET_RESET), + + /* PHY Sideband interface reset. + * Controller main reset + */ + REG_SOC_UNIT_OR(QUARK_SCSS_SOC_UNIT_SOCCLKEN_CONFIG, + SOCCLKEN_CONFIG_SBI_RST_100_CORE_B + | SOCCLKEN_CONFIG_PHY_I_SIDE_RST_L), + TIME_DELAY_USEC(PCIEXP_DELAY_US_WAIT_PLL_LOCK), + + /* Controller sideband interface reset */ + REG_SOC_UNIT_OR(QUARK_SCSS_SOC_UNIT_SOCCLKEN_CONFIG, + SOCCLKEN_CONFIG_SBI_BB_RST_B), + + /* Wait post sideband interface reset */ + TIME_DELAY_USEC(PCIEXP_DELAY_US_POST_SBI_RESET), + + /* Deassert PCIe reset# */ + MAINBOARD_PCIE_RESET(1), + + /* Wait post de assert PERST#. */ + TIME_DELAY_USEC(PCIEXP_DELAY_US_POST_PERST_DEASSERT), + + /* Controller primary interface reset */ + REG_SOC_UNIT_OR(QUARK_SCSS_SOC_UNIT_SOCCLKEN_CONFIG, + SOCCLKEN_CONFIG_BB_RST_B), + + /* Set the mixer load resistance */ + REG_PCIE_AFE_AND(QUARK_PCIE_AFE_PCIE_RXPICTRL0_L0, + OCFGPIMIXLOAD_1_0_MASK), + REG_PCIE_AFE_AND(QUARK_PCIE_AFE_PCIE_RXPICTRL0_L1, + OCFGPIMIXLOAD_1_0_MASK), + REG_SCRIPT_END +}; + +static const struct reg_script pcie_bus_init_script[] = { + /* Setup Message Bus Idle Counter (SBIC) values */ + REG_PCI_RMW8(R_QNC_PCIE_IOSFSBCTL, ~B_QNC_PCIE_IOSFSBCTL_SBIC_MASK, + V_PCIE_ROOT_PORT_SBIC_VALUE), + REG_PCI_READ8(R_QNC_PCIE_IOSFSBCTL), + + /* Set the IPF bit in MCR2 */ + REG_PCI_OR32(R_QNC_PCIE_MPC2, B_QNC_PCIE_MPC2_IPF), + REG_PCI_READ32(R_QNC_PCIE_MPC2), + + /* Set up the Posted and Non Posted Request sizes for PCIe */ + REG_PCI_RMW32(R_QNC_PCIE_CCFG, ~B_QNC_PCIE_CCFG_UPSD, + (B_QNC_PCIE_CCFG_UNRS | B_QNC_PCIE_CCFG_UPRS)), + REG_PCI_READ32(R_QNC_PCIE_CCFG), + REG_SCRIPT_END +}; + +void pcie_init(void) +{ + /* Initialize the PCIe bridges */ + printk(BIOS_DEBUG, "Initializing PCIe controllers\n"); + reg_script_run(pcie_init_script); + printk(BIOS_DEBUG, "Initializing PCIe bus 0\n"); + reg_script_run_on_dev(PCIE_PORT0_BDF, pcie_bus_init_script); + printk(BIOS_DEBUG, "Initializing PCIe bus 1\n"); + reg_script_run_on_dev(PCIE_PORT1_BDF, pcie_bus_init_script); +} diff --git a/src/soc/intel/quark/romstage/romstage.c b/src/soc/intel/quark/romstage/romstage.c index 2f16c5f..4ed5863 100644 --- a/src/soc/intel/quark/romstage/romstage.c +++ b/src/soc/intel/quark/romstage/romstage.c @@ -125,6 +125,9 @@ void soc_after_ram_init(struct romstage_params *params) /* Display the DRAM data */ hexdump((void *)0x000ffff0, 0x10); + + /* Initialize the PCIe bridges */ + pcie_init(); } void soc_display_memory_init_params(const MEMORY_INIT_UPD *old,

1 0

← Newer
1
2
3
4
5
6
7
...
185
Older →

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit May 2016