coreboot-gerrit May 2016

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New patch to review for coreboot: nau8825: Add driver for I2C codec
by Duncan Laurie 31 May '16

31 May '16

Duncan Laurie (dlaurie(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15015 -gerrit commit f0b5867e47e2a69b830b66fa41a8d9654255a6b5 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Tue May 10 20:20:16 2016 -0700 nau8825: Add driver for I2C codec The Nuvoton NAU8825 audio codec is an I2C device that has a number of tunable parameters that can be provided to the kernel device driver for basic configuration and optimal operation. The configuration options are exposed to devicetree as registers and then presented as Device Properties via ACPI to the operation system. This sample configuration in devicetree: device pci 19.2 on chip drivers/i2c/nau8825 register "irq" = "IRQ_LEVEL_LOW(GPP_F10_IRQ)" register "jkdet_enable" = "1" register "sar_threshold_num" = "2" register "sar_threshold[0]" = "0x0c" register "sar_threshold[1]" = "0x1c" device i2c 1a on end end end Will generate the following code in the SSDT, trimmed for this commit message as there are more properties that can be configured: Scope (\_SB.PCI0.I2C4) { Name (_HID, "10508825") Name (_UID, Zero) Name (_DDN, "Nuvoton NAU8825 Codec") Method (_STA) { Return (0xF) } Name (_CRS, ResourceTemplate () { I2cSerialBus (0x1A, ControllerInitiated, 0x61A80, AddressingMode7Bit, "\_SB.PCI0.I2C4", 0, ResourceConsumer) Interrupt (ResourceConsumer, Level, ActiveLow) { 0x3A } }) Name (_DSD, Package () { ToUUID ("daffd814-6eba-4d8c-8a91-bc9bff4aa301"), Package () { Package () { "nuvoton,jkdet-enable", 1 }, Package () { "nuvoton,sar-threshold-num", 2 }, Package () { "nuvoton,sar-threshold", Package () { 0x0c, 0x1c } } } }) } Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Change-Id: I480d72daf5ac3dded9b1cbb5fbc737b9dfde3834 --- src/drivers/i2c/nau8825/Kconfig | 2 + src/drivers/i2c/nau8825/Makefile.inc | 1 + src/drivers/i2c/nau8825/chip.h | 96 ++++++++++++++++++++++++++++ src/drivers/i2c/nau8825/nau8825.c | 117 +++++++++++++++++++++++++++++++++++ 4 files changed, 216 insertions(+) diff --git a/src/drivers/i2c/nau8825/Kconfig b/src/drivers/i2c/nau8825/Kconfig new file mode 100644 index 0000000..d2bdd02 --- /dev/null +++ b/src/drivers/i2c/nau8825/Kconfig @@ -0,0 +1,2 @@ +config DRIVERS_I2C_NAU8825 + bool diff --git a/src/drivers/i2c/nau8825/Makefile.inc b/src/drivers/i2c/nau8825/Makefile.inc new file mode 100644 index 0000000..6f32643 --- /dev/null +++ b/src/drivers/i2c/nau8825/Makefile.inc @@ -0,0 +1 @@ +ramstage-$(CONFIG_DRIVERS_I2C_NAU8825) += nau8825.c diff --git a/src/drivers/i2c/nau8825/chip.h b/src/drivers/i2c/nau8825/chip.h new file mode 100644 index 0000000..e6c88bc --- /dev/null +++ b/src/drivers/i2c/nau8825/chip.h @@ -0,0 +1,96 @@ +#include <arch/acpi_device.h> + +#define NAU8825_MAX_BUTTONS 8 + +/* + * Nuvoton NAU8825 audio codec devicetree bindings + * linux/Documentation/devicetree/bindings/sound/nau8825.txt + */ +struct drivers_i2c_nau8825_config { + /* Interrupt configuration */ + struct acpi_irq irq; + + /* I2C Bus Frequency in Hertz (default 400kHz) */ + unsigned bus_speed; + + /* Enable jack detection via JKDET pin */ + unsigned jkdet_enable; + + /* Enable JKDET pin pull if set, otherwise high impedance state */ + unsigned jkdet_pull_enable; + + /* Pull-up JKDET pin if set, otherwise pull down */ + unsigned jkdet_pull_up; + + /* JKDET pin polarity, 0 => active high, 1 => active low */ + unsigned jkdet_polarity; + + /* + * VREF Impedance selection + * 0 - Open + * 1 - 25 kOhm + * 2 - 125 kOhm + * 3 - 2.5 kOhm + */ + unsigned vref_impedance; + + /* Button impedance measurement hysteresis */ + unsigned sar_hysteresis; + + /* + * Reference voltage for button impedance measurement and micbias + * 0 - VDDA + * 1 - VDDA + * 2 - VDDA * 1.1 + * 3 - VDDA * 1.2 + * 4 - VDDA * 1.3 + * 5 - VDDA * 1.4 + * 6 - VDDA * 1.53 + * 7 - VDDA * 1.53 + */ + unsigned micbias_voltage; + unsigned sar_voltage; + + /* + * SAR compare time + * 0 - 500 ns + * 1 - 1 us + * 2 - 2 us + * 3 - 4 us + */ + unsigned sar_compare_time; + + /* + * SAR sampling time + * 0 - 2 us + * 1 - 4 us + * 2 - 8 us + * 3 - 16 us + */ + unsigned sar_sampling_time; + + /* + * Button short key press debounce time + * 0 - 30 ms + * 1 - 50 ms + * 2 - 100 ms + * 3 - 30 ms + */ + unsigned short_key_debounce; + + /* Debounce time 2^(n+2) ms (0-7) for jack insert */ + unsigned jack_insert_debounce; + + /* Debounce time 2^(n+2) ms (0-7) for jack eject */ + unsigned jack_eject_debounce; + + /* Number of buttons supported, up to 8 */ + unsigned sar_threshold_num; + + /* + * Impedance threshold for each button, up to 8 + * SAR = 255 * micbias_voltage / sar_voltage * R / (2000 + R) + * R is Button impedance + */ + uint64_t sar_threshold[NAU8825_MAX_BUTTONS]; +}; diff --git a/src/drivers/i2c/nau8825/nau8825.c b/src/drivers/i2c/nau8825/nau8825.c new file mode 100644 index 0000000..71aacea --- /dev/null +++ b/src/drivers/i2c/nau8825/nau8825.c @@ -0,0 +1,117 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/acpi.h> +#include <arch/acpi_device.h> +#include <arch/acpigen.h> +#include <console/console.h> +#include <device/i2c.h> +#include <device/device.h> +#include <device/path.h> +#include <stdint.h> +#include <string.h> +#include "chip.h" + +#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) + +#define NAU8825_ACPI_NAME "NAU8" +#define NAU8825_ACPI_HID "10508825" +#define NAU8825_DP_INT(key,val) acpi_dp_write_integer("nuvoton," key, (val)) + +static void nau8825_fill_ssdt(struct device *dev) +{ + struct drivers_i2c_nau8825_config *config = dev->chip_info; + const char *scope = acpi_device_scope(dev); + struct acpi_i2c i2c = { + .address = dev->path.i2c.device, + .mode_10bit = dev->path.i2c.mode_10bit, + .speed = config->bus_speed ? : I2C_SPEED_FAST, + .resource = scope, + }; + + if (!dev->enabled || !scope) + return; + if (config->sar_threshold_num > NAU8825_MAX_BUTTONS) + return; + + /* Device */ + acpigen_write_scope(scope); + acpigen_write_device(acpi_device_name(dev)); + acpigen_write_name_string("_HID", NAU8825_ACPI_HID); + acpigen_write_name_integer("_UID", 0); + acpigen_write_name_string("_DDN", dev->chip_ops->name); + acpigen_write_STA(ACPI_STATUS_DEVICE_ALL_ON); + + /* Resources */ + acpigen_write_name("_CRS"); + acpigen_write_resourcetemplate_header(); + acpi_device_write_i2c(&i2c); + acpi_device_write_interrupt(&config->irq); + acpigen_write_resourcetemplate_footer(); + + /* Device Properties */ + acpi_dp_write_header(); + NAU8825_DP_INT("jkdet-enable", config->jkdet_enable); + NAU8825_DP_INT("jkdet-pull-enable", config->jkdet_pull_enable); + NAU8825_DP_INT("jkdet-pull-up", config->jkdet_pull_up); + NAU8825_DP_INT("jkdet-polarity", config->jkdet_polarity); + NAU8825_DP_INT("vref-impedance", config->vref_impedance); + NAU8825_DP_INT("micbias-voltage", config->micbias_voltage); + NAU8825_DP_INT("sar-hysteresis", config->sar_hysteresis); + NAU8825_DP_INT("sar-voltage", config->sar_voltage); + NAU8825_DP_INT("sar-compare-time", config->sar_compare_time); + NAU8825_DP_INT("sar-sampling-time", config->sar_sampling_time); + NAU8825_DP_INT("short-key-debounce", config->short_key_debounce); + NAU8825_DP_INT("jack-insert-debounce", config->jack_insert_debounce); + NAU8825_DP_INT("jack-eject-deboune", config->jack_eject_debounce); + NAU8825_DP_INT("sar-threshold-num", config->sar_threshold_num); + acpi_dp_write_integer_array("nuvoton,sar-threshold", + config->sar_threshold, + config->sar_threshold_num); + acpi_dp_write_footer(); + + acpigen_pop_len(); /* Device */ + acpigen_pop_len(); /* Scope */ + + printk(BIOS_INFO, "%s: %s address 0%xh irq %d\n", + acpi_device_path(dev), dev->chip_ops->name, + dev->path.i2c.device, config->irq.pin); +} + +static const char *nau8825_acpi_name(struct device *dev) +{ + return NAU8825_ACPI_NAME; +} +#endif + +static struct device_operations nau8825_ops = { + .read_resources = DEVICE_NOOP, + .set_resources = DEVICE_NOOP, + .enable_resources = DEVICE_NOOP, +#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) + .acpi_name = &nau8825_acpi_name, + .acpi_fill_ssdt_generator = &nau8825_fill_ssdt, +#endif +}; + +static void nau8825_enable(struct device *dev) +{ + dev->ops = &nau8825_ops; +} + +struct chip_operations drivers_i2c_nau8825_ops = { + CHIP_NAME("Nuvoton NAU8825 Codec") + .enable_dev = &nau8825_enable +};

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Patch merged into coreboot/master: skylake: Add SD card device to configure card detect GPIO
by gerrit＠coreboot.org 31 May '16

31 May '16

the following patch was just integrated into master: commit b25a45ca46478bb5b0989f7e3f3aa5bdd8b36ef2 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Tue May 10 15:56:16 2016 -0700 skylake: Add SD card device to configure card detect GPIO Add a PCI driver for the skylake SD card device and have it generate an entry in the SSDT for the card detect GPIO if it is provided by the mainboard in devicetree. This sets up a card detect GPIO configuration that will trigger an interrupt on both edges with a 100ms debounce timeout and can wake the SD controller from D3 state. The GpioInt() entry is bound to the "cd-gpio" device property which will be consumed by the kernel driver. The resulting ACPI output in the SSDT will be combined with the SDXC device declaration in the DSDT. Example: Scope (\_SB.PCI0.SDXC) { Name (_CRS, ResourceTemplate () { GpioInt (Edge, ActiveBoth, SharedAndWake, PullNone, 10000, "\\_SB.PCI0.GPIO", 0, ResourceConsumer) { 35 } }) Name (_DSD, Package () { ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), Package () { Package () { "cd-gpio", Package () { \_SB.PCI0.SDXC, 0, 0, 1 } } } }) } Change-Id: Ie4c1bfadd962cf55a987edb9ef86e92174205770 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://review.coreboot.org/14995 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See https://review.coreboot.org/14995 for details. -gerrit

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Patch merged into coreboot/master: skylake: Cleanup formatting in pci_devs.h
by gerrit＠coreboot.org 31 May '16

31 May '16

the following patch was just integrated into master: commit 98d69c0627f47d79554f33893ca332d37d974799 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Fri May 20 16:00:36 2016 -0700 skylake: Cleanup formatting in pci_devs.h Minor cleanups in pci_devs.h for indentation and newlines to be consistent throughout the file. Change-Id: I522df141a6b33d918cfb3de1b9019c0c4a73e3e5 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://review.coreboot.org/14994 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See https://review.coreboot.org/14994 for details. -gerrit

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Patch merged into coreboot/master: skylake: Add Audio DSP device
by gerrit＠coreboot.org 31 May '16

31 May '16

the following patch was just integrated into master: commit 026003e62169f31ea963100bf12cb1324d044882 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Tue May 10 15:42:42 2016 -0700 skylake: Add Audio DSP device Add the Audio DSP device for skylake as a PCI driver with a static scan_bus handler so generic devices can be declared under it. This is for devices like the Maxim 98357A which is connected on the I2S bus for data but has no control channel bus and instead just has a GPIO for channel selection and power down control and needs to describe that GPIO connection to the OS via ACPI. Change-Id: Iae02132ff9c510562483108ab280323f78873afd Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://review.coreboot.org/14993 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See https://review.coreboot.org/14993 for details. -gerrit

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Patch merged into coreboot/master: skylake: Add I2C devices
by gerrit＠coreboot.org 31 May '16

31 May '16

the following patch was just integrated into master: commit 0d8bb7427bb431b3e691dbe78cfbdddee9ec0528 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Tue May 10 15:31:22 2016 -0700 skylake: Add I2C devices Add the I2C devices to skylake with the scan_bus handler for SMBUS devices so that I2C-based devices can be declared in devicetree.cb and get initialized properly during ramstage. This does not yet provide the I2C driver, but it allows for devices that are declared in devicetree.cb to provide ACPI tables to the OS. Change-Id: I9dfe4a06a8b0bc549a2b0e2d7c033c895188ba30 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://review.coreboot.org/14992 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See https://review.coreboot.org/14992 for details. -gerrit

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Patch merged into coreboot/master: skylake: Add GPE header file to chip.h
by gerrit＠coreboot.org 31 May '16

31 May '16

the following patch was just integrated into master: commit 011533e4c3d5fa26b5750a0d400556cbaf9441df Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Wed May 11 15:08:50 2016 -0700 skylake: Add GPE header file to chip.h Add the GPE header file to skylake chip.h so the SOC-defined macros for the various GPE values can be used in devicetree directly. For example: chip drivers/i2c/touchpad register "wake" = "GPE0_DW0_05" device i2c 15.0 on end end Change-Id: Ic322108561b34aa34a24a4daba6ba7a4f7a3f9a4 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://review.coreboot.org/14991 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See https://review.coreboot.org/14991 for details. -gerrit

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Patch merged into coreboot/master: Fix leaking CONFIG_VGA=y
by gerrit＠coreboot.org 31 May '16

31 May '16

the following patch was just integrated into master: commit 8f3aaa8a4c84b3fc18bee57219b8e2927e996808 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Mon May 16 14:49:57 2016 +0300 Fix leaking CONFIG_VGA=y Items under DEVICE_SPECIFIC_OPTIONS got selected without the driver being selected. Change-Id: I1797fa6175620a9291873559a6308eaea85a090e Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/14823 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See https://review.coreboot.org/14823 for details. -gerrit

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New patch to review for coreboot: aopen/dxplplusu: Disable HW scrubber
by Kyösti Mälkki 31 May '16

31 May '16

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15014 -gerrit commit ee652190420f878bc86cb7275cd9a376acde0c8e Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue May 31 17:20:45 2016 +0300 aopen/dxplplusu: Disable HW scrubber See code to see the awful hack that got us around cache-as-ram that gets invalidated on ECC HW scrubbing. It once worked, but compiler nowadays puts more registers on stack we should backup. Not much interest to try fix ECC for this particular board. Change-Id: Ie6a09e28b0af5bbf2d68af72f5d98c03df33c402 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/mainboard/aopen/dxplplusu/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/aopen/dxplplusu/Kconfig b/src/mainboard/aopen/dxplplusu/Kconfig index 1802b5a..b64ac1d 100644 --- a/src/mainboard/aopen/dxplplusu/Kconfig +++ b/src/mainboard/aopen/dxplplusu/Kconfig @@ -12,7 +12,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select UDELAY_TSC select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_512 - select HW_SCRUBBER +# select HW_SCRUBBER config MAINBOARD_DIR string

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Patch merged into coreboot/master: mainboard/asus/[kgpe-d16|kcma-d8]: Enable secondary serial port header
by gerrit＠coreboot.org 31 May '16

31 May '16

the following patch was just integrated into master: commit ca543396a7338a47bf9578d058c6af4f9d8f8ee2 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Wed May 18 13:33:13 2016 -0500 mainboard/asus/[kgpe-d16|kcma-d8]: Enable secondary serial port header The ASUS KGPE-D16/KCMA-D8 have an on-board header for a second RS-232 serial port, however it is disabled by default due to the SuperIO default pin mux settings. Enable the secondary serial port early in romstage to allow use during / after initial boot. Change-Id: I5b83659dd8b0d6af559c9ceccee55c4cc2f17165 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/14892 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply(a)raptorengineeringinc.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> See https://review.coreboot.org/14892 for details. -gerrit

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New patch to review for coreboot: Makefile: Add ifwitool to list of tools to be built
by Furquan Shaikh 31 May '16

31 May '16

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15013 -gerrit commit 03cd660c5a924ac9a220f87a9e31067429ee679c Author: Furquan Shaikh <furquan(a)google.com> Date: Mon May 30 23:03:58 2016 -0700 Makefile: Add ifwitool to list of tools to be built Add ifwitool to list of tools to be built so that it can be used by the build system. Change-Id: Ifcfbfd87ad9b7ba3ea11cfbcf40894f3e0dae694 Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- Makefile.inc | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/Makefile.inc b/Makefile.inc index 574f2fe..19377c9 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -53,7 +53,7 @@ export objgenerated := $(obj)/generated ####################################################################### # root rule to resolve if in build mode (ie. configuration exists) real-target: $(obj)/config.h coreboot files_added -coreboot: build-dirs $(obj)/coreboot.rom $(obj)/cbfstool $(obj)/rmodtool +coreboot: build-dirs $(obj)/coreboot.rom $(obj)/cbfstool $(obj)/rmodtool $(obj)/ifwitool # This target can be used in site local to run scripts or additional # targets after the build completes by creating a Makefile.inc in the @@ -385,6 +385,7 @@ build-dirs: CBFSTOOL:=$(objutil)/cbfstool/cbfstool FMAPTOOL:=$(objutil)/cbfstool/fmaptool RMODTOOL:=$(objutil)/cbfstool/rmodtool +IFWITOOL:=$(objutil)/cbfstool/ifwitool $(obj)/cbfstool: $(CBFSTOOL) cp $< $@ @@ -395,6 +396,9 @@ $(obj)/fmaptool: $(FMAPTOOL) $(obj)/rmodtool: $(RMODTOOL) cp $< $@ +$(obj)/ifwitool: $(IFWITOOL) + cp $< $@ + _WINCHECK=$(shell uname -o 2> /dev/null) STACK= ifeq ($(_WINCHECK),Msys) @@ -512,7 +516,7 @@ gitconfig: include util/crossgcc/Makefile.inc .PHONY: tools -tools: $(objutil)/kconfig/conf $(CBFSTOOL) $(FMAPTOOL) $(RMODTOOL) $(objutil)/nvramtool/nvramtool $(ROMCC_BIN) $(objutil)/sconfig/sconfig $(IFDTOOL) $(IFDFAKE) $(CBOOTIMAGE) $(AMDFWTOOL) $(FUTILITY) +tools: $(objutil)/kconfig/conf $(CBFSTOOL) $(FMAPTOOL) $(RMODTOOL) $(IFWITOOL) $(objutil)/nvramtool/nvramtool $(ROMCC_BIN) $(objutil)/sconfig/sconfig $(IFDTOOL) $(IFDFAKE) $(CBOOTIMAGE) $(AMDFWTOOL) $(FUTILITY) ########################################################################### # Common recipes for all stages

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coreboot-gerrit May 2016