coreboot-gerrit May 2016

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New patch to review for coreboot: Add Board Checklist Support
by Leroy P Leahy 31 May '16

31 May '16

Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15011 -gerrit commit 514687b674103fd60f96f2aa58c4ca7877ac4e77 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Thu May 26 17:12:17 2016 -0700 Add Board Checklist Support Build the <board>_checklist.html file which contains a checklist table for each stage of coreboot. This processing builds a set of implemented (done) routines which are marked green in the table. The remaining required routines (work-to-do) are marked red in the table and the optional routines are marked yellow in the table. The table heading for each stage contains a completion percentage in terms of count of routines (done .vs. required). Add some Kconfig values: * CREATE_BOARD_CHECKLIST - When selected creates the checklist file * MAKE_CHECKLIST_PUBLIC - Copies the checklist file into the Documenation directory * CHECKLIST_DATA_FILE_LOCATION - Location of the checklist data files: * <stage>_complete.dat - Lists all of the weak routines * <stage>_optional.dat - Lists weak routines which may be optionally implemented * <stage>_exclude.dat - Lists the weak functions that should be ignored during the checklist processing TEST=Build with Galileo Gen2. Change-Id: Ie056f8bb6d45ff7f3bc6390b5630b5063f54c527 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- Makefile.inc | 131 +++++++++++++++++++++ src/Kconfig | 8 ++ src/drivers/intel/fsp1_1/Kconfig | 4 + .../fsp/fsp1_1/checklist/ramstage_complete.dat | 17 +++ .../fsp/fsp1_1/checklist/ramstage_exclude.dat | 1 + .../fsp/fsp1_1/checklist/ramstage_optional.dat | 8 ++ .../fsp/fsp1_1/checklist/romstage_complete.dat | 13 ++ .../fsp/fsp1_1/checklist/romstage_exclude.dat | 1 + .../fsp/fsp1_1/checklist/romstage_optional.dat | 10 ++ .../fsp/fsp1_1/checklist/verstage_complete.dat | 10 ++ .../fsp/fsp1_1/checklist/verstage_exclude.dat | 1 + .../fsp/fsp1_1/checklist/verstage_optional.dat | 11 ++ 12 files changed, 215 insertions(+) diff --git a/Makefile.inc b/Makefile.inc index 574f2fe..e2163b2 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -559,6 +559,137 @@ $(objcbfs)/%.elf: $(objcbfs)/%.debug mv $@.tmp $@ ########################################################################### +# Build the board implementation checklist +########################################################################### + +%.weak: %.elf + nm $< | fgrep " W " | sed -r 's/^.{11}//' > $@.tmp + comm -23 $@.tmp $(CONFIG_CHECKLIST_DATA_FILE_LOCATION)/$(basename $(*F))_exclude.dat > $@ + rm $@.tmp + +%.total: %.weak + cp $(CONFIG_CHECKLIST_DATA_FILE_LOCATION)/$(basename $(*F))_complete.dat $@.tmp + # If no separate verstage, combine verstage and romstage routines into a single list + if [ ! -e $(*D)/verstage.elf ]; \ + then \ + echo $(*F); \ + if [ "$(*F)" = "romstage" ]; \ + then \ + sort --merge $(CONFIG_CHECKLIST_DATA_FILE_LOCATION)/verstage_complete.dat $@.tmp > $@.tmp2; \ + sort -u $@.tmp2 > $@.tmp; \ + rm $@.tmp2; \ + fi; \ + fi + comm -23 $@.tmp $(CONFIG_CHECKLIST_DATA_FILE_LOCATION)/$(basename $(*F))_exclude.dat > $@ + rm $@.tmp + +%.done: %.total %.weak + comm -23 $^ | sed "s/^[ \t]*//" > $@.tmp + comm -2 $@.tmp $(CONFIG_CHECKLIST_DATA_FILE_LOCATION)/$(basename $(*F))_optional.dat | sed "s/^[ \t]*//" > $@ + rm $@.tmp + +%.optional: %.done + comm -23 $(CONFIG_CHECKLIST_DATA_FILE_LOCATION)/$(basename $(*F))_optional.dat $< | sed "s/^[ \t]*//" > $@ + +%.weak2: %.weak %.optional + comm -23 $< $(CONFIG_CHECKLIST_DATA_FILE_LOCATION)/$(basename $(*F))_optional.dat | sed "s/^[ \t]*//" > $@ + +# Count the lines in the done file +done_lines = $$(wc -l $(*D)/$(basename $(*F)).done | sed 's/ .*//') + +# Count the lines in the optional file +optional_lines = $$(wc -l $(*D)/$(basename $(*F)).optional | sed 's/ .*//') + +# Count the lines in the total file +total_lines = $$(wc -l $(*D)/$(basename $(*F)).total | sed 's/ .*//') + +# Compute the percentage done by routine count +percent_complete = $$(($(done_lines) * 100 / ($(total_lines) - $(optional_lines)))) + +# Build the implementation table for each stage +%.html: %.optional %.done %.total %.weak2 + # + # Done table rows are in green + # + sed -e 's/^/<tr bgcolor=#c0ffc0><td>Required<\/td><td>/' $(*D)/$(basename $(*F)).done > $@.tmp + # + # Optional table rows are in yellow + # + sed -e 's/^/<tr bgcolor=#ffffc0><td>Optional<\/td><td>/' $(*D)/$(basename $(*F)).optional >> $@.tmp + # + # Weak table rows are in red + # + if [ -s $(*D)/$(basename $(*F)).weak2 ]; \ + then \ + sed -e 's/^/<tr bgcolor=#ffc0c0><td>Required<\/td><td>/' $(*D)/$(basename $(*F)).weak2 >> $@.tmp; \ + fi + # + # Add the table row termination + # + sed -e 's/$$/<\/td><\/tr>/' -i $@.tmp + # + # Sort the table into alphabetical order + # + sort -t ">" -k4 $@.tmp > $@.tmp2 + # + # Build the table + # + echo "<table border=1>" > $@ + echo "<tr><th colspan=2>$(basename $(*F)): $(percent_complete)% Done</th></tr>" >> $@ + echo "<tr><th>Type</th><th>Routine</td></tr>" >> $@ + cat $@.tmp2 >> $@ + echo "</table>" >> $@ + echo "<br>" >> $@ + rm $@.tmp $@.tmp2 + +html_table_files = $(objcbfs)/romstage.html $(objcbfs)/ramstage.html +list_of_html_files = $(subst _NEWLINE_,${\n},${html_table_files}) +current_date = $$(date +"%Y/%m/%d") + +# Build the web page from the implementation tables +$(obj)/$(CONFIG_MAINBOARD_PART_NUMBER)_checklist.html: $(html_table_files) + # + # Add the header to the web page + # + echo "<html>" > $@ + echo "<head>" >> $@ + echo "<title>$(CONFIG_MAINBOARD_PART_NUMBER) Implementation Status</title>" >> $@ + echo "</title>" >> $@ + echo "<body>" >> $@ + echo "<h1>$(CONFIG_MAINBOARD_PART_NUMBER) Implementation Status: $(current_date)</h1>" >> $@ + # + # Add the tables to the web page + # + for table in $(list_of_html_files); do \ + cat $$table >> $@; \ + done + # + # Add the trailer to the web page + # + echo "</body>" >> $@ + echo "</html>" >> $@ + +Documentation/$(CONFIG_MAINBOARD_VENDOR)/Board/$(CONFIG_MAINBOARD_PART_NUMBER)_checklist.html: $(obj)/$(CONFIG_MAINBOARD_PART_NUMBER)_checklist.html + if [ ! -d Documentation/$(CONFIG_MAINBOARD_VENDOR) ]; \ + then \ + mkdir Documentation/$(CONFIG_MAINBOARD_VENDOR); \ + fi + if [ ! -d Documentation/$(CONFIG_MAINBOARD_VENDOR)/Board ]; \ + then \ + mkdir Documentation/$(CONFIG_MAINBOARD_VENDOR)/Board; \ + fi + cp $< $@ + +# Only build the checklist for boards under development +ifeq ($(CONFIG_CREATE_BOARD_CHECKLIST),y) +ifeq ($(CONFIG_MAKE_CHECKLIST_PUBLIC),y) +INTERMEDIATE+=Documentation/$(CONFIG_MAINBOARD_VENDOR)/Board/$(CONFIG_MAINBOARD_PART_NUMBER)_checklist.html +else +INTERMEDIATE+=$(obj)/$(CONFIG_MAINBOARD_PART_NUMBER)_checklist.html +endif +endif + +########################################################################### # Build the final rom image ########################################################################### diff --git a/src/Kconfig b/src/Kconfig index f93c2cc..2b9a136 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -1175,3 +1175,11 @@ config DEBUG_BOOT_STATE help Control debugging of the boot state machine. When selected displays the state boundaries in ramstage. + +config CREATE_BOARD_CHECKLIST + bool + default n + +config MAKE_CHECKLIST_PUBLIC + bool + default n diff --git a/src/drivers/intel/fsp1_1/Kconfig b/src/drivers/intel/fsp1_1/Kconfig index 9b2c463..86f6c7b 100644 --- a/src/drivers/intel/fsp1_1/Kconfig +++ b/src/drivers/intel/fsp1_1/Kconfig @@ -115,4 +115,8 @@ config VBT_FILE depends on GOP_SUPPORT default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/vbt.bin" +config CHECKLIST_DATA_FILE_LOCATION + string + default "src/vendorcode/intel/fsp/fsp1_1/checklist" + endif #PLATFORM_USES_FSP1_1 diff --git a/src/vendorcode/intel/fsp/fsp1_1/checklist/ramstage_complete.dat b/src/vendorcode/intel/fsp/fsp1_1/checklist/ramstage_complete.dat new file mode 100644 index 0000000..55849ac --- /dev/null +++ b/src/vendorcode/intel/fsp/fsp1_1/checklist/ramstage_complete.dat @@ -0,0 +1,17 @@ +arch_segment_loaded +boot_device_init +fw_cfg_acpi_tables +lb_board +lb_framebuffer +mainboard_post +mainboard_silicon_init_params +mirror_payload +platform_prog_run +platform_segment_loaded +smbios_mainboard_bios_version +smbios_mainboard_manufacturer +smbios_mainboard_product_name +smbios_mainboard_serial_number +smbios_mainboard_set_uuid +smbios_mainboard_version +soc_after_silicon_init diff --git a/src/vendorcode/intel/fsp/fsp1_1/checklist/ramstage_exclude.dat b/src/vendorcode/intel/fsp/fsp1_1/checklist/ramstage_exclude.dat new file mode 100644 index 0000000..8b13789 --- /dev/null +++ b/src/vendorcode/intel/fsp/fsp1_1/checklist/ramstage_exclude.dat @@ -0,0 +1 @@ + diff --git a/src/vendorcode/intel/fsp/fsp1_1/checklist/ramstage_optional.dat b/src/vendorcode/intel/fsp/fsp1_1/checklist/ramstage_optional.dat new file mode 100644 index 0000000..29077c9 --- /dev/null +++ b/src/vendorcode/intel/fsp/fsp1_1/checklist/ramstage_optional.dat @@ -0,0 +1,8 @@ +arch_segment_loaded +boot_device_init +lb_board +lb_framebuffer +mainboard_post +mirror_payload +platform_prog_run +platform_segment_loaded diff --git a/src/vendorcode/intel/fsp/fsp1_1/checklist/romstage_complete.dat b/src/vendorcode/intel/fsp/fsp1_1/checklist/romstage_complete.dat new file mode 100644 index 0000000..4f2932e --- /dev/null +++ b/src/vendorcode/intel/fsp/fsp1_1/checklist/romstage_complete.dat @@ -0,0 +1,13 @@ +arch_segment_loaded +boot_device_init +mainboard_add_dimm_info +mainboard_check_ec_image +mainboard_memory_init_params +mainboard_post +mainboard_save_dimm_info +platform_prog_run +platform_segment_loaded +report_memory_config +soc_pre_ram_init +stage_cache_add +stage_cache_load_stage diff --git a/src/vendorcode/intel/fsp/fsp1_1/checklist/romstage_exclude.dat b/src/vendorcode/intel/fsp/fsp1_1/checklist/romstage_exclude.dat new file mode 100644 index 0000000..8b13789 --- /dev/null +++ b/src/vendorcode/intel/fsp/fsp1_1/checklist/romstage_exclude.dat @@ -0,0 +1 @@ + diff --git a/src/vendorcode/intel/fsp/fsp1_1/checklist/romstage_optional.dat b/src/vendorcode/intel/fsp/fsp1_1/checklist/romstage_optional.dat new file mode 100644 index 0000000..7660409 --- /dev/null +++ b/src/vendorcode/intel/fsp/fsp1_1/checklist/romstage_optional.dat @@ -0,0 +1,10 @@ +arch_segment_loaded +boot_device_init +car_mainboard_post_console_init +car_mainboard_pre_console_init +mainboard_check_ec_image +mainboard_post +platform_prog_run +platform_segment_loaded +stage_cache_add +stage_cache_load_stage diff --git a/src/vendorcode/intel/fsp/fsp1_1/checklist/verstage_complete.dat b/src/vendorcode/intel/fsp/fsp1_1/checklist/verstage_complete.dat new file mode 100644 index 0000000..7660409 --- /dev/null +++ b/src/vendorcode/intel/fsp/fsp1_1/checklist/verstage_complete.dat @@ -0,0 +1,10 @@ +arch_segment_loaded +boot_device_init +car_mainboard_post_console_init +car_mainboard_pre_console_init +mainboard_check_ec_image +mainboard_post +platform_prog_run +platform_segment_loaded +stage_cache_add +stage_cache_load_stage diff --git a/src/vendorcode/intel/fsp/fsp1_1/checklist/verstage_exclude.dat b/src/vendorcode/intel/fsp/fsp1_1/checklist/verstage_exclude.dat new file mode 100644 index 0000000..8b13789 --- /dev/null +++ b/src/vendorcode/intel/fsp/fsp1_1/checklist/verstage_exclude.dat @@ -0,0 +1 @@ + diff --git a/src/vendorcode/intel/fsp/fsp1_1/checklist/verstage_optional.dat b/src/vendorcode/intel/fsp/fsp1_1/checklist/verstage_optional.dat new file mode 100644 index 0000000..b1ddfb6 --- /dev/null +++ b/src/vendorcode/intel/fsp/fsp1_1/checklist/verstage_optional.dat @@ -0,0 +1,11 @@ +arch_segment_loaded +boot_device_init +car_mainboard_post_console_init +car_mainboard_pre_console_init +mainboard_check_ec_image +mainboard_post +platform_prog_run +platform_segment_loaded +stage_cache_add +stage_cache_load_stage +

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New patch to review for coreboot: quark: Enable HSUART0 as console
by Leroy P Leahy 31 May '16

31 May '16

Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15010 -gerrit commit ec2d6f2f4812427b3e3e70a817081fc4ae3a64af Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Mon May 30 15:01:06 2016 -0700 quark: Enable HSUART0 as console The use of HSUART0 on galileo requires early initialization of the I2C GPIO expanders to direct the RXD and TXD signals to DIGITAL 0 and 1 on the expansion connector. TEST=None Change-Id: I11195d79e954c1f6bc91eafe257d7ddc1310b2e7 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/mainboard/intel/galileo/gen1.h | 50 ++++++++++++++++++++++++++++ src/mainboard/intel/galileo/gen2.h | 22 ++++++++++++ src/mainboard/intel/galileo/gpio.c | 38 +++++++++++++-------- src/soc/intel/quark/Kconfig | 27 ++++++++++----- src/soc/intel/quark/include/soc/pci_devs.h | 3 ++ src/soc/intel/quark/include/soc/reg_access.h | 1 - src/soc/intel/quark/romstage/romstage.c | 12 ++++--- 7 files changed, 126 insertions(+), 27 deletions(-) diff --git a/src/mainboard/intel/galileo/gen1.h b/src/mainboard/intel/galileo/gen1.h index e1e8f59..23b2309 100644 --- a/src/mainboard/intel/galileo/gen1.h +++ b/src/mainboard/intel/galileo/gen1.h @@ -59,6 +59,56 @@ static const struct reg_script gen1_gpio_init[] = { REG_SCRIPT_END }; +static const struct reg_script gen1_hsuart0_0x20[] = { + /* Route UART0_TXD to LVL_TXD -> IO1 -> DIGITAL 1 + * Set IO1_MUX (EXP.PORT3_5) output, low + * Set LVL_OE (GPIO_SUS2) output, high + */ + + REG_I2C_WRITE(GEN1_I2C_GPIO_EXP_0x20, GEN1_GPIO_EXP_PORT_SELECT, 3), + REG_I2C_AND(GEN1_I2C_GPIO_EXP_0x20, GEN1_GPIO_EXP_PORT_DIR, ~BIT5), + REG_I2C_AND(GEN1_I2C_GPIO_EXP_0x20, GEN1_GPIO_EXP_OUTPUT3, ~BIT5), + + /* Route DIGITAL 0 -> IO0 -> LVL_RXD -> UART0_RXD + * Set IO0_MUX (EXP.PORT3_4) output, low + * Set LVL_OE (GPIO_SUS2) output, high + */ + REG_I2C_WRITE(GEN1_I2C_GPIO_EXP_0x20, GEN1_GPIO_EXP_PORT_SELECT, 3), + REG_I2C_AND(GEN1_I2C_GPIO_EXP_0x20, GEN1_GPIO_EXP_PORT_DIR, ~BIT4), + REG_I2C_AND(GEN1_I2C_GPIO_EXP_0x20, GEN1_GPIO_EXP_OUTPUT3, ~BIT4), + + REG_LEG_GPIO_OR(R_QNC_GPIO_RGEN_RESUME_WELL, BIT2), + REG_LEG_GPIO_AND(R_QNC_GPIO_RGIO_RESUME_WELL, ~BIT2), + REG_LEG_GPIO_OR(R_QNC_GPIO_RGLVL_RESUME_WELL, BIT2), + + REG_SCRIPT_END +}; + +static const struct reg_script gen1_hsuart0_0x21[] = { + /* Route UART0_TXD to LVL_TXD -> IO1 -> DIGITAL 1 + * Set IO1_MUX (EXP.PORT3_5) output, low + * Set LVL_OE (GPIO_SUS2) output, high + */ + + REG_I2C_WRITE(GEN1_I2C_GPIO_EXP_0x21, GEN1_GPIO_EXP_PORT_SELECT, 3), + REG_I2C_AND(GEN1_I2C_GPIO_EXP_0x21, GEN1_GPIO_EXP_PORT_DIR, ~BIT5), + REG_I2C_AND(GEN1_I2C_GPIO_EXP_0x21, GEN1_GPIO_EXP_OUTPUT3, ~BIT5), + + /* Route DIGITAL 0 -> IO0 -> LVL_RXD -> UART0_RXD + * Set IO0_MUX (EXP.PORT3_4) output, low + * Set LVL_OE (GPIO_SUS2) output, high + */ + REG_I2C_WRITE(GEN1_I2C_GPIO_EXP_0x21, GEN1_GPIO_EXP_PORT_SELECT, 3), + REG_I2C_AND(GEN1_I2C_GPIO_EXP_0x21, GEN1_GPIO_EXP_PORT_DIR, ~BIT4), + REG_I2C_AND(GEN1_I2C_GPIO_EXP_0x21, GEN1_GPIO_EXP_OUTPUT3, ~BIT4), + + REG_LEG_GPIO_OR(R_QNC_GPIO_RGEN_RESUME_WELL, BIT2), + REG_LEG_GPIO_AND(R_QNC_GPIO_RGIO_RESUME_WELL, ~BIT2), + REG_LEG_GPIO_OR(R_QNC_GPIO_RGLVL_RESUME_WELL, BIT2), + + REG_SCRIPT_END +}; + static const struct reg_script gen1_i2c_0x20_init[] = { /* Route I2C pins to Arduino header: * Clear I2C_MUX (GPORT1_BIT5) to route I2C to Arduino Shield connector diff --git a/src/mainboard/intel/galileo/gen2.h b/src/mainboard/intel/galileo/gen2.h index 8eee744..10c8321 100644 --- a/src/mainboard/intel/galileo/gen2.h +++ b/src/mainboard/intel/galileo/gen2.h @@ -52,6 +52,28 @@ static const struct reg_script gen2_gpio_init[] = { REG_SCRIPT_END }; +static const struct reg_script gen2_hsuart0[] = { + /* Route UART0_TXD to MUX7_Y -> BUF_IO1 -> IO1 -> DIGITAL 1 + * Set MUX7_SEL (EXP1.P1_5) high + * Configure MUX7_SEL (EXP1.P1_5) as an output + * Set LVL_B_OE6_N (EXP0.P1_4) low + * Configure LVL_B_OE6_N (EXP0.P1_4) as an output + */ + REG_I2C_OR(GEN2_I2C_GPIO_EXP1, GEN2_GPIO_EXP_OUTPUT1, BIT5), + REG_I2C_AND(GEN2_I2C_GPIO_EXP1, GEN2_GPIO_EXP_CONFIG1, ~BIT5), + REG_I2C_AND(GEN2_I2C_GPIO_EXP0, GEN2_GPIO_EXP_OUTPUT1, ~BIT4), + REG_I2C_AND(GEN2_I2C_GPIO_EXP0, GEN2_GPIO_EXP_CONFIG1, ~BIT4), + + /* Route DIGITAL 0 -> IO0 -> UART0_RXD + * Set LVL_C_OE0_N (EXP1.P0_0) high + * Configure LVL_C_OE0_N (EXP1.P0_0) as an output + */ + REG_I2C_OR(GEN2_I2C_GPIO_EXP1, GEN2_GPIO_EXP_OUTPUT0, BIT0), + REG_I2C_AND(GEN2_I2C_GPIO_EXP1, GEN2_GPIO_EXP_CONFIG0, ~BIT0), + + REG_SCRIPT_END +}; + static const struct reg_script gen2_i2c_init[] = { /* Route I2C to Arduino Shield connector: * Set AMUX1_IN (EXP2.P1_4) low diff --git a/src/mainboard/intel/galileo/gpio.c b/src/mainboard/intel/galileo/gpio.c index 0c26ec8..20b1bea 100644 --- a/src/mainboard/intel/galileo/gpio.c +++ b/src/mainboard/intel/galileo/gpio.c @@ -15,11 +15,35 @@ #include <arch/io.h> #include <console/console.h> +#include <fsp/romstage.h> #include <soc/ramstage.h> #include "reg_access.h" #include "gen1.h" #include "gen2.h" +void car_mainboard_pre_console_init(void) +{ + const struct reg_script *script; + + /* Initialize the GPIO controllers */ + if (IS_ENABLED(CONFIG_GALILEO_GEN2)) + script = gen2_gpio_init; + else + script = gen1_gpio_init; + reg_script_run(script); + + /* Initialize the RXD and TXD paths for UART0 */ + if (IS_ENABLED(CONFIG_ENABLE_BUILTIN_HSUART0)) { + if (IS_ENABLED(CONFIG_GALILEO_GEN2)) + script = gen2_hsuart0; + else + script = (reg_legacy_gpio_read (R_QNC_GPIO_RGLVL_RESUME_WELL) + & GALILEO_DETERMINE_IOEXP_SLA_RESUMEWELL_GPIO) + ? gen1_hsuart0_0x21 : gen1_hsuart0_0x20; + reg_script_run(script); + } +} + void mainboard_gpio_i2c_init(device_t dev) { const struct reg_script *script; @@ -33,24 +57,12 @@ void mainboard_gpio_i2c_init(device_t dev) /* Determine which I2C address is in use */ script = (reg_legacy_gpio_read (R_QNC_GPIO_RGLVL_RESUME_WELL) & GALILEO_DETERMINE_IOEXP_SLA_RESUMEWELL_GPIO) - ? gen1_i2c_0x20_init : gen1_i2c_0x21_init; + ? gen1_i2c_0x21_init : gen1_i2c_0x20_init; /* Initialize the I2C chips */ reg_script_run(script); } -void mainboard_gpio_init(void) -{ - const struct reg_script *script; - - /* Initialize the GPIO controllers */ - if (IS_ENABLED(CONFIG_GALILEO_GEN2)) - script = gen2_gpio_init; - else - script = gen1_gpio_init; - reg_script_run(script); -} - void mainboard_gpio_pcie_reset(uint32_t pin_value) { uint32_t pin_number; diff --git a/src/soc/intel/quark/Kconfig b/src/soc/intel/quark/Kconfig index 6a2349f..2c7ec64 100644 --- a/src/soc/intel/quark/Kconfig +++ b/src/soc/intel/quark/Kconfig @@ -40,9 +40,19 @@ config CPU_SPECIFIC_OPTIONS # The following options configure the debug serial port ##### +config ENABLE_BUILTIN_HSUART0 + bool "Enable built-in HSUART0" + default n + select NO_UART_ON_SUPERIO + select DRIVERS_UART_8250MEM_32 + help + The Quark SoC has two HSUART. Choose this option to configure the pads + and enable HSUART0, which can be used for the debug console. + config ENABLE_BUILTIN_HSUART1 bool "Enable built-in HSUART1" - default y + default n + depends on ! ENABLE_BUILTIN_HSUART0 select NO_UART_ON_SUPERIO select DRIVERS_UART_8250MEM_32 help @@ -50,23 +60,24 @@ config ENABLE_BUILTIN_HSUART1 and enable HSUART1, which can be used for the debug console. config TTYS0_BASE - hex "HSUART1 Base Address" - depends on ENABLE_BUILTIN_HSUART1 + hex "HSUART Base Address" default 0xA0019000 + depends on ENABLE_BUILTIN_HSUART0 || ENABLE_BUILTIN_HSUART1 help - Memory mapped MMIO of HSUART1. + Memory mapped MMIO of HSUART. config TTYS0_LCS int - depends on ENABLE_BUILTIN_HSUART1 default 3 + depends on ENABLE_BUILTIN_HSUART0 || ENABLE_BUILTIN_HSUART1 -# Console: PCI UART bus 0 << 20, device 20 << 15, function 5 << 12 +# Console: PCI UART bus 0 << 20, device 20 << 15, function x << 12 # Valid bit, PCI UART in use: 1 << 31 config UART_PCI_ADDR hex - depends on ENABLE_BUILTIN_HSUART1 - default 0x800a5000 + default 0x800a1000 if ENABLE_BUILTIN_HSUART0 + default 0x800a5000 if ENABLE_BUILTIN_HSUART1 + depends on ENABLE_BUILTIN_HSUART0 || ENABLE_BUILTIN_HSUART1 ##### # Debug support diff --git a/src/soc/intel/quark/include/soc/pci_devs.h b/src/soc/intel/quark/include/soc/pci_devs.h index 278a012..0c99eb9 100644 --- a/src/soc/intel/quark/include/soc/pci_devs.h +++ b/src/soc/intel/quark/include/soc/pci_devs.h @@ -33,11 +33,14 @@ /* IO Fabric 1 */ #define SIO1_DEV 0x14 +#define HSUART0_DEV SIO1_DEV #define HSUART1_DEV SIO1_DEV +#define HSUART0_FUNC 1 #define USB_DEV_PORT_FUNC 2 #define EHCI_FUNC 3 #define OHCI_FUNC 4 #define HSUART1_FUNC 5 +#define HSUART0_BDF PCI_DEV(PCI_BUS_NUMBER_QNC, HSUART0_DEV, HSUART0_FUNC) #define HSUART1_BDF PCI_DEV(PCI_BUS_NUMBER_QNC, HSUART1_DEV, HSUART1_FUNC) /* IO Fabric 2 */ diff --git a/src/soc/intel/quark/include/soc/reg_access.h b/src/soc/intel/quark/include/soc/reg_access.h index e7a8963..b934032 100644 --- a/src/soc/intel/quark/include/soc/reg_access.h +++ b/src/soc/intel/quark/include/soc/reg_access.h @@ -203,7 +203,6 @@ enum { REG_USB_RXW(reg_, 0xffffffff, value_) void *get_i2c_address(void); -void mainboard_gpio_init(void); void mainboard_gpio_pcie_reset(uint32_t pin_value); void mcr_write(uint8_t opcode, uint8_t port, uint32_t reg_address); uint32_t mdr_read(void); diff --git a/src/soc/intel/quark/romstage/romstage.c b/src/soc/intel/quark/romstage/romstage.c index 5be022a..e27aa68 100644 --- a/src/soc/intel/quark/romstage/romstage.c +++ b/src/soc/intel/quark/romstage/romstage.c @@ -67,6 +67,13 @@ static const struct reg_script hsuart_init[] = { void car_soc_pre_console_init(void) { + /* Initialize the controllers */ + reg_script_run_on_dev(I2CGPIO_BDF, i2c_gpio_controller_init); + reg_script_run_on_dev(LPC_BDF, legacy_gpio_init); + + /* Enable the HSUART */ + if (IS_ENABLED(CONFIG_ENABLE_BUILTIN_HSUART0)) + reg_script_run_on_dev(HSUART0_BDF, hsuart_init); if (IS_ENABLED(CONFIG_ENABLE_BUILTIN_HSUART1)) reg_script_run_on_dev(HSUART1_BDF, hsuart_init); } @@ -74,11 +81,6 @@ void car_soc_pre_console_init(void) void car_soc_post_console_init(void) { report_platform_info(); - - /* Initialize the controllers */ - reg_script_run_on_dev(I2CGPIO_BDF, i2c_gpio_controller_init); - reg_script_run_on_dev(LPC_BDF, legacy_gpio_init); - mainboard_gpio_init(); }; static struct chipset_power_state power_state CAR_GLOBAL;

1 0

New patch to review for coreboot: soc/intel/quark: Move UART init into romstage.c
by Leroy P Leahy 31 May '16

31 May '16

Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15009 -gerrit commit 7edd989118ec7c5853f5bf2687037ef0c898914e Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Mon May 30 14:35:15 2016 -0700 soc/intel/quark: Move UART init into romstage.c Move UART initialization into romstage.c and eliminate uart.c. TEST=Build and run on Galileo Gen2 Change-Id: I5f2c9b4c566008000c2201c422a0bba63da64487 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/soc/intel/quark/include/soc/pci_devs.h | 1 + src/soc/intel/quark/romstage/Makefile.inc | 1 - src/soc/intel/quark/romstage/romstage.c | 10 +++++-- src/soc/intel/quark/romstage/uart.c | 42 ------------------------------ 4 files changed, 9 insertions(+), 45 deletions(-) diff --git a/src/soc/intel/quark/include/soc/pci_devs.h b/src/soc/intel/quark/include/soc/pci_devs.h index ff9d65f..278a012 100644 --- a/src/soc/intel/quark/include/soc/pci_devs.h +++ b/src/soc/intel/quark/include/soc/pci_devs.h @@ -38,6 +38,7 @@ #define EHCI_FUNC 3 #define OHCI_FUNC 4 #define HSUART1_FUNC 5 +#define HSUART1_BDF PCI_DEV(PCI_BUS_NUMBER_QNC, HSUART1_DEV, HSUART1_FUNC) /* IO Fabric 2 */ #define SIO2_DEV 0x15 diff --git a/src/soc/intel/quark/romstage/Makefile.inc b/src/soc/intel/quark/romstage/Makefile.inc index 2f29b06..6c92ac4 100644 --- a/src/soc/intel/quark/romstage/Makefile.inc +++ b/src/soc/intel/quark/romstage/Makefile.inc @@ -20,4 +20,3 @@ romstage-y += mtrr.c romstage-y += pcie.c romstage-y += report_platform.c romstage-y += romstage.c -romstage-$(CONFIG_ENABLE_BUILTIN_HSUART1) += uart.c diff --git a/src/soc/intel/quark/romstage/romstage.c b/src/soc/intel/quark/romstage/romstage.c index c86c2ea..5be022a 100644 --- a/src/soc/intel/quark/romstage/romstage.c +++ b/src/soc/intel/quark/romstage/romstage.c @@ -58,11 +58,17 @@ static const struct reg_script i2c_gpio_controller_init[] = { REG_SCRIPT_END }; +static const struct reg_script hsuart_init[] = { + /* Enable the HSUART */ + REG_PCI_WRITE32(PCI_BASE_ADDRESS_0, UART_BASE_ADDRESS), + REG_PCI_OR8(PCI_COMMAND, PCI_COMMAND_MEMORY), + REG_SCRIPT_END +}; + void car_soc_pre_console_init(void) { if (IS_ENABLED(CONFIG_ENABLE_BUILTIN_HSUART1)) - set_base_address_and_enable_uart(0, HSUART1_DEV, HSUART1_FUNC, - UART_BASE_ADDRESS); + reg_script_run_on_dev(HSUART1_BDF, hsuart_init); } void car_soc_post_console_init(void) diff --git a/src/soc/intel/quark/romstage/uart.c b/src/soc/intel/quark/romstage/uart.c deleted file mode 100644 index 9e8f6c5..0000000 --- a/src/soc/intel/quark/romstage/uart.c +++ /dev/null @@ -1,42 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2003 Eric Biederman - * Copyright (C) 2006-2010 coresystems GmbH - * Copyright (C) 2015-2016 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -// Use simple device model for this file even in ramstage -#define __SIMPLE_DEVICE__ - -#include <device/pci.h> -#include <device/pci_def.h> -#include <rules.h> -#include <soc/romstage.h> - -int set_base_address_and_enable_uart(u8 bus, u8 dev, u8 func, u32 mmio_base) -{ - uint16_t reg16; - - /* HSUART controller #1 (B0:D20:F5). */ - pci_devfn_t uart_bdf = PCI_DEV(bus, dev, func); - - /* Decode BAR0(offset 0x10). */ - pci_write_config32(uart_bdf, PCI_BASE_ADDRESS_0, mmio_base); - - /* Enable MEMBASE at CMD(offset 0x04). */ - reg16 = pci_read_config16(uart_bdf, PCI_COMMAND); - reg16 |= PCI_COMMAND_MEMORY; - pci_write_config16(uart_bdf, PCI_COMMAND, reg16); - - return 0; -}

1 0

New patch to review for coreboot: mainboard/intel/quark: Enable reg_access during romstage
by Leroy P Leahy 31 May '16

31 May '16

Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15008 -gerrit commit 9b9b660be4ebbad12ccdbb6b7cea013ef962b3de Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Mon May 30 11:23:49 2016 -0700 mainboard/intel/quark: Enable reg_access during romstage Turn on reg_access during romstage. TEST=Build and run on Galileo Gen2 Change-Id: Iff1616836d6031f43d7741693febefa0bf26b948 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/mainboard/intel/galileo/Makefile.inc | 1 + src/mainboard/intel/galileo/reg_access.c | 3 --- 2 files changed, 1 insertion(+), 3 deletions(-) diff --git a/src/mainboard/intel/galileo/Makefile.inc b/src/mainboard/intel/galileo/Makefile.inc index 72c74e1..83fb0db 100644 --- a/src/mainboard/intel/galileo/Makefile.inc +++ b/src/mainboard/intel/galileo/Makefile.inc @@ -18,6 +18,7 @@ CPPFLAGS_common += -I$(src)/vendorcode/intel/fsp/fsp1_1/quark endif romstage-y += gpio.c +romstage-y += reg_access.c ramstage-y += gpio.c ramstage-y += reg_access.c diff --git a/src/mainboard/intel/galileo/reg_access.c b/src/mainboard/intel/galileo/reg_access.c index f19f526..36345ff 100644 --- a/src/mainboard/intel/galileo/reg_access.c +++ b/src/mainboard/intel/galileo/reg_access.c @@ -22,7 +22,6 @@ #include <soc/reg_access.h> #include "reg_access.h" -#if ENV_RAMSTAGE static uint64_t reg_read(struct reg_script_context *ctx) { int ret_code; @@ -89,5 +88,3 @@ const struct reg_script_bus_entry mainboard_reg_script_bus_table = { }; REG_SCRIPT_BUS_ENTRY(mainboard_reg_script_bus_table); - -#endif /* ENV_RAMSTAGE */

1 0

New patch to review for coreboot: soc/intel/quark: Split I2C out from driver
by Leroy P Leahy 31 May '16

31 May '16

Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15007 -gerrit commit 8e3a77c717d8f82635639a90d96131cab4543a18 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Mon May 30 14:06:25 2016 -0700 soc/intel/quark: Split I2C out from driver Split out the I2C code to allow I2C transactions during early romstage. TEST=Build and run on Galileo Gen2 Change-Id: I87ceb0a8cf660e4337738b3bcde9d4fdeae0159d Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/soc/intel/quark/Makefile.inc | 2 + src/soc/intel/quark/gpio_i2c.c | 152 --------------------------------- src/soc/intel/quark/i2c.c | 176 +++++++++++++++++++++++++++++++++++++++ 3 files changed, 178 insertions(+), 152 deletions(-) diff --git a/src/soc/intel/quark/Makefile.inc b/src/soc/intel/quark/Makefile.inc index 08325e7..d747079 100644 --- a/src/soc/intel/quark/Makefile.inc +++ b/src/soc/intel/quark/Makefile.inc @@ -18,6 +18,7 @@ ifeq ($(CONFIG_SOC_INTEL_QUARK),y) subdirs-y += romstage subdirs-y += ../../../cpu/x86/tsc +romstage-y += i2c.c romstage-y += memmap.c romstage-y += reg_access.c romstage-y += tsc_freq.c @@ -27,6 +28,7 @@ ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c ramstage-y += chip.c ramstage-y += ehci.c ramstage-y += gpio_i2c.c +ramstage-y += i2c.c ramstage-y += lpc.c ramstage-y += memmap.c ramstage-y += northcluster.c diff --git a/src/soc/intel/quark/gpio_i2c.c b/src/soc/intel/quark/gpio_i2c.c index d23a905..5580894 100644 --- a/src/soc/intel/quark/gpio_i2c.c +++ b/src/soc/intel/quark/gpio_i2c.c @@ -23,158 +23,6 @@ #include <soc/ramstage.h> #include <soc/reg_access.h> -static void i2c_disable(I2C_REGS *regs) -{ - uint32_t status; - uint32_t timeout; - - /* Disable I2C controller */ - regs->ic_enable = 0; - - /* Wait for the enable bit to clear */ - timeout = 1 * 1000 * 1000; - status = regs->ic_enable_status; - while (status & IC_ENABLE_CONTROLLER) { - udelay(1); - if (--timeout == 0) - die("ERROR - I2C failed to disable!\n"); - status = regs->ic_enable_status; - } - - /* Clear any pending interrupts */ - status = regs->ic_clr_intr; -} - -int platform_i2c_transfer(unsigned bus, struct i2c_seg *segments, int count) -{ - uint8_t *buffer; - int bytes_transferred; - uint8_t chip; - uint32_t cmd; - int length; - int read_length; - I2C_REGS *regs; - uint32_t status; - uint32_t timeout; - - regs = get_i2c_address(); - - /* Disable the I2C controller to get access to the registers */ - i2c_disable(regs); - - /* Set the slave address */ - ASSERT (count > 0); - ASSERT (segments != NULL); - ASSERT (segments->read == 0); - - /* Clear the start and stop detection */ - status = regs->ic_clr_start_det; - status = regs->ic_clr_stop_det; - - /* Set addressing mode to 7-bit and fast mode */ - cmd = regs->ic_con; - cmd &= ~(IC_CON_10B | IC_CON_SPEED); - cmd |= IC_CON_RESTART_EN | IC_CON_7B | IC_CON_SPEED_100_KHz - | IC_CON_MASTER_MODE; - regs->ic_con = cmd; - - /* Set the target chip address */ - chip = segments->chip; - regs->ic_tar = chip; - - /* Enable the I2C controller */ - regs->ic_enable = IC_ENABLE_CONTROLLER; - - /* Clear the interrupts */ - status = regs->ic_clr_rx_under; - status = regs->ic_clr_rx_over; - status = regs->ic_clr_tx_over; - status = regs->ic_clr_tx_abrt; - - /* Process each of the segments */ - bytes_transferred = 0; - read_length = 0; - buffer = NULL; - while (count-- > 0) { - buffer = segments->buf; - length = segments->len; - ASSERT (buffer != NULL); - ASSERT (length >= 1); - ASSERT (segments->chip = chip); - - if (segments->read) { - /* Place read commands into the FIFO */ - read_length = length; - while (length > 0) { - /* Send stop bit after last byte */ - cmd = IC_DATA_CMD_READ; - if ((count == 0) && (length == 1)) - cmd |= IC_DATA_CMD_STOP; - - /* Place read command in transmit FIFO */ - regs->ic_data_cmd = cmd; - length--; - } - } else { - /* Write the data into the FIFO */ - while (length > 0) { - /* End of the transaction? */ - cmd = IC_DATA_CMD_WRITE | *buffer++; - if ((count == 0) && (length == 1)) - cmd |= IC_DATA_CMD_STOP; - - /* Place a data byte into the FIFO */ - regs->ic_data_cmd = cmd; - length--; - bytes_transferred++; - } - } - segments++; - } - - /* Wait for the end of the transaction */ - timeout = 1 * 1000 * 1000; - do { - status = regs->ic_raw_intr_stat; - if (status & IC_INTR_STOP_DET) - break; - if ((status & (IC_INTR_RX_OVER | IC_INTR_RX_UNDER - | IC_INTR_TX_ABRT | IC_INTR_TX_OVER)) - || (timeout == 0)) { - if (timeout == 0) - printk (BIOS_ERR, - "ERROR - I2C stop bit not received!\n"); - if (status & IC_INTR_RX_OVER) - printk (BIOS_ERR, - "ERROR - I2C receive overrun!\n"); - if (status & IC_INTR_RX_UNDER) - printk (BIOS_ERR, - "ERROR - I2C receive underrun!\n"); - if (status & IC_INTR_TX_ABRT) - printk (BIOS_ERR, - "ERROR - I2C transmit abort!\n"); - if (status & IC_INTR_TX_OVER) - printk (BIOS_ERR, - "ERROR - I2C transmit overrun!\n"); - i2c_disable(regs); - return -1; - } - timeout--; - udelay(1); - } while(1); - - /* Finish reading the data bytes */ - while (read_length > 0) { - status = regs->ic_status; - *buffer++ = (UINT8)regs->ic_data_cmd; - read_length--; - bytes_transferred++; - status = regs->ic_status; - } - - return bytes_transferred; -} - __attribute__((weak)) void mainboard_gpio_i2c_init(device_t dev) { /* Initialize any of the GPIOs or I2C devices */ diff --git a/src/soc/intel/quark/i2c.c b/src/soc/intel/quark/i2c.c new file mode 100644 index 0000000..118cbea --- /dev/null +++ b/src/soc/intel/quark/i2c.c @@ -0,0 +1,176 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <delay.h> +#include <device/device.h> +#include <device/i2c.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <soc/i2c.h> +#include <soc/ramstage.h> +#include <soc/reg_access.h> + +static void i2c_disable(I2C_REGS *regs) +{ + uint32_t status; + uint32_t timeout; + + /* Disable I2C controller */ + regs->ic_enable = 0; + + /* Wait for the enable bit to clear */ + timeout = 1 * 1000 * 1000; + status = regs->ic_enable_status; + while (status & IC_ENABLE_CONTROLLER) { + udelay(1); + if (--timeout == 0) + die("ERROR - I2C failed to disable!\n"); + status = regs->ic_enable_status; + } + + /* Clear any pending interrupts */ + status = regs->ic_clr_intr; +} + +int platform_i2c_transfer(unsigned bus, struct i2c_seg *segments, int count) +{ + uint8_t *buffer; + int bytes_transferred; + uint8_t chip; + uint32_t cmd; + int length; + int read_length; + I2C_REGS *regs; + uint32_t status; + uint32_t timeout; + + regs = get_i2c_address(); + + /* Disable the I2C controller to get access to the registers */ + i2c_disable(regs); + + /* Set the slave address */ + ASSERT (count > 0); + ASSERT (segments != NULL); + ASSERT (segments->read == 0); + + /* Clear the start and stop detection */ + status = regs->ic_clr_start_det; + status = regs->ic_clr_stop_det; + + /* Set addressing mode to 7-bit and fast mode */ + cmd = regs->ic_con; + cmd &= ~(IC_CON_10B | IC_CON_SPEED); + cmd |= IC_CON_RESTART_EN | IC_CON_7B | IC_CON_SPEED_100_KHz + | IC_CON_MASTER_MODE; + regs->ic_con = cmd; + + /* Set the target chip address */ + chip = segments->chip; + regs->ic_tar = chip; + + /* Enable the I2C controller */ + regs->ic_enable = IC_ENABLE_CONTROLLER; + + /* Clear the interrupts */ + status = regs->ic_clr_rx_under; + status = regs->ic_clr_rx_over; + status = regs->ic_clr_tx_over; + status = regs->ic_clr_tx_abrt; + + /* Process each of the segments */ + bytes_transferred = 0; + read_length = 0; + buffer = NULL; + while (count-- > 0) { + buffer = segments->buf; + length = segments->len; + ASSERT (buffer != NULL); + ASSERT (length >= 1); + ASSERT (segments->chip = chip); + + if (segments->read) { + /* Place read commands into the FIFO */ + read_length = length; + while (length > 0) { + /* Send stop bit after last byte */ + cmd = IC_DATA_CMD_READ; + if ((count == 0) && (length == 1)) + cmd |= IC_DATA_CMD_STOP; + + /* Place read command in transmit FIFO */ + regs->ic_data_cmd = cmd; + length--; + } + } else { + /* Write the data into the FIFO */ + while (length > 0) { + /* End of the transaction? */ + cmd = IC_DATA_CMD_WRITE | *buffer++; + if ((count == 0) && (length == 1)) + cmd |= IC_DATA_CMD_STOP; + + /* Place a data byte into the FIFO */ + regs->ic_data_cmd = cmd; + length--; + bytes_transferred++; + } + } + segments++; + } + + /* Wait for the end of the transaction */ + timeout = 1 * 1000 * 1000; + do { + status = regs->ic_raw_intr_stat; + if (status & IC_INTR_STOP_DET) + break; + if ((status & (IC_INTR_RX_OVER | IC_INTR_RX_UNDER + | IC_INTR_TX_ABRT | IC_INTR_TX_OVER)) + || (timeout == 0)) { + if (timeout == 0) + printk (BIOS_ERR, + "ERROR - I2C stop bit not received!\n"); + if (status & IC_INTR_RX_OVER) + printk (BIOS_ERR, + "ERROR - I2C receive overrun!\n"); + if (status & IC_INTR_RX_UNDER) + printk (BIOS_ERR, + "ERROR - I2C receive underrun!\n"); + if (status & IC_INTR_TX_ABRT) + printk (BIOS_ERR, + "ERROR - I2C transmit abort!\n"); + if (status & IC_INTR_TX_OVER) + printk (BIOS_ERR, + "ERROR - I2C transmit overrun!\n"); + i2c_disable(regs); + return -1; + } + timeout--; + udelay(1); + } while(1); + + /* Finish reading the data bytes */ + while (read_length > 0) { + status = regs->ic_status; + *buffer++ = (UINT8)regs->ic_data_cmd; + read_length--; + bytes_transferred++; + status = regs->ic_status; + } + + return bytes_transferred; +}

1 0

New patch to review for coreboot: soc/intel/quark: Set temporary I2C base address
by Leroy P Leahy 31 May '16

31 May '16

Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15006 -gerrit commit 45bf46d2823475d0b70cd2e26059e3b43ea0d24a Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Mon May 30 14:16:10 2016 -0700 soc/intel/quark: Set temporary I2C base address Set a temporary I2C base address during romstage. TEST=Build and run on Galileo Gen2 Change-Id: I4b427c66a4e7e6d30cc611d4d3c40bb0ea36066d Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/soc/intel/quark/include/soc/iomap.h | 3 ++- src/soc/intel/quark/romstage/romstage.c | 3 ++- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/src/soc/intel/quark/include/soc/iomap.h b/src/soc/intel/quark/include/soc/iomap.h index 61773d5..1224bcc 100644 --- a/src/soc/intel/quark/include/soc/iomap.h +++ b/src/soc/intel/quark/include/soc/iomap.h @@ -25,7 +25,8 @@ #define UART_BASE_ADDRESS CONFIG_TTYS0_BASE /* I2C/GPIO Controller */ -#define I2C_GPIO_BASE_ADDRESS 0xa0020000 +#define I2C_BASE_ADDRESS 0xa0020000 +#define GPIO_BASE_ADDRESS 0xa0021000 /* * I/O port address space diff --git a/src/soc/intel/quark/romstage/romstage.c b/src/soc/intel/quark/romstage/romstage.c index c4f9844..c86c2ea 100644 --- a/src/soc/intel/quark/romstage/romstage.c +++ b/src/soc/intel/quark/romstage/romstage.c @@ -52,7 +52,8 @@ static const struct reg_script legacy_gpio_init[] = { static const struct reg_script i2c_gpio_controller_init[] = { /* Temporarily enable the GPIO controller */ - REG_PCI_WRITE32(PCI_BASE_ADDRESS_1, I2C_GPIO_BASE_ADDRESS), + REG_PCI_WRITE32(PCI_BASE_ADDRESS_0, I2C_BASE_ADDRESS), + REG_PCI_WRITE32(PCI_BASE_ADDRESS_1, GPIO_BASE_ADDRESS), REG_PCI_OR8(PCI_COMMAND, PCI_COMMAND_MEMORY), REG_SCRIPT_END };

1 0

New patch to review for coreboot: mainboard/intel/galileo: Use HSUART1 for console
by Leroy P Leahy 31 May '16

31 May '16

Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15005 -gerrit commit 3e60ede6ab6718262408b392b3a7219a05ced331 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Mon May 30 14:02:49 2016 -0700 mainboard/intel/galileo: Use HSUART1 for console Select HSUART1 for console. TEST=Build and run on Galileo Gen2 Change-Id: I4425af4dc8b3730b3fa2108d6cc2941bc22c2cdb Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/mainboard/intel/galileo/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mainboard/intel/galileo/Kconfig b/src/mainboard/intel/galileo/Kconfig index b5aaa05..463bb6b 100644 --- a/src/mainboard/intel/galileo/Kconfig +++ b/src/mainboard/intel/galileo/Kconfig @@ -19,6 +19,7 @@ config BOARD_SPECIFIC_OPTIONS def_bool y select BOARD_ROMSIZE_KB_8192 select CREATE_BOARD_CHECKLIST + select ENABLE_BUILTIN_HSUART1 select HAVE_ACPI_TABLES select SOC_INTEL_QUARK select USE_FSP1_1

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New patch to review for coreboot: mainboard/intel/galileo: Add CREATE_BOARD_CHECKLIST
by Leroy P Leahy 31 May '16

31 May '16

Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15004 -gerrit commit 79d2ccc47adaaacce34fe87f1a81361d82e75f24 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Sat May 28 14:34:44 2016 -0700 mainboard/intel/galileo: Add CREATE_BOARD_CHECKLIST Select CREATE_BOARD_CHECKLIST to create the checklist for the Quark SOC and Galileo board. TEST=Build and run on Galileo Gen2. Change-Id: Ieb3e9a5a4c149cf160e11d44a515591b57fe5c83 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/mainboard/intel/galileo/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mainboard/intel/galileo/Kconfig b/src/mainboard/intel/galileo/Kconfig index 225e1c3..b5aaa05 100644 --- a/src/mainboard/intel/galileo/Kconfig +++ b/src/mainboard/intel/galileo/Kconfig @@ -18,6 +18,7 @@ if BOARD_INTEL_GALILEO config BOARD_SPECIFIC_OPTIONS def_bool y select BOARD_ROMSIZE_KB_8192 + select CREATE_BOARD_CHECKLIST select HAVE_ACPI_TABLES select SOC_INTEL_QUARK select USE_FSP1_1

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New patch to review for coreboot: Documentation/Intel/Board: Add analog switch link
by Leroy P Leahy 31 May '16

31 May '16

Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15003 -gerrit commit 2286d75e9680634c954447d1edcbd6dea21ddf44 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Mon May 30 11:25:22 2016 -0700 Documentation/Intel/Board: Add analog switch link Add link for TI TS5A23159 specification. TEST=None Change-Id: I2756ded963fc7597e4db1fa151bf62630b1108d9 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- Documentation/Intel/Board/galileo.html | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/Intel/Board/galileo.html b/Documentation/Intel/Board/galileo.html index 3ed6672..3639419 100644 --- a/Documentation/Intel/Board/galileo.html +++ b/Documentation/Intel/Board/galileo.html @@ -76,6 +76,7 @@ <li>Components <ul> <li>A/D: Analog Devices <a target="_blank" href="http://www.analog.com/media/en/technical-documentation/data-sheets/AD7298-1…">AD7298</a></li> + <li>Analog Switch, 2 channel: Texas Instruments <a target="_blank" href="http://www.ti.com.cn/cn/lit/ds/symlink/ts5a23159.pdf">TS5A23159</a></li> <li>EEPROM & GPIO: Cypress <a target="_blank" href="http://www.cypress.com/file/37971/download">CY8C9540A</a></li> <li>Power Distribution Switch: Texas Instruments <a target="_blank" href="http://www.ti.com/lit/ds/symlink/tps2044b.pdf">TPS2051BDBVR</a></li> <li>RS232 Converter: Texas Instruments <a target="_blank" href="http://www.ti.com/lit/ds/symlink/max3232.pdf">MAX3232</a></li>

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New patch to review for coreboot: soc/intel/quark: Conditionally define BIT names
by Leroy P Leahy 31 May '16

31 May '16

Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15002 -gerrit commit 9a0f420a99f95658c8348b8ac0fe5d0cad7e9c6d Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Mon May 30 05:38:57 2016 -0700 soc/intel/quark: Conditionally define BIT names Only define BIT names if they are not already defined. TEST=Build and run on Galileo Gen2 Change-Id: Ief4c4bb7a42a1bb2a7f46f13dc9b8bbb4d233e3c Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/soc/intel/quark/include/soc/QuarkNcSocId.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/soc/intel/quark/include/soc/QuarkNcSocId.h b/src/soc/intel/quark/include/soc/QuarkNcSocId.h index 12f600a..8b5ca2c 100644 --- a/src/soc/intel/quark/include/soc/QuarkNcSocId.h +++ b/src/soc/intel/quark/include/soc/QuarkNcSocId.h @@ -24,6 +24,7 @@ Definitions beginning with "N_" are the bit position // // Define the bits // +#ifndef BIT0 #define BIT0 0x00000001 #define BIT1 0x00000002 #define BIT2 0x00000004 @@ -56,6 +57,7 @@ Definitions beginning with "N_" are the bit position #define BIT29 0x20000000 #define BIT30 0x40000000 #define BIT31 0x80000000 +#endif // // QNC GMCH Equates

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coreboot-gerrit May 2016