coreboot-gerrit May 2016

coreboot-gerrit@coreboot.org

1 participants
1843 discussions

Patch set updated for coreboot: soc/intel/apollolake: add support for IFWI region
by Furquan Shaikh 30 May '16

30 May '16

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14999 -gerrit commit c3d04fde49ae84803b8e6196562971bf92c6acc9 Author: Furquan Shaikh <furquan(a)google.com> Date: Sat May 28 12:57:05 2016 -0700 soc/intel/apollolake: add support for IFWI region On apollolake, the boot media layout is different in that the traditional "BIOS" region contains another data structure with the boot assets such as CSE firmware, PMC microcode, CPU microcode, and boot firmware to name a few. This region is referred to as the IFWI. Add support for writing the IFWI to a specified FMAP region to accommodate such platforms. Change-Id: Ia61f12a77893c3dd3256a9bd4e0f5eca0065de26 Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- src/soc/intel/apollolake/Kconfig | 21 +++++++++++++++++++++ src/soc/intel/apollolake/Makefile.inc | 5 +++++ 2 files changed, 26 insertions(+) diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index d6c5ffc..7c21ed2 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -160,4 +160,25 @@ config LBP2_FILE_NAME help Name of file to store in the logical boot partition 2 region. +config NEED_IFWI + bool "Write content into IFWI region" + default n + help + Write the content from a file into IFWI region defined by + IFWI_FMAP_NAME. + +config IFWI_FMAP_NAME + string "Name of FMAP region to pull IFWI into" + depends on NEED_IFWI + default "IFWI" + help + Name of FMAP region to write IFWI. + +config IFWI_FILE_NAME + string "Path of file to write to IFWI region" + depends on NEED_IFWI + default "3rdparty/blobs/mainboard/$(CONFIG_MAINBOARD_DIR)/ifwi.bin" + help + Name of file to store in the IFWI region. + endif diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index 1ea21f6..413b999 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -75,4 +75,9 @@ files_added:: $(CBFSTOOL) $(obj)/coreboot.rom write -r $(CONFIG_LBP2_FMAP_NAME) -f $(CONFIG_LBP2_FILE_NAME) --fill-upward endif +ifeq ($(CONFIG_NEED_IFWI),y) +files_added:: + $(CBFSTOOL) $(obj)/coreboot.rom write -r $(CONFIG_IFWI_FMAP_NAME) -f $(CONFIG_IFWI_FILE_NAME) --fill-upward +endif + endif

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Patch set updated for coreboot: mainboard/google/reef: Add IFWI region to chromeos.fmd
by Furquan Shaikh 30 May '16

30 May '16

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15000 -gerrit commit 0f423aef6aa06a0c660f9a7583efcda2059cfaef Author: Furquan Shaikh <furquan(a)google.com> Date: Sun May 29 20:24:37 2016 -0700 mainboard/google/reef: Add IFWI region to chromeos.fmd IFWI region holds different components required for booting including CSE firmware, PMC firmware, CPU microcode as well as the bootblock. Add section for IFWI in chromeos.fmd Change-Id: Ic97980ff222ad7cbd7a2970417b79150256a7a16 Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- src/mainboard/google/reef/chromeos.fmd | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/google/reef/chromeos.fmd b/src/mainboard/google/reef/chromeos.fmd index 3f7c3aa..58959d6 100644 --- a/src/mainboard/google/reef/chromeos.fmd +++ b/src/mainboard/google/reef/chromeos.fmd @@ -2,7 +2,7 @@ FLASH 8M { WP_RO@0x0 0x400000 { SI_ALL@0x0 0x200000 { SI_DESC@0x0 0x1000 - bootblock@0x7c480 0x8000 + IFWI@0x1000 0x1ff000 } RO_SECTION@0x200000 0x200000 { RO_VPD@0x0 0x4000

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Patch set updated for coreboot: SMBIOS: Implement SKU field
by Kyösti Mälkki 30 May '16

30 May '16

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14996 -gerrit commit f2dc2798e69359e0347b356d84a52ebffb184636 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Mon May 30 16:52:31 2016 +0300 SMBIOS: Implement SKU field Leave it for the platform to fill in the string. Change-Id: I7b4fe585f8d1efc8c9743f0d8b38de1f98124aab Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/x86/smbios.c | 7 +++++++ src/include/smbios.h | 1 + 2 files changed, 8 insertions(+) diff --git a/src/arch/x86/smbios.c b/src/arch/x86/smbios.c index 7c5497e..c5a2e44 100644 --- a/src/arch/x86/smbios.c +++ b/src/arch/x86/smbios.c @@ -340,6 +340,12 @@ void __attribute__((weak)) smbios_mainboard_set_uuid(u8 *uuid) } #endif +const char *__attribute__((weak)) smbios_mainboard_sku(void) +{ + static const char empty_sku[] = ""; + return empty_sku; +} + #ifdef CONFIG_MAINBOARD_FAMILY const char *smbios_mainboard_family(void) { @@ -359,6 +365,7 @@ static int smbios_write_type1(unsigned long *current, int handle) t->manufacturer = smbios_add_string(t->eos, smbios_mainboard_manufacturer()); t->product_name = smbios_add_string(t->eos, smbios_mainboard_product_name()); t->serial_number = smbios_add_string(t->eos, smbios_mainboard_serial_number()); + t->sku = smbios_add_string(t->eos, smbios_mainboard_sku()); t->version = smbios_add_string(t->eos, smbios_mainboard_version()); #ifdef CONFIG_MAINBOARD_FAMILY t->family = smbios_add_string(t->eos, smbios_mainboard_family()); diff --git a/src/include/smbios.h b/src/include/smbios.h index 004bcc6..0400262 100644 --- a/src/include/smbios.h +++ b/src/include/smbios.h @@ -35,6 +35,7 @@ const char *smbios_mainboard_serial_number(void); const char *smbios_mainboard_version(void); void smbios_mainboard_set_uuid(u8 *uuid); const char *smbios_mainboard_bios_version(void); +const char *smbios_mainboard_sku(void); u8 smbios_mainboard_enclosure_type(void); #ifdef CONFIG_MAINBOARD_FAMILY const char *smbios_mainboard_family(void);

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Patch set updated for coreboot: pcengines/apu1: Add SMBios SKU field
by Kyösti Mälkki 30 May '16

30 May '16

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14997 -gerrit commit 546cae02b6d84127db073d5d94b2fedd66fdbe3b Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Mon May 30 16:56:11 2016 +0300 pcengines/apu1: Add SMBios SKU field Just the memory size, there is no strap to identify PCB revision. Change-Id: I65b2f5b0ac6930bead60ea0a551f13a6bcab24c7 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/mainboard/pcengines/apu1/mainboard.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/src/mainboard/pcengines/apu1/mainboard.c b/src/mainboard/pcengines/apu1/mainboard.c index 2ebdc75..96b2020 100644 --- a/src/mainboard/pcengines/apu1/mainboard.c +++ b/src/mainboard/pcengines/apu1/mainboard.c @@ -260,6 +260,22 @@ static void usb_oc_setup(void) pci_write_config32(dev, 0x58, 0x011f0); } +/* + * We will stuff the memory size into the smbios sku location. + */ +const char *smbios_mainboard_sku(void) +{ + static char sku[5]; + if (sku[0] != 0) + return sku; + + if (!get_spd_offset()) + snprintf(sku, sizeof(sku), "2 GB"); + else + snprintf(sku, sizeof(sku), "4 GB"); + return sku; +} + static void mainboard_final(void *chip_info) { u32 mmio_base;

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Patch set updated for coreboot: pcengines/apu1: Add RS485 configuration
by Kyösti Mälkki 30 May '16

30 May '16

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14998 -gerrit commit f63ae0ddb215e64c1bcfa099a3d010f641c1b8e8 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Oct 13 15:01:15 2015 +0300 pcengines/apu1: Add RS485 configuration In RS485 mode #RTS line acts as a transceiver direction control. Change-Id: I705fe0c5a5f8369b0a9358a64c74500238b5c4ba Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/mainboard/pcengines/apu1/Kconfig | 6 ++++++ src/mainboard/pcengines/apu1/mainboard.c | 23 +++++++++++++++++++++++ 2 files changed, 29 insertions(+) diff --git a/src/mainboard/pcengines/apu1/Kconfig b/src/mainboard/pcengines/apu1/Kconfig index e9aab8c..3099d14 100644 --- a/src/mainboard/pcengines/apu1/Kconfig +++ b/src/mainboard/pcengines/apu1/Kconfig @@ -95,6 +95,9 @@ config APU1_PINMUX_UART_C endchoice +config UART_C_RS485 + bool "UART C drives RTS# in RS485 mode" if APU1_PINMUX_UART_C + choice prompt "J19 pins 11-20" default APU1_PINMUX_OFF_D @@ -110,4 +113,7 @@ config APU1_PINMUX_UART_D endchoice +config UART_D_RS485 + bool "UART D drives RTS# in RS485 mode" if APU1_PINMUX_UART_D + endif # BOARD_PCENGINES_APU1 diff --git a/src/mainboard/pcengines/apu1/mainboard.c b/src/mainboard/pcengines/apu1/mainboard.c index 96b2020..055cd58 100644 --- a/src/mainboard/pcengines/apu1/mainboard.c +++ b/src/mainboard/pcengines/apu1/mainboard.c @@ -158,6 +158,28 @@ static void config_gpio_mux(void) gpio->enabled = CONFIG_APU1_PINMUX_GPIO1; } +static void pnp_raw_resource(struct device *dev, u8 reg, u8 val) +{ + struct resource *res; + res = new_resource(dev, reg); + res->base = val; + res->size = 0; + res->flags |= IORESOURCE_IRQ | IORESOURCE_ASSIGNED; +} + +static void config_addon_uart(void) +{ + struct device *uart; + + uart = dev_find_slot_pnp(SIO_PORT, NCT5104D_SP3); + if (uart && uart->enabled && CONFIG_UART_C_RS485) + pnp_raw_resource(uart, 0xf2, 0x12); + + uart = dev_find_slot_pnp(SIO_PORT, NCT5104D_SP4); + if (uart && uart->enabled && CONFIG_UART_D_RS485) + pnp_raw_resource(uart, 0xf2, 0x12); +} + /** * TODO * SB CIMx callback @@ -182,6 +204,7 @@ static void mainboard_enable(device_t dev) printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); config_gpio_mux(); + config_addon_uart(); /* Power off unused clock pins of GPP PCIe devices */ u8 *misc_mem_clk_cntrl = (u8 *)(ACPI_MMIO_BASE + MISC_BASE);

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Patch set updated for coreboot: intel/apollolake: Add support to enable google ChromeEC
by Shaunak Saha 30 May '16

30 May '16

Shaunak Saha (shaunak.saha(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14967 -gerrit commit c17f9e4c2932fa72294d27267a778b66cf7112f0 Author: Shaunak Saha <shaunak.saha(a)intel.com> Date: Wed May 25 11:34:43 2016 -0700 intel/apollolake: Add support to enable google ChromeEC ChromeEC is needed for EC controlled features to work properly. This patch adds neccessary support in soc/intel so that mainboard asl files can include the ChromeEC e.g. PNOT method and LPCB and also the nvs fields. BUG = 53096 TEST = This patch is needed by the mainboard specific ASL change to include src/ec/google/chromeec/acpi/ec.asl Change-Id: Icecc437df05cd3efb41579317a353fd22526e0c9 Signed-off-by: Shaunak Saha <shaunak.saha(a)intel.com> --- src/soc/intel/apollolake/acpi/cpu.asl | 118 ++++++++++++++++++++++++++ src/soc/intel/apollolake/acpi/globalnvs.asl | 7 +- src/soc/intel/apollolake/acpi/lpc.asl | 23 +++++ src/soc/intel/apollolake/acpi/southbridge.asl | 3 + src/soc/intel/apollolake/include/soc/nvs.h | 7 +- 5 files changed, 156 insertions(+), 2 deletions(-) diff --git a/src/soc/intel/apollolake/acpi/cpu.asl b/src/soc/intel/apollolake/acpi/cpu.asl new file mode 100644 index 0000000..a202ceb --- /dev/null +++ b/src/soc/intel/apollolake/acpi/cpu.asl @@ -0,0 +1,118 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* These devices are created at runtime */ +External (\_PR.CP00, DeviceObj) +External (\_PR.CP01, DeviceObj) +External (\_PR.CP02, DeviceObj) +External (\_PR.CP03, DeviceObj) +External (\_PR.CP04, DeviceObj) +External (\_PR.CP05, DeviceObj) +External (\_PR.CP06, DeviceObj) +External (\_PR.CP07, DeviceObj) + +/* Notify OS to re-read CPU tables, assuming ^2 CPU count */ +Method (PNOT) +{ + If (LGreaterEqual (\PCNT, 2)) { + Notify (\_PR.CP00, 0x81) // _CST + Notify (\_PR.CP01, 0x81) // _CST + } + If (LGreaterEqual (\PCNT, 4)) { + Notify (\_PR.CP02, 0x81) // _CST + Notify (\_PR.CP03, 0x81) // _CST + } + If (LGreaterEqual (\PCNT, 8)) { + Notify (\_PR.CP04, 0x81) // _CST + Notify (\_PR.CP05, 0x81) // _CST + Notify (\_PR.CP06, 0x81) // _CST + Notify (\_PR.CP07, 0x81) // _CST + } +} + +/* Notify OS to re-read CPU _PPC limit, assuming ^2 CPU count */ +Method (PPCN) +{ + If (LGreaterEqual (\PCNT, 2)) { + Notify (\_PR.CP00, 0x80) // _PPC + Notify (\_PR.CP01, 0x80) // _PPC + } + If (LGreaterEqual (\PCNT, 4)) { + Notify (\_PR.CP02, 0x80) // _PPC + Notify (\_PR.CP03, 0x80) // _PPC + } + If (LGreaterEqual (\PCNT, 8)) { + Notify (\_PR.CP04, 0x80) // _PPC + Notify (\_PR.CP05, 0x80) // _PPC + Notify (\_PR.CP06, 0x80) // _PPC + Notify (\_PR.CP07, 0x80) // _PPC + } +} + +/* Notify OS to re-read Throttle Limit tables, assuming ^2 CPU count */ +Method (TNOT) +{ + If (LGreaterEqual (\PCNT, 2)) { + Notify (\_PR.CP00, 0x82) // _TPC + Notify (\_PR.CP01, 0x82) // _TPC + } + If (LGreaterEqual (\PCNT, 4)) { + Notify (\_PR.CP02, 0x82) // _TPC + Notify (\_PR.CP03, 0x82) // _TPC + } + If (LGreaterEqual (\PCNT, 8)) { + Notify (\_PR.CP04, 0x82) // _TPC + Notify (\_PR.CP05, 0x82) // _TPC + Notify (\_PR.CP06, 0x82) // _TPC + Notify (\_PR.CP07, 0x82) // _TPC + } +} + +/* Return a package containing enabled processor entries */ +Method (PPKG) +{ + If (LGreaterEqual (\PCNT, 8)) { + Return (Package() + { + \_PR.CP00, + \_PR.CP01, + \_PR.CP02, + \_PR.CP03, + \_PR.CP04, + \_PR.CP05, + \_PR.CP06, + \_PR.CP07 + }) + } ElseIf (LGreaterEqual (\PCNT, 4)) { + Return (Package () + { + \_PR.CP00, + \_PR.CP01, + \_PR.CP02, + \_PR.CP03 + }) + } ElseIf (LGreaterEqual (\PCNT, 2)) { + Return (Package () + { + \_PR.CP00, + \_PR.CP01 + }) + } Else { + Return (Package () + { + \_PR.CP00 + }) + } +} diff --git a/src/soc/intel/apollolake/acpi/globalnvs.asl b/src/soc/intel/apollolake/acpi/globalnvs.asl index 2ef5031..e081dcb 100644 --- a/src/soc/intel/apollolake/acpi/globalnvs.asl +++ b/src/soc/intel/apollolake/acpi/globalnvs.asl @@ -26,8 +26,13 @@ External (NVSA) OperationRegion (GNVS, SystemMemory, NVSA, 0x1000) Field (GNVS, ByteAcc, NoLock, Preserve) { - /* Nothing here yet, folks */ + /* Miscellaneous */ Offset (0x00), + PCNT, 8, // 0x01 - Processor Count + PPCM, 8, // 0x02 - Max PPC State + LIDS, 8, // 0x03 - LID State + PWRS, 8, // 0x04 - AC Power State + DPTE, 8, // 0x05 - Enable DPTF /* ChromeOS stuff (0x100 -> 0xfff, size 0xeff) */ Offset (0x100), diff --git a/src/soc/intel/apollolake/acpi/lpc.asl b/src/soc/intel/apollolake/acpi/lpc.asl new file mode 100644 index 0000000..749daf7 --- /dev/null +++ b/src/soc/intel/apollolake/acpi/lpc.asl @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* Intel LPC Bus Device - 0:1f.0 */ + +Device (LPCB) +{ + Name (_ADR, 0x001f0000) +} diff --git a/src/soc/intel/apollolake/acpi/southbridge.asl b/src/soc/intel/apollolake/acpi/southbridge.asl index 9409d5e..44c440e 100644 --- a/src/soc/intel/apollolake/acpi/southbridge.asl +++ b/src/soc/intel/apollolake/acpi/southbridge.asl @@ -27,3 +27,6 @@ #include "gpio.asl" #include "xhci.asl" + +/* LPC */ +#include "lpc.asl" diff --git a/src/soc/intel/apollolake/include/soc/nvs.h b/src/soc/intel/apollolake/include/soc/nvs.h index 8b3a3af..4768aaa 100644 --- a/src/soc/intel/apollolake/include/soc/nvs.h +++ b/src/soc/intel/apollolake/include/soc/nvs.h @@ -28,7 +28,12 @@ struct global_nvs_t { /* Miscellaneous */ - uint8_t unused[256]; + uint8_t pcnt; /* 0x01 - Processor Count */ + uint8_t ppcm; /* 0x02 - Max PPC State */ + uint8_t lids; /* 0x03 - LID State */ + uint8_t pwrs; /* 0x04 - AC Power State */ + uint8_t dpte; /* 0x05 - Enable DPTF */ + uint8_t unused[251]; /* ChromeOS specific (0x100 - 0xfff) */ chromeos_acpi_t chromeos;

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Patch set updated for coreboot: intel/amenia: Add asl code to enable google ChromeEC
by Shaunak Saha 30 May '16

30 May '16

Shaunak Saha (shaunak.saha(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14987 -gerrit commit 9fccd3150e2324b5e1b67b7e86d76293aa61e471 Author: Shaunak Saha <shaunak.saha(a)intel.com> Date: Fri May 27 01:13:16 2016 -0700 intel/amenia: Add asl code to enable google ChromeEC This patch adds asl code to include support for Google ChromeEC. We need this to show the battery icon and notifications like charger connect/disconnect etc. BUG = 53096 TEST = Plug/Unplug AC Adapter multiple times and make sure the battery connected is charging properly. Change-Id: Id908f145789402573ea54fc4f15cf7a0e651ebf4 Signed-off-by: Shaunak Saha <shaunak.saha(a)intel.com> --- src/mainboard/intel/amenia/acpi/ec.asl | 26 ++++++++++++++++++++++++++ src/mainboard/intel/amenia/acpi/mainboard.asl | 26 ++++++++++++++++++++++++++ src/mainboard/intel/amenia/dsdt.asl | 7 ++++++- src/mainboard/intel/amenia/ec.h | 4 ++++ 4 files changed, 62 insertions(+), 1 deletion(-) diff --git a/src/mainboard/intel/amenia/acpi/ec.asl b/src/mainboard/intel/amenia/acpi/ec.asl new file mode 100644 index 0000000..fe53cb5 --- /dev/null +++ b/src/mainboard/intel/amenia/acpi/ec.asl @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* mainboard configuration */ +#include "../ec.h" + +/* Enable EC backed ALS device in ACPI */ +#define EC_ENABLE_ALS_DEVICE + +/* Enable EC backed PD MCU device in ACPI */ +#define EC_ENABLE_PD_MCU_DEVICE + +/* ACPI code for EC functions */ +#include <ec/google/chromeec/acpi/ec.asl> diff --git a/src/mainboard/intel/amenia/acpi/mainboard.asl b/src/mainboard/intel/amenia/acpi/mainboard.asl index 09ef9b4..c83f48f 100644 --- a/src/mainboard/intel/amenia/acpi/mainboard.asl +++ b/src/mainboard/intel/amenia/acpi/mainboard.asl @@ -16,6 +16,23 @@ */ #include <soc/gpio_defs.h> +Scope (\_SB) +{ + Device (LID0) + { + Name (_HID, EisaId ("PNP0C0D")) + Method (_LID, 0) + { + Return (\_SB.PCI0.LPCB.EC0.LIDS) + } + } + + Device (PWRB) + { + Name (_HID, EisaId ("PNP0C0C")) + } +} + Scope (\_SB.PCI0.I2C4) { /* Standard Mode: HCNT, LCNT, SDA Hold Register */ @@ -91,3 +108,12 @@ Scope (\_SB.PCI0.I2C3) } } } + +/* + * LPC Trusted Platform Module + */ +Scope (\_SB.PCI0.LPCB) +{ + #include <drivers/pc80/tpm/acpi/tpm.asl> + #include "ec.asl" +} diff --git a/src/mainboard/intel/amenia/dsdt.asl b/src/mainboard/intel/amenia/dsdt.asl index 19e7360..4a64f87 100644 --- a/src/mainboard/intel/amenia/dsdt.asl +++ b/src/mainboard/intel/amenia/dsdt.asl @@ -24,6 +24,12 @@ DefinitionBlock( 0x20110725 // OEM revision ) { + /* global NVS and variables */ + #include <soc/intel/apollolake/acpi/globalnvs.asl> + + /* CPU */ + #include <soc/intel/apollolake/acpi/cpu.asl> + Scope (\_SB) { Device (PCI0) { @@ -38,5 +44,4 @@ DefinitionBlock( #include <soc/intel/apollolake/acpi/sleepstates.asl> #include "acpi/superio.asl" - } diff --git a/src/mainboard/intel/amenia/ec.h b/src/mainboard/intel/amenia/ec.h index ab8bcba..91890fd 100644 --- a/src/mainboard/intel/amenia/ec.h +++ b/src/mainboard/intel/amenia/ec.h @@ -20,6 +20,10 @@ #include <ec/google/chromeec/ec_commands.h> +/* This is the GPE status bit. + TODO: Fix this to proper bit matching GPE routing table */ +#define EC_SCI_GPI 15 + #define MAINBOARD_EC_SCI_EVENTS \ (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED) |\ EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\

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New patch to review for coreboot: mainboard/google/reef: Add IFWI region to chromeos.fmd
by Furquan Shaikh 30 May '16

30 May '16

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15000 -gerrit commit 8e40d3e92d59043864fff76e5f31151d83d81840 Author: Furquan Shaikh <furquan(a)google.com> Date: Sun May 29 20:24:37 2016 -0700 mainboard/google/reef: Add IFWI region to chromeos.fmd IFWI region holds different components required for booting including CSE firmware, PMC firmware, CPU microcode as well as the bootblock. Add section for IFWI in chromeos.fmd Change-Id: Ic97980ff222ad7cbd7a2970417b79150256a7a16 Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- src/mainboard/google/reef/chromeos.fmd | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/google/reef/chromeos.fmd b/src/mainboard/google/reef/chromeos.fmd index 3f7c3aa..58959d6 100644 --- a/src/mainboard/google/reef/chromeos.fmd +++ b/src/mainboard/google/reef/chromeos.fmd @@ -2,7 +2,7 @@ FLASH 8M { WP_RO@0x0 0x400000 { SI_ALL@0x0 0x200000 { SI_DESC@0x0 0x1000 - bootblock@0x7c480 0x8000 + IFWI@0x1000 0x1ff000 } RO_SECTION@0x200000 0x200000 { RO_VPD@0x0 0x4000

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New patch to review for coreboot: soc/intel/apollolake: add support for IFWI region
by Furquan Shaikh 30 May '16

30 May '16

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14999 -gerrit commit 9ec19757f2b685a3de514b575caed8d27483463d Author: Furquan Shaikh <furquan(a)google.com> Date: Sat May 28 12:57:05 2016 -0700 soc/intel/apollolake: add support for IFWI region On apollolake, the boot media layout is different in that the traditional "BIOS" region contains another data structure with the boot assets such as CSE firmware, PMC microcode, CPU microcode, and boot firmware to name a few. This region is referred to as the IFWI. Add support for writing the IFWI to a specified FMAP region to accommodate such platforms. Change-Id: Ia61f12a77893c3dd3256a9bd4e0f5eca0065de26 Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- src/soc/intel/apollolake/Kconfig | 21 +++++++++++++++++++++ src/soc/intel/apollolake/Makefile.inc | 3 +++ 2 files changed, 24 insertions(+) diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index d6c5ffc..7c21ed2 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -160,4 +160,25 @@ config LBP2_FILE_NAME help Name of file to store in the logical boot partition 2 region. +config NEED_IFWI + bool "Write content into IFWI region" + default n + help + Write the content from a file into IFWI region defined by + IFWI_FMAP_NAME. + +config IFWI_FMAP_NAME + string "Name of FMAP region to pull IFWI into" + depends on NEED_IFWI + default "IFWI" + help + Name of FMAP region to write IFWI. + +config IFWI_FILE_NAME + string "Path of file to write to IFWI region" + depends on NEED_IFWI + default "3rdparty/blobs/mainboard/$(CONFIG_MAINBOARD_DIR)/ifwi.bin" + help + Name of file to store in the IFWI region. + endif diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index 1ea21f6..d5165b3 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -75,4 +75,7 @@ files_added:: $(CBFSTOOL) $(obj)/coreboot.rom write -r $(CONFIG_LBP2_FMAP_NAME) -f $(CONFIG_LBP2_FILE_NAME) --fill-upward endif +files_added:: + $(CBFSTOOL) $(obj)/coreboot.rom write -r $(CONFIG_IFWI_FMAP_NAME) -f $(CONFIG_IFWI_FILE_NAME) --fill-upward + endif

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New patch to review for coreboot: pcengines/apu1: Add RS485 configuration
by Kyösti Mälkki 30 May '16

30 May '16

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14998 -gerrit commit b502b004bacf8744f7583362a4d77418eed3b9af Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Oct 13 15:01:15 2015 +0300 pcengines/apu1: Add RS485 configuration In RS485 mode #RTS line acts as a transceiver direction control. Change-Id: I705fe0c5a5f8369b0a9358a64c74500238b5c4ba Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/mainboard/pcengines/apu1/Kconfig | 6 ++++++ src/mainboard/pcengines/apu1/mainboard.c | 23 +++++++++++++++++++++++ 2 files changed, 29 insertions(+) diff --git a/src/mainboard/pcengines/apu1/Kconfig b/src/mainboard/pcengines/apu1/Kconfig index e9aab8c..3099d14 100644 --- a/src/mainboard/pcengines/apu1/Kconfig +++ b/src/mainboard/pcengines/apu1/Kconfig @@ -95,6 +95,9 @@ config APU1_PINMUX_UART_C endchoice +config UART_C_RS485 + bool "UART C drives RTS# in RS485 mode" if APU1_PINMUX_UART_C + choice prompt "J19 pins 11-20" default APU1_PINMUX_OFF_D @@ -110,4 +113,7 @@ config APU1_PINMUX_UART_D endchoice +config UART_D_RS485 + bool "UART D drives RTS# in RS485 mode" if APU1_PINMUX_UART_D + endif # BOARD_PCENGINES_APU1 diff --git a/src/mainboard/pcengines/apu1/mainboard.c b/src/mainboard/pcengines/apu1/mainboard.c index 96b2020..055cd58 100644 --- a/src/mainboard/pcengines/apu1/mainboard.c +++ b/src/mainboard/pcengines/apu1/mainboard.c @@ -158,6 +158,28 @@ static void config_gpio_mux(void) gpio->enabled = CONFIG_APU1_PINMUX_GPIO1; } +static void pnp_raw_resource(struct device *dev, u8 reg, u8 val) +{ + struct resource *res; + res = new_resource(dev, reg); + res->base = val; + res->size = 0; + res->flags |= IORESOURCE_IRQ | IORESOURCE_ASSIGNED; +} + +static void config_addon_uart(void) +{ + struct device *uart; + + uart = dev_find_slot_pnp(SIO_PORT, NCT5104D_SP3); + if (uart && uart->enabled && CONFIG_UART_C_RS485) + pnp_raw_resource(uart, 0xf2, 0x12); + + uart = dev_find_slot_pnp(SIO_PORT, NCT5104D_SP4); + if (uart && uart->enabled && CONFIG_UART_D_RS485) + pnp_raw_resource(uart, 0xf2, 0x12); +} + /** * TODO * SB CIMx callback @@ -182,6 +204,7 @@ static void mainboard_enable(device_t dev) printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); config_gpio_mux(); + config_addon_uart(); /* Power off unused clock pins of GPP PCIe devices */ u8 *misc_mem_clk_cntrl = (u8 *)(ACPI_MMIO_BASE + MISC_BASE);

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coreboot-gerrit May 2016