coreboot-gerrit May 2016

coreboot-gerrit@coreboot.org

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New patch to review for coreboot: mainboard/intel/galileo: Split out enabling FSP1_1
by Leroy P Leahy 31 May '16

31 May '16

Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15001 -gerrit commit 910f6b50fbbef080edcdff36b485e0317252e27f Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Sat May 28 14:58:57 2016 -0700 mainboard/intel/galileo: Split out enabling FSP1_1 Split out enabling FSP 1.1 support to prepare for enabling FSP 2.0 support. TEST=Build and run on Galileo Gen2. Change-Id: Ic4e814bcf61f9480f98e2d7bc7a1648dec43a07d Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/mainboard/intel/galileo/Kconfig | 9 ++++++++- src/mainboard/intel/galileo/Makefile.inc | 2 ++ 2 files changed, 10 insertions(+), 1 deletion(-) diff --git a/src/mainboard/intel/galileo/Kconfig b/src/mainboard/intel/galileo/Kconfig index 6381ae8..225e1c3 100644 --- a/src/mainboard/intel/galileo/Kconfig +++ b/src/mainboard/intel/galileo/Kconfig @@ -19,8 +19,8 @@ config BOARD_SPECIFIC_OPTIONS def_bool y select BOARD_ROMSIZE_KB_8192 select HAVE_ACPI_TABLES - select PLATFORM_USES_FSP1_1 select SOC_INTEL_QUARK + select USE_FSP1_1 config MAINBOARD_DIR string @@ -43,4 +43,11 @@ config GALILEO_GEN2 runtime. Select which generation of the Galileo that coreboot should initialize. +config USE_FSP1_1 + bool + default n + select ADD_FSP_PDAT_FILE + select ADD_FSP_RAW_BIN + select PLATFORM_USES_FSP1_1 + endif # BOARD_INTEL_QUARK diff --git a/src/mainboard/intel/galileo/Makefile.inc b/src/mainboard/intel/galileo/Makefile.inc index 4db9e31..72c74e1 100644 --- a/src/mainboard/intel/galileo/Makefile.inc +++ b/src/mainboard/intel/galileo/Makefile.inc @@ -13,7 +13,9 @@ ## GNU General Public License for more details. ## +ifeq ($(CONFIG_PLATFORM_USES_FSP1_1),y) CPPFLAGS_common += -I$(src)/vendorcode/intel/fsp/fsp1_1/quark +endif romstage-y += gpio.c

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Patch set updated for coreboot: soc/intel/quark: Fix reg_script display
by Leroy P Leahy 31 May '16

31 May '16

Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14948 -gerrit commit a223cbc2f929e9d8c55415dd6250bfef8bbfd755 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Sun May 22 16:24:36 2016 -0700 soc/intel/quark: Fix reg_script display Remove extra ": " following reigster type. TEST=Build and run on Galileo Gen2 Change-Id: I57dd40a540d7b5371a6c45174f47a311b83a2aab Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/soc/intel/quark/reg_access.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/src/soc/intel/quark/reg_access.c b/src/soc/intel/quark/reg_access.c index 30cc7db..1dd0d3c 100644 --- a/src/soc/intel/quark/reg_access.c +++ b/src/soc/intel/quark/reg_access.c @@ -216,21 +216,21 @@ static uint64_t reg_read(struct reg_script_context *ctx) return 0; case GPE0_REGS: - ctx->display_prefix = "GPE0: "; + ctx->display_prefix = "GPE0"; value = reg_gpe0_read(step->reg); break; case GPIO_REGS: - ctx->display_prefix = "GPIO: "; + ctx->display_prefix = "GPIO"; value = reg_gpio_read(step->reg); break; case LEG_GPIO_REGS: - ctx->display_prefix = "Legacy GPIO: "; + ctx->display_prefix = "Legacy GPIO"; value = reg_legacy_gpio_read(step->reg); case PCIE_AFE_REGS: - ctx->display_prefix = "PCIe AFE: "; + ctx->display_prefix = "PCIe AFE"; value = reg_pcie_afe_read(step->reg); break; @@ -265,28 +265,28 @@ static void reg_write(struct reg_script_context *ctx) return; case GPE0_REGS: - ctx->display_prefix = "GPE0: "; + ctx->display_prefix = "GPE0"; reg_gpe0_write(step->reg, (uint32_t)step->value); break; case GPIO_REGS: - ctx->display_prefix = "GPIO: "; + ctx->display_prefix = "GPIO"; reg_gpio_write(step->reg, (uint32_t)step->value); break; case LEG_GPIO_REGS: - ctx->display_prefix = "Legacy GPIO: "; + ctx->display_prefix = "Legacy GPIO"; reg_legacy_gpio_write(step->reg, (uint32_t)step->value); break; case PCIE_AFE_REGS: - ctx->display_prefix = "PCIe AFE: "; + ctx->display_prefix = "PCIe AFE"; reg_pcie_afe_write(step->reg, (uint32_t)step->value); break; case PCIE_RESET: if (ctx->display_features) { - ctx->display_prefix = "PCIe reset: "; + ctx->display_prefix = "PCIe reset"; ctx->display_features &= ~REG_SCRIPT_DISPLAY_REGISTER; } mainboard_gpio_pcie_reset(step->value);

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Patch set updated for coreboot: soc/intel/quark: Rename pmc.c to lpc.c
by Leroy P Leahy 31 May '16

31 May '16

Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14946 -gerrit commit 2d35659dfbe69262cd3bcc96552d353d5c558ec6 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Sun May 22 15:34:11 2016 -0700 soc/intel/quark: Rename pmc.c to lpc.c Rename the file pmc.c to lpc.c to prepare for further additions. TEST=Build and run on Galileo Gen2 Change-Id: If98825d72878f0601f77bff8c766276dbda8a9ae Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/soc/intel/quark/Makefile.inc | 2 +- src/soc/intel/quark/lpc.c | 51 ++++++++++++++++++++++++++++++++++++++++ src/soc/intel/quark/pmc.c | 51 ---------------------------------------- 3 files changed, 52 insertions(+), 52 deletions(-) diff --git a/src/soc/intel/quark/Makefile.inc b/src/soc/intel/quark/Makefile.inc index a6d03b1..08325e7 100644 --- a/src/soc/intel/quark/Makefile.inc +++ b/src/soc/intel/quark/Makefile.inc @@ -27,9 +27,9 @@ ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c ramstage-y += chip.c ramstage-y += ehci.c ramstage-y += gpio_i2c.c +ramstage-y += lpc.c ramstage-y += memmap.c ramstage-y += northcluster.c -ramstage-y += pmc.c ramstage-y += reg_access.c ramstage-y += tsc_freq.c ramstage-$(CONFIG_ENABLE_BUILTIN_HSUART1) += uart_common.c diff --git a/src/soc/intel/quark/lpc.c b/src/soc/intel/quark/lpc.c new file mode 100644 index 0000000..fbed935 --- /dev/null +++ b/src/soc/intel/quark/lpc.c @@ -0,0 +1,51 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Google Inc. + * Copyright (C) 2015-2016 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/pci.h> +#include <device/pci_ids.h> +#include <soc/iomap.h> +#include <soc/pci_devs.h> +#include <soc/pm.h> +#include <soc/ramstage.h> + +static void pmc_read_resources(device_t dev) +{ + unsigned index = 0; + struct resource *res; + + /* Get the normal PCI resources of this device. */ + pci_dev_read_resources(dev); + + /* PMBASE */ + res = new_resource(dev, index++); + res->base = ACPI_BASE_ADDRESS; + res->size = ACPI_BASE_SIZE; + res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; +} + +static struct device_operations device_ops = { + .read_resources = &pmc_read_resources, + .set_resources = &pci_dev_set_resources, + .enable_resources = &pci_dev_enable_resources, + .scan_bus = &scan_lpc_bus, +}; + +static const struct pci_driver pmc __pci_driver = { + .ops = &device_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = QUARK_V_LPC_DEVICE_ID_0, +}; diff --git a/src/soc/intel/quark/pmc.c b/src/soc/intel/quark/pmc.c deleted file mode 100644 index fbed935..0000000 --- a/src/soc/intel/quark/pmc.c +++ /dev/null @@ -1,51 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015-2016 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <device/pci.h> -#include <device/pci_ids.h> -#include <soc/iomap.h> -#include <soc/pci_devs.h> -#include <soc/pm.h> -#include <soc/ramstage.h> - -static void pmc_read_resources(device_t dev) -{ - unsigned index = 0; - struct resource *res; - - /* Get the normal PCI resources of this device. */ - pci_dev_read_resources(dev); - - /* PMBASE */ - res = new_resource(dev, index++); - res->base = ACPI_BASE_ADDRESS; - res->size = ACPI_BASE_SIZE; - res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; -} - -static struct device_operations device_ops = { - .read_resources = &pmc_read_resources, - .set_resources = &pci_dev_set_resources, - .enable_resources = &pci_dev_enable_resources, - .scan_bus = &scan_lpc_bus, -}; - -static const struct pci_driver pmc __pci_driver = { - .ops = &device_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = QUARK_V_LPC_DEVICE_ID_0, -};

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Patch set updated for coreboot: soc/intel/quark: Add PCIe reset support
by Leroy P Leahy 31 May '16

31 May '16

Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14944 -gerrit commit 35a042de0e4193116b67ad639f76b50b31021385 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Fri Apr 29 15:16:54 2016 -0700 soc/intel/quark: Add PCIe reset support Migrate PCIe reset from PlatformPciHelperLib in QuarkFspPkg into coreboot. Change-Id: I1c33fa16b0323091e8f9bd503bbfdb8a253a76d4 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/mainboard/intel/galileo/gen1.h | 3 + src/mainboard/intel/galileo/gen2.h | 3 + src/mainboard/intel/galileo/gpio.c | 17 +++++ src/soc/intel/quark/include/soc/pci_devs.h | 17 ++++- src/soc/intel/quark/include/soc/reg_access.h | 31 ++++++++ src/soc/intel/quark/include/soc/romstage.h | 1 + src/soc/intel/quark/reg_access.c | 38 +++++++++- src/soc/intel/quark/romstage/Makefile.inc | 1 + src/soc/intel/quark/romstage/pcie.c | 109 +++++++++++++++++++++++++++ src/soc/intel/quark/romstage/romstage.c | 3 + 10 files changed, 219 insertions(+), 4 deletions(-) diff --git a/src/mainboard/intel/galileo/gen1.h b/src/mainboard/intel/galileo/gen1.h index 26335da..e1e8f59 100644 --- a/src/mainboard/intel/galileo/gen1.h +++ b/src/mainboard/intel/galileo/gen1.h @@ -13,6 +13,9 @@ * GNU General Public License for more details. */ +/* PCIe reset pin */ +#define GEN1_PCI_RESET_RESUMEWELL_GPIO 3 + /* Jumper J2 determines the slave address of Cypress I/O GPIO expander */ #define GALILEO_DETERMINE_IOEXP_SLA_RESUMEWELL_GPIO 5 diff --git a/src/mainboard/intel/galileo/gen2.h b/src/mainboard/intel/galileo/gen2.h index 108971b..8eee744 100644 --- a/src/mainboard/intel/galileo/gen2.h +++ b/src/mainboard/intel/galileo/gen2.h @@ -13,6 +13,9 @@ * GNU General Public License for more details. */ +/* PCIe reset pin */ +#define GEN2_PCI_RESET_RESUMEWELL_GPIO 0 + static const struct reg_script gen2_gpio_init[] = { /* Initialize the legacy GPIO controller */ REG_LEG_GPIO_WRITE(R_QNC_GPIO_CGEN_CORE_WELL, 0x03), diff --git a/src/mainboard/intel/galileo/gpio.c b/src/mainboard/intel/galileo/gpio.c index a411c5a..0c26ec8 100644 --- a/src/mainboard/intel/galileo/gpio.c +++ b/src/mainboard/intel/galileo/gpio.c @@ -50,3 +50,20 @@ void mainboard_gpio_init(void) script = gen1_gpio_init; reg_script_run(script); } + +void mainboard_gpio_pcie_reset(uint32_t pin_value) +{ + uint32_t pin_number; + uint32_t value; + + /* Determine the correct PCIe reset pin */ + if (IS_ENABLED(CONFIG_GALILEO_GEN2)) + pin_number = GEN2_PCI_RESET_RESUMEWELL_GPIO; + else + pin_number = GEN1_PCI_RESET_RESUMEWELL_GPIO; + + /* Update the PCIe reset value */ + value = reg_legacy_gpio_read(R_QNC_GPIO_RGLVL_RESUME_WELL); + value = (value & ~(1 << pin_number)) | pin_value; + reg_legacy_gpio_write(R_QNC_GPIO_RGLVL_RESUME_WELL, value); +} diff --git a/src/soc/intel/quark/include/soc/pci_devs.h b/src/soc/intel/quark/include/soc/pci_devs.h index 67d8d32..ff9d65f 100644 --- a/src/soc/intel/quark/include/soc/pci_devs.h +++ b/src/soc/intel/quark/include/soc/pci_devs.h @@ -18,9 +18,8 @@ #ifndef _QUARK_PCI_DEVS_H_ #define _QUARK_PCI_DEVS_H_ -#include <arch/io.h> #include <device/pci.h> -#include <soc/QuarkNcSocId.h> +#include <soc/reg_access.h> /* DEVICE 0 (Memory Controller Hub) */ #define MC_BDF PCI_DEV(PCI_BUS_NUMBER_QNC, MC_DEV, MC_FUN) @@ -29,6 +28,8 @@ #define I2CGPIO_DEVID 0x0934 #define HSUART_DEVID 0x0936 #define EHCI_DEVID 0x0939 +#define PCIE_PORT0_DEVID 0x11c3 +#define PCIE_PORT1_DEVID 0x11c4 /* IO Fabric 1 */ #define SIO1_DEV 0x14 @@ -45,6 +46,18 @@ #define I2CGPIO_DEV_FUNC PCI_DEVFN(I2CGPIO_DEV, I2CGPIO_FUNC) #define I2CGPIO_BDF PCI_DEV(PCI_BUS_NUMBER_QNC, I2CGPIO_DEV, I2CGPIO_FUNC) +/* PCIe Ports */ +#define PCIE_DEV 0x17 +#define PCIE_PORT0_DEV PCIE_DEV +#define PCIE_PORT0_FUNC 0 +#define PCIE_PORT0_DEV_FUNC DEV_FUNC(PCIE_DEV, PCIE_PORT0_FUNC) +#define PCIE_PORT0_BDF PCI_DEV(PCI_BUS_NUMBER_QNC, PCIE_DEV, PCIE_PORT0_FUNC) + +#define PCIE_PORT1_DEV PCIE_DEV +#define PCIE_PORT1_FUNC 1 +#define PCIE_PORT1_DEV_FUNC DEV_FUNC(PCIE_DEV,PCIE_PORT1_FUNC) +#define PCIE_PORT1_BDF PCI_DEV(PCI_BUS_NUMBER_QNC, PCIE_DEV, PCIE_PORT1_FUNC) + /* Platform Controller Unit */ #define LPC_DEV PCI_DEVICE_NUMBER_QNC_LPC #define LPC_FUNC PCI_FUNCTION_NUMBER_QNC_LPC diff --git a/src/soc/intel/quark/include/soc/reg_access.h b/src/soc/intel/quark/include/soc/reg_access.h index 66ab7b8..580400c 100644 --- a/src/soc/intel/quark/include/soc/reg_access.h +++ b/src/soc/intel/quark/include/soc/reg_access.h @@ -16,6 +16,9 @@ #ifndef _QUARK_REG_ACCESS_H_ #define _QUARK_REG_ACCESS_H_ +#define __SIMPLE_DEVICE__ + +#include <arch/io.h> #include <delay.h> #include <fsp/util.h> #include <reg_script.h> @@ -30,6 +33,8 @@ enum { MICROSECOND_DELAY, LEG_GPIO_REGS, GPIO_REGS, + PCIE_AFE_REGS, + PCIE_RESET, }; enum { @@ -83,6 +88,31 @@ enum { #define REG_LEG_GPIO_XOR(reg_, value_) \ REG_LEG_GPIO_RXW(reg_, 0xffffffff, value_) +/* PCIE AFE register access macros */ +#define REG_PCIE_AFE_ACCESS(cmd_, reg_, mask_, value_, timeout_) \ + SOC_ACCESS(cmd_, reg_, REG_SCRIPT_SIZE_32, mask_, value_, timeout_, \ + PCIE_AFE_REGS) +#define REG_PCIE_AFE_READ(reg_) \ + REG_PCIE_AFE_ACCESS(READ, reg_, 0, 0, 0) +#define REG_PCIE_AFE_WRITE(reg_, value_) \ + REG_PCIE_AFE_ACCESS(WRITE, reg_, 0, value_, 0) +#define REG_PCIE_AFE_AND(reg_, value_) \ + REG_PCIE_AFE_RMW(reg_, value_, 0) +#define REG_PCIE_AFE_RMW(reg_, mask_, value_) \ + REG_PCIE_AFE_ACCESS(RMW, reg_, mask_, value_, 0) +#define REG_PCIE_AFE_RXW(reg_, mask_, value_) \ + REG_PCIE_AFE_ACCESS(RXW, reg_, mask_, value_, 0) +#define REG_PCIE_AFE_OR(reg_, value_) \ + REG_PCIE_AFE_RMW(reg_, 0xffffffff, value_) +#define REG_PCIE_AFE_POLL(reg_, mask_, value_, timeout_) \ + REG_PCIE_AFE_ACCESS(POLL, reg_, mask_, value_, timeout_) +#define REG_PCIE_AFE_XOR(reg_, value_) \ + REG_PCIE_AFE_RXW(reg_, 0xffffffff, value_) + +/* PCIe reset */ +#define MAINBOARD_PCIE_RESET(pin_value_) \ + SOC_ACCESS(WRITE, 0, REG_SCRIPT_SIZE_32, 1, pin_value_, 0, PCIE_RESET) + /* RMU temperature register access macros */ #define REG_RMU_TEMP_ACCESS(cmd_, reg_, mask_, value_, timeout_) \ SOC_ACCESS(cmd_, reg_, REG_SCRIPT_SIZE_32, mask_, value_, timeout_, \ @@ -152,6 +182,7 @@ enum { void *get_i2c_address(void); void mainboard_gpio_init(void); +void mainboard_gpio_pcie_reset(uint32_t pin_value); void mcr_write(uint8_t opcode, uint8_t port, uint32_t reg_address); uint32_t mdr_read(void); void mdr_write(uint32_t value); diff --git a/src/soc/intel/quark/include/soc/romstage.h b/src/soc/intel/quark/include/soc/romstage.h index c344ada..3a9e7a8 100644 --- a/src/soc/intel/quark/include/soc/romstage.h +++ b/src/soc/intel/quark/include/soc/romstage.h @@ -29,5 +29,6 @@ uint32_t port_reg_read(uint8_t port, uint32_t offset); void port_reg_write(uint8_t port, uint32_t offset, uint32_t value); void report_platform_info(void); int set_base_address_and_enable_uart(u8 bus, u8 dev, u8 func, u32 mmio_base); +void pcie_init(void); #endif /* _QUARK_ROMSTAGE_H_ */ diff --git a/src/soc/intel/quark/reg_access.c b/src/soc/intel/quark/reg_access.c index 4734135..f7820e9 100644 --- a/src/soc/intel/quark/reg_access.c +++ b/src/soc/intel/quark/reg_access.c @@ -15,10 +15,9 @@ #define __SIMPLE_DEVICE__ -#include <arch/io.h> #include <console/console.h> #include <soc/pci_devs.h> -#include <soc/reg_access.h> +#include <soc/ramstage.h> static uint32_t *get_gpio_address(uint32_t reg_address) { @@ -108,6 +107,24 @@ void reg_legacy_gpio_write(uint32_t reg_address, uint32_t value) outl(value, get_legacy_gpio_address(reg_address)); } +static uint32_t reg_pcie_afe_read(uint32_t reg_address) +{ + /* Read the PCIE AFE register */ + mea_write(reg_address); + mcr_write(QUARK_OPCODE_IO_READ, QUARK_SC_PCIE_AFE_SB_PORT_ID, + reg_address); + return mdr_read(); +} + +static void reg_pcie_afe_write(uint32_t reg_address, uint32_t value) +{ + /* Write the PCIE AFE register */ + mea_write(reg_address); + mdr_write(value); + mcr_write(QUARK_OPCODE_IO_WRITE, QUARK_SC_PCIE_AFE_SB_PORT_ID, + reg_address); +} + uint32_t reg_rmu_temp_read(uint32_t reg_address) { /* Read the RMU temperature register */ @@ -181,6 +198,10 @@ static uint64_t reg_read(struct reg_script_context *ctx) case LEG_GPIO_REGS: ctx->display_prefix = "Legacy GPIO: "; value = reg_legacy_gpio_read(step->reg); + + case PCIE_AFE_REGS: + ctx->display_prefix = "PCIe AFE: "; + value = reg_pcie_afe_read(step->reg); break; case RMU_TEMP_REGS: @@ -223,6 +244,19 @@ static void reg_write(struct reg_script_context *ctx) reg_legacy_gpio_write(step->reg, (uint32_t)step->value); break; + case PCIE_AFE_REGS: + ctx->display_prefix = "PCIe AFE: "; + reg_pcie_afe_write(step->reg, (uint32_t)step->value); + break; + + case PCIE_RESET: + if (ctx->display_features) { + ctx->display_prefix = "PCIe reset: "; + ctx->display_features &= ~REG_SCRIPT_DISPLAY_REGISTER; + } + mainboard_gpio_pcie_reset(step->value); + break; + case RMU_TEMP_REGS: ctx->display_prefix = "RMU TEMP"; reg_rmu_temp_write(step->reg, (uint32_t)step->value); diff --git a/src/soc/intel/quark/romstage/Makefile.inc b/src/soc/intel/quark/romstage/Makefile.inc index fc7bd6a..2f29b06 100644 --- a/src/soc/intel/quark/romstage/Makefile.inc +++ b/src/soc/intel/quark/romstage/Makefile.inc @@ -17,6 +17,7 @@ cpu_incs-y += $(src)/soc/intel/quark/romstage/esram_init.inc cpu_incs-y += $(src)/soc/intel/quark/romstage/cache_as_ram.inc romstage-y += mtrr.c +romstage-y += pcie.c romstage-y += report_platform.c romstage-y += romstage.c romstage-$(CONFIG_ENABLE_BUILTIN_HSUART1) += uart.c diff --git a/src/soc/intel/quark/romstage/pcie.c b/src/soc/intel/quark/romstage/pcie.c new file mode 100644 index 0000000..f2adc18 --- /dev/null +++ b/src/soc/intel/quark/romstage/pcie.c @@ -0,0 +1,109 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <delay.h> +#include <device/device.h> +#include <device/pci_ids.h> +#include <soc/pci_devs.h> +#include <soc/reg_access.h> +#include <soc/romstage.h> + +/* Minimum time in microseconds for assertion of PERST# signal */ +#define PCIEXP_PERST_MIN_ASSERT_US 100 + +/* Microsecond delay post issuing common lane reset */ +#define PCIEXP_DELAY_US_POST_CMNRESET_RESET 1 + +/* Microsecond delay to wait for PLL to lock */ +#define PCIEXP_DELAY_US_WAIT_PLL_LOCK 80 + +/* Microsecond delay post issuing sideband interface reset */ +#define PCIEXP_DELAY_US_POST_SBI_RESET 20 + +/* Microsecond delay post deasserting PERST# */ +#define PCIEXP_DELAY_US_POST_PERST_DEASSERT 10 + +const struct reg_script pcie_init_script[] = { + /* Assert PCIe reset# */ + MAINBOARD_PCIE_RESET(0), + + /* PHY Common lane reset */ + REG_SOC_UNIT_OR(QUARK_SCSS_SOC_UNIT_SOCCLKEN_CONFIG, + SOCCLKEN_CONFIG_PHY_I_CMNRESET_L), + + /* Wait post common lane reset */ + TIME_DELAY_USEC(PCIEXP_DELAY_US_POST_CMNRESET_RESET), + + /* PHY Sideband interface reset. + * Controller main reset + */ + REG_SOC_UNIT_OR(QUARK_SCSS_SOC_UNIT_SOCCLKEN_CONFIG, + SOCCLKEN_CONFIG_SBI_RST_100_CORE_B + | SOCCLKEN_CONFIG_PHY_I_SIDE_RST_L), + TIME_DELAY_USEC(PCIEXP_DELAY_US_WAIT_PLL_LOCK), + + /* Controller sideband interface reset */ + REG_SOC_UNIT_OR(QUARK_SCSS_SOC_UNIT_SOCCLKEN_CONFIG, + SOCCLKEN_CONFIG_SBI_BB_RST_B), + + /* Wait post sideband interface reset */ + TIME_DELAY_USEC(PCIEXP_DELAY_US_POST_SBI_RESET), + + /* Deassert PCIe reset# */ + MAINBOARD_PCIE_RESET(1), + + /* Wait post de assert PERST#. */ + TIME_DELAY_USEC(PCIEXP_DELAY_US_POST_PERST_DEASSERT), + + /* Controller primary interface reset */ + REG_SOC_UNIT_OR(QUARK_SCSS_SOC_UNIT_SOCCLKEN_CONFIG, + SOCCLKEN_CONFIG_BB_RST_B), + + /* Set the mixer load resistance */ + REG_PCIE_AFE_AND(QUARK_PCIE_AFE_PCIE_RXPICTRL0_L0, + OCFGPIMIXLOAD_1_0_MASK), + REG_PCIE_AFE_AND(QUARK_PCIE_AFE_PCIE_RXPICTRL0_L1, + OCFGPIMIXLOAD_1_0_MASK), + REG_SCRIPT_END +}; + +static const struct reg_script pcie_bus_init_script[] = { + /* Setup Message Bus Idle Counter (SBIC) values */ + REG_PCI_RMW8(R_QNC_PCIE_IOSFSBCTL, ~B_QNC_PCIE_IOSFSBCTL_SBIC_MASK, + V_PCIE_ROOT_PORT_SBIC_VALUE), + REG_PCI_READ8(R_QNC_PCIE_IOSFSBCTL), + + /* Set the IPF bit in MCR2 */ + REG_PCI_OR32(R_QNC_PCIE_MPC2, B_QNC_PCIE_MPC2_IPF), + REG_PCI_READ32(R_QNC_PCIE_MPC2), + + /* Set up the Posted and Non Posted Request sizes for PCIe */ + REG_PCI_RMW32(R_QNC_PCIE_CCFG, ~B_QNC_PCIE_CCFG_UPSD, + (B_QNC_PCIE_CCFG_UNRS | B_QNC_PCIE_CCFG_UPRS)), + REG_PCI_READ32(R_QNC_PCIE_CCFG), + REG_SCRIPT_END +}; + +void pcie_init(void) +{ + /* Initialize the PCIe bridges */ + printk(BIOS_DEBUG, "Initializing PCIe controllers\n"); + reg_script_run(pcie_init_script); + printk(BIOS_DEBUG, "Initializing PCIe bus 0\n"); + reg_script_run_on_dev(PCIE_PORT0_BDF, pcie_bus_init_script); + printk(BIOS_DEBUG, "Initializing PCIe bus 1\n"); + reg_script_run_on_dev(PCIE_PORT1_BDF, pcie_bus_init_script); +} diff --git a/src/soc/intel/quark/romstage/romstage.c b/src/soc/intel/quark/romstage/romstage.c index 2f16c5f..4ed5863 100644 --- a/src/soc/intel/quark/romstage/romstage.c +++ b/src/soc/intel/quark/romstage/romstage.c @@ -125,6 +125,9 @@ void soc_after_ram_init(struct romstage_params *params) /* Display the DRAM data */ hexdump((void *)0x000ffff0, 0x10); + + /* Initialize the PCIe bridges */ + pcie_init(); } void soc_display_memory_init_params(const MEMORY_INIT_UPD *old,

1 0

Patch set updated for coreboot: soc/intel/quark: Clear SMI interrupts and wake events
by Leroy P Leahy 31 May '16

31 May '16

Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14945 -gerrit commit 9b14de6046752f8e9cf73a2f416e15a1660c03b2 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Sun May 22 11:52:28 2016 -0700 soc/intel/quark: Clear SMI interrupts and wake events Migrate the clearing of the SMI interrupts and wake events from FSP into coreboot. TEST=Build and run on Galileo Gen2 Change-Id: Ia369801da87a16bc00fb2c05475831ebe8a315f8 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/soc/intel/quark/include/soc/iomap.h | 9 ++++--- src/soc/intel/quark/include/soc/reg_access.h | 22 +++++++++++++++++ src/soc/intel/quark/lpc.c | 18 +++++++++++--- src/soc/intel/quark/reg_access.c | 35 ++++++++++++++++++++++++++++ src/soc/intel/quark/romstage/romstage.c | 19 +++++++++++++++ 5 files changed, 97 insertions(+), 6 deletions(-) diff --git a/src/soc/intel/quark/include/soc/iomap.h b/src/soc/intel/quark/include/soc/iomap.h index ce92676..61773d5 100644 --- a/src/soc/intel/quark/include/soc/iomap.h +++ b/src/soc/intel/quark/include/soc/iomap.h @@ -30,10 +30,13 @@ /* * I/O port address space */ -#define ACPI_BASE_ADDRESS 0x1000 -#define ACPI_BASE_SIZE 0x100 +#define GPE0_BASE_ADDRESS 0x2000 +#define GPE0_SIZE 0x40 -#define LEGACY_GPIO_BASE_ADDRESS 0x1080 +#define PM1BLK_BASE_ADDRESS 0x2040 +#define PM1BLK_SIZE 0x10 + +#define LEGACY_GPIO_BASE_ADDRESS 0x2080 #define LEGACY_GPIO_SIZE 0x80 #define IO_ADDRESS_VALID 0x80000000 diff --git a/src/soc/intel/quark/include/soc/reg_access.h b/src/soc/intel/quark/include/soc/reg_access.h index 580400c..e7a8963 100644 --- a/src/soc/intel/quark/include/soc/reg_access.h +++ b/src/soc/intel/quark/include/soc/reg_access.h @@ -35,6 +35,7 @@ enum { GPIO_REGS, PCIE_AFE_REGS, PCIE_RESET, + GPE0_REGS, }; enum { @@ -46,6 +47,27 @@ enum { _REG_SCRIPT_ENCODE_RAW(REG_SCRIPT_COMMAND_##cmd_, SOC_TYPE, \ size_, reg_, mask_, value_, timeout_, reg_set_) +/* GPE0 controller register access macros */ +#define REG_GPE0_ACCESS(cmd_, reg_, mask_, value_, timeout_) \ + SOC_ACCESS(cmd_, reg_, REG_SCRIPT_SIZE_32, mask_, value_, timeout_, \ + GPE0_REGS) +#define REG_GPE0_READ(reg_) \ + REG_GPE0_ACCESS(READ, reg_, 0, 0, 0) +#define REG_GPE0_WRITE(reg_, value_) \ + REG_GPE0_ACCESS(WRITE, reg_, 0, value_, 0) +#define REG_GPE0_AND(reg_, value_) \ + REG_GPE0_RMW(reg_, value_, 0) +#define REG_GPE0_RMW(reg_, mask_, value_) \ + REG_GPE0_ACCESS(RMW, reg_, mask_, value_, 0) +#define REG_GPE0_RXW(reg_, mask_, value_) \ + REG_GPE0_ACCESS(RXW, reg_, mask_, value_, 0) +#define REG_GPE0_OR(reg_, value_) \ + REG_GPE0_RMW(reg_, 0xffffffff, value_) +#define REG_GPE0_POLL(reg_, mask_, value_, timeout_) \ + REG_GPE0_ACCESS(POLL, reg_, mask_, value_, timeout_) +#define REG_GPE0_XOR(reg_, value_) \ + REG_GPE0_RXW(reg_, 0xffffffff, value_) + /* GPIO controller register access macros */ #define REG_GPIO_ACCESS(cmd_, reg_, mask_, value_, timeout_) \ SOC_ACCESS(cmd_, reg_, REG_SCRIPT_SIZE_32, mask_, value_, timeout_, \ diff --git a/src/soc/intel/quark/lpc.c b/src/soc/intel/quark/lpc.c index fbed935..e57b717 100644 --- a/src/soc/intel/quark/lpc.c +++ b/src/soc/intel/quark/lpc.c @@ -30,10 +30,22 @@ static void pmc_read_resources(device_t dev) /* Get the normal PCI resources of this device. */ pci_dev_read_resources(dev); - /* PMBASE */ + /* GPE0 */ res = new_resource(dev, index++); - res->base = ACPI_BASE_ADDRESS; - res->size = ACPI_BASE_SIZE; + res->base = GPE0_BASE_ADDRESS; + res->size = GPE0_SIZE; + res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + + /* PM1BLK */ + res = new_resource(dev, index++); + res->base = PM1BLK_BASE_ADDRESS; + res->size = PM1BLK_SIZE; + res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + + /* Legacy GPIO */ + res = new_resource(dev, index++); + res->base = LEGACY_GPIO_BASE_ADDRESS; + res->size = LEGACY_GPIO_SIZE; res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } diff --git a/src/soc/intel/quark/reg_access.c b/src/soc/intel/quark/reg_access.c index f7820e9..30cc7db 100644 --- a/src/soc/intel/quark/reg_access.c +++ b/src/soc/intel/quark/reg_access.c @@ -19,6 +19,19 @@ #include <soc/pci_devs.h> #include <soc/ramstage.h> +static uint16_t get_gpe0_address(uint32_t reg_address) +{ + uint32_t gpe0_base_address; + + /* Get the GPE0 base address */ + gpe0_base_address = pci_read_config32(LPC_BDF, R_QNC_LPC_GPE0BLK); + ASSERT (gpe0_base_address >= 0x80000000); + gpe0_base_address &= B_QNC_LPC_GPE0BLK_MASK; + + /* Return the GPE0 register address */ + return (uint16_t)(gpe0_base_address + reg_address); +} + static uint32_t *get_gpio_address(uint32_t reg_address) { uint32_t gpio_base_address; @@ -83,6 +96,18 @@ void mea_write(uint32_t reg_address) & QNC_MEA_MASK); } +static uint32_t reg_gpe0_read(uint32_t reg_address) +{ + /* Read the GPE0 register */ + return inl(get_gpe0_address(reg_address)); +} + +static void reg_gpe0_write(uint32_t reg_address, uint32_t value) +{ + /* Write the GPE0 register */ + outl(get_gpe0_address(reg_address), value); +} + static uint32_t reg_gpio_read(uint32_t reg_address) { /* Read the GPIO register */ @@ -190,6 +215,11 @@ static uint64_t reg_read(struct reg_script_context *ctx) ctx->display_features = REG_SCRIPT_DISPLAY_NOTHING; return 0; + case GPE0_REGS: + ctx->display_prefix = "GPE0: "; + value = reg_gpe0_read(step->reg); + break; + case GPIO_REGS: ctx->display_prefix = "GPIO: "; value = reg_gpio_read(step->reg); @@ -234,6 +264,11 @@ static void reg_write(struct reg_script_context *ctx) ctx->display_features = REG_SCRIPT_DISPLAY_NOTHING; return; + case GPE0_REGS: + ctx->display_prefix = "GPE0: "; + reg_gpe0_write(step->reg, (uint32_t)step->value); + break; + case GPIO_REGS: ctx->display_prefix = "GPIO: "; reg_gpio_write(step->reg, (uint32_t)step->value); diff --git a/src/soc/intel/quark/romstage/romstage.c b/src/soc/intel/quark/romstage/romstage.c index 4ed5863..c4f9844 100644 --- a/src/soc/intel/quark/romstage/romstage.c +++ b/src/soc/intel/quark/romstage/romstage.c @@ -30,10 +30,22 @@ #include <soc/romstage.h> #include <soc/reg_access.h> +static const struct reg_script clear_smi_and_wake_events[] = { + /* Clear any SMI or wake events */ + REG_GPE0_READ(R_QNC_GPE0BLK_GPE0S), + REG_GPE0_READ(R_QNC_GPE0BLK_SMIS), + REG_GPE0_OR(R_QNC_GPE0BLK_GPE0S, B_QNC_GPE0BLK_GPE0S_ALL), + REG_GPE0_OR(R_QNC_GPE0BLK_SMIS, B_QNC_GPE0BLK_SMIS_ALL), + REG_SCRIPT_END +}; + static const struct reg_script legacy_gpio_init[] = { /* Temporarily enable the legacy GPIO controller */ REG_PCI_WRITE32(R_QNC_LPC_GBA_BASE, IO_ADDRESS_VALID | LEGACY_GPIO_BASE_ADDRESS), + /* Temporarily enable the GPE controller */ + REG_PCI_WRITE32(R_QNC_LPC_GPE0BLK, IO_ADDRESS_VALID + | GPE0_BASE_ADDRESS), REG_PCI_OR8(PCI_COMMAND, PCI_COMMAND_IO), REG_SCRIPT_END }; @@ -81,6 +93,7 @@ void soc_memory_init_params(struct romstage_params *params, char *pdat_file; size_t pdat_file_len; const struct soc_intel_quark_config *config; + struct chipset_power_state *ps = car_get_var_ptr(&power_state); /* Locate the pdat.bin file */ pdat_file = cbfs_boot_map_with_leak("pdat.bin", CBFS_TYPE_RAW, @@ -104,6 +117,12 @@ void soc_memory_init_params(struct romstage_params *params, /* Display the ROM shadow data */ hexdump((void *)0x000ffff0, 0x10); + + /* Clear SMI and wake events */ + if (ps->prev_sleep_state != 3) { + printk(BIOS_SPEW, "Clearing SMI interrupts and wake events\n"); + reg_script_run_on_dev(LPC_BDF, clear_smi_and_wake_events); + } } void soc_after_ram_init(struct romstage_params *params)

1 0

Patch set updated for coreboot: soc/intel/apollolake: add support for IFWI region
by Furquan Shaikh 31 May '16

31 May '16

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14999 -gerrit commit 05126ab00595ae60946a5d2a324702d77ac8b31a Author: Furquan Shaikh <furquan(a)google.com> Date: Sat May 28 12:57:05 2016 -0700 soc/intel/apollolake: add support for IFWI region On apollolake, the boot media layout is different in that the traditional "BIOS" region contains another data structure with the boot assets such as CSE firmware, PMC microcode, CPU microcode, and boot firmware to name a few. This region is referred to as the IFWI. Add support for writing the IFWI to a specified FMAP region to accommodate such platforms. Change-Id: Ia61f12a77893c3dd3256a9bd4e0f5eca0065de26 Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- src/soc/intel/apollolake/Kconfig | 21 +++++++++++++++++++++ src/soc/intel/apollolake/Makefile.inc | 5 +++++ 2 files changed, 26 insertions(+) diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index d6c5ffc..7c21ed2 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -160,4 +160,25 @@ config LBP2_FILE_NAME help Name of file to store in the logical boot partition 2 region. +config NEED_IFWI + bool "Write content into IFWI region" + default n + help + Write the content from a file into IFWI region defined by + IFWI_FMAP_NAME. + +config IFWI_FMAP_NAME + string "Name of FMAP region to pull IFWI into" + depends on NEED_IFWI + default "IFWI" + help + Name of FMAP region to write IFWI. + +config IFWI_FILE_NAME + string "Path of file to write to IFWI region" + depends on NEED_IFWI + default "3rdparty/blobs/mainboard/$(CONFIG_MAINBOARD_DIR)/ifwi.bin" + help + Name of file to store in the IFWI region. + endif diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index 1ea21f6..413b999 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -75,4 +75,9 @@ files_added:: $(CBFSTOOL) $(obj)/coreboot.rom write -r $(CONFIG_LBP2_FMAP_NAME) -f $(CONFIG_LBP2_FILE_NAME) --fill-upward endif +ifeq ($(CONFIG_NEED_IFWI),y) +files_added:: + $(CBFSTOOL) $(obj)/coreboot.rom write -r $(CONFIG_IFWI_FMAP_NAME) -f $(CONFIG_IFWI_FILE_NAME) --fill-upward +endif + endif

1 0

Patch set updated for coreboot: mainboard/google/reef: Add IFWI region to chromeos.fmd
by Furquan Shaikh 31 May '16

31 May '16

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15000 -gerrit commit 77d6e81f5d0d13c2cd7be4ec76b846278b4f4d38 Author: Furquan Shaikh <furquan(a)google.com> Date: Sun May 29 20:24:37 2016 -0700 mainboard/google/reef: Add IFWI region to chromeos.fmd IFWI region holds different components required for booting including CSE firmware, PMC firmware, CPU microcode as well as the bootblock. Add section for IFWI in chromeos.fmd Change-Id: Ic97980ff222ad7cbd7a2970417b79150256a7a16 Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- src/mainboard/google/reef/chromeos.fmd | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/google/reef/chromeos.fmd b/src/mainboard/google/reef/chromeos.fmd index 2a581be..be87cb4 100644 --- a/src/mainboard/google/reef/chromeos.fmd +++ b/src/mainboard/google/reef/chromeos.fmd @@ -1,7 +1,7 @@ FLASH 8M { WP_RO@0x0 0x400000 { SI_DESC@0x0 0x1000 - bootblock@0x7c480 0x8000 + IFWI@0x1000 0x1ff000 RO_SECTION@0x200000 0x200000 { RO_VPD@0x0 0x4000 FMAP@0x4000 0x800

1 0

Patch merged into coreboot/master: ifwitool: Add new tool for managing IFWI images
by gerrit＠coreboot.org 30 May '16

30 May '16

the following patch was just integrated into master: commit 233f1b6a386995038e3d6d72db80b4a325bbe39b Author: Furquan Shaikh <furquan(a)google.com> Date: Thu May 19 16:12:16 2016 -0700 ifwitool: Add new tool for managing IFWI images - Supports following operations: 1. add raw/dir sub-partition 2. extract raw/dir sub-partition 3. print info 4. delete raw sub-partition 5. replace raw/dir sub-partition Change-Id: I683a0ab13cc50eb60eecca34db4a8ffefc8dccbd Signed-off-by: Furquan Shaikh <furquan(a)google.com> Reviewed-on: https://review.coreboot.org/14896 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See https://review.coreboot.org/14896 for details. -gerrit

1 0

Patch merged into coreboot/master: reef: Remove si-all region from chromeos.fmd
by gerrit＠coreboot.org 30 May '16

30 May '16

the following patch was just integrated into master: commit 97d56fa1a2b2103ca6cf01cf45d0b9bf123cbef5 Author: Furquan Shaikh <furquan(a)google.com> Date: Fri May 27 16:43:26 2016 -0700 reef: Remove si-all region from chromeos.fmd This matches the change in depthcharge fmap.dts to remove si-all region and mark si-desc as ifd. CQ-DEPEND=CL:347986 BUG=chrome-os-partner:53689 BRANCH=None TEST=Compiles successfully Change-Id: Ic7ed94fcdfb9a79bd6ceb960830f67678b0291b6 Signed-off-by: Furquan Shaikh <furquan(a)google.com> Reviewed-on: https://review.coreboot.org/14990 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See https://review.coreboot.org/14990 for details. -gerrit

1 0

Patch set updated for coreboot: mainboard/asus/[kgpe-d16|kcma-d8]: Enable secondary serial port header
by Timothy Pearson 30 May '16

30 May '16

Timothy Pearson (tpearson(a)raptorengineering.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14892 -gerrit commit 8249d8120da668a962fb6542a8c58d566c7fd09e Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Wed May 18 13:33:13 2016 -0500 mainboard/asus/[kgpe-d16|kcma-d8]: Enable secondary serial port header The ASUS KGPE-D16/KCMA-D8 have an on-board header for a second RS-232 serial port, however it is disabled by default due to the SuperIO default pin mux settings. Enable the secondary serial port early in romstage to allow use during / after initial boot. Change-Id: I5b83659dd8b0d6af559c9ceccee55c4cc2f17165 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/mainboard/asus/kcma-d8/dsdt.asl | 24 ++++++++++++++++++++++++ src/mainboard/asus/kcma-d8/romstage.c | 8 ++++++-- src/mainboard/asus/kgpe-d16/dsdt.asl | 24 ++++++++++++++++++++++++ src/mainboard/asus/kgpe-d16/romstage.c | 8 ++++++-- 4 files changed, 60 insertions(+), 4 deletions(-) diff --git a/src/mainboard/asus/kcma-d8/dsdt.asl b/src/mainboard/asus/kcma-d8/dsdt.asl index ef87d31..d305af5 100644 --- a/src/mainboard/asus/kcma-d8/dsdt.asl +++ b/src/mainboard/asus/kcma-d8/dsdt.asl @@ -587,6 +587,30 @@ DefinitionBlock ( }) } } + + /* UART 2 */ + Device (URT2) + { + Name (_HID, EisaId ("PNP0501")) // "PNP0501" for UART + Name(_PRW, Package () {0x03, 0x04}) // Wake from S1-S4 + Method (_STA, 0, NotSerialized) + { + Return (0x0f) // Always enable + } + Name (_PRS, ResourceTemplate() { + StartDependentFn(0, 1) { + IO(Decode16, 0x2f8, 0x2f8, 0x8, 0x8) + IRQNoFlags() { 3 } + } EndDependentFn() + }) + Method (_CRS, 0) + { + Return(ResourceTemplate() { + IO(Decode16, 0x2f8, 0x2f8, 0x8, 0x8) + IRQNoFlags() { 3 } + }) + } + } } /* High Precision Event Timer */ diff --git a/src/mainboard/asus/kcma-d8/romstage.c b/src/mainboard/asus/kcma-d8/romstage.c index 9d1d95f..cf0ab39 100644 --- a/src/mainboard/asus/kcma-d8/romstage.c +++ b/src/mainboard/asus/kcma-d8/romstage.c @@ -46,7 +46,8 @@ #include "northbridge/amd/amdfam10/debug.c" #include "northbridge/amd/amdfam10/setup_resource_map.c" -#define SERIAL_DEV PNP_DEV(0x2e, W83667HG_A_SP1) +#define SERIAL_0_DEV PNP_DEV(0x2e, W83667HG_A_SP1) +#define SERIAL_1_DEV PNP_DEV(0x2e, W83667HG_A_SP2) static void activate_spd_rom(const struct mem_controller *ctrl); @@ -400,8 +401,11 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* Initialize southbridge */ sb7xx_51xx_pci_port80(); + /* Configure secondary serial port pin mux */ + winbond_set_pinmux(SERIAL_1_DEV, 0x2a, W83667HG_SPI_PINMUX_GPIO4_SERIAL_B_MASK, W83667HG_SPI_PINMUX_SERIAL_B); + /* Initialize early serial */ - winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + winbond_enable_serial(SERIAL_0_DEV, CONFIG_TTYS0_BASE); console_init(); /* Disable LPC legacy DMA support to prevent lockup */ diff --git a/src/mainboard/asus/kgpe-d16/dsdt.asl b/src/mainboard/asus/kgpe-d16/dsdt.asl index 5f9195a..d364f1f 100644 --- a/src/mainboard/asus/kgpe-d16/dsdt.asl +++ b/src/mainboard/asus/kgpe-d16/dsdt.asl @@ -587,6 +587,30 @@ DefinitionBlock ( }) } } + + /* UART 2 */ + Device (URT2) + { + Name (_HID, EisaId ("PNP0501")) // "PNP0501" for UART + Name(_PRW, Package () {0x03, 0x04}) // Wake from S1-S4 + Method (_STA, 0, NotSerialized) + { + Return (0x0f) // Always enable + } + Name (_PRS, ResourceTemplate() { + StartDependentFn(0, 1) { + IO(Decode16, 0x2f8, 0x2f8, 0x8, 0x8) + IRQNoFlags() { 3 } + } EndDependentFn() + }) + Method (_CRS, 0) + { + Return(ResourceTemplate() { + IO(Decode16, 0x2f8, 0x2f8, 0x8, 0x8) + IRQNoFlags() { 3 } + }) + } + } } /* High Precision Event Timer */ diff --git a/src/mainboard/asus/kgpe-d16/romstage.c b/src/mainboard/asus/kgpe-d16/romstage.c index 5a7400e..8825b23 100644 --- a/src/mainboard/asus/kgpe-d16/romstage.c +++ b/src/mainboard/asus/kgpe-d16/romstage.c @@ -46,7 +46,8 @@ #include "northbridge/amd/amdfam10/debug.c" #include "northbridge/amd/amdfam10/setup_resource_map.c" -#define SERIAL_DEV PNP_DEV(0x2e, W83667HG_A_SP1) +#define SERIAL_0_DEV PNP_DEV(0x2e, W83667HG_A_SP1) +#define SERIAL_1_DEV PNP_DEV(0x2e, W83667HG_A_SP2) static void activate_spd_rom(const struct mem_controller *ctrl); @@ -441,8 +442,11 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* Initialize southbridge */ sb7xx_51xx_pci_port80(); + /* Configure secondary serial port pin mux */ + winbond_set_pinmux(SERIAL_1_DEV, 0x2a, W83667HG_SPI_PINMUX_GPIO4_SERIAL_B_MASK, W83667HG_SPI_PINMUX_SERIAL_B); + /* Initialize early serial */ - winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + winbond_enable_serial(SERIAL_0_DEV, CONFIG_TTYS0_BASE); console_init(); /* Disable LPC legacy DMA support to prevent lockup */

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coreboot-gerrit May 2016