Duncan Laurie (dlaurie(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14995
-gerrit
commit e478b4d8840ab0c4e1df582c178bae977138303c
Author: Duncan Laurie <dlaurie(a)chromium.org>
Date: Tue May 10 15:56:16 2016 -0700
skylake: Add SD card device to configure card detect GPIO
Add a PCI driver for the skylake SD card device and have it generate
an entry in the SSDT for the card detect GPIO if it is provided by the
mainboard in devicetree.
This sets up a card detect GPIO configuration that will trigger an
interrupt on both edges with a 100ms debounce timeout and can wake the
SD controller from D3 state.
The GpioInt() entry is bound to the "cd-gpio" device property which will
be consumed by the kernel driver.
The resulting ACPI output in the SSDT will be combined with the SDXC
device declaration in the DSDT.
Example:
Scope (\_SB.PCI0.SDXC)
{
Name (_CRS, ResourceTemplate () {
GpioInt (Edge, ActiveBoth, SharedAndWake, PullNone, 10000,
"\\_SB.PCI0.GPIO", 0, ResourceConsumer) { 35 }
})
Name (_DSD, Package () {
ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
Package () {
Package () { "cd-gpio", Package () { \_SB.PCI0.SDXC, 0, 0, 1 } }
}
})
}
Change-Id: Ie4c1bfadd962cf55a987edb9ef86e92174205770
Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org>
---
src/soc/intel/skylake/Makefile.inc | 1 +
src/soc/intel/skylake/chip.h | 18 ++++++++
src/soc/intel/skylake/sd.c | 87 ++++++++++++++++++++++++++++++++++++++
3 files changed, 106 insertions(+)
diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc
index e22214f..ea1895d 100644
--- a/src/soc/intel/skylake/Makefile.inc
+++ b/src/soc/intel/skylake/Makefile.inc
@@ -53,6 +53,7 @@ ramstage-y += pei_data.c
ramstage-y += pmc.c
ramstage-y += pmutil.c
ramstage-y += ramstage.c
+ramstage-y += sd.c
ramstage-y += smbus.c
ramstage-y += smbus_common.c
ramstage-y += smi.c
diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h
index 8910479..2db84b7 100644
--- a/src/soc/intel/skylake/chip.h
+++ b/src/soc/intel/skylake/chip.h
@@ -19,6 +19,7 @@
#ifndef _SOC_CHIP_H_
#define _SOC_CHIP_H_
+#include <arch/acpi_device.h>
#include <stdint.h>
#include <soc/gpio_defs.h>
#include <soc/gpe.h>
@@ -339,6 +340,23 @@ struct soc_intel_skylake_config {
u8 SendVrMbxCmd;
/* Statically clock gate 8254 PIT. */
u8 clock_gate_8254;
+
+ /*
+ * Use SD card detect GPIO with default config:
+ * - Edge triggered
+ * - No internal pull
+ * - Active both (high + low)
+ * - Can wake device from D3
+ * - 100ms debounce timeout
+ *
+ * GpioInt (Edge, ActiveBoth, SharedAndWake, PullNone, 10000,
+ * "\\_SB.PCI0.GPIO", 0, ResourceConsumer)
+ * { sdcard_cd_gpio_default }
+ */
+ unsigned sdcard_cd_gpio_default;
+
+ /* Use custom SD card detect GPIO configuration */
+ struct acpi_gpio sdcard_cd_gpio;
};
typedef struct soc_intel_skylake_config config_t;
diff --git a/src/soc/intel/skylake/sd.c b/src/soc/intel/skylake/sd.c
new file mode 100644
index 0000000..bab6279
--- /dev/null
+++ b/src/soc/intel/skylake/sd.c
@@ -0,0 +1,87 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2016 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/acpi_device.h>
+#include <arch/acpigen.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <gpio.h>
+#include <soc/ramstage.h>
+#include "chip.h"
+
+#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES)
+static void sd_fill_ssdt(struct device *dev)
+{
+ config_t *config = dev->chip_info;
+ const char *path;
+ struct acpi_gpio default_gpio = {
+ .type = ACPI_GPIO_TYPE_INTERRUPT,
+ .pull = ACPI_GPIO_PULL_NONE,
+ .irq.mode = IRQ_EDGE_TRIGGERED,
+ .irq.polarity = IRQ_ACTIVE_BOTH,
+ .irq.shared = IRQ_SHARED,
+ .irq.wake = IRQ_WAKE,
+ .interrupt_debounce_timeout = 10000, /* 100ms */
+ .pin_count = 1,
+ .pins = { config->sdcard_cd_gpio_default }
+ };
+
+ if (!dev->enabled)
+ return;
+
+ /* Nothing to write if GPIO is not set in devicetree */
+ if (!config->sdcard_cd_gpio_default && !config->sdcard_cd_gpio.pins[0])
+ return;
+
+ /* Use device path as the Scope for the SSDT */
+ path = acpi_device_path(dev);
+ if (!path)
+ return;
+ acpigen_write_scope(path);
+ acpigen_write_name("_CRS");
+
+ /* Write GpioInt() as default (if set) or custom from devicetree */
+ acpigen_write_resourcetemplate_header();
+ if (config->sdcard_cd_gpio_default)
+ acpi_device_write_gpio(&default_gpio);
+ else
+ acpi_device_write_gpio(&config->sdcard_cd_gpio);
+ acpigen_write_resourcetemplate_footer();
+
+ /* Bind the cd-gpio name to the GpioInt() resource */
+ acpi_dp_write_header();
+ acpi_dp_write_gpio("cd-gpio", path, 0, 0, 1);
+ acpi_dp_write_footer();
+
+ acpigen_pop_len();
+}
+#endif
+
+static struct device_operations dev_ops = {
+ .read_resources = &pci_dev_read_resources,
+ .set_resources = &pci_dev_set_resources,
+ .enable_resources = &pci_dev_enable_resources,
+ .ops_pci = &soc_pci_ops,
+#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES)
+ .acpi_fill_ssdt_generator = &sd_fill_ssdt,
+#endif
+};
+
+static const struct pci_driver pch_sd __pci_driver = {
+ .ops = &dev_ops,
+ .vendor = PCI_VENDOR_ID_INTEL,
+ .device = 0x9d2d
+};
Duncan Laurie (dlaurie(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14993
-gerrit
commit 7f6676642a08542bd248e1d3b412862dba20115b
Author: Duncan Laurie <dlaurie(a)chromium.org>
Date: Tue May 10 15:42:42 2016 -0700
skylake: Add Audio DSP device
Add the Audio DSP device for skylake as a PCI driver with a static
scan_bus handler so generic devices can be declared under it.
This is for devices like the Maxim 98357A which is connected on the
I2S bus for data but has no control channel bus and instead just has
a GPIO for channel selection and power down control and needs to
describe that GPIO connection to the OS via ACPI.
Change-Id: Iae02132ff9c510562483108ab280323f78873afd
Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org>
---
src/soc/intel/skylake/Makefile.inc | 1 +
src/soc/intel/skylake/dsp.c | 33 ++++++++++++++++++++++++++++
src/soc/intel/skylake/include/soc/pci_devs.h | 4 ++++
3 files changed, 38 insertions(+)
diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc
index f835282..e22214f 100644
--- a/src/soc/intel/skylake/Makefile.inc
+++ b/src/soc/intel/skylake/Makefile.inc
@@ -34,6 +34,7 @@ ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c
ramstage-y += chip.c
ramstage-y += cpu.c
ramstage-y += cpu_info.c
+ramstage-y += dsp.c
ramstage-y += elog.c
ramstage-y += finalize.c
ramstage-y += flash_controller.c
diff --git a/src/soc/intel/skylake/dsp.c b/src/soc/intel/skylake/dsp.c
new file mode 100644
index 0000000..13051a0
--- /dev/null
+++ b/src/soc/intel/skylake/dsp.c
@@ -0,0 +1,33 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2016 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <soc/ramstage.h>
+
+static struct device_operations dsp_dev_ops = {
+ .read_resources = &pci_dev_read_resources,
+ .set_resources = &pci_dev_set_resources,
+ .enable_resources = &pci_dev_enable_resources,
+ .scan_bus = &scan_static_bus,
+ .ops_pci = &soc_pci_ops,
+};
+
+static const struct pci_driver skylake_dsp __pci_driver = {
+ .ops = &dsp_dev_ops,
+ .vendor = PCI_VENDOR_ID_INTEL,
+ .device = 0x9d70
+};
diff --git a/src/soc/intel/skylake/include/soc/pci_devs.h b/src/soc/intel/skylake/include/soc/pci_devs.h
index 2dba3de..53dddcb 100644
--- a/src/soc/intel/skylake/include/soc/pci_devs.h
+++ b/src/soc/intel/skylake/include/soc/pci_devs.h
@@ -43,6 +43,10 @@
#define SA_DEVFN_IGD _SA_DEVFN(IGD)
#define SA_DEV_IGD _SA_DEV(IGD)
+#define SA_DEV_SLOT_DSP 0x04
+#define SA_DEVFN_DSP _SA_DEVFN(DSP)
+#define SA_DEV_DSP _SA_DEV(DSP)
+
/* PCH Devices */
#define PCH_DEV_SLOT_ISH 0x13
#define PCH_DEVFN_ISH _PCH_DEVFN(ISH, 0)
Duncan Laurie (dlaurie(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14992
-gerrit
commit 0c63d093e6440ddb19abf4ac104169c1d46bf60c
Author: Duncan Laurie <dlaurie(a)chromium.org>
Date: Tue May 10 15:31:22 2016 -0700
skylake: Add I2C devices
Add the I2C devices to skylake with the scan_bus handler for SMBUS
devices so that I2C-based devices can be declared in devicetree.cb
and get initialized properly during ramstage.
This does not yet provide the I2C driver, but it allows for devices
that are declared in devicetree.cb to provide ACPI tables to the OS.
Change-Id: I9dfe4a06a8b0bc549a2b0e2d7c033c895188ba30
Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org>
---
src/soc/intel/skylake/Makefile.inc | 1 +
src/soc/intel/skylake/i2c.c | 37 +++++++++++++++++++++++++++++++++++++
2 files changed, 38 insertions(+)
diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc
index a4dd057..f835282 100644
--- a/src/soc/intel/skylake/Makefile.inc
+++ b/src/soc/intel/skylake/Makefile.inc
@@ -39,6 +39,7 @@ ramstage-y += finalize.c
ramstage-y += flash_controller.c
ramstage-$(CONFIG_VBOOT_VERIFY_FIRMWARE) += fsp_reset.c
ramstage-y += gpio.c
+ramstage-y += i2c.c
ramstage-y += igd.c
ramstage-y += lpc.c
ramstage-y += me_status.c
diff --git a/src/soc/intel/skylake/i2c.c b/src/soc/intel/skylake/i2c.c
new file mode 100644
index 0000000..76e7bf1
--- /dev/null
+++ b/src/soc/intel/skylake/i2c.c
@@ -0,0 +1,37 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2016 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <soc/ramstage.h>
+
+static struct device_operations i2c_dev_ops = {
+ .read_resources = &pci_dev_read_resources,
+ .set_resources = &pci_dev_set_resources,
+ .enable_resources = &pci_dev_enable_resources,
+ .scan_bus = &scan_smbus,
+ .ops_pci = &soc_pci_ops,
+};
+
+static const unsigned short pci_device_ids[] = {
+ 0x9d60, 0x9d61, 0x9d62, 0x9d63, 0x9d64, 0x9d65, 0
+};
+
+static const struct pci_driver pch_i2c __pci_driver = {
+ .ops = &i2c_dev_ops,
+ .vendor = PCI_VENDOR_ID_INTEL,
+ .devices = pci_device_ids,
+};
Duncan Laurie (dlaurie(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14991
-gerrit
commit 17a2f39e648e7c62eee2ea54b267878d676118bc
Author: Duncan Laurie <dlaurie(a)chromium.org>
Date: Wed May 11 15:08:50 2016 -0700
skylake: Add GPE header file to chip.h
Add the GPE header file to skylake chip.h so the SOC-defined macros
for the various GPE values can be used in devicetree directly.
For example:
chip drivers/i2c/touchpad
register "wake" = "GPE0_DW0_05"
device i2c 15.0 on end
end
Change-Id: Ic322108561b34aa34a24a4daba6ba7a4f7a3f9a4
Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org>
---
src/soc/intel/skylake/chip.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h
index 857d8a1..8910479 100644
--- a/src/soc/intel/skylake/chip.h
+++ b/src/soc/intel/skylake/chip.h
@@ -21,6 +21,7 @@
#include <stdint.h>
#include <soc/gpio_defs.h>
+#include <soc/gpe.h>
#include <soc/pci_devs.h>
#include <soc/pmc.h>
#include <soc/serialio.h>
the following patch was just integrated into master:
commit 161d2334e863b26fc893c6bbf8f8cb8b811ce586
Author: Furquan Shaikh <furquan(a)google.com>
Date: Thu May 26 14:41:02 2016 -0700
util/cbfstool: Include commonlib/helpers.h in common.h
This avoids re-declaring common macros like ARRAY_SIZE, MIN, MAX and
ALIGN. Also removes the issues around including both files in any
tool.
Also, fix comparison error in various files by replacing int with
size_t.
Change-Id: I06c763e5dd1bec97e8335499468bbdb016eb28e5
Signed-off-by: Furquan Shaikh <furquan(a)google.com>
Reviewed-on: https://review.coreboot.org/14978
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
See https://review.coreboot.org/14978 for details.
-gerrit