coreboot-gerrit May 2016

coreboot-gerrit@coreboot.org

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1843 discussions

Patch merged into coreboot/master: mainboard/google/reef: support verstage
by gerrit＠coreboot.org 27 May '16

27 May '16

the following patch was just integrated into master: commit 7a3edb6f279f26e7a64c604b90adf38a78d6cb03 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu May 26 11:02:56 2016 -0500 mainboard/google/reef: support verstage The chromeos.c suport needs to be linked into verstage so it will link. Change-Id: If85e232a3721443edfbbd278b32f72302f13f3a8 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://review.coreboot.org/14973 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan(a)google.com> See https://review.coreboot.org/14973 for details. -gerrit

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Patch merged into coreboot/master: soc/intel/apollolake: add support for verstage
by gerrit＠coreboot.org 27 May '16

27 May '16

the following patch was just integrated into master: commit bef75e7dd9450679d1605df8326a4dfbf2800ff9 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu May 26 11:00:44 2016 -0500 soc/intel/apollolake: add support for verstage There previously was no support for building verstage on apollolake. Add that suport by linking in the appropriate modules as well as providing vboot_platform_is_resuming(). The link address for verstage is the same as FSP-M because they would never be in CAR along side each other. Additionally, program the ACPI I/O BAR and enable decoding so sleep state can be determined for early firmware verification. Change-Id: I1a0baab342ac55fd82dbed476abe0063787e3491 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://review.coreboot.org/14972 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan(a)google.com> See https://review.coreboot.org/14972 for details. -gerrit

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Patch merged into coreboot/master: arch/x86: provide verstage support for CONFIG_C_ENVIRONMENT_BOOTBLOCK
by gerrit＠coreboot.org 27 May '16

27 May '16

the following patch was just integrated into master: commit 10221a0e570717760087163b075f7f535f882b61 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu May 26 10:55:48 2016 -0500 arch/x86: provide verstage support for CONFIG_C_ENVIRONMENT_BOOTBLOCK When CONFIG_C_ENVIRONMENT_BOOTBLOCK is employed there's no need for a chipset specific verstage entry point because cache-as-ram has already been initialized. Therefore, provide a default entry point for verstage in that environment. Change-Id: Idd8f45bd58d3e5b251d1e38cca7ae794b8b77a28 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://review.coreboot.org/14971 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan(a)google.com> Reviewed-by: Andrey Petrov <andrey.petrov(a)intel.com> See https://review.coreboot.org/14971 for details. -gerrit

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New patch to review for coreboot: pcengines/apu1: Rename Kconfig variables for pinmux
by Kyösti Mälkki 27 May '16

27 May '16

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14988 -gerrit commit 4a8f05a5624df5b25165c433c2c8502f8f45f441 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Fri May 27 13:07:50 2016 +0300 pcengines/apu1: Rename Kconfig variables for pinmux Add APU1 prefix because Kconfig throws errors if we try to define the same variables as choice-entry for APU2 board. Change-Id: Ic071600dd88e391a8a278d63aad13abd01fd3c9d Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/mainboard/pcengines/apu1/Kconfig | 16 ++++++++-------- src/mainboard/pcengines/apu1/mainboard.c | 8 ++++---- 2 files changed, 12 insertions(+), 12 deletions(-) diff --git a/src/mainboard/pcengines/apu1/Kconfig b/src/mainboard/pcengines/apu1/Kconfig index 2328776..e9aab8c 100644 --- a/src/mainboard/pcengines/apu1/Kconfig +++ b/src/mainboard/pcengines/apu1/Kconfig @@ -82,30 +82,30 @@ config DRIVERS_PS2_KEYBOARD choice prompt "J19 pins 1-10" - default PINMUX_OFF_C + default APU1_PINMUX_OFF_C -config PINMUX_OFF_C +config APU1_PINMUX_OFF_C bool "disable" -config PINMUX_GPIO0 +config APU1_PINMUX_GPIO0 bool "GPIO" -config PINMUX_UART_C +config APU1_PINMUX_UART_C bool "UART 0x3e8" endchoice choice prompt "J19 pins 11-20" - default PINMUX_OFF_D + default APU1_PINMUX_OFF_D -config PINMUX_OFF_D +config APU1_PINMUX_OFF_D bool "disable" -config PINMUX_GPIO1 +config APU1_PINMUX_GPIO1 bool "GPIO" -config PINMUX_UART_D +config APU1_PINMUX_UART_D bool "UART 0x2e8" endchoice diff --git a/src/mainboard/pcengines/apu1/mainboard.c b/src/mainboard/pcengines/apu1/mainboard.c index f11d94b..2ebdc75 100644 --- a/src/mainboard/pcengines/apu1/mainboard.c +++ b/src/mainboard/pcengines/apu1/mainboard.c @@ -146,16 +146,16 @@ static void config_gpio_mux(void) uart = dev_find_slot_pnp(SIO_PORT, NCT5104D_SP3); gpio = dev_find_slot_pnp(SIO_PORT, NCT5104D_GPIO0); if (uart) - uart->enabled = CONFIG_PINMUX_UART_C; + uart->enabled = CONFIG_APU1_PINMUX_UART_C; if (gpio) - gpio->enabled = CONFIG_PINMUX_GPIO0; + gpio->enabled = CONFIG_APU1_PINMUX_GPIO0; uart = dev_find_slot_pnp(SIO_PORT, NCT5104D_SP4); gpio = dev_find_slot_pnp(SIO_PORT, NCT5104D_GPIO1); if (uart) - uart->enabled = CONFIG_PINMUX_UART_D; + uart->enabled = CONFIG_APU1_PINMUX_UART_D; if (gpio) - gpio->enabled = CONFIG_PINMUX_GPIO1; + gpio->enabled = CONFIG_APU1_PINMUX_GPIO1; } /**

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Patch set updated for coreboot: xcompile: rename riscv to riscv64
by Iru Cai 27 May '16

27 May '16

Iru Cai (mytbk920423(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14257 -gerrit commit 6a60a257041ecd5130bc83c40b65f375a3b69c1b Author: Iru Cai <mytbk920423(a)gmail.com> Date: Tue Apr 5 23:43:59 2016 +0800 xcompile: rename riscv to riscv64 In newer toolchain with binutils 2.26 and GCC 5.3.0, we build binutils and GCC with machine type riscv32 and riscv64 instead of riscv. We can see it in this riscv-gnu-toolchain commit: https://github.com/riscv/riscv-gnu-toolchain/commit/dedbf07 Signed-off-by: Iru Cai <mytbk920423(a)gmail.com> Change-Id: Id552859ec256d80108e073d25cd51dd1fc3fbfac --- util/xcompile/xcompile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/util/xcompile/xcompile b/util/xcompile/xcompile index 13a0e8f..84306f7 100755 --- a/util/xcompile/xcompile +++ b/util/xcompile/xcompile @@ -332,7 +332,7 @@ arch_config_arm64() { arch_config_riscv() { TARCH="riscv" TBFDARCHS="littleriscv" - TCLIST="riscv" + TCLIST="riscv64" TWIDTH="64" TABI="elf" }

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Patch set updated for coreboot: util/riscvtools: Add script that turns coreboot.rom into an ELF
by Jonathan Neuschäfer 27 May '16

27 May '16

Jonathan Neuschäfer (j.neuschaefer(a)gmx.net) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14964 -gerrit commit 695976f3eabd000b68f5b2cb045bbfa38d7db9f3 Author: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Date: Fri May 27 09:05:03 2016 +0200 util/riscvtools: Add script that turns coreboot.rom into an ELF This is required because the current version of SPIKE doesn't support loading flat files yet. Change-Id: If745d78712ca8108b5dcc21591201bc2d3f70b86 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> --- util/riscvtools/make-spike-elf.sh | 27 +++++++++++++++++++++++++++ util/riscvtools/spike-elf.ld | 11 +++++++++++ 2 files changed, 38 insertions(+) diff --git a/util/riscvtools/make-spike-elf.sh b/util/riscvtools/make-spike-elf.sh new file mode 100755 index 0000000..4241c54 --- /dev/null +++ b/util/riscvtools/make-spike-elf.sh @@ -0,0 +1,27 @@ +#!/bin/sh +# +# This script is based on: +# https://docs.google.com/document/d/1Pvf9Yxorcd3sbgs8WcomcTl3J4bmX6e1UE0ROCe… + +set -e + +usage() { + echo "This script converts a flat file into an ELF, that can be passed" + echo "to SPIKE, the RISC-V reference emulator." + echo "" + echo "Usage: $0 coreboot.rom coreboot.elf" +} + +if [ $# -ne 2 ]; then + usage + exit 1 +fi + +FLAT_FILE="$1" +OBJECT_FILE=$(mktemp /tmp/coreboot-spike.XXXXXX.o) +ELF_FILE="$2" +TOOL_PATH="$(dirname "$0")" + +objcopy -I binary -O elf32-i386 --binary-architecture i386 "$FLAT_FILE" "$OBJECT_FILE" +ld -m elf_i386 "$OBJECT_FILE" -T "$TOOL_PATH/spike-elf.ld" -o "$ELF_FILE" +rm "$OBJECT_FILE" diff --git a/util/riscvtools/spike-elf.ld b/util/riscvtools/spike-elf.ld new file mode 100644 index 0000000..c103136 --- /dev/null +++ b/util/riscvtools/spike-elf.ld @@ -0,0 +1,11 @@ +/* See make-spike-elf.sh */ + +ENTRY(_start); +SECTIONS +{ + _start = 0x0000; + . = 0x0000; + .data : { + *(.data) + } +}

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Patch set updated for coreboot: [DO NOT MERGE] Add new RISC-V HTIF console driver
by Jonathan Neuschäfer 27 May '16

27 May '16

Jonathan Neuschäfer (j.neuschaefer(a)gmx.net) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14982 -gerrit commit 369a9244b74bb876ce737019ece9a9c7fb5694c6 Author: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Date: Fri May 27 09:05:02 2016 +0200 [DO NOT MERGE] Add new RISC-V HTIF console driver The HTIF is already deprecated and has been removed in newer versions of Spike. In the older Spike 3bfc00ef this driver works. Maybe src/drivers/emulation/riscv would be a better place. Change-Id: I8b25829e8cc17ec9604c6e1391a2f96eefe71d07 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> --- src/drivers/uart/Kconfig | 9 ++++++ src/drivers/uart/Makefile.inc | 7 ++++ src/drivers/uart/htif.c | 75 +++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 91 insertions(+) diff --git a/src/drivers/uart/Kconfig b/src/drivers/uart/Kconfig index 4faa48d..12514b9 100644 --- a/src/drivers/uart/Kconfig +++ b/src/drivers/uart/Kconfig @@ -73,3 +73,12 @@ config UART_PCI_ADDR * Bus << 20 * Device << 15 * Function << 12 + +config DRIVERS_UART_HTIF + bool "RISC-V HTIF console" + default n + depends on ARCH_RISCV + help + Support for the console part of the RISC-V Host-Target Interface. + + Currently, only output is implemented. diff --git a/src/drivers/uart/Makefile.inc b/src/drivers/uart/Makefile.inc index 4b2aa53..232e80a 100644 --- a/src/drivers/uart/Makefile.inc +++ b/src/drivers/uart/Makefile.inc @@ -36,4 +36,11 @@ romstage-y += pl011.c ramstage-y += pl011.c endif +ifeq ($(CONFIG_DRIVERS_UART_HTIF),y) +bootblock-y += htif.c +verstage-y += htif.c +romstage-y += htif.c +ramstage-y += htif.c +endif + endif diff --git a/src/drivers/uart/htif.c b/src/drivers/uart/htif.c new file mode 100644 index 0000000..7533981 --- /dev/null +++ b/src/drivers/uart/htif.c @@ -0,0 +1,75 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/encoding.h> +#include <arch/io.h> +#include <boot/coreboot_tables.h> +#include <console/uart.h> +#include <delay.h> +#include <device/device.h> +#include <rules.h> +#include <spike_util.h> +#include <stdint.h> + +/* Driver for console output over RISC-V's Host-Target Interface (HTIF) */ + +uintptr_t uart_platform_base(int idx) +{ + if (idx == 0) + return CSR_MTOHOST; + return 0; +} + +void uart_init(int idx) +{ +} + +void uart_tx_byte(int idx, unsigned char data) +{ + if (idx != 0) + return; + + /* Device 1: console; command 1: write */ + write_csr(mtohost, TOHOST_CMD(1, 1, data)); + + /* Read from mfromhost to avoid some kind of race condition when + * characters are printed to fast */ + read_csr(mfromhost); +} + +unsigned char uart_rx_byte(int idx) +{ + // not yet implemented + return 0; +} + +void uart_tx_flush(int idx) +{ +} + +#if ENV_RAMSTAGE +void uart_fill_lb(void *data) +{ + /* bogus: */ + struct lb_serial serial; + serial.type = LB_SERIAL_TYPE_IO_MAPPED; + serial.baseaddr = uart_platform_base(CONFIG_UART_FOR_CONSOLE); + serial.baud = default_baudrate(); + serial.regwidth = sizeof(uint8_t); + lb_add_serial(&serial, data); + + lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data); +} +#endif

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Patch set updated for coreboot: lib/hardwaremain: Add \n to "Boot failed" message
by Jonathan Neuschäfer 27 May '16

27 May '16

Jonathan Neuschäfer (j.neuschaefer(a)gmx.net) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14984 -gerrit commit a6e9e23ba631b70501fad33e7edc3204c7e704e9 Author: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Date: Fri May 27 09:05:02 2016 +0200 lib/hardwaremain: Add \n to "Boot failed" message Change-Id: I106fccd725a5c944f4e8e0f196b31c9344f588c7 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> --- src/lib/hardwaremain.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/lib/hardwaremain.c b/src/lib/hardwaremain.c index 10ef96c..ab4d9f4 100644 --- a/src/lib/hardwaremain.c +++ b/src/lib/hardwaremain.c @@ -227,7 +227,7 @@ static boot_state_t bs_payload_boot(void *arg) { payload_run(); - printk(BIOS_EMERG, "Boot failed"); + printk(BIOS_EMERG, "Boot failed\n"); /* Returning from this state will fail because the following signals * return to a completed state. */ return BS_PAYLOAD_BOOT;

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New patch to review for coreboot: [ASL]: Add asl code to enable google ChromeEC.
by Shaunak Saha 27 May '16

27 May '16

Shaunak Saha (shaunak.saha(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14987 -gerrit commit 13febc2d8cee395759c1be5793b1756218e137be Author: Shaunak Saha <shaunak.saha(a)intel.com> Date: Fri May 27 01:13:16 2016 -0700 [ASL]: Add asl code to enable google ChromeEC. This patch adds asl code to include support for Google ChromeEC. We need this to show the battery icon and notifications like charger connect/disconnect etc. BUG = SYSCROS-13310 TEST = Plug/Unplug AC Adapter multiple times and make sure the battery connected is charging properly. Change-Id: Id908f145789402573ea54fc4f15cf7a0e651ebf4 Signed-off-by: Shaunak Saha <shaunak.saha(a)intel.com> --- src/mainboard/intel/amenia/acpi/ec.asl | 26 ++++++++++++++++++++++++++ src/mainboard/intel/amenia/acpi/mainboard.asl | 26 ++++++++++++++++++++++++++ src/mainboard/intel/amenia/dsdt.asl | 11 +++++++++++ src/mainboard/intel/amenia/ec.h | 4 ++++ 4 files changed, 67 insertions(+) diff --git a/src/mainboard/intel/amenia/acpi/ec.asl b/src/mainboard/intel/amenia/acpi/ec.asl new file mode 100644 index 0000000..fe53cb5 --- /dev/null +++ b/src/mainboard/intel/amenia/acpi/ec.asl @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* mainboard configuration */ +#include "../ec.h" + +/* Enable EC backed ALS device in ACPI */ +#define EC_ENABLE_ALS_DEVICE + +/* Enable EC backed PD MCU device in ACPI */ +#define EC_ENABLE_PD_MCU_DEVICE + +/* ACPI code for EC functions */ +#include <ec/google/chromeec/acpi/ec.asl> diff --git a/src/mainboard/intel/amenia/acpi/mainboard.asl b/src/mainboard/intel/amenia/acpi/mainboard.asl index 09ef9b4..e3f7776 100644 --- a/src/mainboard/intel/amenia/acpi/mainboard.asl +++ b/src/mainboard/intel/amenia/acpi/mainboard.asl @@ -16,6 +16,24 @@ */ #include <soc/gpio_defs.h> +Scope (\_SB) +{ + Device (LID0) + { + Name (_HID, EisaId ("PNP0C0D")) + Method (_LID, 0) + { + Return (\_SB.PCI0.LPCB.EC0.LIDS) + } + + } + + Device (PWRB) + { + Name (_HID, EisaId ("PNP0C0C")) + } +} + Scope (\_SB.PCI0.I2C4) { /* Standard Mode: HCNT, LCNT, SDA Hold Register */ @@ -91,3 +109,11 @@ Scope (\_SB.PCI0.I2C3) } } } + +/* + * LPC Trusted Platform Module + */ +Scope (\_SB.PCI0.LPCB) +{ + #include <drivers/pc80/tpm/acpi/tpm.asl> +} diff --git a/src/mainboard/intel/amenia/dsdt.asl b/src/mainboard/intel/amenia/dsdt.asl index 19e7360..6b4df8f 100644 --- a/src/mainboard/intel/amenia/dsdt.asl +++ b/src/mainboard/intel/amenia/dsdt.asl @@ -24,6 +24,12 @@ DefinitionBlock( 0x20110725 // OEM revision ) { + // global NVS and variables + #include <soc/intel/apollolake/acpi/globalnvs.asl> + + // CPU + #include <soc/intel/apollolake/acpi/cpu.asl> + Scope (\_SB) { Device (PCI0) { @@ -39,4 +45,9 @@ DefinitionBlock( #include "acpi/superio.asl" + // TODO: This actually should be called from soc specific directory + // e.g. in skylake it was included in lpc.asl. But right now we cannot do it + // as other boards lile reef does not have ec.asl in mainboard yet. + // Move it to soc's asl code onve all the mainboards have ec.asl + #include "acpi/ec.asl" } diff --git a/src/mainboard/intel/amenia/ec.h b/src/mainboard/intel/amenia/ec.h index ab8bcba..91890fd 100644 --- a/src/mainboard/intel/amenia/ec.h +++ b/src/mainboard/intel/amenia/ec.h @@ -20,6 +20,10 @@ #include <ec/google/chromeec/ec_commands.h> +/* This is the GPE status bit. + TODO: Fix this to proper bit matching GPE routing table */ +#define EC_SCI_GPI 15 + #define MAINBOARD_EC_SCI_EVENTS \ (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED) |\ EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\

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Patch set updated for coreboot: arch/riscv/trap_util.S: Use "li" pseudo-instruction to load a constant
by Jonathan Neuschäfer 27 May '16

27 May '16

Jonathan Neuschäfer (j.neuschaefer(a)gmx.net) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14962 -gerrit commit bf26d1a6f50803b1547178edb3b129946f11c812 Author: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Date: Fri May 27 09:05:03 2016 +0200 arch/riscv/trap_util.S: Use "li" pseudo-instruction to load a constant Change-Id: I9759771fa6fc708d7d97509c5f5e0cefb8ab4c96 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> --- src/arch/riscv/trap_util.S | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/arch/riscv/trap_util.S b/src/arch/riscv/trap_util.S index bc09dc9..0118ffc 100644 --- a/src/arch/riscv/trap_util.S +++ b/src/arch/riscv/trap_util.S @@ -108,7 +108,7 @@ supervisor_trap_entry: csrw mscratch, sp # load in the top of the machine stack - la sp, 0x80FFF0 - 64 + li sp, 0x80FFF0 - 64 1:addi sp,sp,-320 save_tf move a0,sp

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coreboot-gerrit May 2016