the following patch was just integrated into master:
commit 6b7c1f605c67f18996c584970a83fc5296c94747
Author: Duncan Laurie <dlaurie(a)chromium.org>
Date: Mon May 9 15:38:36 2016 -0700
acpi_device: Add support for writing ACPI Interrupt descriptors
Add definitions for ACPI device extended interrupts and a method to
write an Interrupt() descriptor to the SSDT output stream.
Interrupts are often tied together with other resources and some
configuration items are shared (though not always compatibly) with
other constructs like GPIOs and GPEs.
These will get used by device drivers to write _CRS sections for
devices into the SSDT. One usage is to include a "struct acpi_irq"
inside a config struct for a device so it can be initialized based
on settings in devicetree.
Example usage:
chip.h:
struct drivers_i2c_generic_config {
struct acpi_irq irq;
};
generic.c:
void acpi_fill_ssdt_generator(struct device *dev) {
struct drivers_i2c_generic_config *config = dev->chip_info;
...
acpi_device_write_interrupt(&config->irq);
...
}
devicetree.cb:
device pci 15.0 on
chip drivers/i2c/generic
register "irq" = "IRQ_EDGE_LOW(GPP_E7_IRQ)"
device i2c 10 on end
end
end
SSDT.dsl:
Interrupt (ResourceConsumer, Edge, ActiveLow, Exclusive,,,) { 31 }
Change-Id: I3b64170cc2ebac178e7a17df479eda7670a42703
Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org>
Reviewed-on: https://review.coreboot.org/14933
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
See https://review.coreboot.org/14933 for details.
-gerrit
Shaunak Saha (shaunak.saha(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14987
-gerrit
commit 58f331329f950efa870ac0ef5417a0642ec9d4d7
Author: Shaunak Saha <shaunak.saha(a)intel.com>
Date: Fri May 27 01:13:16 2016 -0700
[intel/amenia]: Add asl code to enable google ChromeEC
This patch adds asl code to include support for Google ChromeEC.
We need this to show the battery icon and notifications like charger
connect/disconnect etc.
BUG = 53096
TEST = Plug/Unplug AC Adapter multiple times and make sure the battery
connected is charging properly.
Change-Id: Id908f145789402573ea54fc4f15cf7a0e651ebf4
Signed-off-by: Shaunak Saha <shaunak.saha(a)intel.com>
---
src/mainboard/intel/amenia/acpi/ec.asl | 26 ++++++++++++++++++++++++++
src/mainboard/intel/amenia/acpi/mainboard.asl | 26 ++++++++++++++++++++++++++
src/mainboard/intel/amenia/dsdt.asl | 7 ++++++-
src/mainboard/intel/amenia/ec.h | 4 ++++
4 files changed, 62 insertions(+), 1 deletion(-)
diff --git a/src/mainboard/intel/amenia/acpi/ec.asl b/src/mainboard/intel/amenia/acpi/ec.asl
new file mode 100644
index 0000000..fe53cb5
--- /dev/null
+++ b/src/mainboard/intel/amenia/acpi/ec.asl
@@ -0,0 +1,26 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/* mainboard configuration */
+#include "../ec.h"
+
+/* Enable EC backed ALS device in ACPI */
+#define EC_ENABLE_ALS_DEVICE
+
+/* Enable EC backed PD MCU device in ACPI */
+#define EC_ENABLE_PD_MCU_DEVICE
+
+/* ACPI code for EC functions */
+#include <ec/google/chromeec/acpi/ec.asl>
diff --git a/src/mainboard/intel/amenia/acpi/mainboard.asl b/src/mainboard/intel/amenia/acpi/mainboard.asl
index 09ef9b4..c83f48f 100644
--- a/src/mainboard/intel/amenia/acpi/mainboard.asl
+++ b/src/mainboard/intel/amenia/acpi/mainboard.asl
@@ -16,6 +16,23 @@
*/
#include <soc/gpio_defs.h>
+Scope (\_SB)
+{
+ Device (LID0)
+ {
+ Name (_HID, EisaId ("PNP0C0D"))
+ Method (_LID, 0)
+ {
+ Return (\_SB.PCI0.LPCB.EC0.LIDS)
+ }
+ }
+
+ Device (PWRB)
+ {
+ Name (_HID, EisaId ("PNP0C0C"))
+ }
+}
+
Scope (\_SB.PCI0.I2C4)
{
/* Standard Mode: HCNT, LCNT, SDA Hold Register */
@@ -91,3 +108,12 @@ Scope (\_SB.PCI0.I2C3)
}
}
}
+
+/*
+ * LPC Trusted Platform Module
+ */
+Scope (\_SB.PCI0.LPCB)
+{
+ #include <drivers/pc80/tpm/acpi/tpm.asl>
+ #include "ec.asl"
+}
diff --git a/src/mainboard/intel/amenia/dsdt.asl b/src/mainboard/intel/amenia/dsdt.asl
index 19e7360..4a64f87 100644
--- a/src/mainboard/intel/amenia/dsdt.asl
+++ b/src/mainboard/intel/amenia/dsdt.asl
@@ -24,6 +24,12 @@ DefinitionBlock(
0x20110725 // OEM revision
)
{
+ /* global NVS and variables */
+ #include <soc/intel/apollolake/acpi/globalnvs.asl>
+
+ /* CPU */
+ #include <soc/intel/apollolake/acpi/cpu.asl>
+
Scope (\_SB) {
Device (PCI0)
{
@@ -38,5 +44,4 @@ DefinitionBlock(
#include <soc/intel/apollolake/acpi/sleepstates.asl>
#include "acpi/superio.asl"
-
}
diff --git a/src/mainboard/intel/amenia/ec.h b/src/mainboard/intel/amenia/ec.h
index ab8bcba..91890fd 100644
--- a/src/mainboard/intel/amenia/ec.h
+++ b/src/mainboard/intel/amenia/ec.h
@@ -20,6 +20,10 @@
#include <ec/google/chromeec/ec_commands.h>
+/* This is the GPE status bit.
+ TODO: Fix this to proper bit matching GPE routing table */
+#define EC_SCI_GPI 15
+
#define MAINBOARD_EC_SCI_EVENTS \
(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED) |\
EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\
the following patch was just integrated into master:
commit b3f5418ec16b1c0cdc913d0afd49bde94c26728e
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Thu May 26 14:22:34 2016 -0500
soc/intel/apollolake: provide SMM dependency requirements
Depending on which options are selected there needs to be certain
functions supplied. However, the spi, mmap_boot, and tsc_freq modules
were not included in the SMM builds. Fix the omission.
Change-Id: I25ab42886cfd46770ce0f4beee65f2f4d15649f3
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-on: https://review.coreboot.org/14977
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan(a)google.com>
See https://review.coreboot.org/14977 for details.
-gerrit
the following patch was just integrated into master:
commit 07dd474d658545b6b284195e7a003c6fe8ca8c44
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Thu May 26 12:01:19 2016 -0500
mainboard/google/reef: increase BIOS region size
An updated descriptor expands the BIOS region while descreasing
the 'device expansion region' utilized by the CSE. Update the
end region marker to reflect this new size as well as the
chromeos.fmd file which needs to be adjusted for logical boot
parition 2 requirement which resides halfway through the BIOS
region. The GBB was moved and shunk to accommodate the change.
Change-Id: I7baa5282d7c608af648b5773c4dfa123060a6e45
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-on: https://review.coreboot.org/14974
Reviewed-by: Furquan Shaikh <furquan(a)google.com>
Tested-by: build bot (Jenkins)
See https://review.coreboot.org/14974 for details.
-gerrit