coreboot-gerrit May 2016

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Patch set updated for coreboot: soc/intel/apollolake: add support for IFWI region
by Furquan Shaikh 31 May '16

31 May '16

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14999 -gerrit commit 3bfb0c5abfcdbb3f95587471fe29191d9288d8b0 Author: Furquan Shaikh <furquan(a)google.com> Date: Sat May 28 12:57:05 2016 -0700 soc/intel/apollolake: add support for IFWI region On apollolake, the boot media layout is different in that the traditional "BIOS" region contains another data structure with the boot assets such as CSE firmware, PMC microcode, CPU microcode, and boot firmware to name a few. This region is referred to as the IFWI. Add support for writing the IFWI to a specified FMAP region to accommodate such platforms. Change-Id: Ia61f12a77893c3dd3256a9bd4e0f5eca0065de26 Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- src/soc/intel/apollolake/Kconfig | 21 +++++++++++++++++++++ src/soc/intel/apollolake/Makefile.inc | 15 +++++++++++++++ 2 files changed, 36 insertions(+) diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index d6c5ffc..7c21ed2 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -160,4 +160,25 @@ config LBP2_FILE_NAME help Name of file to store in the logical boot partition 2 region. +config NEED_IFWI + bool "Write content into IFWI region" + default n + help + Write the content from a file into IFWI region defined by + IFWI_FMAP_NAME. + +config IFWI_FMAP_NAME + string "Name of FMAP region to pull IFWI into" + depends on NEED_IFWI + default "IFWI" + help + Name of FMAP region to write IFWI. + +config IFWI_FILE_NAME + string "Path of file to write to IFWI region" + depends on NEED_IFWI + default "3rdparty/blobs/mainboard/$(CONFIG_MAINBOARD_DIR)/ifwi.bin" + help + Name of file to store in the IFWI region. + endif diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index 1ea21f6..275c97c 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -75,4 +75,19 @@ files_added:: $(CBFSTOOL) $(obj)/coreboot.rom write -r $(CONFIG_LBP2_FMAP_NAME) -f $(CONFIG_LBP2_FILE_NAME) --fill-upward endif +# Bootblock on Apollolake platform lies in the IFWI region. In order to place +# the bootblock at the right location in IFWI image: +# 1. We need to copy the sample ifwi image (CONFIG_IFWI_FILE_NAME) to a +# temporary file (ifwi.bin.tmp). +# 2. Replace the IBBL directory entry in sub-partition IBBP in the ifwi.bin.tmp +# file with currently generated bootblock.bin using ifwitool. +# 3. Use cbfstool to write ifwi.bin.tmp to coreboot.rom using +# CONFIG_IFWI_FMAP_NAME. +ifeq ($(CONFIG_NEED_IFWI),y) +files_added:: $(IFWITOOL) + cp $(CONFIG_IFWI_FILE_NAME) $(objcbfs)/ifwi.bin.tmp + $(IFWITOOL) $(objcbfs)/ifwi.bin.tmp replace -n IBBP -f $(objcbfs)/bootblock.bin -d -e IBBL + $(CBFSTOOL) $(obj)/coreboot.rom write -r $(CONFIG_IFWI_FMAP_NAME) -f $(objcbfs)/ifwi.bin.tmp --fill-upward +endif + endif

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Patch set updated for coreboot: mainboard/google/reef: Add IFWI region to chromeos.fmd
by Furquan Shaikh 31 May '16

31 May '16

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15000 -gerrit commit 1c7705983e17451fba850ee3e357c07fb7010f97 Author: Furquan Shaikh <furquan(a)google.com> Date: Sun May 29 20:24:37 2016 -0700 mainboard/google/reef: Add IFWI region to chromeos.fmd IFWI region holds different components required for booting including CSE firmware, PMC firmware, CPU microcode as well as the bootblock. Add section for IFWI in chromeos.fmd Change-Id: Ic97980ff222ad7cbd7a2970417b79150256a7a16 Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- src/mainboard/google/reef/chromeos.fmd | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/google/reef/chromeos.fmd b/src/mainboard/google/reef/chromeos.fmd index 2a581be..be87cb4 100644 --- a/src/mainboard/google/reef/chromeos.fmd +++ b/src/mainboard/google/reef/chromeos.fmd @@ -1,7 +1,7 @@ FLASH 8M { WP_RO@0x0 0x400000 { SI_DESC@0x0 0x1000 - bootblock@0x7c480 0x8000 + IFWI@0x1000 0x1ff000 RO_SECTION@0x200000 0x200000 { RO_VPD@0x0 0x4000 FMAP@0x4000 0x800

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Patch set updated for coreboot: Fix leaking CONFIG_VGA=y
by Kyösti Mälkki 31 May '16

31 May '16

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14823 -gerrit commit 5c9245d5123af9d8f32b593d9ad7fb789838c9f3 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Mon May 16 14:49:57 2016 +0300 Fix leaking CONFIG_VGA=y Items under DEVICE_SPECIFIC_OPTIONS got selected without the driver being selected. Change-Id: I1797fa6175620a9291873559a6308eaea85a090e Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/drivers/aspeed/ast2050/Kconfig | 5 +---- src/drivers/aspeed/common/Kconfig | 7 ------- src/drivers/xgi/common/Kconfig | 7 ------- src/drivers/xgi/z9s/Kconfig | 5 +---- src/northbridge/intel/sandybridge/Kconfig | 1 + 5 files changed, 3 insertions(+), 22 deletions(-) diff --git a/src/drivers/aspeed/ast2050/Kconfig b/src/drivers/aspeed/ast2050/Kconfig index f110d58..088d258 100644 --- a/src/drivers/aspeed/ast2050/Kconfig +++ b/src/drivers/aspeed/ast2050/Kconfig @@ -1,12 +1,9 @@ config DRIVERS_ASPEED_AST2050 bool + select DRIVERS_ASPEED_AST_COMMON if DRIVERS_ASPEED_AST2050 -config DEVICE_SPECIFIC_OPTIONS # dummy - def_bool y - select DRIVERS_ASPEED_AST_COMMON - config NATIVE_VGA_INIT_USE_EDID bool default n diff --git a/src/drivers/aspeed/common/Kconfig b/src/drivers/aspeed/common/Kconfig index 0f7056b..653782f 100644 --- a/src/drivers/aspeed/common/Kconfig +++ b/src/drivers/aspeed/common/Kconfig @@ -1,10 +1,3 @@ config DRIVERS_ASPEED_AST_COMMON bool - -if !MAINBOARD_DO_NATIVE_VGA_INIT - -config DEVICE_SPECIFIC_OPTIONS # dummy - def_bool y select VGA - -endif # MAINBOARD_DO_NATIVE_VGA_INIT diff --git a/src/drivers/xgi/common/Kconfig b/src/drivers/xgi/common/Kconfig index e0ed9d6..a0b6fed 100644 --- a/src/drivers/xgi/common/Kconfig +++ b/src/drivers/xgi/common/Kconfig @@ -1,10 +1,3 @@ config DRIVERS_XGI_Z79_COMMON bool - -if !MAINBOARD_DO_NATIVE_VGA_INIT - -config DEVICE_SPECIFIC_OPTIONS # dummy - def_bool y select VGA - -endif # MAINBOARD_DO_NATIVE_VGA_INIT diff --git a/src/drivers/xgi/z9s/Kconfig b/src/drivers/xgi/z9s/Kconfig index bae03d7..66cd566 100644 --- a/src/drivers/xgi/z9s/Kconfig +++ b/src/drivers/xgi/z9s/Kconfig @@ -1,12 +1,9 @@ config DRIVERS_XGI_Z9S bool + select DRIVERS_XGI_Z79_COMMON if DRIVERS_XGI_Z9S -config DEVICE_SPECIFIC_OPTIONS # dummy - def_bool y - select DRIVERS_XGI_Z79_COMMON - config NATIVE_VGA_INIT_USE_EDID bool default n diff --git a/src/northbridge/intel/sandybridge/Kconfig b/src/northbridge/intel/sandybridge/Kconfig index 64f4a14..0cfdf2b 100644 --- a/src/northbridge/intel/sandybridge/Kconfig +++ b/src/northbridge/intel/sandybridge/Kconfig @@ -55,6 +55,7 @@ config CACHE_MRC_SIZE_KB config SANDYBRIDGE_IVYBRIDGE_LVDS def_bool n + select VGA select MAINBOARD_HAS_NATIVE_VGA_INIT select MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG

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Patch set updated for coreboot: Add Board Checklist Support
by Leroy P Leahy 31 May '16

31 May '16

Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15011 -gerrit commit 70064a5c6a94687b33d6af0ea82cac86939d54ca Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Thu May 26 17:12:17 2016 -0700 Add Board Checklist Support Build the <board>_checklist.html file which contains a checklist table for each stage of coreboot. This processing builds a set of implemented (done) routines which are marked green in the table. The remaining required routines (work-to-do) are marked red in the table and the optional routines are marked yellow in the table. The table heading for each stage contains a completion percentage in terms of count of routines (done .vs. required). Add some Kconfig values: * CREATE_BOARD_CHECKLIST - When selected creates the checklist file * MAKE_CHECKLIST_PUBLIC - Copies the checklist file into the Documenation directory * CHECKLIST_DATA_FILE_LOCATION - Location of the checklist data files: * <stage>_complete.dat - Lists all of the weak routines * <stage>_optional.dat - Lists weak routines which may be optionally implemented * <stage>_exclude.dat - Lists the weak functions that should be ignored during the checklist processing TEST=Build with Galileo Gen2. Change-Id: Ie056f8bb6d45ff7f3bc6390b5630b5063f54c527 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- Makefile.inc | 131 +++++++++++++++++++++ src/Kconfig | 8 ++ src/drivers/intel/fsp1_1/Kconfig | 4 + .../fsp/fsp1_1/checklist/ramstage_complete.dat | 17 +++ .../fsp/fsp1_1/checklist/ramstage_exclude.dat | 1 + .../fsp/fsp1_1/checklist/ramstage_optional.dat | 8 ++ .../fsp/fsp1_1/checklist/romstage_complete.dat | 13 ++ .../fsp/fsp1_1/checklist/romstage_exclude.dat | 1 + .../fsp/fsp1_1/checklist/romstage_optional.dat | 10 ++ .../fsp/fsp1_1/checklist/verstage_complete.dat | 10 ++ .../fsp/fsp1_1/checklist/verstage_exclude.dat | 1 + .../fsp/fsp1_1/checklist/verstage_optional.dat | 11 ++ 12 files changed, 215 insertions(+) diff --git a/Makefile.inc b/Makefile.inc index 574f2fe..e2163b2 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -559,6 +559,137 @@ $(objcbfs)/%.elf: $(objcbfs)/%.debug mv $@.tmp $@ ########################################################################### +# Build the board implementation checklist +########################################################################### + +%.weak: %.elf + nm $< | fgrep " W " | sed -r 's/^.{11}//' > $@.tmp + comm -23 $@.tmp $(CONFIG_CHECKLIST_DATA_FILE_LOCATION)/$(basename $(*F))_exclude.dat > $@ + rm $@.tmp + +%.total: %.weak + cp $(CONFIG_CHECKLIST_DATA_FILE_LOCATION)/$(basename $(*F))_complete.dat $@.tmp + # If no separate verstage, combine verstage and romstage routines into a single list + if [ ! -e $(*D)/verstage.elf ]; \ + then \ + echo $(*F); \ + if [ "$(*F)" = "romstage" ]; \ + then \ + sort --merge $(CONFIG_CHECKLIST_DATA_FILE_LOCATION)/verstage_complete.dat $@.tmp > $@.tmp2; \ + sort -u $@.tmp2 > $@.tmp; \ + rm $@.tmp2; \ + fi; \ + fi + comm -23 $@.tmp $(CONFIG_CHECKLIST_DATA_FILE_LOCATION)/$(basename $(*F))_exclude.dat > $@ + rm $@.tmp + +%.done: %.total %.weak + comm -23 $^ | sed "s/^[ \t]*//" > $@.tmp + comm -2 $@.tmp $(CONFIG_CHECKLIST_DATA_FILE_LOCATION)/$(basename $(*F))_optional.dat | sed "s/^[ \t]*//" > $@ + rm $@.tmp + +%.optional: %.done + comm -23 $(CONFIG_CHECKLIST_DATA_FILE_LOCATION)/$(basename $(*F))_optional.dat $< | sed "s/^[ \t]*//" > $@ + +%.weak2: %.weak %.optional + comm -23 $< $(CONFIG_CHECKLIST_DATA_FILE_LOCATION)/$(basename $(*F))_optional.dat | sed "s/^[ \t]*//" > $@ + +# Count the lines in the done file +done_lines = $$(wc -l $(*D)/$(basename $(*F)).done | sed 's/ .*//') + +# Count the lines in the optional file +optional_lines = $$(wc -l $(*D)/$(basename $(*F)).optional | sed 's/ .*//') + +# Count the lines in the total file +total_lines = $$(wc -l $(*D)/$(basename $(*F)).total | sed 's/ .*//') + +# Compute the percentage done by routine count +percent_complete = $$(($(done_lines) * 100 / ($(total_lines) - $(optional_lines)))) + +# Build the implementation table for each stage +%.html: %.optional %.done %.total %.weak2 + # + # Done table rows are in green + # + sed -e 's/^/<tr bgcolor=#c0ffc0><td>Required<\/td><td>/' $(*D)/$(basename $(*F)).done > $@.tmp + # + # Optional table rows are in yellow + # + sed -e 's/^/<tr bgcolor=#ffffc0><td>Optional<\/td><td>/' $(*D)/$(basename $(*F)).optional >> $@.tmp + # + # Weak table rows are in red + # + if [ -s $(*D)/$(basename $(*F)).weak2 ]; \ + then \ + sed -e 's/^/<tr bgcolor=#ffc0c0><td>Required<\/td><td>/' $(*D)/$(basename $(*F)).weak2 >> $@.tmp; \ + fi + # + # Add the table row termination + # + sed -e 's/$$/<\/td><\/tr>/' -i $@.tmp + # + # Sort the table into alphabetical order + # + sort -t ">" -k4 $@.tmp > $@.tmp2 + # + # Build the table + # + echo "<table border=1>" > $@ + echo "<tr><th colspan=2>$(basename $(*F)): $(percent_complete)% Done</th></tr>" >> $@ + echo "<tr><th>Type</th><th>Routine</td></tr>" >> $@ + cat $@.tmp2 >> $@ + echo "</table>" >> $@ + echo "<br>" >> $@ + rm $@.tmp $@.tmp2 + +html_table_files = $(objcbfs)/romstage.html $(objcbfs)/ramstage.html +list_of_html_files = $(subst _NEWLINE_,${\n},${html_table_files}) +current_date = $$(date +"%Y/%m/%d") + +# Build the web page from the implementation tables +$(obj)/$(CONFIG_MAINBOARD_PART_NUMBER)_checklist.html: $(html_table_files) + # + # Add the header to the web page + # + echo "<html>" > $@ + echo "<head>" >> $@ + echo "<title>$(CONFIG_MAINBOARD_PART_NUMBER) Implementation Status</title>" >> $@ + echo "</title>" >> $@ + echo "<body>" >> $@ + echo "<h1>$(CONFIG_MAINBOARD_PART_NUMBER) Implementation Status: $(current_date)</h1>" >> $@ + # + # Add the tables to the web page + # + for table in $(list_of_html_files); do \ + cat $$table >> $@; \ + done + # + # Add the trailer to the web page + # + echo "</body>" >> $@ + echo "</html>" >> $@ + +Documentation/$(CONFIG_MAINBOARD_VENDOR)/Board/$(CONFIG_MAINBOARD_PART_NUMBER)_checklist.html: $(obj)/$(CONFIG_MAINBOARD_PART_NUMBER)_checklist.html + if [ ! -d Documentation/$(CONFIG_MAINBOARD_VENDOR) ]; \ + then \ + mkdir Documentation/$(CONFIG_MAINBOARD_VENDOR); \ + fi + if [ ! -d Documentation/$(CONFIG_MAINBOARD_VENDOR)/Board ]; \ + then \ + mkdir Documentation/$(CONFIG_MAINBOARD_VENDOR)/Board; \ + fi + cp $< $@ + +# Only build the checklist for boards under development +ifeq ($(CONFIG_CREATE_BOARD_CHECKLIST),y) +ifeq ($(CONFIG_MAKE_CHECKLIST_PUBLIC),y) +INTERMEDIATE+=Documentation/$(CONFIG_MAINBOARD_VENDOR)/Board/$(CONFIG_MAINBOARD_PART_NUMBER)_checklist.html +else +INTERMEDIATE+=$(obj)/$(CONFIG_MAINBOARD_PART_NUMBER)_checklist.html +endif +endif + +########################################################################### # Build the final rom image ########################################################################### diff --git a/src/Kconfig b/src/Kconfig index f93c2cc..2b9a136 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -1175,3 +1175,11 @@ config DEBUG_BOOT_STATE help Control debugging of the boot state machine. When selected displays the state boundaries in ramstage. + +config CREATE_BOARD_CHECKLIST + bool + default n + +config MAKE_CHECKLIST_PUBLIC + bool + default n diff --git a/src/drivers/intel/fsp1_1/Kconfig b/src/drivers/intel/fsp1_1/Kconfig index 9b2c463..86f6c7b 100644 --- a/src/drivers/intel/fsp1_1/Kconfig +++ b/src/drivers/intel/fsp1_1/Kconfig @@ -115,4 +115,8 @@ config VBT_FILE depends on GOP_SUPPORT default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/vbt.bin" +config CHECKLIST_DATA_FILE_LOCATION + string + default "src/vendorcode/intel/fsp/fsp1_1/checklist" + endif #PLATFORM_USES_FSP1_1 diff --git a/src/vendorcode/intel/fsp/fsp1_1/checklist/ramstage_complete.dat b/src/vendorcode/intel/fsp/fsp1_1/checklist/ramstage_complete.dat new file mode 100644 index 0000000..55849ac --- /dev/null +++ b/src/vendorcode/intel/fsp/fsp1_1/checklist/ramstage_complete.dat @@ -0,0 +1,17 @@ +arch_segment_loaded +boot_device_init +fw_cfg_acpi_tables +lb_board +lb_framebuffer +mainboard_post +mainboard_silicon_init_params +mirror_payload +platform_prog_run +platform_segment_loaded +smbios_mainboard_bios_version +smbios_mainboard_manufacturer +smbios_mainboard_product_name +smbios_mainboard_serial_number +smbios_mainboard_set_uuid +smbios_mainboard_version +soc_after_silicon_init diff --git a/src/vendorcode/intel/fsp/fsp1_1/checklist/ramstage_exclude.dat b/src/vendorcode/intel/fsp/fsp1_1/checklist/ramstage_exclude.dat new file mode 100644 index 0000000..8b13789 --- /dev/null +++ b/src/vendorcode/intel/fsp/fsp1_1/checklist/ramstage_exclude.dat @@ -0,0 +1 @@ + diff --git a/src/vendorcode/intel/fsp/fsp1_1/checklist/ramstage_optional.dat b/src/vendorcode/intel/fsp/fsp1_1/checklist/ramstage_optional.dat new file mode 100644 index 0000000..29077c9 --- /dev/null +++ b/src/vendorcode/intel/fsp/fsp1_1/checklist/ramstage_optional.dat @@ -0,0 +1,8 @@ +arch_segment_loaded +boot_device_init +lb_board +lb_framebuffer +mainboard_post +mirror_payload +platform_prog_run +platform_segment_loaded diff --git a/src/vendorcode/intel/fsp/fsp1_1/checklist/romstage_complete.dat b/src/vendorcode/intel/fsp/fsp1_1/checklist/romstage_complete.dat new file mode 100644 index 0000000..4f2932e --- /dev/null +++ b/src/vendorcode/intel/fsp/fsp1_1/checklist/romstage_complete.dat @@ -0,0 +1,13 @@ +arch_segment_loaded +boot_device_init +mainboard_add_dimm_info +mainboard_check_ec_image +mainboard_memory_init_params +mainboard_post +mainboard_save_dimm_info +platform_prog_run +platform_segment_loaded +report_memory_config +soc_pre_ram_init +stage_cache_add +stage_cache_load_stage diff --git a/src/vendorcode/intel/fsp/fsp1_1/checklist/romstage_exclude.dat b/src/vendorcode/intel/fsp/fsp1_1/checklist/romstage_exclude.dat new file mode 100644 index 0000000..8b13789 --- /dev/null +++ b/src/vendorcode/intel/fsp/fsp1_1/checklist/romstage_exclude.dat @@ -0,0 +1 @@ + diff --git a/src/vendorcode/intel/fsp/fsp1_1/checklist/romstage_optional.dat b/src/vendorcode/intel/fsp/fsp1_1/checklist/romstage_optional.dat new file mode 100644 index 0000000..7660409 --- /dev/null +++ b/src/vendorcode/intel/fsp/fsp1_1/checklist/romstage_optional.dat @@ -0,0 +1,10 @@ +arch_segment_loaded +boot_device_init +car_mainboard_post_console_init +car_mainboard_pre_console_init +mainboard_check_ec_image +mainboard_post +platform_prog_run +platform_segment_loaded +stage_cache_add +stage_cache_load_stage diff --git a/src/vendorcode/intel/fsp/fsp1_1/checklist/verstage_complete.dat b/src/vendorcode/intel/fsp/fsp1_1/checklist/verstage_complete.dat new file mode 100644 index 0000000..7660409 --- /dev/null +++ b/src/vendorcode/intel/fsp/fsp1_1/checklist/verstage_complete.dat @@ -0,0 +1,10 @@ +arch_segment_loaded +boot_device_init +car_mainboard_post_console_init +car_mainboard_pre_console_init +mainboard_check_ec_image +mainboard_post +platform_prog_run +platform_segment_loaded +stage_cache_add +stage_cache_load_stage diff --git a/src/vendorcode/intel/fsp/fsp1_1/checklist/verstage_exclude.dat b/src/vendorcode/intel/fsp/fsp1_1/checklist/verstage_exclude.dat new file mode 100644 index 0000000..8b13789 --- /dev/null +++ b/src/vendorcode/intel/fsp/fsp1_1/checklist/verstage_exclude.dat @@ -0,0 +1 @@ + diff --git a/src/vendorcode/intel/fsp/fsp1_1/checklist/verstage_optional.dat b/src/vendorcode/intel/fsp/fsp1_1/checklist/verstage_optional.dat new file mode 100644 index 0000000..b1ddfb6 --- /dev/null +++ b/src/vendorcode/intel/fsp/fsp1_1/checklist/verstage_optional.dat @@ -0,0 +1,11 @@ +arch_segment_loaded +boot_device_init +car_mainboard_post_console_init +car_mainboard_pre_console_init +mainboard_check_ec_image +mainboard_post +platform_prog_run +platform_segment_loaded +stage_cache_add +stage_cache_load_stage +

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Patch set updated for coreboot: quark: Enable HSUART0 as console
by Leroy P Leahy 31 May '16

31 May '16

Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15010 -gerrit commit 472bfdfcf8ea63a36b90e1a0e333f68c44bea610 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Mon May 30 15:01:06 2016 -0700 quark: Enable HSUART0 as console The use of HSUART0 on galileo requires early initialization of the I2C GPIO expanders to direct the RXD and TXD signals to DIGITAL 0 and 1 on the expansion connector. TEST=None Change-Id: I11195d79e954c1f6bc91eafe257d7ddc1310b2e7 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/mainboard/intel/galileo/gen1.h | 50 ++++++++++++++++++++++++++++ src/mainboard/intel/galileo/gen2.h | 22 ++++++++++++ src/mainboard/intel/galileo/gpio.c | 38 +++++++++++++-------- src/soc/intel/quark/Kconfig | 27 ++++++++++----- src/soc/intel/quark/include/soc/pci_devs.h | 3 ++ src/soc/intel/quark/include/soc/reg_access.h | 1 - src/soc/intel/quark/romstage/romstage.c | 12 ++++--- 7 files changed, 126 insertions(+), 27 deletions(-) diff --git a/src/mainboard/intel/galileo/gen1.h b/src/mainboard/intel/galileo/gen1.h index e1e8f59..23b2309 100644 --- a/src/mainboard/intel/galileo/gen1.h +++ b/src/mainboard/intel/galileo/gen1.h @@ -59,6 +59,56 @@ static const struct reg_script gen1_gpio_init[] = { REG_SCRIPT_END }; +static const struct reg_script gen1_hsuart0_0x20[] = { + /* Route UART0_TXD to LVL_TXD -> IO1 -> DIGITAL 1 + * Set IO1_MUX (EXP.PORT3_5) output, low + * Set LVL_OE (GPIO_SUS2) output, high + */ + + REG_I2C_WRITE(GEN1_I2C_GPIO_EXP_0x20, GEN1_GPIO_EXP_PORT_SELECT, 3), + REG_I2C_AND(GEN1_I2C_GPIO_EXP_0x20, GEN1_GPIO_EXP_PORT_DIR, ~BIT5), + REG_I2C_AND(GEN1_I2C_GPIO_EXP_0x20, GEN1_GPIO_EXP_OUTPUT3, ~BIT5), + + /* Route DIGITAL 0 -> IO0 -> LVL_RXD -> UART0_RXD + * Set IO0_MUX (EXP.PORT3_4) output, low + * Set LVL_OE (GPIO_SUS2) output, high + */ + REG_I2C_WRITE(GEN1_I2C_GPIO_EXP_0x20, GEN1_GPIO_EXP_PORT_SELECT, 3), + REG_I2C_AND(GEN1_I2C_GPIO_EXP_0x20, GEN1_GPIO_EXP_PORT_DIR, ~BIT4), + REG_I2C_AND(GEN1_I2C_GPIO_EXP_0x20, GEN1_GPIO_EXP_OUTPUT3, ~BIT4), + + REG_LEG_GPIO_OR(R_QNC_GPIO_RGEN_RESUME_WELL, BIT2), + REG_LEG_GPIO_AND(R_QNC_GPIO_RGIO_RESUME_WELL, ~BIT2), + REG_LEG_GPIO_OR(R_QNC_GPIO_RGLVL_RESUME_WELL, BIT2), + + REG_SCRIPT_END +}; + +static const struct reg_script gen1_hsuart0_0x21[] = { + /* Route UART0_TXD to LVL_TXD -> IO1 -> DIGITAL 1 + * Set IO1_MUX (EXP.PORT3_5) output, low + * Set LVL_OE (GPIO_SUS2) output, high + */ + + REG_I2C_WRITE(GEN1_I2C_GPIO_EXP_0x21, GEN1_GPIO_EXP_PORT_SELECT, 3), + REG_I2C_AND(GEN1_I2C_GPIO_EXP_0x21, GEN1_GPIO_EXP_PORT_DIR, ~BIT5), + REG_I2C_AND(GEN1_I2C_GPIO_EXP_0x21, GEN1_GPIO_EXP_OUTPUT3, ~BIT5), + + /* Route DIGITAL 0 -> IO0 -> LVL_RXD -> UART0_RXD + * Set IO0_MUX (EXP.PORT3_4) output, low + * Set LVL_OE (GPIO_SUS2) output, high + */ + REG_I2C_WRITE(GEN1_I2C_GPIO_EXP_0x21, GEN1_GPIO_EXP_PORT_SELECT, 3), + REG_I2C_AND(GEN1_I2C_GPIO_EXP_0x21, GEN1_GPIO_EXP_PORT_DIR, ~BIT4), + REG_I2C_AND(GEN1_I2C_GPIO_EXP_0x21, GEN1_GPIO_EXP_OUTPUT3, ~BIT4), + + REG_LEG_GPIO_OR(R_QNC_GPIO_RGEN_RESUME_WELL, BIT2), + REG_LEG_GPIO_AND(R_QNC_GPIO_RGIO_RESUME_WELL, ~BIT2), + REG_LEG_GPIO_OR(R_QNC_GPIO_RGLVL_RESUME_WELL, BIT2), + + REG_SCRIPT_END +}; + static const struct reg_script gen1_i2c_0x20_init[] = { /* Route I2C pins to Arduino header: * Clear I2C_MUX (GPORT1_BIT5) to route I2C to Arduino Shield connector diff --git a/src/mainboard/intel/galileo/gen2.h b/src/mainboard/intel/galileo/gen2.h index 8eee744..10c8321 100644 --- a/src/mainboard/intel/galileo/gen2.h +++ b/src/mainboard/intel/galileo/gen2.h @@ -52,6 +52,28 @@ static const struct reg_script gen2_gpio_init[] = { REG_SCRIPT_END }; +static const struct reg_script gen2_hsuart0[] = { + /* Route UART0_TXD to MUX7_Y -> BUF_IO1 -> IO1 -> DIGITAL 1 + * Set MUX7_SEL (EXP1.P1_5) high + * Configure MUX7_SEL (EXP1.P1_5) as an output + * Set LVL_B_OE6_N (EXP0.P1_4) low + * Configure LVL_B_OE6_N (EXP0.P1_4) as an output + */ + REG_I2C_OR(GEN2_I2C_GPIO_EXP1, GEN2_GPIO_EXP_OUTPUT1, BIT5), + REG_I2C_AND(GEN2_I2C_GPIO_EXP1, GEN2_GPIO_EXP_CONFIG1, ~BIT5), + REG_I2C_AND(GEN2_I2C_GPIO_EXP0, GEN2_GPIO_EXP_OUTPUT1, ~BIT4), + REG_I2C_AND(GEN2_I2C_GPIO_EXP0, GEN2_GPIO_EXP_CONFIG1, ~BIT4), + + /* Route DIGITAL 0 -> IO0 -> UART0_RXD + * Set LVL_C_OE0_N (EXP1.P0_0) high + * Configure LVL_C_OE0_N (EXP1.P0_0) as an output + */ + REG_I2C_OR(GEN2_I2C_GPIO_EXP1, GEN2_GPIO_EXP_OUTPUT0, BIT0), + REG_I2C_AND(GEN2_I2C_GPIO_EXP1, GEN2_GPIO_EXP_CONFIG0, ~BIT0), + + REG_SCRIPT_END +}; + static const struct reg_script gen2_i2c_init[] = { /* Route I2C to Arduino Shield connector: * Set AMUX1_IN (EXP2.P1_4) low diff --git a/src/mainboard/intel/galileo/gpio.c b/src/mainboard/intel/galileo/gpio.c index 0c26ec8..20b1bea 100644 --- a/src/mainboard/intel/galileo/gpio.c +++ b/src/mainboard/intel/galileo/gpio.c @@ -15,11 +15,35 @@ #include <arch/io.h> #include <console/console.h> +#include <fsp/romstage.h> #include <soc/ramstage.h> #include "reg_access.h" #include "gen1.h" #include "gen2.h" +void car_mainboard_pre_console_init(void) +{ + const struct reg_script *script; + + /* Initialize the GPIO controllers */ + if (IS_ENABLED(CONFIG_GALILEO_GEN2)) + script = gen2_gpio_init; + else + script = gen1_gpio_init; + reg_script_run(script); + + /* Initialize the RXD and TXD paths for UART0 */ + if (IS_ENABLED(CONFIG_ENABLE_BUILTIN_HSUART0)) { + if (IS_ENABLED(CONFIG_GALILEO_GEN2)) + script = gen2_hsuart0; + else + script = (reg_legacy_gpio_read (R_QNC_GPIO_RGLVL_RESUME_WELL) + & GALILEO_DETERMINE_IOEXP_SLA_RESUMEWELL_GPIO) + ? gen1_hsuart0_0x21 : gen1_hsuart0_0x20; + reg_script_run(script); + } +} + void mainboard_gpio_i2c_init(device_t dev) { const struct reg_script *script; @@ -33,24 +57,12 @@ void mainboard_gpio_i2c_init(device_t dev) /* Determine which I2C address is in use */ script = (reg_legacy_gpio_read (R_QNC_GPIO_RGLVL_RESUME_WELL) & GALILEO_DETERMINE_IOEXP_SLA_RESUMEWELL_GPIO) - ? gen1_i2c_0x20_init : gen1_i2c_0x21_init; + ? gen1_i2c_0x21_init : gen1_i2c_0x20_init; /* Initialize the I2C chips */ reg_script_run(script); } -void mainboard_gpio_init(void) -{ - const struct reg_script *script; - - /* Initialize the GPIO controllers */ - if (IS_ENABLED(CONFIG_GALILEO_GEN2)) - script = gen2_gpio_init; - else - script = gen1_gpio_init; - reg_script_run(script); -} - void mainboard_gpio_pcie_reset(uint32_t pin_value) { uint32_t pin_number; diff --git a/src/soc/intel/quark/Kconfig b/src/soc/intel/quark/Kconfig index 6a2349f..2c7ec64 100644 --- a/src/soc/intel/quark/Kconfig +++ b/src/soc/intel/quark/Kconfig @@ -40,9 +40,19 @@ config CPU_SPECIFIC_OPTIONS # The following options configure the debug serial port ##### +config ENABLE_BUILTIN_HSUART0 + bool "Enable built-in HSUART0" + default n + select NO_UART_ON_SUPERIO + select DRIVERS_UART_8250MEM_32 + help + The Quark SoC has two HSUART. Choose this option to configure the pads + and enable HSUART0, which can be used for the debug console. + config ENABLE_BUILTIN_HSUART1 bool "Enable built-in HSUART1" - default y + default n + depends on ! ENABLE_BUILTIN_HSUART0 select NO_UART_ON_SUPERIO select DRIVERS_UART_8250MEM_32 help @@ -50,23 +60,24 @@ config ENABLE_BUILTIN_HSUART1 and enable HSUART1, which can be used for the debug console. config TTYS0_BASE - hex "HSUART1 Base Address" - depends on ENABLE_BUILTIN_HSUART1 + hex "HSUART Base Address" default 0xA0019000 + depends on ENABLE_BUILTIN_HSUART0 || ENABLE_BUILTIN_HSUART1 help - Memory mapped MMIO of HSUART1. + Memory mapped MMIO of HSUART. config TTYS0_LCS int - depends on ENABLE_BUILTIN_HSUART1 default 3 + depends on ENABLE_BUILTIN_HSUART0 || ENABLE_BUILTIN_HSUART1 -# Console: PCI UART bus 0 << 20, device 20 << 15, function 5 << 12 +# Console: PCI UART bus 0 << 20, device 20 << 15, function x << 12 # Valid bit, PCI UART in use: 1 << 31 config UART_PCI_ADDR hex - depends on ENABLE_BUILTIN_HSUART1 - default 0x800a5000 + default 0x800a1000 if ENABLE_BUILTIN_HSUART0 + default 0x800a5000 if ENABLE_BUILTIN_HSUART1 + depends on ENABLE_BUILTIN_HSUART0 || ENABLE_BUILTIN_HSUART1 ##### # Debug support diff --git a/src/soc/intel/quark/include/soc/pci_devs.h b/src/soc/intel/quark/include/soc/pci_devs.h index 278a012..0c99eb9 100644 --- a/src/soc/intel/quark/include/soc/pci_devs.h +++ b/src/soc/intel/quark/include/soc/pci_devs.h @@ -33,11 +33,14 @@ /* IO Fabric 1 */ #define SIO1_DEV 0x14 +#define HSUART0_DEV SIO1_DEV #define HSUART1_DEV SIO1_DEV +#define HSUART0_FUNC 1 #define USB_DEV_PORT_FUNC 2 #define EHCI_FUNC 3 #define OHCI_FUNC 4 #define HSUART1_FUNC 5 +#define HSUART0_BDF PCI_DEV(PCI_BUS_NUMBER_QNC, HSUART0_DEV, HSUART0_FUNC) #define HSUART1_BDF PCI_DEV(PCI_BUS_NUMBER_QNC, HSUART1_DEV, HSUART1_FUNC) /* IO Fabric 2 */ diff --git a/src/soc/intel/quark/include/soc/reg_access.h b/src/soc/intel/quark/include/soc/reg_access.h index e7a8963..b934032 100644 --- a/src/soc/intel/quark/include/soc/reg_access.h +++ b/src/soc/intel/quark/include/soc/reg_access.h @@ -203,7 +203,6 @@ enum { REG_USB_RXW(reg_, 0xffffffff, value_) void *get_i2c_address(void); -void mainboard_gpio_init(void); void mainboard_gpio_pcie_reset(uint32_t pin_value); void mcr_write(uint8_t opcode, uint8_t port, uint32_t reg_address); uint32_t mdr_read(void); diff --git a/src/soc/intel/quark/romstage/romstage.c b/src/soc/intel/quark/romstage/romstage.c index 5be022a..e27aa68 100644 --- a/src/soc/intel/quark/romstage/romstage.c +++ b/src/soc/intel/quark/romstage/romstage.c @@ -67,6 +67,13 @@ static const struct reg_script hsuart_init[] = { void car_soc_pre_console_init(void) { + /* Initialize the controllers */ + reg_script_run_on_dev(I2CGPIO_BDF, i2c_gpio_controller_init); + reg_script_run_on_dev(LPC_BDF, legacy_gpio_init); + + /* Enable the HSUART */ + if (IS_ENABLED(CONFIG_ENABLE_BUILTIN_HSUART0)) + reg_script_run_on_dev(HSUART0_BDF, hsuart_init); if (IS_ENABLED(CONFIG_ENABLE_BUILTIN_HSUART1)) reg_script_run_on_dev(HSUART1_BDF, hsuart_init); } @@ -74,11 +81,6 @@ void car_soc_pre_console_init(void) void car_soc_post_console_init(void) { report_platform_info(); - - /* Initialize the controllers */ - reg_script_run_on_dev(I2CGPIO_BDF, i2c_gpio_controller_init); - reg_script_run_on_dev(LPC_BDF, legacy_gpio_init); - mainboard_gpio_init(); }; static struct chipset_power_state power_state CAR_GLOBAL;

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Patch set updated for coreboot: soc/intel/quark: Move UART init into romstage.c
by Leroy P Leahy 31 May '16

31 May '16

Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15009 -gerrit commit d5b5428ef15c0cc57ff670494675cdf0b4506318 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Mon May 30 14:35:15 2016 -0700 soc/intel/quark: Move UART init into romstage.c Move UART initialization into romstage.c and eliminate uart.c. TEST=Build and run on Galileo Gen2 Change-Id: I5f2c9b4c566008000c2201c422a0bba63da64487 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/soc/intel/quark/include/soc/pci_devs.h | 1 + src/soc/intel/quark/romstage/Makefile.inc | 1 - src/soc/intel/quark/romstage/romstage.c | 10 +++++-- src/soc/intel/quark/romstage/uart.c | 42 ------------------------------ 4 files changed, 9 insertions(+), 45 deletions(-) diff --git a/src/soc/intel/quark/include/soc/pci_devs.h b/src/soc/intel/quark/include/soc/pci_devs.h index ff9d65f..278a012 100644 --- a/src/soc/intel/quark/include/soc/pci_devs.h +++ b/src/soc/intel/quark/include/soc/pci_devs.h @@ -38,6 +38,7 @@ #define EHCI_FUNC 3 #define OHCI_FUNC 4 #define HSUART1_FUNC 5 +#define HSUART1_BDF PCI_DEV(PCI_BUS_NUMBER_QNC, HSUART1_DEV, HSUART1_FUNC) /* IO Fabric 2 */ #define SIO2_DEV 0x15 diff --git a/src/soc/intel/quark/romstage/Makefile.inc b/src/soc/intel/quark/romstage/Makefile.inc index 2f29b06..6c92ac4 100644 --- a/src/soc/intel/quark/romstage/Makefile.inc +++ b/src/soc/intel/quark/romstage/Makefile.inc @@ -20,4 +20,3 @@ romstage-y += mtrr.c romstage-y += pcie.c romstage-y += report_platform.c romstage-y += romstage.c -romstage-$(CONFIG_ENABLE_BUILTIN_HSUART1) += uart.c diff --git a/src/soc/intel/quark/romstage/romstage.c b/src/soc/intel/quark/romstage/romstage.c index c86c2ea..5be022a 100644 --- a/src/soc/intel/quark/romstage/romstage.c +++ b/src/soc/intel/quark/romstage/romstage.c @@ -58,11 +58,17 @@ static const struct reg_script i2c_gpio_controller_init[] = { REG_SCRIPT_END }; +static const struct reg_script hsuart_init[] = { + /* Enable the HSUART */ + REG_PCI_WRITE32(PCI_BASE_ADDRESS_0, UART_BASE_ADDRESS), + REG_PCI_OR8(PCI_COMMAND, PCI_COMMAND_MEMORY), + REG_SCRIPT_END +}; + void car_soc_pre_console_init(void) { if (IS_ENABLED(CONFIG_ENABLE_BUILTIN_HSUART1)) - set_base_address_and_enable_uart(0, HSUART1_DEV, HSUART1_FUNC, - UART_BASE_ADDRESS); + reg_script_run_on_dev(HSUART1_BDF, hsuart_init); } void car_soc_post_console_init(void) diff --git a/src/soc/intel/quark/romstage/uart.c b/src/soc/intel/quark/romstage/uart.c deleted file mode 100644 index 9e8f6c5..0000000 --- a/src/soc/intel/quark/romstage/uart.c +++ /dev/null @@ -1,42 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2003 Eric Biederman - * Copyright (C) 2006-2010 coresystems GmbH - * Copyright (C) 2015-2016 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -// Use simple device model for this file even in ramstage -#define __SIMPLE_DEVICE__ - -#include <device/pci.h> -#include <device/pci_def.h> -#include <rules.h> -#include <soc/romstage.h> - -int set_base_address_and_enable_uart(u8 bus, u8 dev, u8 func, u32 mmio_base) -{ - uint16_t reg16; - - /* HSUART controller #1 (B0:D20:F5). */ - pci_devfn_t uart_bdf = PCI_DEV(bus, dev, func); - - /* Decode BAR0(offset 0x10). */ - pci_write_config32(uart_bdf, PCI_BASE_ADDRESS_0, mmio_base); - - /* Enable MEMBASE at CMD(offset 0x04). */ - reg16 = pci_read_config16(uart_bdf, PCI_COMMAND); - reg16 |= PCI_COMMAND_MEMORY; - pci_write_config16(uart_bdf, PCI_COMMAND, reg16); - - return 0; -}

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Patch set updated for coreboot: mainboard/intel/quark: Enable reg_access during romstage
by Leroy P Leahy 31 May '16

31 May '16

Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15008 -gerrit commit da103694eaafdeac03e7f9db7240fcbcff61610d Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Mon May 30 11:23:49 2016 -0700 mainboard/intel/quark: Enable reg_access during romstage Turn on reg_access during romstage. TEST=Build and run on Galileo Gen2 Change-Id: Iff1616836d6031f43d7741693febefa0bf26b948 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/mainboard/intel/galileo/Makefile.inc | 1 + src/mainboard/intel/galileo/reg_access.c | 3 --- 2 files changed, 1 insertion(+), 3 deletions(-) diff --git a/src/mainboard/intel/galileo/Makefile.inc b/src/mainboard/intel/galileo/Makefile.inc index 72c74e1..83fb0db 100644 --- a/src/mainboard/intel/galileo/Makefile.inc +++ b/src/mainboard/intel/galileo/Makefile.inc @@ -18,6 +18,7 @@ CPPFLAGS_common += -I$(src)/vendorcode/intel/fsp/fsp1_1/quark endif romstage-y += gpio.c +romstage-y += reg_access.c ramstage-y += gpio.c ramstage-y += reg_access.c diff --git a/src/mainboard/intel/galileo/reg_access.c b/src/mainboard/intel/galileo/reg_access.c index f19f526..36345ff 100644 --- a/src/mainboard/intel/galileo/reg_access.c +++ b/src/mainboard/intel/galileo/reg_access.c @@ -22,7 +22,6 @@ #include <soc/reg_access.h> #include "reg_access.h" -#if ENV_RAMSTAGE static uint64_t reg_read(struct reg_script_context *ctx) { int ret_code; @@ -89,5 +88,3 @@ const struct reg_script_bus_entry mainboard_reg_script_bus_table = { }; REG_SCRIPT_BUS_ENTRY(mainboard_reg_script_bus_table); - -#endif /* ENV_RAMSTAGE */

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Patch set updated for coreboot: Documentation/Intel/Board: Add Galileo checklist
by Leroy P Leahy 31 May '16

31 May '16

Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15012 -gerrit commit c009ffb9e002abfa7e2c9cd702bfa386c981c9a4 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Mon May 30 17:09:09 2016 -0700 Documentation/Intel/Board: Add Galileo checklist Add the Galileo implementation checklist. TEST=None Change-Id: I47e87a496cf3ae125d45c09fe6a36200f5fe724f Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- Documentation/Intel/Board/Galileo_checklist.html | 50 ++++++++++++++++++++++++ Documentation/Intel/Board/galileo.html | 1 + 2 files changed, 51 insertions(+) diff --git a/Documentation/Intel/Board/Galileo_checklist.html b/Documentation/Intel/Board/Galileo_checklist.html new file mode 100644 index 0000000..95a6c4d --- /dev/null +++ b/Documentation/Intel/Board/Galileo_checklist.html @@ -0,0 +1,50 @@ +<html> +<head> +<title>Galileo Implementation Status</title> +</title> +<body> +<h1>Galileo Implementation Status: 2016/05/30</h1> +<table border=1> +<tr><th colspan=2>romstage: 16% Done</th></tr> +<tr><th>Type</th><th>Routine</td></tr> +<tr bgcolor=#ffffc0><td>Optional</td><td>arch_segment_loaded</td></tr> +<tr bgcolor=#ffffc0><td>Optional</td><td>boot_device_init</td></tr> +<tr bgcolor=#ffffc0><td>Optional</td><td>car_mainboard_post_console_init</td></tr> +<tr bgcolor=#c0ffc0><td>Required</td><td>car_mainboard_pre_console_init</td></tr> +<tr bgcolor=#ffc0c0><td>Required</td><td>mainboard_add_dimm_info</td></tr> +<tr bgcolor=#ffffc0><td>Optional</td><td>mainboard_check_ec_image</td></tr> +<tr bgcolor=#ffc0c0><td>Required</td><td>mainboard_memory_init_params</td></tr> +<tr bgcolor=#ffffc0><td>Optional</td><td>mainboard_post</td></tr> +<tr bgcolor=#ffc0c0><td>Required</td><td>mainboard_save_dimm_info</td></tr> +<tr bgcolor=#ffffc0><td>Optional</td><td>platform_prog_run</td></tr> +<tr bgcolor=#ffffc0><td>Optional</td><td>platform_segment_loaded</td></tr> +<tr bgcolor=#ffc0c0><td>Required</td><td>report_memory_config</td></tr> +<tr bgcolor=#ffc0c0><td>Required</td><td>soc_pre_ram_init</td></tr> +<tr bgcolor=#ffffc0><td>Optional</td><td>stage_cache_add</td></tr> +<tr bgcolor=#ffffc0><td>Optional</td><td>stage_cache_load_stage</td></tr> +</table> +<br> +<table border=1> +<tr><th colspan=2>ramstage: 0% Done</th></tr> +<tr><th>Type</th><th>Routine</td></tr> +<tr bgcolor=#ffffc0><td>Optional</td><td>arch_segment_loaded</td></tr> +<tr bgcolor=#ffffc0><td>Optional</td><td>boot_device_init</td></tr> +<tr bgcolor=#ffc0c0><td>Required</td><td>fw_cfg_acpi_tables</td></tr> +<tr bgcolor=#ffffc0><td>Optional</td><td>lb_board</td></tr> +<tr bgcolor=#ffffc0><td>Optional</td><td>lb_framebuffer</td></tr> +<tr bgcolor=#ffffc0><td>Optional</td><td>mainboard_post</td></tr> +<tr bgcolor=#ffc0c0><td>Required</td><td>mainboard_silicon_init_params</td></tr> +<tr bgcolor=#ffffc0><td>Optional</td><td>mirror_payload</td></tr> +<tr bgcolor=#ffffc0><td>Optional</td><td>platform_prog_run</td></tr> +<tr bgcolor=#ffffc0><td>Optional</td><td>platform_segment_loaded</td></tr> +<tr bgcolor=#ffc0c0><td>Required</td><td>smbios_mainboard_bios_version</td></tr> +<tr bgcolor=#ffc0c0><td>Required</td><td>smbios_mainboard_manufacturer</td></tr> +<tr bgcolor=#ffc0c0><td>Required</td><td>smbios_mainboard_product_name</td></tr> +<tr bgcolor=#ffc0c0><td>Required</td><td>smbios_mainboard_serial_number</td></tr> +<tr bgcolor=#ffc0c0><td>Required</td><td>smbios_mainboard_set_uuid</td></tr> +<tr bgcolor=#ffc0c0><td>Required</td><td>smbios_mainboard_version</td></tr> +<tr bgcolor=#ffc0c0><td>Required</td><td>soc_after_silicon_init</td></tr> +</table> +<br> +</body> +</html> diff --git a/Documentation/Intel/Board/galileo.html b/Documentation/Intel/Board/galileo.html index 3639419..cdc8fda 100644 --- a/Documentation/Intel/Board/galileo.html +++ b/Documentation/Intel/Board/galileo.html @@ -17,6 +17,7 @@ <li><a target="_blank" href="../SoC/soc.html">SoC</a> support</li> <li><a target="_blank" href="../fsp1_1.html">FSP 1.1</a> integration</li> <li><a target="_blank" href="board.html">Board</a> support</li> + <li><a target="_blank" href="Galileo_checklist.html">Implementation Checklist</a></li> </ul> </td> </tr>

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Patch set updated for coreboot: soc/intel/quark: Fix reg_script display
by Leroy P Leahy 31 May '16

31 May '16

Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14948 -gerrit commit 122e79bff14d7a0400c55e9041b802f684f3cb05 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Sun May 22 16:24:36 2016 -0700 soc/intel/quark: Fix reg_script display Remove extra ": " following reigster type. TEST=Build and run on Galileo Gen2 Change-Id: I57dd40a540d7b5371a6c45174f47a311b83a2aab Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/soc/intel/quark/reg_access.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/src/soc/intel/quark/reg_access.c b/src/soc/intel/quark/reg_access.c index 30cc7db..1dd0d3c 100644 --- a/src/soc/intel/quark/reg_access.c +++ b/src/soc/intel/quark/reg_access.c @@ -216,21 +216,21 @@ static uint64_t reg_read(struct reg_script_context *ctx) return 0; case GPE0_REGS: - ctx->display_prefix = "GPE0: "; + ctx->display_prefix = "GPE0"; value = reg_gpe0_read(step->reg); break; case GPIO_REGS: - ctx->display_prefix = "GPIO: "; + ctx->display_prefix = "GPIO"; value = reg_gpio_read(step->reg); break; case LEG_GPIO_REGS: - ctx->display_prefix = "Legacy GPIO: "; + ctx->display_prefix = "Legacy GPIO"; value = reg_legacy_gpio_read(step->reg); case PCIE_AFE_REGS: - ctx->display_prefix = "PCIe AFE: "; + ctx->display_prefix = "PCIe AFE"; value = reg_pcie_afe_read(step->reg); break; @@ -265,28 +265,28 @@ static void reg_write(struct reg_script_context *ctx) return; case GPE0_REGS: - ctx->display_prefix = "GPE0: "; + ctx->display_prefix = "GPE0"; reg_gpe0_write(step->reg, (uint32_t)step->value); break; case GPIO_REGS: - ctx->display_prefix = "GPIO: "; + ctx->display_prefix = "GPIO"; reg_gpio_write(step->reg, (uint32_t)step->value); break; case LEG_GPIO_REGS: - ctx->display_prefix = "Legacy GPIO: "; + ctx->display_prefix = "Legacy GPIO"; reg_legacy_gpio_write(step->reg, (uint32_t)step->value); break; case PCIE_AFE_REGS: - ctx->display_prefix = "PCIe AFE: "; + ctx->display_prefix = "PCIe AFE"; reg_pcie_afe_write(step->reg, (uint32_t)step->value); break; case PCIE_RESET: if (ctx->display_features) { - ctx->display_prefix = "PCIe reset: "; + ctx->display_prefix = "PCIe reset"; ctx->display_features &= ~REG_SCRIPT_DISPLAY_REGISTER; } mainboard_gpio_pcie_reset(step->value);

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Patch set updated for coreboot: soc/intel/quark: Rename pmc.c to lpc.c
by Leroy P Leahy 31 May '16

31 May '16

Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14946 -gerrit commit d5eea22e138d533fcba249664c6d2582966bd1cb Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Sun May 22 15:34:11 2016 -0700 soc/intel/quark: Rename pmc.c to lpc.c Rename the file pmc.c to lpc.c to prepare for further additions. TEST=Build and run on Galileo Gen2 Change-Id: If98825d72878f0601f77bff8c766276dbda8a9ae Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/soc/intel/quark/Makefile.inc | 2 +- src/soc/intel/quark/lpc.c | 51 ++++++++++++++++++++++++++++++++++++++++ src/soc/intel/quark/pmc.c | 51 ---------------------------------------- 3 files changed, 52 insertions(+), 52 deletions(-) diff --git a/src/soc/intel/quark/Makefile.inc b/src/soc/intel/quark/Makefile.inc index a6d03b1..08325e7 100644 --- a/src/soc/intel/quark/Makefile.inc +++ b/src/soc/intel/quark/Makefile.inc @@ -27,9 +27,9 @@ ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c ramstage-y += chip.c ramstage-y += ehci.c ramstage-y += gpio_i2c.c +ramstage-y += lpc.c ramstage-y += memmap.c ramstage-y += northcluster.c -ramstage-y += pmc.c ramstage-y += reg_access.c ramstage-y += tsc_freq.c ramstage-$(CONFIG_ENABLE_BUILTIN_HSUART1) += uart_common.c diff --git a/src/soc/intel/quark/lpc.c b/src/soc/intel/quark/lpc.c new file mode 100644 index 0000000..fbed935 --- /dev/null +++ b/src/soc/intel/quark/lpc.c @@ -0,0 +1,51 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Google Inc. + * Copyright (C) 2015-2016 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/pci.h> +#include <device/pci_ids.h> +#include <soc/iomap.h> +#include <soc/pci_devs.h> +#include <soc/pm.h> +#include <soc/ramstage.h> + +static void pmc_read_resources(device_t dev) +{ + unsigned index = 0; + struct resource *res; + + /* Get the normal PCI resources of this device. */ + pci_dev_read_resources(dev); + + /* PMBASE */ + res = new_resource(dev, index++); + res->base = ACPI_BASE_ADDRESS; + res->size = ACPI_BASE_SIZE; + res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; +} + +static struct device_operations device_ops = { + .read_resources = &pmc_read_resources, + .set_resources = &pci_dev_set_resources, + .enable_resources = &pci_dev_enable_resources, + .scan_bus = &scan_lpc_bus, +}; + +static const struct pci_driver pmc __pci_driver = { + .ops = &device_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = QUARK_V_LPC_DEVICE_ID_0, +}; diff --git a/src/soc/intel/quark/pmc.c b/src/soc/intel/quark/pmc.c deleted file mode 100644 index fbed935..0000000 --- a/src/soc/intel/quark/pmc.c +++ /dev/null @@ -1,51 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015-2016 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <device/pci.h> -#include <device/pci_ids.h> -#include <soc/iomap.h> -#include <soc/pci_devs.h> -#include <soc/pm.h> -#include <soc/ramstage.h> - -static void pmc_read_resources(device_t dev) -{ - unsigned index = 0; - struct resource *res; - - /* Get the normal PCI resources of this device. */ - pci_dev_read_resources(dev); - - /* PMBASE */ - res = new_resource(dev, index++); - res->base = ACPI_BASE_ADDRESS; - res->size = ACPI_BASE_SIZE; - res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; -} - -static struct device_operations device_ops = { - .read_resources = &pmc_read_resources, - .set_resources = &pci_dev_set_resources, - .enable_resources = &pci_dev_enable_resources, - .scan_bus = &scan_lpc_bus, -}; - -static const struct pci_driver pmc __pci_driver = { - .ops = &device_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = QUARK_V_LPC_DEVICE_ID_0, -};

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coreboot-gerrit May 2016