Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15035
-gerrit
commit 1b2fc37c41ddd2cbedae911b5e0eb9d7d7b8ab23
Author: Julius Werner <jwerner(a)chromium.org>
Date: Mon May 16 15:39:12 2016 -0700
libpayload: Replace majority of timer drivers with a generic one
Currently every non-x86 platform supported by libpayload needs to
provide its own timer driver. Most of the ones we have accumulated there
look almost identical: For the frequency, return a preset constant. For
the value, read a 32-bit register, possibly read another 32-bit register
and shift+OR it with the previous one, then return that.
Let's replace this with a single .c file that can easily handle all of
those cases. Menuconfig convenience can still be maintained by providing
several presets that select different defaults for the driver's
configuration options (register address(es) and frequency).
Removes an "enabled" check from Samsung MCT driver since coreboot always
unconditionally enables that timer anyway.
CQ-DEPEND=CL:344809
BRANCH=None
BUG=None
TEST=Booted Oak and Veyron, observed how dev-mode delay was still ~30s
Change-Id: I61cb7d2ffd4902aa841c57f9afa9cd991f770ace
Signed-off-by: Martin Roth <martinroth(a)chromium.org>
Original-Commit-Id: a036af6
Original-Change-Id: I9784e7c6aa5abd6d92478ea7ec1cf42c9a437546
Original-Signed-off-by: Julius Werner <jwerner(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/347749
---
payloads/libpayload/Kconfig | 101 ++++++++++------------
payloads/libpayload/drivers/Makefile.inc | 11 +--
payloads/libpayload/drivers/timer/bg4cd.c | 26 ------
payloads/libpayload/drivers/timer/cygnus.c | 52 ------------
payloads/libpayload/drivers/timer/generic.c | 45 ++++++++++
payloads/libpayload/drivers/timer/ipq40xx.c | 52 ------------
payloads/libpayload/drivers/timer/ipq806x.c | 58 -------------
payloads/libpayload/drivers/timer/mct.c | 115 --------------------------
payloads/libpayload/drivers/timer/mtk_timer.c | 30 -------
payloads/libpayload/drivers/timer/rktimer.c | 42 ----------
payloads/libpayload/drivers/timer/tegra_1us.c | 41 ---------
11 files changed, 92 insertions(+), 481 deletions(-)
diff --git a/payloads/libpayload/Kconfig b/payloads/libpayload/Kconfig
index 276eb30..20f10ee 100644
--- a/payloads/libpayload/Kconfig
+++ b/payloads/libpayload/Kconfig
@@ -438,11 +438,11 @@ config TIMER_IPQ40XX
This is the timer driver for QCA IPQ40xx based
platforms.
-config TIMER_RK
- bool "Timer for Rockchip"
+config TIMER_RK3288
+ bool "Timer for Rockchip RK3288"
-config TIMER_BG4CD
- bool "Marvell BG4CD"
+config TIMER_RK3399
+ bool "Timer for Rockchip RK3399"
config TIMER_CYGNUS
bool "Timer for Cygnus"
@@ -455,41 +455,6 @@ config TIMER_MTK
endchoice
-config TIMER_MCT_HZ
- int "Exynos MCT frequency"
- depends on TIMER_MCT
- default 24000000
-
-config TIMER_MCT_ADDRESS
- hex "Exynos MCT base address"
- depends on TIMER_MCT
- default 0x101c0000
-
-config TIMER_RK_ADDRESS
- hex "Rockchip timer base address"
- depends on TIMER_RK
- default 0xff810020
-
-config TIMER_TEGRA_1US_ADDRESS
- hex "Tegra u1s timer base address"
- depends on TIMER_TEGRA_1US
- default 0x60005010
-
-config IPQ806X_TIMER_FREQ
- int "Hardware timer frequency"
- default 32000
- depends on TIMER_IPQ806X
- help
- IPQ hardware presently provides a single timer running at 32KHz, a
- finer granulariry timer is available but is not yet enabled.
-
-config IPQ806X_TIMER_REG
- hex "Timer register address"
- default 0x0200A008
- depends on TIMER_IPQ806X
- help
- Address of the register to read a free running timer value.
-
config ARMADA38X_TIMER_FREQ
int "Hardware timer frequency"
depends on TIMER_ARMADA38X
@@ -500,24 +465,46 @@ config ARMADA38X_TIMER_REG
default 0xF1020314
depends on TIMER_ARMADA38X
-config IPROC_PERIPH_GLB_TIM_REG_BASE
- hex "Cygnus timer base address"
- depends on TIMER_CYGNUS
- default 0x19020200
-
-config TIMER_MTK_HZ
- int "MediaTek GPT frequency"
- depends on TIMER_MTK
- default 13000000
- help
- Clock frequency of MediaTek General Purpose Timer.
-
-config TIMER_MTK_ADDRESS
- hex "MTK GPT register address"
- depends on TIMER_MTK
- default 0x10008048
- help
- Address of GPT4's counter register to read the FREERUN-mode timer value.
+config TIMER_GENERIC_HZ
+ int "Generic Timer Frequency"
+ default 500000000 if TIMER_CYGNUS
+ default 48000000 if TIMER_IPQ40XX
+ default 6250000 if TIMER_IPQ806X
+ default 24000000 if TIMER_MCT
+ default 13000000 if TIMER_MTK
+ default 24000000 if TIMER_RK3288
+ default 24000000 if TIMER_RK3399
+ default 1000000 if TIMER_TEGRA_1US
+ default 0
+ help
+ Clock frequency of generic time counter in Hertz. Leave at 0 to
+ disable when using a non-generic timer driver.
+
+config TIMER_GENERIC_REG
+ hex "Generic Timer Register Address"
+ default 0x19020200 if TIMER_CYGNUS
+ default 0x004A2000 if TIMER_IPQ40XX
+ default 0x0200A028 if TIMER_IPQ806X
+ default 0x101C0100 if TIMER_MCT
+ default 0x10008048 if TIMER_MTK
+ default 0xff810028 if TIMER_RK3288
+ default 0xff850008 if TIMER_RK3399
+ default 0x60005010 if TIMER_TEGRA_1US
+ default 0x0
+ help
+ Register address to read generic time counter from.
+
+config TIMER_GENERIC_HIGH_REG
+ hex "Generic Timer High Register Address"
+ default 0x19020204 if TIMER_CYGNUS
+ default 0x004A2004 if TIMER_IPQ40XX
+ default 0x101C0104 if TIMER_MCT
+ default 0xff81002C if TIMER_RK3288
+ default 0xff85000C if TIMER_RK3399
+ default 0x0
+ help
+ Register address to read high 32 bits of generic time counter from.
+ Leave at 0x0 for 32-bit counters.
config USB
bool "USB Support"
diff --git a/payloads/libpayload/drivers/Makefile.inc b/payloads/libpayload/drivers/Makefile.inc
index 75f08f2..3c6b12b 100644
--- a/payloads/libpayload/drivers/Makefile.inc
+++ b/payloads/libpayload/drivers/Makefile.inc
@@ -46,16 +46,11 @@ libc-$(CONFIG_LP_NVRAM) += nvram.c
libc-$(CONFIG_LP_NVRAM) += options.c
# Timer drivers
-libc-$(CONFIG_LP_TIMER_MTK) += timer/mtk_timer.c
-libc-$(CONFIG_LP_TIMER_MCT) += timer/mct.c
+ifneq ($(CONFIG_LP_TIMER_GENERIC_HZ),0)
+libc-y += timer/generic.c
+endif
libc-$(CONFIG_LP_TIMER_RDTSC) += timer/rdtsc.c
-libc-$(CONFIG_LP_TIMER_TEGRA_1US) += timer/tegra_1us.c
-libc-$(CONFIG_LP_TIMER_IPQ806X) += timer/ipq806x.c
-libc-$(CONFIG_LP_TIMER_IPQ40XX) += timer/ipq40xx.c
-libc-$(CONFIG_LP_TIMER_RK) += timer/rktimer.c
-libc-$(CONFIG_LP_TIMER_BG4CD) += timer/bg4cd.c
libc-$(CONFIG_LP_TIMER_IMG_PISTACHIO) += timer/img_pistachio.c
-libc-$(CONFIG_LP_TIMER_CYGNUS) += timer/cygnus.c
libc-$(CONFIG_LP_TIMER_ARMADA38X) += timer/armada38x.c
# Video console drivers
diff --git a/payloads/libpayload/drivers/timer/bg4cd.c b/payloads/libpayload/drivers/timer/bg4cd.c
deleted file mode 100644
index 649622b..0000000
--- a/payloads/libpayload/drivers/timer/bg4cd.c
+++ /dev/null
@@ -1,26 +0,0 @@
-
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Google Electronics
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-#include <libpayload.h>
-
-uint64_t timer_hz(void)
-{
- return 0;
-}
-
-uint64_t timer_raw_value(void)
-{
- return 0;
-}
diff --git a/payloads/libpayload/drivers/timer/cygnus.c b/payloads/libpayload/drivers/timer/cygnus.c
deleted file mode 100644
index c8f2098..0000000
--- a/payloads/libpayload/drivers/timer/cygnus.c
+++ /dev/null
@@ -1,52 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2015 Google Electronics
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-#include <libpayload.h>
-
-struct cygnus_timer {
- u32 gtim_glob_low;
- u32 gtim_glob_hi;
- u32 gtim_glob_ctrl;
-};
-
-static struct cygnus_timer * const timer_ptr =
- (void *)CONFIG_LP_IPROC_PERIPH_GLB_TIM_REG_BASE;
-
-uint64_t timer_hz(void)
-{
- /*
- * this is set up by coreboot as follows:
- *
- * PERIPH_CLOCK /
- * (((TIMER_GLB_TIM_CTRL_PRESC & TIMER_GLB_TIM_CTRL_PRESC_MASK)>>8) + 1)
- *
- * where PERIPH_CLOCK is typically 500000000.
- */
- return 500000000;
-}
-
-uint64_t timer_raw_value(void)
-{
- uint64_t cur_tick;
- uint32_t count_h;
- uint32_t count_l;
-
- do {
- count_h = readl(&timer_ptr->gtim_glob_hi);
- count_l = readl(&timer_ptr->gtim_glob_low);
- cur_tick = readl(&timer_ptr->gtim_glob_hi);
- } while (cur_tick != count_h);
-
- return (cur_tick << 32) + count_l;
-}
diff --git a/payloads/libpayload/drivers/timer/generic.c b/payloads/libpayload/drivers/timer/generic.c
new file mode 100644
index 0000000..1f516a2
--- /dev/null
+++ b/payloads/libpayload/drivers/timer/generic.c
@@ -0,0 +1,45 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2016 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <assert.h>
+#include <libpayload.h>
+
+static uint32_t *low_reg = (void *)CONFIG_LP_TIMER_GENERIC_REG;
+static uint32_t *high_reg = (void *)CONFIG_LP_TIMER_GENERIC_HIGH_REG;
+
+uint64_t timer_hz(void)
+{
+ /* libc/time.c currently requires all timers to be at least 1MHz. */
+ assert(CONFIG_LP_TIMER_GENERIC_HZ >= 1000000);
+ return CONFIG_LP_TIMER_GENERIC_HZ;
+}
+
+uint64_t timer_raw_value(void)
+{
+ uint64_t cur_tick;
+ uint32_t count_h;
+ uint32_t count_l;
+
+ if (!high_reg)
+ return readl(low_reg);
+
+ do {
+ count_h = readl(high_reg);
+ count_l = readl(low_reg);
+ cur_tick = readl(high_reg);
+ } while (cur_tick != count_h);
+
+ return (cur_tick << 32) + count_l;
+}
diff --git a/payloads/libpayload/drivers/timer/ipq40xx.c b/payloads/libpayload/drivers/timer/ipq40xx.c
deleted file mode 100644
index 0ca2600..0000000
--- a/payloads/libpayload/drivers/timer/ipq40xx.c
+++ /dev/null
@@ -1,52 +0,0 @@
-/*
- * Copyright (c) 2015, 2016, The Linux Foundation. All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above
- * copyright notice, this list of conditions and the following
- * disclaimer in the documentation and/or other materials provided
- * with the distribution.
- * * Neither the name of The Linux Foundation nor the names of its
- * contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
- * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
- * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
- * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
- * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
- * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-#include <libpayload.h>
-
-#define GCNT_FREQ_MHZ 48
-
-#define MSM_TMR_BASE ((void *)0x004a1000u)
-#define GCNT_CNTCV_LO (MSM_TMR_BASE + 0x1000)
-#define GCNT_CNTCV_HI (MSM_TMR_BASE + 0x1004)
-
-uint64_t timer_hz(void)
-{
- return GCNT_FREQ_MHZ * 1000 * 1000;
-}
-
-uint64_t timer_raw_value(void)
-{
- uint32_t hi, lo;
-
- do {
- hi = read32(GCNT_CNTCV_HI);
- lo = read32(GCNT_CNTCV_LO);
- } while (hi != read32(GCNT_CNTCV_HI));
-
- return ((((uint64_t)hi) << 32) | lo);
-}
diff --git a/payloads/libpayload/drivers/timer/ipq806x.c b/payloads/libpayload/drivers/timer/ipq806x.c
deleted file mode 100644
index f39f23d..0000000
--- a/payloads/libpayload/drivers/timer/ipq806x.c
+++ /dev/null
@@ -1,58 +0,0 @@
-/*
- * This file is part of the depthcharge project.
- *
- * Copyright (C) 2014 The Linux Foundation. All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- */
-
-#include <libpayload.h>
-
-/*
- * TODO(vbendeb): reverted this hack once proper timer code is in place (see
- * http://crosbug.com/p/28880 for details.
- */
-#define MIN_TIMER_FREQ 1000000
-
-uint64_t timer_hz(void)
-{
- return (CONFIG_LP_IPQ806X_TIMER_FREQ >= MIN_TIMER_FREQ) ?
- CONFIG_LP_IPQ806X_TIMER_FREQ : MIN_TIMER_FREQ;
-}
-
-uint64_t timer_raw_value(void)
-{
- uint64_t rawv = readl((void *)CONFIG_LP_IPQ806X_TIMER_REG);
-
- /*
- * This is extremely crude, but it kicks in only for the case when the
- * timer clock frequency is below 1MHz, which should never be the case
- * on a properly configured system. The compiler will eliminate the
- * check as long as config value exceeds 1MHz.
- */
- if (CONFIG_LP_IPQ806X_TIMER_FREQ < MIN_TIMER_FREQ)
- rawv *= (MIN_TIMER_FREQ / CONFIG_LP_IPQ806X_TIMER_FREQ);
-
- return rawv;
-}
diff --git a/payloads/libpayload/drivers/timer/mct.c b/payloads/libpayload/drivers/timer/mct.c
deleted file mode 100644
index 992643d..0000000
--- a/payloads/libpayload/drivers/timer/mct.c
+++ /dev/null
@@ -1,115 +0,0 @@
-/*
- * Copyright 2013 Google Inc.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- */
-
-#include <arch/io.h>
-#include <libpayload.h>
-#include <libpayload-config.h>
-#include <stdint.h>
-
-#include "config.h"
-
-struct __attribute__((packed)) mct_regs
-{
- uint32_t mct_cfg;
- uint8_t reserved0[0xfc];
- uint32_t g_cnt_l;
- uint32_t g_cnt_u;
- uint8_t reserved1[0x8];
- uint32_t g_cnt_wstat;
- uint8_t reserved2[0xec];
- uint32_t g_comp0_l;
- uint32_t g_comp0_u;
- uint32_t g_comp0_addr_incr;
- uint8_t reserved3[0x4];
- uint32_t g_comp1_l;
- uint32_t g_comp1_u;
- uint32_t g_comp1_addr_incr;
- uint8_t reserved4[0x4];
- uint32_t g_comp2_l;
- uint32_t g_comp2_u;
- uint32_t g_comp2_addr_incr;
- uint8_t reserved5[0x4];
- uint32_t g_comp3_l;
- uint32_t g_comp3_u;
- uint32_t g_comp3_addr_incr;
- uint8_t reserved6[0x4];
- uint32_t g_tcon;
- uint32_t g_int_cstat;
- uint32_t g_int_enb;
- uint32_t g_wstat;
- uint8_t reserved7[0xb0];
- uint32_t l0_tcntb;
- uint32_t l0_tcnto;
- uint32_t l0_icntb;
- uint32_t l0_icnto;
- uint32_t l0_frcntb;
- uint32_t l0_frcnto;
- uint8_t reserved8[0x8];
- uint32_t l0_tcon;
- uint8_t reserved9[0xc];
- uint32_t l0_int_cstat;
- uint32_t l0_int_enb;
- uint8_t reserved10[0x8];
- uint32_t l0_wstat;
- uint8_t reserved11[0xbc];
- uint32_t l1_tcntb;
- uint32_t l1_tcnto;
- uint32_t l1_icntb;
- uint32_t l1_icnto;
- uint32_t l1_frcntb;
- uint32_t l1_frcnto;
- uint8_t reserved12[0x8];
- uint32_t l1_tcon;
- uint8_t reserved13[0xc];
- uint32_t l1_int_cstat;
- uint32_t l1_int_enb;
- uint8_t reserved14[0x8];
- uint32_t l1_wstat;
-};
-
-uint64_t timer_hz(void)
-{
- return CONFIG_LP_TIMER_MCT_HZ;
-}
-
-uint64_t timer_raw_value(void)
-{
- static int enabled = 0;
-
- struct mct_regs * const mct =
- (struct mct_regs *)(uintptr_t)CONFIG_LP_TIMER_MCT_ADDRESS;
-
- if (!enabled) {
- writel(readl(&mct->g_tcon) | (0x1 << 8), &mct->g_tcon);
- enabled = 1;
- }
-
- uint64_t upper = readl(&mct->g_cnt_u);
- uint64_t lower = readl(&mct->g_cnt_l);
-
- return (upper << 32) | lower;
-}
diff --git a/payloads/libpayload/drivers/timer/mtk_timer.c b/payloads/libpayload/drivers/timer/mtk_timer.c
deleted file mode 100644
index 706ef48..0000000
--- a/payloads/libpayload/drivers/timer/mtk_timer.c
+++ /dev/null
@@ -1,30 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 MediaTek Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-#include <arch/io.h>
-#include <libpayload.h>
-#include <libpayload-config.h>
-#include <stdint.h>
-
-static uint32_t *const mtk_tmrus = (void*)CONFIG_LP_TIMER_MTK_ADDRESS;
-
-uint64_t timer_hz(void)
-{
- return CONFIG_LP_TIMER_MTK_HZ;
-}
-
-uint64_t timer_raw_value(void)
-{
- return (uint64_t)readl(mtk_tmrus);
-}
diff --git a/payloads/libpayload/drivers/timer/rktimer.c b/payloads/libpayload/drivers/timer/rktimer.c
deleted file mode 100644
index 5b4ce6b..0000000
--- a/payloads/libpayload/drivers/timer/rktimer.c
+++ /dev/null
@@ -1,42 +0,0 @@
-
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Rockchip Electronics
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-#include <arch/io.h>
-#include <libpayload.h>
-#include <stdint.h>
-struct rk_timer {
- u32 timer_load_count0;
- u32 timer_load_count1;
- u32 timer_curr_value0;
- u32 timer_curr_value1;
- u32 timer_ctrl_reg;
- u32 timer_int_status;
-};
-
-uint64_t timer_hz(void)
-{
- return 24000000;
-}
-
-uint64_t timer_raw_value(void)
-{
- uint64_t upper;
- uint64_t lower;
- struct rk_timer *rk_timer;
- rk_timer = (struct rk_timer *) CONFIG_LP_TIMER_RK_ADDRESS;
- lower = (uint64_t) rk_timer->timer_curr_value0;
- upper = (uint64_t) rk_timer->timer_curr_value1;
- return (upper << 32) | lower;
-}
diff --git a/payloads/libpayload/drivers/timer/tegra_1us.c b/payloads/libpayload/drivers/timer/tegra_1us.c
deleted file mode 100644
index f227ad0..0000000
--- a/payloads/libpayload/drivers/timer/tegra_1us.c
+++ /dev/null
@@ -1,41 +0,0 @@
-/*
- * Copyright 2013 Google Inc.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- */
-
-#include <libpayload.h>
-#include <libpayload-config.h>
-
-static uint32_t * const tegra_tmrus = (void *)CONFIG_LP_TIMER_TEGRA_1US_ADDRESS;
-
-uint64_t timer_hz(void)
-{
- return 1000 * 1000;
-}
-
-uint64_t timer_raw_value(void)
-{
- return readl(tegra_tmrus);
-}
Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15029
-gerrit
commit 7a1444efcd2311b8231c5fa61c5b04ee664868e1
Author: Vadim Bendebury <vbendeb(a)chromium.org>
Date: Sun May 22 15:53:37 2016 -0700
gru: kevin: define GPIOs used on both platforms
The same GPIOs are used on both platforms, definitions are added an a
new .h to make it easier to re-use them across the code.
BRANCH=none
BUG=chrome-os-partner:51537
TEST=panel backlight still enabled on Gru as before. The rest of the
GPIOs are used in the upcoming patches.
Change-Id: If06f4b33720ab4bf098d23fb91322bba23fe6e90
Signed-off-by: Martin Roth <martinroth(a)chromium.org>
Original-Commit-Id: c587880
Original-Change-Id: I1a6c5b5beb82ffcc5fea397e8e9ec2f183f4a7e0
Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/346219
Original-Tested-by: Shunqian Zheng <zhengsq(a)rock-chips.com>
---
src/mainboard/google/gru/board.h | 30 ++++++++++++++++++
src/mainboard/google/gru/mainboard.c | 60 ++++++++++++++++++++++++++++++++++++
2 files changed, 90 insertions(+)
diff --git a/src/mainboard/google/gru/board.h b/src/mainboard/google/gru/board.h
new file mode 100644
index 0000000..6d80cdf
--- /dev/null
+++ b/src/mainboard/google/gru/board.h
@@ -0,0 +1,30 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2016 Rockchip Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef __COREBOOT_SRC_MAINBOARD_GOOGLE_GRU_BOARD_H
+#define __COREBOOT_SRC_MAINBOARD_GOOGLE_GRU_BOARD_H
+
+#include <gpio.h>
+
+#define GPIO_BACKLIGHT GPIO(1, C, 1)
+#define GPIO_EC_IN_RW GPIO(3, B, 0)
+#define GPIO_EC_IRQ GPIO(0, A, 1)
+#define GPIO_RESET GPIO(0, B, 3)
+#define GPIO_WP GPIO(1, C, 2)
+
+void setup_chromeos_gpios(void);
+
+#endif /* ! __COREBOOT_SRC_MAINBOARD_GOOGLE_GRU_BOARD_H */
diff --git a/src/mainboard/google/gru/mainboard.c b/src/mainboard/google/gru/mainboard.c
index 6824cbf..54443bc 100644
--- a/src/mainboard/google/gru/mainboard.c
+++ b/src/mainboard/google/gru/mainboard.c
@@ -15,11 +15,17 @@
*/
#include <boardid.h>
+#include <delay.h>
#include <device/device.h>
+#include <device/i2c.h>
#include <gpio.h>
#include <soc/clock.h>
+#include <soc/display.h>
#include <soc/emmc.h>
#include <soc/grf.h>
+#include <soc/i2c.h>
+
+#include "board.h"
static void configure_emmc(void)
{
@@ -86,10 +92,64 @@ static void configure_sdmmc(void)
write32(&rk3399_grf->iomux_sdmmc, IOMUX_SDMMC);
}
+static void configure_display(void)
+{
+ /* set pinmux for edp HPD*/
+ gpio_input_pulldown(GPIO(4, C, 7));
+ write32(&rk3399_grf->iomux_edp_hotplug, IOMUX_EDP_HOTPLUG);
+
+ gpio_output(GPIO(4, D, 3), 1); /* CPU3_EDP_VDDEN for P3.3V_DISP */
+}
+
static void mainboard_init(device_t dev)
{
configure_sdmmc();
configure_emmc();
+ configure_display();
+}
+
+static void enable_backlight_booster(void)
+{
+ const struct {
+ uint8_t reg;
+ uint8_t value;
+ } i2c_writes[] = {
+ {1, 0x84},
+ {1, 0x85},
+ {0, 0x26}
+ };
+ int i;
+ const int booster_i2c_port = 0;
+ uint8_t i2c_buf[2];
+ struct i2c_seg i2c_command = { .read = 0, .chip = 0x2c,
+ .buf = i2c_buf, .len = sizeof(i2c_buf)
+ };
+
+ /*
+ * This function is called on Gru right after BL_EN is asserted. It
+ * takes time for the switcher chip to come online, let's wait a bit
+ * to let the voltage settle, so that the chip can be accessed.
+ */
+ udelay(1000);
+
+ /* Select pinmux for i2c0, which is the display backlight booster. */
+ write32(&rk3399_pmugrf->iomux_i2c0_sda, IOMUX_I2C0_SDA);
+ write32(&rk3399_pmugrf->iomux_i2c0_scl, IOMUX_I2C0_SCL);
+ i2c_init(0, 100*KHz);
+
+ for (i = 0; i < ARRAY_SIZE(i2c_writes); i++) {
+ i2c_buf[0] = i2c_writes[i].reg;
+ i2c_buf[1] = i2c_writes[i].value;
+ i2c_transfer(booster_i2c_port, &i2c_command, 1);
+ }
+}
+
+void mainboard_power_on_backlight(void)
+{
+ gpio_output(GPIO(1, C, 1), 1); /* BL_EN */
+
+ if (IS_ENABLED(CONFIG_BOARD_GOOGLE_GRU))
+ enable_backlight_booster();
}
static void mainboard_enable(device_t dev)
Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15028
-gerrit
commit 09ae857e6ece97b7065f0668978889b19ec09b07
Author: jongpil19.jung <jongpil19.jung(a)samsung.com>
Date: Thu May 19 12:40:00 2016 +0900
Kevin/Gru : Update Board ID table.
Add board id table as kevin/gru configuration.
BUG=chrome-os-partner:53519
BRANCH=chromeos-2016.02
TEST=check boot on Kevin board.
Change-Id: I30c16916f3cda0ac88d2ce5a922e936a405fcc89
Signed-off-by: Martin Roth <martinroth(a)chromium.org>
Original-Commit-Id: 16c7b5486befd73c3e31624970ba1c97e526676f
Original-Change-Id: Ib69ed9dad8e1a9e08717545c6be19a90e0298c43
Original-Signed-off-by: jongpil19.jung <jongpil19.jung(a)samsung.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/345736
Original-Commit-Ready: Vadim Bendebury <vbendeb(a)chromium.org>
Original-Tested-by: Vadim Bendebury <vbendeb(a)chromium.org>
Original-Reviewed-by: Vadim Bendebury <vbendeb(a)chromium.org>
---
src/mainboard/google/gru/boardid.c | 7 ++++---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/src/mainboard/google/gru/boardid.c b/src/mainboard/google/gru/boardid.c
index 5f030ad..1d37a86 100644
--- a/src/mainboard/google/gru/boardid.c
+++ b/src/mainboard/google/gru/boardid.c
@@ -19,10 +19,11 @@
#include <soc/saradc.h>
/*
- * This matches two Kevin prototypes, needs to be sorted out with HW engs to
- * have more regular mapping between the voltage and board ID.
+ * This matches Kevin/Gru ADC value for board id.
*/
-static const int board_id_readings[] = { 42, 120 };
+static const int board_id_readings[] = { 42, 120, 181, 242, 307, 378, 444,
+ 511, 581, 646, 704, 763, 828,
+ 895, 956, 1023 };
/*
* The ADC produces a 10 bit value, the resistor accuracy is 1%, let's leave
Saurabh Satija (saurabh.satija(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15026
-gerrit
commit 5936c393b49201a593cc4e2847a0207be4ac7c03
Author: Saurabh Satija <saurabh.satija(a)intel.com>
Date: Tue Mar 8 17:33:29 2016 -0800
apollolake: Add ACPI device for audio controller
Add the audio controller device to ACPI and define the _DSM handler
to return the address of the NHLT table, if set in NVS.
Change-Id: I619dbfb562b94255e42a3e5d5a3926c28b14db3e
Signed-off-by: Saurabh Satija <saurabh.satija(a)intel.com>
---
src/soc/intel/apollolake/acpi/pch.asl | 23 ++++++++
src/soc/intel/apollolake/acpi/pch_hda.asl | 89 +++++++++++++++++++++++++++++++
2 files changed, 112 insertions(+)
diff --git a/src/soc/intel/apollolake/acpi/pch.asl b/src/soc/intel/apollolake/acpi/pch.asl
new file mode 100644
index 0000000..8bcbfd7
--- /dev/null
+++ b/src/soc/intel/apollolake/acpi/pch.asl
@@ -0,0 +1,23 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2015 Google Inc.
+ * Copyright (C) 2015 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+/* PCH HDA */
+#include "pch_hda.asl"
diff --git a/src/soc/intel/apollolake/acpi/pch_hda.asl b/src/soc/intel/apollolake/acpi/pch_hda.asl
new file mode 100644
index 0000000..ac027e6
--- /dev/null
+++ b/src/soc/intel/apollolake/acpi/pch_hda.asl
@@ -0,0 +1,89 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Intel Corporation.
+ * Copyright (C) 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+/* Audio Controller - Device 14, Function 0 */
+
+Device (HDAS)
+{
+ Name (_ADR, 0x000E0000)
+ Name (_DDN, "Audio Controller")
+ Name (UUID, ToUUID ("A69F886E-6CEB-4594-A41F-7B5DCE24C553"))
+
+ /* Device is D3 wake capable */
+ Name (_S0W, 3)
+
+ /* NHLT Table Address populated from GNVS values */
+ Name (NBUF, ResourceTemplate () {
+ QWordMemory (ResourceConsumer, PosDecode, MinFixed,
+ MaxFixed, NonCacheable, ReadOnly,
+ 0, 0, 0, 0, 1,,, NHLT, AddressRangeACPI)
+ })
+
+ /*
+ * Device Specific Method
+ * Arg0 - UUID
+ * Arg1 - Revision
+ * Arg2 - Function Index
+ */
+ Method (_DSM, 4)
+ {
+ If (LEqual (Arg0, ^UUID)) {
+ /*
+ * Function 0: Function Support Query
+ * Returns a bitmask of functions supported.
+ */
+ If (LEqual (Arg2, Zero)) {
+ /*
+ * NHLT Query only supported for revision 1 and
+ * if NHLT address and length are set in NVS.
+ */
+ If (LAnd (LEqual (Arg1, One),
+ LAnd (LNotEqual (NHLA, Zero),
+ LNotEqual (NHLL, Zero)))) {
+ Return (Buffer (One) { 0x03 })
+ } Else {
+ Return (Buffer (One) { 0x01 })
+ }
+ }
+
+ /*
+ * Function 1: Query NHLT memory address used by
+ * Intel Offload Engine Driver to discover any non-HDA
+ * devices that are supported by the DSP.
+ *
+ * Returns a pointer to NHLT table in memory.
+ */
+ If (LEqual (Arg2, One)) {
+ CreateQWordField (NBUF, ^NHLT._MIN, NBAS)
+ CreateQWordField (NBUF, ^NHLT._MAX, NMAS)
+ CreateQWordField (NBUF, ^NHLT._LEN, NLEN)
+
+ Store (NHLA, NBAS)
+ Store (NHLA, NMAS)
+ Store (NHLL, NLEN)
+
+ Return (NBUF)
+ }
+ }
+
+ Return (Buffer (One) { 0x00 })
+ }
+}
+