coreboot-gerrit March 2016

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: ipq806x/storm: Return NULL for cbmem_top if DRAM is not initialized
by Furquan Shaikh 29 Mar '16

29 Mar '16

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14182 -gerrit commit 170df3445552b21110dae322b322493788f26bb3 Author: Furquan Shaikh <furquan(a)google.com> Date: Mon Mar 28 13:29:33 2016 -0700 ipq806x/storm: Return NULL for cbmem_top if DRAM is not initialized DRAM initialization on storm requires ipq blobs to be loaded from cbfs. vboot_locator first checks cbmem_find to see if cbmem is initialized and contains selected region info, else it falls back to vboot work buffer. Since cbmem_find calls into cbmem_top to identify the location of cbmem area, board/chipset is expected to return NULL until the backing store is ready, which in this case until DRAM is initialized in romstage, return NULL for cbmem_top. Change-Id: I1880ce61dcfdabaa527d7a6dcc3482dfe5d5fd17 Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- src/mainboard/google/storm/mmu.c | 2 ++ src/soc/qualcomm/ipq806x/cbmem.c | 16 ++++++++++++++++ src/soc/qualcomm/ipq806x/include/soc/soc_services.h | 3 +++ 3 files changed, 21 insertions(+) diff --git a/src/mainboard/google/storm/mmu.c b/src/mainboard/google/storm/mmu.c index 4d2e9a0..fcea8e2 100644 --- a/src/mainboard/google/storm/mmu.c +++ b/src/mainboard/google/storm/mmu.c @@ -34,6 +34,8 @@ void setup_dram_mappings(enum dram_state dram) mmu_config_range(DRAM_START, DRAM_SIZE, DCACHE_WRITEBACK); /* Map DMA memory */ mmu_config_range(DMA_START, DMA_SIZE, DCACHE_OFF); + /* Mark cbmem backing store as ready. */ + ipq_cbmem_backing_store_ready(); } else { mmu_disable_range(DRAM_START, DRAM_SIZE); /* Map DMA memory */ diff --git a/src/soc/qualcomm/ipq806x/cbmem.c b/src/soc/qualcomm/ipq806x/cbmem.c index 7aff231..05325cc 100644 --- a/src/soc/qualcomm/ipq806x/cbmem.c +++ b/src/soc/qualcomm/ipq806x/cbmem.c @@ -16,7 +16,23 @@ #include <cbmem.h> #include <soc/soc_services.h> +static int cbmem_backing_store_ready; + +void ipq_cbmem_backing_store_ready(void) +{ + cbmem_backing_store_ready = 1; +} + void *cbmem_top(void) { + /* + * In romstage, make sure that cbmem backing store is ready before + * returning pointer to cbmem top. Otherwise, it could lead to issues + * with components that utilize cbmem in romstage (e.g. vboot_locator + * for loading ipq blobs before DRAM is initialized). + */ + if (ENV_ROMSTAGE && (cbmem_backing_store_ready == 0)) + return NULL; + return _memlayout_cbmem_top; } diff --git a/src/soc/qualcomm/ipq806x/include/soc/soc_services.h b/src/soc/qualcomm/ipq806x/include/soc/soc_services.h index 7006b82..e7a6d68 100644 --- a/src/soc/qualcomm/ipq806x/include/soc/soc_services.h +++ b/src/soc/qualcomm/ipq806x/include/soc/soc_services.h @@ -32,4 +32,7 @@ int tz_init_wrapper(int, int, void *); /* Load RPM code into memory and trigger its execution. */ void start_rpm(void); +/* Mark cbmem backing store as ready. */ +void ipq_cbmem_backing_store_ready(void); + #endif

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Patch set updated for coreboot: cbmem: Add comment for cbmem_top returning NULL if backing store is not ready
by Furquan Shaikh 29 Mar '16

29 Mar '16

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14181 -gerrit commit cf920bbac86730335a1744dc136f9a6e1833c68f Author: Furquan Shaikh <furquan(a)google.com> Date: Mon Mar 28 13:23:13 2016 -0700 cbmem: Add comment for cbmem_top returning NULL if backing store is not ready Board or chipset needs to ensure that cbmem backing store is ready when returning the cbmem top address. cbmem infrastructure has no support for checking the validity of the backing store/address. E.g.: If romstage handles cbmem coming online, chipset or board need to ensure that call to cbmem_top in romstage returns NULL if the backing store is not yet initialized. Added a comment to ensure that developers know this requirement while implementing cbmem_top for future chipsets/boards. Change-Id: I0086b8e528f65190b764a84365cf9bf970b69c3f Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- src/include/cbmem.h | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/src/include/cbmem.h b/src/include/cbmem.h index 2e947a1..524bfb5 100644 --- a/src/include/cbmem.h +++ b/src/include/cbmem.h @@ -80,7 +80,10 @@ void cbmem_initialize_empty_id_size(u32 id, u64 size); /* Return the top address for dynamic cbmem. The address returned needs to * be consistent across romstage and ramstage, and it is required to be - * below 4GiB. */ + * below 4GiB. + * Board or chipset should return NULL if any interface that might rely on cbmem + * (e.g. cbfs, vboot) is used before the cbmem backing store has been + * initialized. */ void *cbmem_top(void); /* Add a cbmem entry of a given size and id. These return NULL on failure. The

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Patch set updated for coreboot: ipq806x/storm: Return NULL for cbmem_top if DRAM is not initialized
by Furquan Shaikh 29 Mar '16

29 Mar '16

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14182 -gerrit commit d2dbac9c3787fad006ddaa48556de1b28ff86b17 Author: Furquan Shaikh <furquan(a)google.com> Date: Mon Mar 28 13:29:33 2016 -0700 ipq806x/storm: Return NULL for cbmem_top if DRAM is not initialized DRAM initialization on storm requires ipq blobs to be loaded from cbfs. vboot_locator first checks cbmem_find to see if cbmem is initialized and contains selected region info, else it falls back to vboot work buffer. Since cbmem_find calls into cbmem_top to identify the location of cbmem area, board/chipset is expected to return NULL until the backing store is ready, which in this case until DRAM is initialized in romstage, return NULL for cbmem_top. Change-Id: I1880ce61dcfdabaa527d7a6dcc3482dfe5d5fd17 Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- src/mainboard/google/storm/mmu.c | 2 ++ src/soc/qualcomm/ipq806x/cbmem.c | 16 ++++++++++++++++ src/soc/qualcomm/ipq806x/include/soc/soc_services.h | 3 +++ 3 files changed, 21 insertions(+) diff --git a/src/mainboard/google/storm/mmu.c b/src/mainboard/google/storm/mmu.c index 4d2e9a0..fcea8e2 100644 --- a/src/mainboard/google/storm/mmu.c +++ b/src/mainboard/google/storm/mmu.c @@ -34,6 +34,8 @@ void setup_dram_mappings(enum dram_state dram) mmu_config_range(DRAM_START, DRAM_SIZE, DCACHE_WRITEBACK); /* Map DMA memory */ mmu_config_range(DMA_START, DMA_SIZE, DCACHE_OFF); + /* Mark cbmem backing store as ready. */ + ipq_cbmem_backing_store_ready(); } else { mmu_disable_range(DRAM_START, DRAM_SIZE); /* Map DMA memory */ diff --git a/src/soc/qualcomm/ipq806x/cbmem.c b/src/soc/qualcomm/ipq806x/cbmem.c index 7aff231..05325cc 100644 --- a/src/soc/qualcomm/ipq806x/cbmem.c +++ b/src/soc/qualcomm/ipq806x/cbmem.c @@ -16,7 +16,23 @@ #include <cbmem.h> #include <soc/soc_services.h> +static int cbmem_backing_store_ready; + +void ipq_cbmem_backing_store_ready(void) +{ + cbmem_backing_store_ready = 1; +} + void *cbmem_top(void) { + /* + * In romstage, make sure that cbmem backing store is ready before + * returning pointer to cbmem top. Otherwise, it could lead to issues + * with components that utilize cbmem in romstage (e.g. vboot_locator + * for loading ipq blobs before DRAM is initialized). + */ + if (ENV_ROMSTAGE && (cbmem_backing_store_ready == 0)) + return NULL; + return _memlayout_cbmem_top; } diff --git a/src/soc/qualcomm/ipq806x/include/soc/soc_services.h b/src/soc/qualcomm/ipq806x/include/soc/soc_services.h index 7006b82..e7a6d68 100644 --- a/src/soc/qualcomm/ipq806x/include/soc/soc_services.h +++ b/src/soc/qualcomm/ipq806x/include/soc/soc_services.h @@ -32,4 +32,7 @@ int tz_init_wrapper(int, int, void *); /* Load RPM code into memory and trigger its execution. */ void start_rpm(void); +/* Mark cbmem backing store as ready. */ +void ipq_cbmem_backing_store_ready(void); + #endif

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Patch merged into coreboot/master: nvidia/ck804/sata: Remove space before newline in debug output
by gerrit＠coreboot.org 29 Mar '16

29 Mar '16

the following patch was just integrated into master: commit 169956db9d1ad1f7751d57595a459e9e1b782957 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Sun Mar 27 22:24:08 2016 +0200 nvidia/ck804/sata: Remove space before newline in debug output In the board status repository, there is trailing whitespace in the coreboot log of the board ASUS KFSN4-DRE. ``` SATA S SATA P ``` Remove it, as it’s unnecessary. Change-Id: I5c505eb7c734dca3fa18235e2bc0bc82b5b50b16 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-on: https://review.coreboot.org/14175 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> Reviewed-by: Jonathan A. Kollasch <jakllsch(a)kollasch.net> See https://review.coreboot.org/14175 for details. -gerrit

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Patch set updated for coreboot: ipq806x/storm: Return NULL for cbmem_top if DRAM is not initialized
by Furquan Shaikh 28 Mar '16

28 Mar '16

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14182 -gerrit commit 5f8b7f41544d63a8f9e5fe871006ef7bbf547c02 Author: Furquan Shaikh <furquan(a)google.com> Date: Mon Mar 28 13:29:33 2016 -0700 ipq806x/storm: Return NULL for cbmem_top if DRAM is not initialized DRAM initialization on storm requires ipq blobs to be loaded from cbfs. vboot_locator first checks cbmem_find to see if cbmem is initialized and contains selected region info, else it falls back to vboot work buffer. Since cbmem_find calls into cbmem_top to identify the location of cbmem area, board/chipset is expected to return NULL until the backing store is ready, which in this case until DRAM is initialized in romstage, return NULL for cbmem_top. Change-Id: I1880ce61dcfdabaa527d7a6dcc3482dfe5d5fd17 Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- src/mainboard/google/storm/mmu.c | 2 ++ src/soc/qualcomm/ipq806x/cbmem.c | 16 ++++++++++++++++ src/soc/qualcomm/ipq806x/include/soc/soc_services.h | 3 +++ 3 files changed, 21 insertions(+) diff --git a/src/mainboard/google/storm/mmu.c b/src/mainboard/google/storm/mmu.c index 4d2e9a0..fcea8e2 100644 --- a/src/mainboard/google/storm/mmu.c +++ b/src/mainboard/google/storm/mmu.c @@ -34,6 +34,8 @@ void setup_dram_mappings(enum dram_state dram) mmu_config_range(DRAM_START, DRAM_SIZE, DCACHE_WRITEBACK); /* Map DMA memory */ mmu_config_range(DMA_START, DMA_SIZE, DCACHE_OFF); + /* Mark cbmem backing store as ready. */ + ipq_cbmem_backing_store_ready(); } else { mmu_disable_range(DRAM_START, DRAM_SIZE); /* Map DMA memory */ diff --git a/src/soc/qualcomm/ipq806x/cbmem.c b/src/soc/qualcomm/ipq806x/cbmem.c index 7aff231..05325cc 100644 --- a/src/soc/qualcomm/ipq806x/cbmem.c +++ b/src/soc/qualcomm/ipq806x/cbmem.c @@ -16,7 +16,23 @@ #include <cbmem.h> #include <soc/soc_services.h> +static int cbmem_backing_store_ready; + +void ipq_cbmem_backing_store_ready(void) +{ + cbmem_backing_store_ready = 1; +} + void *cbmem_top(void) { + /* + * In romstage, make sure that cbmem backing store is ready before + * returning pointer to cbmem top. Otherwise, it could lead to issues + * with components that utilize cbmem in romstage (e.g. vboot_locator + * for loading ipq blobs before DRAM is initialized). + */ + if (ENV_ROMSTAGE && (cbmem_backing_store_ready == 0)) + return NULL; + return _memlayout_cbmem_top; } diff --git a/src/soc/qualcomm/ipq806x/include/soc/soc_services.h b/src/soc/qualcomm/ipq806x/include/soc/soc_services.h index 7006b82..e7a6d68 100644 --- a/src/soc/qualcomm/ipq806x/include/soc/soc_services.h +++ b/src/soc/qualcomm/ipq806x/include/soc/soc_services.h @@ -32,4 +32,7 @@ int tz_init_wrapper(int, int, void *); /* Load RPM code into memory and trigger its execution. */ void start_rpm(void); +/* Mark cbmem backing store as ready. */ +void ipq_cbmem_backing_store_ready(void); + #endif

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New patch to review for coreboot: ipq806x/storm: Return NULL for cbmem_top if DRAM is not initialized
by Furquan Shaikh 28 Mar '16

28 Mar '16

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14182 -gerrit commit 80e2164df7b342e6504196c729ef82a1cad04342 Author: Furquan Shaikh <furquan(a)google.com> Date: Mon Mar 28 13:29:33 2016 -0700 ipq806x/storm: Return NULL for cbmem_top if DRAM is not initialized DRAM initialization on storm requires ipq blobs to be loaded from cbfs. vboot_locator first checks cbmem_find to see if cbmem is initialized and contains selected region info, else it falls back to vboot work buffer. Since cbmem_find calls into cbmem_top to identify the location of cbmem area, board/chipset is expected to return NULL until the backing store is ready, which in this case until DRAM is initialized in romstage, return NULL for cbmem_top. Change-Id: I1880ce61dcfdabaa527d7a6dcc3482dfe5d5fd17 Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- src/mainboard/google/storm/romstage.c | 3 +++ src/soc/qualcomm/ipq806x/cbmem.c | 16 ++++++++++++++++ src/soc/qualcomm/ipq806x/include/soc/soc_services.h | 3 +++ 3 files changed, 22 insertions(+) diff --git a/src/mainboard/google/storm/romstage.c b/src/mainboard/google/storm/romstage.c index c1b8654..a5438e1 100644 --- a/src/mainboard/google/storm/romstage.c +++ b/src/mainboard/google/storm/romstage.c @@ -28,6 +28,9 @@ void main(void) /* Add dram mappings to mmu tables. */ setup_dram_mappings(DRAM_INITIALIZED); + ipq_cbmem_backing_store_ready(); + cbmem_initialize_empty(); + run_ramstage(); } diff --git a/src/soc/qualcomm/ipq806x/cbmem.c b/src/soc/qualcomm/ipq806x/cbmem.c index 7aff231..05325cc 100644 --- a/src/soc/qualcomm/ipq806x/cbmem.c +++ b/src/soc/qualcomm/ipq806x/cbmem.c @@ -16,7 +16,23 @@ #include <cbmem.h> #include <soc/soc_services.h> +static int cbmem_backing_store_ready; + +void ipq_cbmem_backing_store_ready(void) +{ + cbmem_backing_store_ready = 1; +} + void *cbmem_top(void) { + /* + * In romstage, make sure that cbmem backing store is ready before + * returning pointer to cbmem top. Otherwise, it could lead to issues + * with components that utilize cbmem in romstage (e.g. vboot_locator + * for loading ipq blobs before DRAM is initialized). + */ + if (ENV_ROMSTAGE && (cbmem_backing_store_ready == 0)) + return NULL; + return _memlayout_cbmem_top; } diff --git a/src/soc/qualcomm/ipq806x/include/soc/soc_services.h b/src/soc/qualcomm/ipq806x/include/soc/soc_services.h index 7006b82..e7a6d68 100644 --- a/src/soc/qualcomm/ipq806x/include/soc/soc_services.h +++ b/src/soc/qualcomm/ipq806x/include/soc/soc_services.h @@ -32,4 +32,7 @@ int tz_init_wrapper(int, int, void *); /* Load RPM code into memory and trigger its execution. */ void start_rpm(void); +/* Mark cbmem backing store as ready. */ +void ipq_cbmem_backing_store_ready(void); + #endif

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New patch to review for coreboot: cbmem: Add comment for cbmem_top returning NULL if backing store is not ready
by Furquan Shaikh 28 Mar '16

28 Mar '16

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14181 -gerrit commit 24f05d43ae86b7cfa850d7fec4b22881a2ce3cbd Author: Furquan Shaikh <furquan(a)google.com> Date: Mon Mar 28 13:23:13 2016 -0700 cbmem: Add comment for cbmem_top returning NULL if backing store is not ready Board or chipset needs to ensure that cbmem backing store is ready when returning the cbmem top address. cbmem infrastructure has no support for checking the validity of the backing store/address. E.g.: If romstage handles cbmem coming online, chipset or board need to ensure that call to cbmem_top in romstage returns NULL if the backing store is not yet initialized. Added a comment to ensure that developers know this requirement while implementing cbmem_top for future chipsets/boards. Change-Id: I0086b8e528f65190b764a84365cf9bf970b69c3f Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- src/include/cbmem.h | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/include/cbmem.h b/src/include/cbmem.h index 2e947a1..aacc2c8 100644 --- a/src/include/cbmem.h +++ b/src/include/cbmem.h @@ -80,7 +80,9 @@ void cbmem_initialize_empty_id_size(u32 id, u64 size); /* Return the top address for dynamic cbmem. The address returned needs to * be consistent across romstage and ramstage, and it is required to be - * below 4GiB. */ + * below 4GiB. + * Board or chipset should return NULL if cbmem backing store has not been + * initialized yet. */ void *cbmem_top(void); /* Add a cbmem entry of a given size and id. These return NULL on failure. The

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Patch merged into coreboot/master: nb/amd/mct_ddr3: Use standard C function calls in mct_ResetDataStruct_D()
by gerrit＠coreboot.org 28 Mar '16

28 Mar '16

the following patch was just integrated into master: commit e2e0057ee786d0b4d5ce7b71a6dc9210fc52ae0f Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Thu Mar 24 19:31:02 2016 -0500 nb/amd/mct_ddr3: Use standard C function calls in mct_ResetDataStruct_D() Replace open coded memset() functions with calls to the library function. The new code also explicitly backs up and restores the data structures that are preserved across calls to mct_ResetDataStruct_D(), and no longer relies on structure member order to function correctly. Change-Id: I6dd6377deda0087cd1b65f7555588978657d6516 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/14165 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply(a)raptorengineeringinc.com> Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/14165 for details. -gerrit

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Patch set updated for coreboot: nb/amd/mct_ddr3: Use standard C function calls in mct_ResetDataStruct_D()
by Timothy Pearson 28 Mar '16

28 Mar '16

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14165 -gerrit commit 3344fd44180933dd635c61672e9fea42e91d5e21 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Thu Mar 24 19:31:02 2016 -0500 nb/amd/mct_ddr3: Use standard C function calls in mct_ResetDataStruct_D() Replace open coded memset() functions with calls to the library function. The new code also explicitly backs up and restores the data structures that are preserved across calls to mct_ResetDataStruct_D(), and no longer relies on structure member order to function correctly. Change-Id: I6dd6377deda0087cd1b65f7555588978657d6516 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 29 ++++++++--------------------- 1 file changed, 8 insertions(+), 21 deletions(-) diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c index e6628d5..4d9bc58 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering + * Copyright (C) 2015-2016 Raptor Engineering, LLC * Copyright (C) 2010 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify @@ -7407,38 +7407,25 @@ static u8 CheckNBCOFEarlyArbEn(struct MCTStatStruc *pMCTstat, static void mct_ResetDataStruct_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) { - u8 Node; - u32 i; + uint8_t Node; struct DCTStatStruc *pDCTstat; - u32 start, stop; - u8 *p; - u16 host_serv1, host_serv2; + uint16_t host_serv1, host_serv2; + uint8_t CH_D_B_TxDqs_bkp[2][4][9]; /* Initialize Data structures by clearing all entries to 0 */ - p = (u8 *) pMCTstat; - for (i = 0; i < sizeof(struct MCTStatStruc); i++) { - p[i] = 0; - } + memset(pMCTstat, 0, sizeof(struct MCTStatStruc)); for (Node = 0; Node < 8; Node++) { pDCTstat = pDCTstatA + Node; host_serv1 = pDCTstat->HostBiosSrvc1; host_serv2 = pDCTstat->HostBiosSrvc2; + memcpy(CH_D_B_TxDqs_bkp, pDCTstat->CH_D_B_TxDqs, sizeof(CH_D_B_TxDqs_bkp)); - p = (u8 *) pDCTstat; - start = 0; - stop = ((u32) &((struct DCTStatStruc *)0)->CH_D_DIR_B_DQS); - for (i = start; i < stop ; i++) { - p[i] = 0; - } + memset(pDCTstat, 0, sizeof(struct DCTStatStruc)); - start = ((u32) &((struct DCTStatStruc *)0)->CH_D_BC_RCVRDLY[2][4]); - stop = sizeof(struct DCTStatStruc); - for (i = start; i < stop; i++) { - p[i] = 0; - } pDCTstat->HostBiosSrvc1 = host_serv1; pDCTstat->HostBiosSrvc2 = host_serv2; + memcpy(pDCTstat->CH_D_B_TxDqs, CH_D_B_TxDqs_bkp, sizeof(pDCTstat->CH_D_B_TxDqs)); } }

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New patch to review for coreboot: nvidia/ck804/sata: Remove space before newline in debug output
by Paul Menzel 27 Mar '16

27 Mar '16

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14175 -gerrit commit 73b50b7812ab2571bf3e0a05757944f9c9dfea6e Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Sun Mar 27 22:24:08 2016 +0200 nvidia/ck804/sata: Remove space before newline in debug output In the board status repository, there is trailing whitespace in the coreboot log of the board ASUS KFSN4-DRE. ``` SATA S SATA P ``` Remove it, as it’s unnecessary. Change-Id: I5c505eb7c734dca3fa18235e2bc0bc82b5b50b16 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/southbridge/nvidia/ck804/sata.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/southbridge/nvidia/ck804/sata.c b/src/southbridge/nvidia/ck804/sata.c index 8df09bc..eeebf89 100644 --- a/src/southbridge/nvidia/ck804/sata.c +++ b/src/southbridge/nvidia/ck804/sata.c @@ -107,7 +107,7 @@ static void sata_init(struct device *dev) if (conf->sata0_enable) { /* Enable primary SATA interface. */ dword |= (1 << 1); - printk(BIOS_DEBUG, "SATA P \n"); + printk(BIOS_DEBUG, "SATA P\n"); } #if 0 /* Write back */

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coreboot-gerrit March 2016