coreboot-gerrit March 2016

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Patch set updated for coreboot: nb/intel/sandybridge/raminit: prepare raminit for fallback
by Patrick Rudolph 26 Mar '16

26 Mar '16

Patrick Rudolph (siro(a)das-labor.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14170 -gerrit commit 02d2ecf2e1a1bb8aeab6af039d673ca1f05d7e7c Author: Patrick Rudolph <siro(a)das-labor.org> Date: Fri Mar 25 18:19:47 2016 +0100 nb/intel/sandybridge/raminit: prepare raminit for fallback Return errors to top level ram init function. Required by the folowing series to implement a fallback. No functionality is changed. On error case the system still halts in every test. Change-Id: I6278c4a1d7b4a96be8988a60671fc3d72cd6cb3d Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- src/northbridge/intel/sandybridge/raminit.c | 201 ++++++++++++++++++++-------- 1 file changed, 148 insertions(+), 53 deletions(-) diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index dbec9fb..cf096a2 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -199,6 +199,8 @@ typedef struct ramctr_timing_st { #define MAX_TIMB 511 #define MAX_TIMA 127 +#define MAKE_ERR ((channel<<16)|(slotrank<<8)|1) + static void program_timings(ramctr_timing * ctrl, int channel); static const char *ecc_decoder[] = { @@ -1877,7 +1879,7 @@ static void discover_timA_fine(ramctr_timing * ctrl, int channel, int slotrank, } } -static void discover_402x(ramctr_timing * ctrl, int channel, int slotrank, +static int discover_402x(ramctr_timing *ctrl, int channel, int slotrank, int *upperA) { int works[NUM_LANES]; @@ -1895,18 +1897,26 @@ static void discover_402x(ramctr_timing * ctrl, int channel, int slotrank, all_works = 0; } if (all_works) - return; + return 0; if (!some_works) { - if (ctrl->timings[channel][slotrank].val_4024 < 2) - die("402x discovery failed"); + if (ctrl->timings[channel][slotrank].val_4024 < 2) { + printk(BIOS_EMERG, "402x discovery failed (1): %d, %d\n", + channel, slotrank); + halt(); + return MAKE_ERR; + } ctrl->timings[channel][slotrank].val_4024 -= 2; printram("4024 -= 2;\n"); continue; } ctrl->timings[channel][slotrank].val_4028 += 2; printram("4028 += 2;\n"); - if (ctrl->timings[channel][slotrank].val_4028 >= 0x10) - die("402x discovery failed"); + if (ctrl->timings[channel][slotrank].val_4028 >= 0x10) { + printk(BIOS_EMERG, "402x discovery failed (2): %d, %d\n", + channel, slotrank); + halt(); + return MAKE_ERR; + } FOR_ALL_LANES if (works[lane]) { ctrl->timings[channel][slotrank].lanes[lane].timA += 128; @@ -1915,6 +1925,7 @@ static void discover_402x(ramctr_timing * ctrl, int channel, int slotrank, slotrank, lane); } } + return 0; } struct timA_minmax { @@ -1983,9 +1994,10 @@ static void post_timA_change(ramctr_timing * ctrl, int channel, int slotrank, * Once the controller has detected this pattern a bit in the result register is * set for the current phase shift. */ -static void read_training(ramctr_timing * ctrl) +static int read_training(ramctr_timing * ctrl) { int channel, slotrank, lane; + int err; FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS { int all_high, some_high; @@ -2041,7 +2053,9 @@ static void read_training(ramctr_timing * ctrl) pre_timA_change(ctrl, channel, slotrank, &mnmx); - discover_402x(ctrl, channel, slotrank, upperA); + err = discover_402x(ctrl, channel, slotrank, upperA); + if (err) + return err; post_timA_change(ctrl, channel, slotrank, &mnmx); pre_timA_change(ctrl, channel, slotrank, &mnmx); @@ -2081,6 +2095,7 @@ static void read_training(ramctr_timing * ctrl) write32(DEFAULT_MCHBAR + 0x4080 + 0x400 * channel + 4 * lane, 0); } + return 0; } static void test_timC(ramctr_timing * ctrl, int channel, int slotrank) @@ -2167,7 +2182,7 @@ static void test_timC(ramctr_timing * ctrl, int channel, int slotrank) wait_428c(channel); } -static void discover_timC(ramctr_timing * ctrl, int channel, int slotrank) +static int discover_timC(ramctr_timing *ctrl, int channel, int slotrank) { int timC; int statistics[NUM_LANES][MAX_TIMC + 1]; @@ -2204,11 +2219,16 @@ static void discover_timC(ramctr_timing * ctrl, int channel, int slotrank) struct run rn = get_longest_zero_run(statistics[lane], MAX_TIMC + 1); ctrl->timings[channel][slotrank].lanes[lane].timC = rn.middle; - if (rn.all) - die("timC discovery failed"); + if (rn.all) { + printk(BIOS_EMERG, "timC discovery failed: %d, %d, %d\n", + channel, slotrank, lane); + halt(); + return MAKE_ERR; + } printram("Cval: %d, %d, %d: %x\n", channel, slotrank, lane, ctrl->timings[channel][slotrank].lanes[lane].timC); } + return 0; } static int get_precedening_channels(ramctr_timing * ctrl, int target_channel) @@ -2402,7 +2422,7 @@ static void test_timB(ramctr_timing * ctrl, int channel, int slotrank) 0x1080 | make_mr1(ctrl, slotrank, channel)); } -static void discover_timB(ramctr_timing * ctrl, int channel, int slotrank) +static int discover_timB(ramctr_timing *ctrl, int channel, int slotrank) { int timB; int statistics[NUM_LANES][128]; @@ -2445,11 +2465,16 @@ static void discover_timB(ramctr_timing * ctrl, int channel, int slotrank) else if ((rn.start & 0x3F) == 0x3F) rn.start += 1; ctrl->timings[channel][slotrank].lanes[lane].timB = rn.start; - if (rn.all) - die("timB discovery failed"); + if (rn.all) { + printk(BIOS_EMERG, "timB discovery failed: %d, %d, %d\n", + channel, slotrank, lane); + halt(); + return MAKE_ERR; + } printram("Bval: %d, %d, %d: %x\n", channel, slotrank, lane, ctrl->timings[channel][slotrank].lanes[lane].timB); } + return 0; } static int get_timB_high_adjust(u64 val) @@ -2606,9 +2631,10 @@ static void write_op(ramctr_timing * ctrl, int channel) * In this mode the DRAM-chip samples the CLK on every DQS edge and feeds back the * sampled value on the data lanes (DQs). */ -static void write_training(ramctr_timing * ctrl) +static int write_training(ramctr_timing * ctrl) { int channel, slotrank, lane; + int err; FOR_ALL_POPULATED_CHANNELS write32(DEFAULT_MCHBAR + 0x4008 + 0x400 * channel, @@ -2641,8 +2667,11 @@ static void write_training(ramctr_timing * ctrl) toggle_io_reset(); /* set any valid value for timB, it gets corrected later */ - FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS - discover_timB(ctrl, channel, slotrank); + FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS { + err = discover_timB(ctrl, channel, slotrank); + if (err) + return err; + } /* disable write leveling on all ranks */ FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS @@ -2691,8 +2720,11 @@ static void write_training(ramctr_timing * ctrl) write32(DEFAULT_MCHBAR + 0x4288 + (channel << 10), 0); } - FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS - discover_timC(ctrl, channel, slotrank); + FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS { + err = discover_timC(ctrl, channel, slotrank); + if (err) + return err; + } FOR_ALL_POPULATED_CHANNELS program_timings(ctrl, channel); @@ -2708,6 +2740,7 @@ static void write_training(ramctr_timing * ctrl) write32(DEFAULT_MCHBAR + 0x4080 + 0x400 * channel + 4 * lane, 0); } + return 0; } static int test_320c(ramctr_timing * ctrl, int channel, int slotrank) @@ -2876,7 +2909,7 @@ static void reprogram_320c(ramctr_timing * ctrl) #define MIN_C320C_LEN 13 -static int try_cmd_stretch(ramctr_timing * ctrl, int cmd_stretch) +static int try_cmd_stretch(ramctr_timing *ctrl, int cmd_stretch) { struct ram_rank_timings saved_timings[NUM_CHANNELS][NUM_SLOTRANKS]; int channel, slotrank; @@ -2941,19 +2974,20 @@ static int try_cmd_stretch(ramctr_timing * ctrl, int cmd_stretch) FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS { ctrl->timings[channel][slotrank] = saved_timings[channel][slotrank]; } - return 0; + return MAKE_ERR; } } } - return 1; + return 0; } /* Adjust CMD phase shift and try multiple command rates. * A command rate of 2T doubles the time needed for address and * command decode. */ -static void command_training(ramctr_timing * ctrl) +static int command_training(ramctr_timing *ctrl) { int channel; + int err; FOR_ALL_POPULATED_CHANNELS { fill_pattern5(ctrl, channel, 0); @@ -2961,17 +2995,25 @@ static void command_training(ramctr_timing * ctrl) } /* try command rate 1T and 2T */ - if (!try_cmd_stretch(ctrl, 0) && !try_cmd_stretch(ctrl, 2)) - die("c320c discovery failed"); + err = try_cmd_stretch(ctrl, 0); + if (err) { + err = try_cmd_stretch(ctrl, 2); + if (err) { + printk(BIOS_EMERG, "c320c discovery failed\n"); + halt(); + return err; + } + } FOR_ALL_POPULATED_CHANNELS { program_timings(ctrl, channel); } reprogram_320c(ctrl); + return 0; } -static void discover_edges_real(ramctr_timing * ctrl, int channel, int slotrank, +static int discover_edges_real(ramctr_timing *ctrl, int channel, int slotrank, int *edges) { int edge; @@ -3044,18 +3086,24 @@ static void discover_edges_real(ramctr_timing * ctrl, int channel, int slotrank, struct run rn = get_longest_zero_run(statistics[lane], MAX_EDGE_TIMING + 1); edges[lane] = rn.middle; - if (rn.all) - die("edge discovery failed"); + if (rn.all) { + printk(BIOS_EMERG, "edge discovery failed: %d, %d, %d\n", + channel, slotrank, lane); + halt(); + return MAKE_ERR; + } printram("eval %d, %d, %d: %02x\n", channel, slotrank, lane, edges[lane]); } + return 0; } -static void discover_edges(ramctr_timing * ctrl) +static int discover_edges(ramctr_timing *ctrl) { int falling_edges[NUM_CHANNELS][NUM_SLOTRANKS][NUM_LANES]; int rising_edges[NUM_CHANNELS][NUM_SLOTRANKS][NUM_LANES]; int channel, slotrank, lane; + int err; write32(DEFAULT_MCHBAR + 0x3400, 0); @@ -3210,16 +3258,20 @@ static void discover_edges(ramctr_timing * ctrl) printram("discover falling edges:\n[%x] = %x\n", 0x4eb0, 0x300); FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS { - discover_edges_real(ctrl, channel, slotrank, + err = discover_edges_real(ctrl, channel, slotrank, falling_edges[channel][slotrank]); + if (err) + return err; } write32(DEFAULT_MCHBAR + 0x4eb0, 0x200); printram("discover rising edges:\n[%x] = %x\n", 0x4eb0, 0x200); FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS { - discover_edges_real(ctrl, channel, slotrank, + err = discover_edges_real(ctrl, channel, slotrank, rising_edges[channel][slotrank]); + if (err) + return err; } write32(DEFAULT_MCHBAR + 0x4eb0, 0); @@ -3239,9 +3291,10 @@ static void discover_edges(ramctr_timing * ctrl) write32(DEFAULT_MCHBAR + 0x4080 + 0x400 * channel + 4 * lane, 0); } + return 0; } -static void discover_edges_write_real(ramctr_timing * ctrl, int channel, +static int discover_edges_write_real(ramctr_timing *ctrl, int channel, int slotrank, int *edges) { int edge; @@ -3353,38 +3406,47 @@ static void discover_edges_write_real(ramctr_timing * ctrl, int channel, upper[lane] = min(rn.end - ctrl->edge_offset[i], upper[lane]); edges[lane] = (lower[lane] + upper[lane]) / 2; - if (rn.all || (lower[lane] > upper[lane])) - die("edge write discovery failed"); - + if (rn.all || (lower[lane] > upper[lane])) { + printk(BIOS_EMERG, "edge write discovery failed: %d, %d, %d\n", + channel, slotrank, lane); + halt(); + return MAKE_ERR; + } } } } write32(DEFAULT_MCHBAR + 0x3000, 0); printram("CPA\n"); + return 0; } -static void discover_edges_write(ramctr_timing * ctrl) +static int discover_edges_write(ramctr_timing *ctrl) { int falling_edges[NUM_CHANNELS][NUM_SLOTRANKS][NUM_LANES]; int rising_edges[NUM_CHANNELS][NUM_SLOTRANKS][NUM_LANES]; int channel, slotrank, lane; + int err; /* FIXME: under some conditions (older chipsets?) vendor BIOS sets both edges to the same value. */ write32(DEFAULT_MCHBAR + 0x4eb0, 0x300); printram("discover falling edges write:\n[%x] = %x\n", 0x4eb0, 0x300); FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS { - discover_edges_write_real(ctrl, channel, slotrank, + err = discover_edges_write_real(ctrl, channel, slotrank, falling_edges[channel][slotrank]); + if (err) + return err; } write32(DEFAULT_MCHBAR + 0x4eb0, 0x200); printram("discover rising edges write:\n[%x] = %x\n", 0x4eb0, 0x200); FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS { - discover_edges_write_real(ctrl, channel, slotrank, + err = discover_edges_write_real(ctrl, channel, slotrank, rising_edges[channel][slotrank]); + if (err) + return err; } write32(DEFAULT_MCHBAR + 0x4eb0, 0); @@ -3403,6 +3465,7 @@ static void discover_edges_write(ramctr_timing * ctrl) write32(DEFAULT_MCHBAR + 0x4080 + 0x400 * channel + 4 * lane, 0); } + return 0; } static void test_timC_write(ramctr_timing *ctrl, int channel, int slotrank) @@ -3455,7 +3518,7 @@ static void test_timC_write(ramctr_timing *ctrl, int channel, int slotrank) wait_428c(channel); } -static void discover_timC_write(ramctr_timing * ctrl) +static int discover_timC_write(ramctr_timing *ctrl) { const u8 rege3c_b24[3] = { 0, 0xf, 0x2f }; int i, pat; @@ -3509,8 +3572,12 @@ static void discover_timC_write(ramctr_timing * ctrl) rn = get_longest_zero_run(statistics, MAX_TIMC + 1); - if (rn.all) - die("timC write discovery failed"); + if (rn.all) { + printk(BIOS_EMERG, "timC write discovery failed: %d, %d, %d\n", + channel, slotrank, lane); + halt(); + return MAKE_ERR; + } printram("timC: %d, %d, %d: 0x%02x-0x%02x-0x%02x, 0x%02x-0x%02x\n", channel, slotrank, i, rn.start, rn.middle, rn.end, @@ -3551,6 +3618,7 @@ static void discover_timC_write(ramctr_timing * ctrl) FOR_ALL_POPULATED_CHANNELS { program_timings(ctrl, channel); } + return 0; } static void normalize_training(ramctr_timing * ctrl) @@ -3585,13 +3653,18 @@ static void write_controller_mr(ramctr_timing * ctrl) } } -static void channel_test(ramctr_timing * ctrl) +static int channel_test(ramctr_timing *ctrl) { int channel, slotrank, lane; + slotrank = 0; FOR_ALL_POPULATED_CHANNELS - if (read32(DEFAULT_MCHBAR + 0x42a0 + (channel << 10)) & 0xa000) - die("Mini channel test failed (1)\n"); + if (read32(DEFAULT_MCHBAR + 0x42a0 + (channel << 10)) & 0xa000) { + printk(BIOS_EMERG, "Mini channel test failed (1): %d\n", + channel); + halt(); + return MAKE_ERR; + } FOR_ALL_POPULATED_CHANNELS { fill_pattern0(ctrl, channel, 0x12345678, 0x98765432); @@ -3633,9 +3706,14 @@ static void channel_test(ramctr_timing * ctrl) write32(DEFAULT_MCHBAR + 0x4284 + (channel << 10), 0x000c0001); wait_428c(channel); FOR_ALL_LANES - if (read32(DEFAULT_MCHBAR + 0x4340 + (channel << 10) + 4 * lane)) - die("Mini channel test failed (2)\n"); + if (read32(DEFAULT_MCHBAR + 0x4340 + (channel << 10) + 4 * lane)) { + printk(BIOS_EMERG, "Mini channel test failed (2): %d, %d, %d\n", + channel, slotrank, lane); + halt(); + return MAKE_ERR; + } } + return 0; } static void set_scrambling_seed(ramctr_timing * ctrl) @@ -3949,6 +4027,8 @@ static void restore_timings(ramctr_timing * ctrl) static int try_init_dram_ddr3(ramctr_timing *ctrl, int s3resume, int me_uma_size) { + int err; + if (!s3resume) { /* Find fastest common supported parameters */ dram_find_common_params(ctrl); @@ -4016,22 +4096,35 @@ static int try_init_dram_ddr3(ramctr_timing *ctrl, int s3resume, /* Prepare for memory training */ prepare_training(ctrl); - read_training(ctrl); - write_training(ctrl); + err = read_training(ctrl); + if (err) + return err; + + err = write_training(ctrl); + if (err) + return err; printram("CP5a\n"); - discover_edges(ctrl); + err = discover_edges(ctrl); + if (err) + return err; printram("CP5b\n"); - command_training(ctrl); + err = command_training(ctrl); + if (err) + return err; printram("CP5c\n"); - discover_edges_write(ctrl); + err = discover_edges_write(ctrl); + if (err) + return err; - discover_timC_write(ctrl); + err = discover_timC_write(ctrl); + if (err) + return err; normalize_training(ctrl); } @@ -4041,7 +4134,9 @@ static int try_init_dram_ddr3(ramctr_timing *ctrl, int s3resume, write_controller_mr(ctrl); if (!s3resume) { - channel_test(ctrl); + err = channel_test(ctrl); + if (err) + return err; } return 0;

1 0

New patch to review for coreboot: nb/intel/sandybridge/raminit: add additional fallbacks
by Patrick Rudolph 26 Mar '16

26 Mar '16

Patrick Rudolph (siro(a)das-labor.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14173 -gerrit commit 4294b0975421608aff72793fa6f6ea156692160f Author: Patrick Rudolph <siro(a)das-labor.org> Date: Sat Mar 26 12:16:29 2016 +0100 nb/intel/sandybridge/raminit: add additional fallbacks Try decreasing clock frequency twice. Disable failing channel. The system may be able to boot with a single channel enabled. Change-Id: I3be7034ad25312b3ebf47a54f335a3893f8d7cc1 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- src/northbridge/intel/sandybridge/raminit.c | 50 +++++++++++++++++++++++++++-- 1 file changed, 48 insertions(+), 2 deletions(-) diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index 3bfb900..d370da4 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -201,6 +201,7 @@ typedef struct ramctr_timing_st { #define MAX_TIMA 127 #define MAKE_ERR ((channel<<16)|(slotrank<<8)|1) +#define GET_ERR_CHANNEL(x) (x>>16) static void program_timings(ramctr_timing * ctrl, int channel); @@ -241,6 +242,18 @@ static void toggle_io_reset(void) { } /* + * Disable a channel in ramctr_timing. + */ +static void disable_channel(ramctr_timing *ctrl, int channel) { + ctrl->rankmap[channel] = 0; + memset(&ctrl->rank_mirror[channel][0], 0, sizeof(ctrl->rank_mirror[0])); + ctrl->channel_size_mb[channel] = 0; + ctrl->cmd_stretch[channel] = 0; + ctrl->mad_dimm[channel] = 0; + memset(&ctrl->timings[channel][0], 0, sizeof(ctrl->timings[0])); +} + +/* * Fill cbmem with information for SMBIOS type 17. */ static void fill_smbios17(ramctr_timing *ctrl) @@ -4042,6 +4055,8 @@ static int try_init_dram_ddr3(ramctr_timing *ctrl, int fast_boot, { int err; + printk(BIOS_DEBUG, "Starting RAM training.\n"); + if (!fast_boot) { /* Find fastest common supported parameters */ dram_find_common_params(ctrl); @@ -4233,16 +4248,47 @@ void init_dram_ddr3(spd_raw_data *spds, int mobile, int min_tck, ctrl.mobile = mobile; ctrl.tCK = min_tck; - printk(BIOS_DEBUG, "Starting RAM training.\n"); - /* Get DDR3 SPD data */ dram_find_spds_ddr3(spds, &ctrl); } err = try_init_dram_ddr3(&ctrl, fast_boot, me_uma_size); + if (!err) + goto done; + + /* fallback: lower clock frequency */ + printk(BIOS_ERR, "RAM training failed, trying fallback.\n"); + printram("Decreasing clock frequency.\n"); + ctrl.tCK++; + + err = try_init_dram_ddr3(&ctrl, fast_boot, me_uma_size); + if (!err) + goto done; + + /* fallback: lower clock frequency */ + printk(BIOS_ERR, "RAM training failed, trying fallback.\n"); + printram("Decreasing clock frequency.\n"); + ctrl.tCK++; + + err = try_init_dram_ddr3(&ctrl, fast_boot, me_uma_size); + if (!err) + goto done; + + /* fallback: disable failing channel */ + printk(BIOS_ERR, "RAM training failed, trying fallback.\n"); + printram("Disable failing channel.\n"); + + /* Reset DDR3 frequency */ + dram_find_spds_ddr3(spds, &ctrl); + + /* disable failing channel */ + disable_channel(&ctrl, GET_ERR_CHANNEL(err)); + + err = try_init_dram_ddr3(&ctrl, fast_boot, me_uma_size); if (err) die("raminit failed"); +done: /* FIXME: should be hardware revision-dependent. */ write32(DEFAULT_MCHBAR + 0x5024, 0x00a030ce);

1 0

New patch to review for coreboot: nb/intel/sandybridge/raminit: always use mrccache
by Patrick Rudolph 26 Mar '16

26 Mar '16

Patrick Rudolph (siro(a)das-labor.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14172 -gerrit commit dd3089844841717d4c00b722301ac2fc0686b769 Author: Patrick Rudolph <siro(a)das-labor.org> Date: Sun Mar 13 11:07:45 2016 +0100 nb/intel/sandybridge/raminit: always use mrccache Always use MRC cache if possible. Added a CRC16 array to make sure the DIMMs haven't been replaced. In case one of the CRC's doesn't match, start normal RAM training. Use new fallback in case of broken mrc cache. Test system: * Gigabyte GA-B75M-D3H * Intel Pentium CPU G2130 Change-Id: Ib48fe8380446846df17d37b22968f7d4fd6b9b13 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- src/northbridge/intel/sandybridge/raminit.c | 95 +++++++++++++++++++++-------- 1 file changed, 71 insertions(+), 24 deletions(-) diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index 48ec5b5..3bfb900 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -135,6 +135,7 @@ struct ram_rank_timings { struct ramctr_timing_st; typedef struct ramctr_timing_st { + u16 spd_crc[NUM_CHANNELS][NUM_SLOTS]; int mobile; u16 cas_supported; @@ -324,6 +325,24 @@ static void report_memory_config(void) } } +/* + * Return CRC16 match for all SPDs. + */ +static int verify_crc16_spds_ddr3(spd_raw_data *spd, ramctr_timing *ctrl) +{ + int channel, slot, spd_slot; + int match = 1; + + FOR_ALL_CHANNELS { + for (slot = 0; slot < NUM_SLOTS; slot++) { + spd_slot = 2 * channel + slot; + match &= ctrl->spd_crc[channel][slot] == + spd_ddr3_calc_crc(spd[spd_slot], sizeof(spd_raw_data)); + } + } + return match; +} + void read_spd(spd_raw_data * spd, u8 addr) { int j; @@ -376,6 +395,10 @@ static void dram_find_spds_ddr3(spd_raw_data *spd, ramctr_timing *ctrl) spd_decode_ddr3(&dimm->dimm[channel][slot], spd[spd_slot]); } + /* fill in CRC16 for MRC cache */ + ctrl->spd_crc[channel][slot] = + spd_ddr3_calc_crc(spd[spd_slot], sizeof(spd_raw_data)); + if (dimm->dimm[channel][slot].dram_type != SPD_MEMORY_TYPE_SDRAM_DDR3) { // set dimm invalid dimm->dimm[channel][slot].ranks = 0; @@ -4014,12 +4037,12 @@ static void restore_timings(ramctr_timing * ctrl) write32(DEFAULT_MCHBAR + 0x4ea8, 0); } -static int try_init_dram_ddr3(ramctr_timing *ctrl, int s3resume, +static int try_init_dram_ddr3(ramctr_timing *ctrl, int fast_boot, int me_uma_size) { int err; - if (!s3resume) { + if (!fast_boot) { /* Find fastest common supported parameters */ dram_find_common_params(ctrl); @@ -4029,7 +4052,7 @@ static int try_init_dram_ddr3(ramctr_timing *ctrl, int s3resume, /* Set MCU frequency */ dram_freq(ctrl); - if (!s3resume) { + if (!fast_boot) { /* Calculate timings */ dram_timing(ctrl); } @@ -4072,7 +4095,7 @@ static int try_init_dram_ddr3(ramctr_timing *ctrl, int s3resume, udelay(1); - if (s3resume) { + if (fast_boot) { restore_timings(ctrl); } else { /* Do jedec ddr3 reset sequence */ @@ -4123,11 +4146,9 @@ static int try_init_dram_ddr3(ramctr_timing *ctrl, int s3resume, write_controller_mr(ctrl); - if (!s3resume) { - err = channel_test(ctrl); - if (err) - return err; - } + err = channel_test(ctrl); + if (err) + return err; return 0; } @@ -4138,6 +4159,9 @@ void init_dram_ddr3(spd_raw_data *spds, int mobile, int min_tck, int me_uma_size; int cbmem_was_inited; ramctr_timing ctrl; + int fast_boot; + struct mrc_data_container *mrc_cache; + ramctr_timing *ctrl_cached; int err; MCHBAR32(0x5f00) |= 1; @@ -4171,28 +4195,51 @@ void init_dram_ddr3(spd_raw_data *spds, int mobile, int min_tck, early_pch_init_native(); early_thermal_init(); - ctrl.mobile = mobile; - ctrl.tCK = min_tck; - - /* FIXME: for non-S3 we should be able to use timing caching with - proper verification. Right now we use timings only for S3 case. - */ - if (s3resume) { - struct mrc_data_container *mrc_cache; - - mrc_cache = find_current_mrc_cache(); - if (!mrc_cache || (mrc_cache->mrc_data_size < sizeof(ctrl))) { + /* try to find timings in MRC cache */ + mrc_cache = find_current_mrc_cache(); + if (!mrc_cache || (mrc_cache->mrc_data_size < sizeof(ctrl))) { + if (s3resume) { /* Failed S3 resume, reset to come up cleanly */ outb(0x6, 0xcf9); halt(); } - memcpy(&ctrl, mrc_cache->mrc_data, sizeof(ctrl)); + ctrl_cached = NULL; } else { + ctrl_cached = (ramctr_timing *)mrc_cache->mrc_data; + } + + /* verify MRC cache for fast boot */ + if (ctrl_cached) { + /* check SPD CRC16 to make sure the DIMMs haven't been replaced */ + fast_boot = verify_crc16_spds_ddr3(spds, ctrl_cached); + if (!fast_boot) + printk(BIOS_DEBUG, "Stored timings CRC16 mismatch.\n"); + } else + fast_boot = 0; + + if (fast_boot) { + printk(BIOS_DEBUG, "Trying stored timings.\n"); + memcpy(&ctrl, ctrl_cached, sizeof(ctrl)); + + err = try_init_dram_ddr3(&ctrl, fast_boot, me_uma_size); + if (err) { + printk(BIOS_ERR, "Stored timings are invalid !\n"); + fast_boot = 0; + /* no need to erase bad mrc cache here, it gets overritten on + * successful boot. */ + } + } + if (!fast_boot) { + ctrl.mobile = mobile; + ctrl.tCK = min_tck; + + printk(BIOS_DEBUG, "Starting RAM training.\n"); + /* Get DDR3 SPD data */ dram_find_spds_ddr3(spds, &ctrl); } - err = try_init_dram_ddr3(&ctrl, s3resume, me_uma_size); + err = try_init_dram_ddr3(&ctrl, fast_boot, me_uma_size); if (err) die("raminit failed"); @@ -4208,7 +4255,7 @@ void init_dram_ddr3(spd_raw_data *spds, int mobile, int min_tck, /* Zone config */ dram_zones(&ctrl, 0); - if (!s3resume) + if (!fast_boot) quick_ram_check(); intel_early_me_status(); @@ -4218,7 +4265,7 @@ void init_dram_ddr3(spd_raw_data *spds, int mobile, int min_tck, report_memory_config(); cbmem_was_inited = !cbmem_recovery(s3resume); - if (!s3resume) + if (!fast_boot) save_timings(&ctrl); if (s3resume && !cbmem_was_inited) { /* Failed S3 resume, reset to come up cleanly */

1 0

New patch to review for coreboot: nb/intel/sandybridge/raminit: die in toplevel function
by Patrick Rudolph 26 Mar '16

26 Mar '16

Patrick Rudolph (siro(a)das-labor.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14171 -gerrit commit 4e0ac74c0ac7fe9f3d080f124d781e80f039fa74 Author: Patrick Rudolph <siro(a)das-labor.org> Date: Sat Mar 26 12:22:34 2016 +0100 nb/intel/sandybridge/raminit: die in toplevel function In error case die in top level function. No functionality is changed. Change-Id: Ie15b01184d40bdbce20d49dcab2f9fb607068c7a Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- src/northbridge/intel/sandybridge/raminit.c | 15 ++++----------- 1 file changed, 4 insertions(+), 11 deletions(-) diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index cf096a2..48ec5b5 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -1902,7 +1902,6 @@ static int discover_402x(ramctr_timing *ctrl, int channel, int slotrank, if (ctrl->timings[channel][slotrank].val_4024 < 2) { printk(BIOS_EMERG, "402x discovery failed (1): %d, %d\n", channel, slotrank); - halt(); return MAKE_ERR; } ctrl->timings[channel][slotrank].val_4024 -= 2; @@ -1914,7 +1913,6 @@ static int discover_402x(ramctr_timing *ctrl, int channel, int slotrank, if (ctrl->timings[channel][slotrank].val_4028 >= 0x10) { printk(BIOS_EMERG, "402x discovery failed (2): %d, %d\n", channel, slotrank); - halt(); return MAKE_ERR; } FOR_ALL_LANES if (works[lane]) { @@ -2222,7 +2220,6 @@ static int discover_timC(ramctr_timing *ctrl, int channel, int slotrank) if (rn.all) { printk(BIOS_EMERG, "timC discovery failed: %d, %d, %d\n", channel, slotrank, lane); - halt(); return MAKE_ERR; } printram("Cval: %d, %d, %d: %x\n", channel, slotrank, @@ -2468,7 +2465,6 @@ static int discover_timB(ramctr_timing *ctrl, int channel, int slotrank) if (rn.all) { printk(BIOS_EMERG, "timB discovery failed: %d, %d, %d\n", channel, slotrank, lane); - halt(); return MAKE_ERR; } printram("Bval: %d, %d, %d: %x\n", channel, slotrank, @@ -3000,7 +2996,6 @@ static int command_training(ramctr_timing *ctrl) err = try_cmd_stretch(ctrl, 2); if (err) { printk(BIOS_EMERG, "c320c discovery failed\n"); - halt(); return err; } } @@ -3089,7 +3084,6 @@ static int discover_edges_real(ramctr_timing *ctrl, int channel, int slotrank, if (rn.all) { printk(BIOS_EMERG, "edge discovery failed: %d, %d, %d\n", channel, slotrank, lane); - halt(); return MAKE_ERR; } printram("eval %d, %d, %d: %02x\n", channel, slotrank, @@ -3409,7 +3403,6 @@ static int discover_edges_write_real(ramctr_timing *ctrl, int channel, if (rn.all || (lower[lane] > upper[lane])) { printk(BIOS_EMERG, "edge write discovery failed: %d, %d, %d\n", channel, slotrank, lane); - halt(); return MAKE_ERR; } } @@ -3575,7 +3568,6 @@ static int discover_timC_write(ramctr_timing *ctrl) if (rn.all) { printk(BIOS_EMERG, "timC write discovery failed: %d, %d, %d\n", channel, slotrank, lane); - halt(); return MAKE_ERR; } printram("timC: %d, %d, %d: 0x%02x-0x%02x-0x%02x, 0x%02x-0x%02x\n", @@ -3662,7 +3654,6 @@ static int channel_test(ramctr_timing *ctrl) if (read32(DEFAULT_MCHBAR + 0x42a0 + (channel << 10)) & 0xa000) { printk(BIOS_EMERG, "Mini channel test failed (1): %d\n", channel); - halt(); return MAKE_ERR; } FOR_ALL_POPULATED_CHANNELS { @@ -3709,7 +3700,6 @@ static int channel_test(ramctr_timing *ctrl) if (read32(DEFAULT_MCHBAR + 0x4340 + (channel << 10) + 4 * lane)) { printk(BIOS_EMERG, "Mini channel test failed (2): %d, %d, %d\n", channel, slotrank, lane); - halt(); return MAKE_ERR; } } @@ -4148,6 +4138,7 @@ void init_dram_ddr3(spd_raw_data *spds, int mobile, int min_tck, int me_uma_size; int cbmem_was_inited; ramctr_timing ctrl; + int err; MCHBAR32(0x5f00) |= 1; @@ -4201,7 +4192,9 @@ void init_dram_ddr3(spd_raw_data *spds, int mobile, int min_tck, dram_find_spds_ddr3(spds, &ctrl); } - try_init_dram_ddr3(&ctrl, s3resume, me_uma_size); + err = try_init_dram_ddr3(&ctrl, s3resume, me_uma_size); + if (err) + die("raminit failed"); /* FIXME: should be hardware revision-dependent. */ write32(DEFAULT_MCHBAR + 0x5024, 0x00a030ce);

1 0

New patch to review for coreboot: nb/sandybridge/raminit: prepare raminit for fallback
by Patrick Rudolph 26 Mar '16

26 Mar '16

Patrick Rudolph (siro(a)das-labor.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14170 -gerrit commit a075f2f68db3c52c7cab35879ee94e83cd4ab3bd Author: Patrick Rudolph <siro(a)das-labor.org> Date: Fri Mar 25 18:19:47 2016 +0100 nb/sandybridge/raminit: prepare raminit for fallback Return errors to top level ram init function. Required by the folowing series to implement a fallback. No functionality is changed. On error case the system still halts in every test. Change-Id: I6278c4a1d7b4a96be8988a60671fc3d72cd6cb3d Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- src/northbridge/intel/sandybridge/raminit.c | 201 ++++++++++++++++++++-------- 1 file changed, 148 insertions(+), 53 deletions(-) diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index dbec9fb..cf096a2 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -199,6 +199,8 @@ typedef struct ramctr_timing_st { #define MAX_TIMB 511 #define MAX_TIMA 127 +#define MAKE_ERR ((channel<<16)|(slotrank<<8)|1) + static void program_timings(ramctr_timing * ctrl, int channel); static const char *ecc_decoder[] = { @@ -1877,7 +1879,7 @@ static void discover_timA_fine(ramctr_timing * ctrl, int channel, int slotrank, } } -static void discover_402x(ramctr_timing * ctrl, int channel, int slotrank, +static int discover_402x(ramctr_timing *ctrl, int channel, int slotrank, int *upperA) { int works[NUM_LANES]; @@ -1895,18 +1897,26 @@ static void discover_402x(ramctr_timing * ctrl, int channel, int slotrank, all_works = 0; } if (all_works) - return; + return 0; if (!some_works) { - if (ctrl->timings[channel][slotrank].val_4024 < 2) - die("402x discovery failed"); + if (ctrl->timings[channel][slotrank].val_4024 < 2) { + printk(BIOS_EMERG, "402x discovery failed (1): %d, %d\n", + channel, slotrank); + halt(); + return MAKE_ERR; + } ctrl->timings[channel][slotrank].val_4024 -= 2; printram("4024 -= 2;\n"); continue; } ctrl->timings[channel][slotrank].val_4028 += 2; printram("4028 += 2;\n"); - if (ctrl->timings[channel][slotrank].val_4028 >= 0x10) - die("402x discovery failed"); + if (ctrl->timings[channel][slotrank].val_4028 >= 0x10) { + printk(BIOS_EMERG, "402x discovery failed (2): %d, %d\n", + channel, slotrank); + halt(); + return MAKE_ERR; + } FOR_ALL_LANES if (works[lane]) { ctrl->timings[channel][slotrank].lanes[lane].timA += 128; @@ -1915,6 +1925,7 @@ static void discover_402x(ramctr_timing * ctrl, int channel, int slotrank, slotrank, lane); } } + return 0; } struct timA_minmax { @@ -1983,9 +1994,10 @@ static void post_timA_change(ramctr_timing * ctrl, int channel, int slotrank, * Once the controller has detected this pattern a bit in the result register is * set for the current phase shift. */ -static void read_training(ramctr_timing * ctrl) +static int read_training(ramctr_timing * ctrl) { int channel, slotrank, lane; + int err; FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS { int all_high, some_high; @@ -2041,7 +2053,9 @@ static void read_training(ramctr_timing * ctrl) pre_timA_change(ctrl, channel, slotrank, &mnmx); - discover_402x(ctrl, channel, slotrank, upperA); + err = discover_402x(ctrl, channel, slotrank, upperA); + if (err) + return err; post_timA_change(ctrl, channel, slotrank, &mnmx); pre_timA_change(ctrl, channel, slotrank, &mnmx); @@ -2081,6 +2095,7 @@ static void read_training(ramctr_timing * ctrl) write32(DEFAULT_MCHBAR + 0x4080 + 0x400 * channel + 4 * lane, 0); } + return 0; } static void test_timC(ramctr_timing * ctrl, int channel, int slotrank) @@ -2167,7 +2182,7 @@ static void test_timC(ramctr_timing * ctrl, int channel, int slotrank) wait_428c(channel); } -static void discover_timC(ramctr_timing * ctrl, int channel, int slotrank) +static int discover_timC(ramctr_timing *ctrl, int channel, int slotrank) { int timC; int statistics[NUM_LANES][MAX_TIMC + 1]; @@ -2204,11 +2219,16 @@ static void discover_timC(ramctr_timing * ctrl, int channel, int slotrank) struct run rn = get_longest_zero_run(statistics[lane], MAX_TIMC + 1); ctrl->timings[channel][slotrank].lanes[lane].timC = rn.middle; - if (rn.all) - die("timC discovery failed"); + if (rn.all) { + printk(BIOS_EMERG, "timC discovery failed: %d, %d, %d\n", + channel, slotrank, lane); + halt(); + return MAKE_ERR; + } printram("Cval: %d, %d, %d: %x\n", channel, slotrank, lane, ctrl->timings[channel][slotrank].lanes[lane].timC); } + return 0; } static int get_precedening_channels(ramctr_timing * ctrl, int target_channel) @@ -2402,7 +2422,7 @@ static void test_timB(ramctr_timing * ctrl, int channel, int slotrank) 0x1080 | make_mr1(ctrl, slotrank, channel)); } -static void discover_timB(ramctr_timing * ctrl, int channel, int slotrank) +static int discover_timB(ramctr_timing *ctrl, int channel, int slotrank) { int timB; int statistics[NUM_LANES][128]; @@ -2445,11 +2465,16 @@ static void discover_timB(ramctr_timing * ctrl, int channel, int slotrank) else if ((rn.start & 0x3F) == 0x3F) rn.start += 1; ctrl->timings[channel][slotrank].lanes[lane].timB = rn.start; - if (rn.all) - die("timB discovery failed"); + if (rn.all) { + printk(BIOS_EMERG, "timB discovery failed: %d, %d, %d\n", + channel, slotrank, lane); + halt(); + return MAKE_ERR; + } printram("Bval: %d, %d, %d: %x\n", channel, slotrank, lane, ctrl->timings[channel][slotrank].lanes[lane].timB); } + return 0; } static int get_timB_high_adjust(u64 val) @@ -2606,9 +2631,10 @@ static void write_op(ramctr_timing * ctrl, int channel) * In this mode the DRAM-chip samples the CLK on every DQS edge and feeds back the * sampled value on the data lanes (DQs). */ -static void write_training(ramctr_timing * ctrl) +static int write_training(ramctr_timing * ctrl) { int channel, slotrank, lane; + int err; FOR_ALL_POPULATED_CHANNELS write32(DEFAULT_MCHBAR + 0x4008 + 0x400 * channel, @@ -2641,8 +2667,11 @@ static void write_training(ramctr_timing * ctrl) toggle_io_reset(); /* set any valid value for timB, it gets corrected later */ - FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS - discover_timB(ctrl, channel, slotrank); + FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS { + err = discover_timB(ctrl, channel, slotrank); + if (err) + return err; + } /* disable write leveling on all ranks */ FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS @@ -2691,8 +2720,11 @@ static void write_training(ramctr_timing * ctrl) write32(DEFAULT_MCHBAR + 0x4288 + (channel << 10), 0); } - FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS - discover_timC(ctrl, channel, slotrank); + FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS { + err = discover_timC(ctrl, channel, slotrank); + if (err) + return err; + } FOR_ALL_POPULATED_CHANNELS program_timings(ctrl, channel); @@ -2708,6 +2740,7 @@ static void write_training(ramctr_timing * ctrl) write32(DEFAULT_MCHBAR + 0x4080 + 0x400 * channel + 4 * lane, 0); } + return 0; } static int test_320c(ramctr_timing * ctrl, int channel, int slotrank) @@ -2876,7 +2909,7 @@ static void reprogram_320c(ramctr_timing * ctrl) #define MIN_C320C_LEN 13 -static int try_cmd_stretch(ramctr_timing * ctrl, int cmd_stretch) +static int try_cmd_stretch(ramctr_timing *ctrl, int cmd_stretch) { struct ram_rank_timings saved_timings[NUM_CHANNELS][NUM_SLOTRANKS]; int channel, slotrank; @@ -2941,19 +2974,20 @@ static int try_cmd_stretch(ramctr_timing * ctrl, int cmd_stretch) FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS { ctrl->timings[channel][slotrank] = saved_timings[channel][slotrank]; } - return 0; + return MAKE_ERR; } } } - return 1; + return 0; } /* Adjust CMD phase shift and try multiple command rates. * A command rate of 2T doubles the time needed for address and * command decode. */ -static void command_training(ramctr_timing * ctrl) +static int command_training(ramctr_timing *ctrl) { int channel; + int err; FOR_ALL_POPULATED_CHANNELS { fill_pattern5(ctrl, channel, 0); @@ -2961,17 +2995,25 @@ static void command_training(ramctr_timing * ctrl) } /* try command rate 1T and 2T */ - if (!try_cmd_stretch(ctrl, 0) && !try_cmd_stretch(ctrl, 2)) - die("c320c discovery failed"); + err = try_cmd_stretch(ctrl, 0); + if (err) { + err = try_cmd_stretch(ctrl, 2); + if (err) { + printk(BIOS_EMERG, "c320c discovery failed\n"); + halt(); + return err; + } + } FOR_ALL_POPULATED_CHANNELS { program_timings(ctrl, channel); } reprogram_320c(ctrl); + return 0; } -static void discover_edges_real(ramctr_timing * ctrl, int channel, int slotrank, +static int discover_edges_real(ramctr_timing *ctrl, int channel, int slotrank, int *edges) { int edge; @@ -3044,18 +3086,24 @@ static void discover_edges_real(ramctr_timing * ctrl, int channel, int slotrank, struct run rn = get_longest_zero_run(statistics[lane], MAX_EDGE_TIMING + 1); edges[lane] = rn.middle; - if (rn.all) - die("edge discovery failed"); + if (rn.all) { + printk(BIOS_EMERG, "edge discovery failed: %d, %d, %d\n", + channel, slotrank, lane); + halt(); + return MAKE_ERR; + } printram("eval %d, %d, %d: %02x\n", channel, slotrank, lane, edges[lane]); } + return 0; } -static void discover_edges(ramctr_timing * ctrl) +static int discover_edges(ramctr_timing *ctrl) { int falling_edges[NUM_CHANNELS][NUM_SLOTRANKS][NUM_LANES]; int rising_edges[NUM_CHANNELS][NUM_SLOTRANKS][NUM_LANES]; int channel, slotrank, lane; + int err; write32(DEFAULT_MCHBAR + 0x3400, 0); @@ -3210,16 +3258,20 @@ static void discover_edges(ramctr_timing * ctrl) printram("discover falling edges:\n[%x] = %x\n", 0x4eb0, 0x300); FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS { - discover_edges_real(ctrl, channel, slotrank, + err = discover_edges_real(ctrl, channel, slotrank, falling_edges[channel][slotrank]); + if (err) + return err; } write32(DEFAULT_MCHBAR + 0x4eb0, 0x200); printram("discover rising edges:\n[%x] = %x\n", 0x4eb0, 0x200); FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS { - discover_edges_real(ctrl, channel, slotrank, + err = discover_edges_real(ctrl, channel, slotrank, rising_edges[channel][slotrank]); + if (err) + return err; } write32(DEFAULT_MCHBAR + 0x4eb0, 0); @@ -3239,9 +3291,10 @@ static void discover_edges(ramctr_timing * ctrl) write32(DEFAULT_MCHBAR + 0x4080 + 0x400 * channel + 4 * lane, 0); } + return 0; } -static void discover_edges_write_real(ramctr_timing * ctrl, int channel, +static int discover_edges_write_real(ramctr_timing *ctrl, int channel, int slotrank, int *edges) { int edge; @@ -3353,38 +3406,47 @@ static void discover_edges_write_real(ramctr_timing * ctrl, int channel, upper[lane] = min(rn.end - ctrl->edge_offset[i], upper[lane]); edges[lane] = (lower[lane] + upper[lane]) / 2; - if (rn.all || (lower[lane] > upper[lane])) - die("edge write discovery failed"); - + if (rn.all || (lower[lane] > upper[lane])) { + printk(BIOS_EMERG, "edge write discovery failed: %d, %d, %d\n", + channel, slotrank, lane); + halt(); + return MAKE_ERR; + } } } } write32(DEFAULT_MCHBAR + 0x3000, 0); printram("CPA\n"); + return 0; } -static void discover_edges_write(ramctr_timing * ctrl) +static int discover_edges_write(ramctr_timing *ctrl) { int falling_edges[NUM_CHANNELS][NUM_SLOTRANKS][NUM_LANES]; int rising_edges[NUM_CHANNELS][NUM_SLOTRANKS][NUM_LANES]; int channel, slotrank, lane; + int err; /* FIXME: under some conditions (older chipsets?) vendor BIOS sets both edges to the same value. */ write32(DEFAULT_MCHBAR + 0x4eb0, 0x300); printram("discover falling edges write:\n[%x] = %x\n", 0x4eb0, 0x300); FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS { - discover_edges_write_real(ctrl, channel, slotrank, + err = discover_edges_write_real(ctrl, channel, slotrank, falling_edges[channel][slotrank]); + if (err) + return err; } write32(DEFAULT_MCHBAR + 0x4eb0, 0x200); printram("discover rising edges write:\n[%x] = %x\n", 0x4eb0, 0x200); FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS { - discover_edges_write_real(ctrl, channel, slotrank, + err = discover_edges_write_real(ctrl, channel, slotrank, rising_edges[channel][slotrank]); + if (err) + return err; } write32(DEFAULT_MCHBAR + 0x4eb0, 0); @@ -3403,6 +3465,7 @@ static void discover_edges_write(ramctr_timing * ctrl) write32(DEFAULT_MCHBAR + 0x4080 + 0x400 * channel + 4 * lane, 0); } + return 0; } static void test_timC_write(ramctr_timing *ctrl, int channel, int slotrank) @@ -3455,7 +3518,7 @@ static void test_timC_write(ramctr_timing *ctrl, int channel, int slotrank) wait_428c(channel); } -static void discover_timC_write(ramctr_timing * ctrl) +static int discover_timC_write(ramctr_timing *ctrl) { const u8 rege3c_b24[3] = { 0, 0xf, 0x2f }; int i, pat; @@ -3509,8 +3572,12 @@ static void discover_timC_write(ramctr_timing * ctrl) rn = get_longest_zero_run(statistics, MAX_TIMC + 1); - if (rn.all) - die("timC write discovery failed"); + if (rn.all) { + printk(BIOS_EMERG, "timC write discovery failed: %d, %d, %d\n", + channel, slotrank, lane); + halt(); + return MAKE_ERR; + } printram("timC: %d, %d, %d: 0x%02x-0x%02x-0x%02x, 0x%02x-0x%02x\n", channel, slotrank, i, rn.start, rn.middle, rn.end, @@ -3551,6 +3618,7 @@ static void discover_timC_write(ramctr_timing * ctrl) FOR_ALL_POPULATED_CHANNELS { program_timings(ctrl, channel); } + return 0; } static void normalize_training(ramctr_timing * ctrl) @@ -3585,13 +3653,18 @@ static void write_controller_mr(ramctr_timing * ctrl) } } -static void channel_test(ramctr_timing * ctrl) +static int channel_test(ramctr_timing *ctrl) { int channel, slotrank, lane; + slotrank = 0; FOR_ALL_POPULATED_CHANNELS - if (read32(DEFAULT_MCHBAR + 0x42a0 + (channel << 10)) & 0xa000) - die("Mini channel test failed (1)\n"); + if (read32(DEFAULT_MCHBAR + 0x42a0 + (channel << 10)) & 0xa000) { + printk(BIOS_EMERG, "Mini channel test failed (1): %d\n", + channel); + halt(); + return MAKE_ERR; + } FOR_ALL_POPULATED_CHANNELS { fill_pattern0(ctrl, channel, 0x12345678, 0x98765432); @@ -3633,9 +3706,14 @@ static void channel_test(ramctr_timing * ctrl) write32(DEFAULT_MCHBAR + 0x4284 + (channel << 10), 0x000c0001); wait_428c(channel); FOR_ALL_LANES - if (read32(DEFAULT_MCHBAR + 0x4340 + (channel << 10) + 4 * lane)) - die("Mini channel test failed (2)\n"); + if (read32(DEFAULT_MCHBAR + 0x4340 + (channel << 10) + 4 * lane)) { + printk(BIOS_EMERG, "Mini channel test failed (2): %d, %d, %d\n", + channel, slotrank, lane); + halt(); + return MAKE_ERR; + } } + return 0; } static void set_scrambling_seed(ramctr_timing * ctrl) @@ -3949,6 +4027,8 @@ static void restore_timings(ramctr_timing * ctrl) static int try_init_dram_ddr3(ramctr_timing *ctrl, int s3resume, int me_uma_size) { + int err; + if (!s3resume) { /* Find fastest common supported parameters */ dram_find_common_params(ctrl); @@ -4016,22 +4096,35 @@ static int try_init_dram_ddr3(ramctr_timing *ctrl, int s3resume, /* Prepare for memory training */ prepare_training(ctrl); - read_training(ctrl); - write_training(ctrl); + err = read_training(ctrl); + if (err) + return err; + + err = write_training(ctrl); + if (err) + return err; printram("CP5a\n"); - discover_edges(ctrl); + err = discover_edges(ctrl); + if (err) + return err; printram("CP5b\n"); - command_training(ctrl); + err = command_training(ctrl); + if (err) + return err; printram("CP5c\n"); - discover_edges_write(ctrl); + err = discover_edges_write(ctrl); + if (err) + return err; - discover_timC_write(ctrl); + err = discover_timC_write(ctrl); + if (err) + return err; normalize_training(ctrl); } @@ -4041,7 +4134,9 @@ static int try_init_dram_ddr3(ramctr_timing *ctrl, int s3resume, write_controller_mr(ctrl); if (!s3resume) { - channel_test(ctrl); + err = channel_test(ctrl); + if (err) + return err; } return 0;

1 0

New patch to review for coreboot: nb/intel/sandybridge/raminit: move ram training into seperate function
by Patrick Rudolph 26 Mar '16

26 Mar '16

Patrick Rudolph (siro(a)das-labor.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14169 -gerrit commit 3e75968711cf24a8c1ccfd01101670141a789e7f Author: Patrick Rudolph <siro(a)das-labor.org> Date: Sat Mar 26 10:59:02 2016 +0100 nb/intel/sandybridge/raminit: move ram training into seperate function In order to add a fallback mechanism, move the ram training code into a new function. This function will be called multiple times and must return error or success to the calling function. Change-Id: I5ee1b3a528290d8252d236b9152b81291736958a Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- src/northbridge/intel/sandybridge/raminit.c | 172 +++++++++++++++------------- 1 file changed, 90 insertions(+), 82 deletions(-) diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index 7d946af..dbec9fb 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -3946,88 +3946,32 @@ static void restore_timings(ramctr_timing * ctrl) write32(DEFAULT_MCHBAR + 0x4ea8, 0); } -void init_dram_ddr3(spd_raw_data * spds, int mobile, int min_tck, - int s3resume) +static int try_init_dram_ddr3(ramctr_timing *ctrl, int s3resume, + int me_uma_size) { - int me_uma_size; - int cbmem_was_inited; - ramctr_timing ctrl; - - MCHBAR32(0x5f00) |= 1; - - report_platform_info(); - - /* Wait for ME to be ready */ - intel_early_me_init(); - me_uma_size = intel_early_me_uma_size(); - - printk(BIOS_DEBUG, "Starting native Platform init\n"); - - u32 reg_5d10; - - wait_txt_clear(); - - wrmsr(0x000002e6, (msr_t) { .lo = 0, .hi = 0 }); - - reg_5d10 = read32(DEFAULT_MCHBAR + 0x5d10); // !!! = 0x00000000 - if ((pcie_read_config16(SOUTHBRIDGE, 0xa2) & 0xa0) == 0x20 /* 0x0004 */ - && reg_5d10 && !s3resume) { - write32(DEFAULT_MCHBAR + 0x5d10, 0); - /* Need reset. */ - outb(0x6, 0xcf9); - - halt(); - } - - memset(&ctrl, 0, sizeof (ctrl)); - - early_pch_init_native(); - early_thermal_init(); - - ctrl.mobile = mobile; - ctrl.tCK = min_tck; - - /* FIXME: for non-S3 we should be able to use timing caching with - proper verification. Right now we use timings only for S3 case. - */ - if (s3resume) { - struct mrc_data_container *mrc_cache; - - mrc_cache = find_current_mrc_cache(); - if (!mrc_cache || mrc_cache->mrc_data_size < sizeof (ctrl)) { - /* Failed S3 resume, reset to come up cleanly */ - outb(0x6, 0xcf9); - halt(); - } - memcpy(&ctrl, mrc_cache->mrc_data, sizeof (ctrl)); - } - if (!s3resume) { - /* Get DDR3 SPD data */ - dram_find_spds_ddr3(spds, &ctrl); - /* Find fastest common supported parameters */ - dram_find_common_params(&ctrl); + dram_find_common_params(ctrl); - dram_dimm_mapping(&ctrl); + dram_dimm_mapping(ctrl); } /* Set MCU frequency */ - dram_freq(&ctrl); + dram_freq(ctrl); if (!s3resume) { /* Calculate timings */ - dram_timing(&ctrl); + dram_timing(ctrl); } /* Set version register */ MCHBAR32(0x5034) = 0xC04EB002; /* Enable crossover */ - dram_xover(&ctrl); + dram_xover(ctrl); /* Set timing and refresh registers */ - dram_timing_regs(&ctrl); + dram_timing_regs(ctrl); /* Power mode preset */ MCHBAR32(0x4e80) = 0x5500; @@ -4042,64 +3986,128 @@ void init_dram_ddr3(spd_raw_data * spds, int mobile, int min_tck, MCHBAR32(0x5030) &= ~0x20; /* Set MAD-DIMM registers */ - dram_dimm_set_mapping(&ctrl); + dram_dimm_set_mapping(ctrl); printk(BIOS_DEBUG, "Done dimm mapping\n"); /* Zone config */ - dram_zones(&ctrl, 1); + dram_zones(ctrl, 1); /* Set memory map */ - dram_memorymap(&ctrl, me_uma_size); + dram_memorymap(ctrl, me_uma_size); printk(BIOS_DEBUG, "Done memory map\n"); /* Set IO registers */ - dram_ioregs(&ctrl); + dram_ioregs(ctrl); printk(BIOS_DEBUG, "Done io registers\n"); udelay(1); if (s3resume) { - restore_timings(&ctrl); + restore_timings(ctrl); } else { /* Do jedec ddr3 reset sequence */ - dram_jedecreset(&ctrl); + dram_jedecreset(ctrl); printk(BIOS_DEBUG, "Done jedec reset\n"); /* MRS commands */ - dram_mrscommands(&ctrl); + dram_mrscommands(ctrl); printk(BIOS_DEBUG, "Done MRS commands\n"); /* Prepare for memory training */ - prepare_training(&ctrl); + prepare_training(ctrl); - read_training(&ctrl); - write_training(&ctrl); + read_training(ctrl); + write_training(ctrl); printram("CP5a\n"); - discover_edges(&ctrl); + discover_edges(ctrl); printram("CP5b\n"); - command_training(&ctrl); + command_training(ctrl); printram("CP5c\n"); - discover_edges_write(&ctrl); + discover_edges_write(ctrl); - discover_timC_write(&ctrl); + discover_timC_write(ctrl); - normalize_training(&ctrl); + normalize_training(ctrl); } - set_4008c(&ctrl); + set_4008c(ctrl); - write_controller_mr(&ctrl); + write_controller_mr(ctrl); if (!s3resume) { - channel_test(&ctrl); + channel_test(ctrl); + } + + return 0; +} + +void init_dram_ddr3(spd_raw_data *spds, int mobile, int min_tck, + int s3resume) +{ + int me_uma_size; + int cbmem_was_inited; + ramctr_timing ctrl; + + MCHBAR32(0x5f00) |= 1; + + report_platform_info(); + + /* Wait for ME to be ready */ + intel_early_me_init(); + me_uma_size = intel_early_me_uma_size(); + + printk(BIOS_DEBUG, "Starting native Platform init\n"); + + u32 reg_5d10; + + wait_txt_clear(); + + wrmsr(0x000002e6, (msr_t) { .lo = 0, .hi = 0 }); + + reg_5d10 = read32(DEFAULT_MCHBAR + 0x5d10); // !!! = 0x00000000 + if ((pcie_read_config16(SOUTHBRIDGE, 0xa2) & 0xa0) == 0x20 /* 0x0004 */ + && reg_5d10 && !s3resume) { + write32(DEFAULT_MCHBAR + 0x5d10, 0); + /* Need reset. */ + outb(0x6, 0xcf9); + + halt(); + } + + memset(&ctrl, 0, sizeof (ctrl)); + + early_pch_init_native(); + early_thermal_init(); + + ctrl.mobile = mobile; + ctrl.tCK = min_tck; + + /* FIXME: for non-S3 we should be able to use timing caching with + proper verification. Right now we use timings only for S3 case. + */ + if (s3resume) { + struct mrc_data_container *mrc_cache; + + mrc_cache = find_current_mrc_cache(); + if (!mrc_cache || (mrc_cache->mrc_data_size < sizeof(ctrl))) { + /* Failed S3 resume, reset to come up cleanly */ + outb(0x6, 0xcf9); + halt(); + } + memcpy(&ctrl, mrc_cache->mrc_data, sizeof(ctrl)); + } else { + /* Get DDR3 SPD data */ + dram_find_spds_ddr3(spds, &ctrl); } + try_init_dram_ddr3(&ctrl, s3resume, me_uma_size); + /* FIXME: should be hardware revision-dependent. */ write32(DEFAULT_MCHBAR + 0x5024, 0x00a030ce);

1 0

New patch to review for coreboot: nb/intel/sandybridge/raminit: move dimm_info into ramctr_timing
by Patrick Rudolph 26 Mar '16

26 Mar '16

Patrick Rudolph (siro(a)das-labor.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14168 -gerrit commit a881c393403a83ede8e928d16d925fc188f5b051 Author: Patrick Rudolph <siro(a)das-labor.org> Date: Sat Mar 26 10:42:27 2016 +0100 nb/intel/sandybridge/raminit: move dimm_info into ramctr_timing It's required to store the dimm_info in ramctr_timing as only ramctr_timing is written to mrc cache. Allows to fill SMBIOS type 17 if mrc cache is used. Change-Id: I7634b05069df307d471938d9854997a018de81b3 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- src/northbridge/intel/sandybridge/raminit.c | 32 +++++++++++++++++------------ 1 file changed, 19 insertions(+), 13 deletions(-) diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index 0b27fe5..7d946af 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -184,6 +184,8 @@ typedef struct ramctr_timing_st { int rank_mirror[NUM_CHANNELS][NUM_SLOTRANKS]; struct ram_rank_timings timings[NUM_CHANNELS][NUM_SLOTRANKS]; + + dimm_info info; } ramctr_timing; #define SOUTHBRIDGE PCI_DEV(0, 0x1f, 0) @@ -238,11 +240,15 @@ static void toggle_io_reset(void) { /* * Fill cbmem with information for SMBIOS type 17. */ -static void fill_smbios17(dimm_info *info, uint16_t ddr_freq) +static void fill_smbios17(ramctr_timing *ctrl) { struct memory_info *mem_info; int channel, slot; struct dimm_info *dimm; + uint16_t ddr_freq; + dimm_info *info = &ctrl->info; + + ddr_freq = (1000 << 8) / ctrl->tCK; /* * Allocate CBMEM area for DIMM information used to populate SMBIOS @@ -323,11 +329,11 @@ void read_spd(spd_raw_data * spd, u8 addr) (*spd)[j] = do_smbus_read_byte(SMBUS_IO_BASE, addr, j); } -static void dram_find_spds_ddr3(spd_raw_data * spd, dimm_info * dimm, - ramctr_timing * ctrl) +static void dram_find_spds_ddr3(spd_raw_data *spd, ramctr_timing *ctrl) { int dimms = 0, dimms_on_channel; int channel, slot, spd_slot; + dimm_info *dimm = &ctrl->info; memset (ctrl->rankmap, 0, sizeof (ctrl->rankmap)); @@ -408,11 +414,12 @@ static void dram_find_spds_ddr3(spd_raw_data * spd, dimm_info * dimm, die("No DIMMs were found"); } -static void dram_find_common_params(const dimm_info * dimms, - ramctr_timing * ctrl) +static void dram_find_common_params(ramctr_timing *ctrl) { size_t valid_dimms; int channel, slot; + dimm_info *dimms = &ctrl->info; + ctrl->cas_supported = 0xff; valid_dimms = 0; FOR_ALL_CHANNELS for (slot = 0; slot < 2; slot++) { @@ -928,10 +935,11 @@ static void dram_timing_regs(ramctr_timing * ctrl) } } -static void dram_dimm_mapping(dimm_info * info, ramctr_timing * ctrl) +static void dram_dimm_mapping(ramctr_timing *ctrl) { u32 reg, val32; int channel; + dimm_info *info = &ctrl->info; FOR_ALL_CHANNELS { dimm_attr *dimmA = 0; @@ -3943,7 +3951,7 @@ void init_dram_ddr3(spd_raw_data * spds, int mobile, int min_tck, { int me_uma_size; int cbmem_was_inited; - dimm_info info; + ramctr_timing ctrl; MCHBAR32(0x5f00) |= 1; @@ -3971,8 +3979,6 @@ void init_dram_ddr3(spd_raw_data * spds, int mobile, int min_tck, halt(); } - ramctr_timing ctrl; - memset(&ctrl, 0, sizeof (ctrl)); early_pch_init_native(); @@ -3998,12 +4004,12 @@ void init_dram_ddr3(spd_raw_data * spds, int mobile, int min_tck, if (!s3resume) { /* Get DDR3 SPD data */ - dram_find_spds_ddr3(spds, &info, &ctrl); + dram_find_spds_ddr3(spds, &ctrl); /* Find fastest common supported parameters */ - dram_find_common_params(&info, &ctrl); + dram_find_common_params(&ctrl); - dram_dimm_mapping(&info, &ctrl); + dram_dimm_mapping(&ctrl); } /* Set MCU frequency */ @@ -4124,7 +4130,7 @@ void init_dram_ddr3(spd_raw_data * spds, int mobile, int min_tck, halt(); } - fill_smbios17(&info, (1000 << 8) / ctrl.tCK); + fill_smbios17(&ctrl); } #define HOST_BRIDGE PCI_DEVFN(0, 0)

1 0

Patch set updated for coreboot: gpio: Add support for extended binary number system
by David Hendricks 25 Mar '16

25 Mar '16

David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14143 -gerrit commit c499cad619bfdc7e0b9dc1bacef23b83f5132f38 Author: David Hendricks <dhendrix(a)chromium.org> Date: Fri Mar 18 20:23:05 2016 -0700 gpio: Add support for extended binary number system This adds yet another number system. In it, binary representation is extended to allow floating/high-Z values to count in the result. A 'Z' value at position N will yield a value of 0 at position N and a value of 1 at position (1 << N << num_gpio). For example: 000Z => 0b1_0000 100Z => 0b1_1000 The advantage is that the value is simple to compute and translate to/from hex. The drawback is that the number space is not contiguous. BRANCH=none BUG=none TEST=stubbed out and tested for a 3-wide raw value, see comments in gerrit for the full table. Change-Id: I121e0cac9fa84fcbb261d1d84dcb20cfd49e5518 Signed-off-by: David Hendricks <dhendrix(a)chromium.org> --- src/include/gpio.h | 13 +++++++++++++ src/lib/gpio.c | 18 ++++++++++++++++++ 2 files changed, 31 insertions(+) diff --git a/src/include/gpio.h b/src/include/gpio.h index 4627e44..0acd5b0 100644 --- a/src/include/gpio.h +++ b/src/include/gpio.h @@ -42,6 +42,19 @@ int gpio_base2_value(gpio_t gpio[], int num_gpio); /* * Read the value presented by the set of GPIOs, when each pin is interpreted + * as a base-2 digit (LOW = 0, HIGH = 1). If a pin is in its Z/floating state + * the value becomes (1 << pin_num << num_gpio). + * + * Caveat: This scheme makes the number space discontinuous. The advantage is + * that it's simple to compute and translate to/from hex. + * + * gpio[]: pin positions to read. gpio[0] is less significant than gpio[1]. + * num_gpio: number of pins to read. + */ +int gpio_base2_ext_value(gpio_t gpio[], int num_gpio); + +/* + * Read the value presented by the set of GPIOs, when each pin is interpreted * as a base-3 digit (LOW = 0, HIGH = 1, Z/floating = 2). * Example: X1 = Z, X2 = 1 -> gpio_base3_value({GPIO(X1), GPIO(X2)}) = 5 * BASE3() from <base3.h> can generate numbers to compare the result to. diff --git a/src/lib/gpio.c b/src/lib/gpio.c index 2e34595..78a383a 100644 --- a/src/lib/gpio.c +++ b/src/lib/gpio.c @@ -35,6 +35,24 @@ int gpio_base2_value(gpio_t gpio[], int num_gpio) return result; } +int gpio_base2_ext_value(gpio_t gpio[], int num_gpio) +{ + int temp, index, result = 0; + + for (index = num_gpio - 1; index >= 0; --index) { + temp = gpio_get(gpio[index]); + printk(BIOS_DEBUG, "%c ", temp == Z ? 'Z' : temp + 0x30); + + if (temp == Z) + result += (1 << index << num_gpio); + else + result += temp * (1 << index); + } + + printk(BIOS_DEBUG, "= 0x%x (extended binary number system)\n", result); + return result; +} + int _gpio_base3_value(gpio_t gpio[], int num_gpio, int binary_first) { /*

1 0

Patch merged into coreboot/master: google/intel mainboards: Add missing board_info.txt files
by gerrit＠coreboot.org 25 Mar '16

25 Mar '16

the following patch was just integrated into master: commit cc9963e3f2b6e7282f75b5fcbff24593a4e5e78f Author: Martin Roth <martinroth(a)google.com> Date: Wed Mar 16 18:36:35 2016 -0600 google/intel mainboards: Add missing board_info.txt files The lint script didn't catch that these mainboard directories didn't have board_info files. Add all missing board_info.txt files Change-Id: Ib1d61a3c04e91b22480527885faf60c22093d98a Signed-off-by: Martin Roth <martinroth(a)google.com> Reviewed-on: https://review.coreboot.org/14117 Reviewed-by: Furquan Shaikh <furquan(a)google.com> Tested-by: build bot (Jenkins) See https://review.coreboot.org/14117 for details. -gerrit

1 0

Patch set updated for coreboot: Makefile: Update jenkins-build-toolchain to run build tests
by Martin Roth 25 Mar '16

25 Mar '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14156 -gerrit commit e597905e01d2da5dbb29a05877b7940ad1b1e028 Author: Martin Roth <martinroth(a)google.com> Date: Tue Mar 22 13:05:42 2016 -0600 Makefile: Update jenkins-build-toolchain to run build tests Add coreboot build tests after running the toolchain build. This verifies that everything still builds with the new toolchain. Change-Id: Ifa51db897925c0b77791c83bbcbfd75045c907b5 Signed-off-by: Martin Roth <martinroth(a)google.com> --- util/crossgcc/Makefile.inc | 2 ++ 1 file changed, 2 insertions(+) diff --git a/util/crossgcc/Makefile.inc b/util/crossgcc/Makefile.inc index dfa1ec8..5be4c10 100644 --- a/util/crossgcc/Makefile.inc +++ b/util/crossgcc/Makefile.inc @@ -71,3 +71,5 @@ endif # ifeq ($(COMPILER_OUT_OF_DATE),1) jenkins-build-toolchain: $(MAKE) crosstools clang \ BUILDGCC_OPTIONS='-y --nocolor' + rm -f .xcompile + $(MAKE) what-jenkins-does

1 0

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