coreboot-gerrit March 2016

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: intel/fsp_baytrail: Use read32() and write32() in i2c.c
by Ben Gardner 24 Mar '16

24 Mar '16

Ben Gardner (gardner.ben(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14162 -gerrit commit 35da7a780d458b54b8326bb77cb40853e15bb7be Author: Ben Gardner <gardner.ben(a)gmail.com> Date: Wed Mar 23 10:11:24 2016 -0500 intel/fsp_baytrail: Use read32() and write32() in i2c.c i2c.c uses "*(volatile unsigned int *)" constructs where it could use read32() and write32(). Switch to using read32() and write32(). The remaining instances in wait_tx_fifo() and wait_rx_fifo() are fixed in https://review.coreboot.org/#/c/14160/ I also fixed a few minor white space issues. Change-Id: I587551272ac171ef1f42c7eb26daf877dc56646b Signed-off-by: Ben Gardner <gardner.ben(a)gmail.com> --- src/soc/intel/fsp_baytrail/i2c.c | 47 ++++++++++++++++++++-------------------- 1 file changed, 24 insertions(+), 23 deletions(-) diff --git a/src/soc/intel/fsp_baytrail/i2c.c b/src/soc/intel/fsp_baytrail/i2c.c index c6c8f65..5a0d59d 100644 --- a/src/soc/intel/fsp_baytrail/i2c.c +++ b/src/soc/intel/fsp_baytrail/i2c.c @@ -23,7 +23,8 @@ /* Wait for the transmit FIFO till there is at least one slot empty. * FIFO stall due to transmit abort will be checked and resolved */ -static int wait_tx_fifo(char *base_adr) { +static int wait_tx_fifo(char *base_adr) +{ int i; if (read32(base_adr + I2C_ABORT_SOURCE) & 0x1ffff) { @@ -35,7 +36,7 @@ static int wait_tx_fifo(char *base_adr) { /* Wait here for a free slot in TX-FIFO */ i = I2C_TIMEOUT_US; - while ((!(*((volatile unsigned int *)(base_adr + I2C_STATUS)) & I2C_TFNF))) { + while (!(read32(base_adr + I2C_STATUS) & I2C_TFNF)) { udelay(1); if (!--i) return I2C_ERR_TIMEOUT; @@ -47,7 +48,8 @@ static int wait_tx_fifo(char *base_adr) { /* Wait for the receive FIFO till there is at least one valid entry to read. * FIFO stall due to transmit abort will be checked and resolved */ -static int wait_rx_fifo(char *base_adr) { +static int wait_rx_fifo(char *base_adr) +{ int i; if (read32(base_adr + I2C_ABORT_SOURCE) & 0x1ffff) { /* Reading back I2C_CLR_TX_ABRT resets abort lock on TX FIFO */ @@ -58,7 +60,7 @@ static int wait_rx_fifo(char *base_adr) { /* Wait here for a received entry in RX-FIFO */ i = I2C_TIMEOUT_US; - while ((!(*((volatile unsigned int *)(base_adr + I2C_STATUS)) & I2C_RFNE))) { + while (!(read32(base_adr + I2C_STATUS) & I2C_RFNE)) { udelay(1); if (!--i) return I2C_ERR_TIMEOUT; @@ -74,20 +76,19 @@ static int wait_rx_fifo(char *base_adr) { static int wait_for_idle(char *base_adr) { int i; - volatile int status; + int status; /* For IDLE, increase timeout by ten times */ i = I2C_TIMEOUT_US * 10; - status = *((volatile unsigned int *)(base_adr + I2C_STATUS)); + status = read32(base_adr + I2C_STATUS); while (((status & I2C_MST_ACTIVITY) || (!(status & I2C_TFE)))) { - status = *((volatile unsigned int *)(base_adr + I2C_STATUS)); + status = read32(base_adr + I2C_STATUS); udelay(1); if (!--i) return I2C_ERR_TIMEOUT; } return I2C_SUCCESS; - } /** \brief Enables I2C-controller, sets up BAR and timing parameters @@ -101,6 +102,7 @@ int i2c_init(unsigned bus) I2C3_MEM_BASE, I2C4_MEM_BASE, I2C5_MEM_BASE, I2C6_MEM_BASE}; char *base_ptr; + /* Ensure the desired device is valid */ if (bus >= ARRAY_SIZE(base_adr)) { printk(BIOS_ERR, "I2C: Only I2C controllers 0...6 are available.\n"); @@ -126,20 +128,19 @@ int i2c_init(unsigned bus) (pci_read_config32(dev, PCI_COMMAND) | 0x2)); /* Set up some settings of I2C controller */ - *((unsigned int *)(base_ptr + I2C_CTRL)) = (I2C_RESTART_EN | - (I2C_STANDARD_MODE << 1) | - I2C_MASTER_ENABLE); + write32(base_ptr + I2C_CTRL, + I2C_RESTART_EN | (I2C_STANDARD_MODE << 1) | I2C_MASTER_ENABLE); /* Adjust frequency for standard mode to 100 kHz */ /* The counter value can be computed by N=100MHz/2/I2C_CLK */ /* Thus, for 100 kHz I2C_CLK, N is 0x1F4 */ - *((unsigned int *)(base_ptr + I2C_SS_SCL_HCNT)) = 0x1f4; - *((unsigned int *)(base_ptr + I2C_SS_SCL_LCNT)) = 0x1f4; + write32(base_ptr + I2C_SS_SCL_HCNT, 0x1f4); + write32(base_ptr + I2C_SS_SCL_LCNT, 0x1f4); /* For 400 kHz, the counter value is 0x7d */ - *((unsigned int *)(base_ptr + I2C_FS_SCL_HCNT)) = 0x7d; - *((unsigned int *)(base_ptr + I2C_FS_SCL_LCNT)) = 0x7d; + write32(base_ptr + I2C_FS_SCL_HCNT, 0x7d); + write32(base_ptr + I2C_FS_SCL_LCNT, 0x7d); /* Enable the I2C controller for operation */ - *((unsigned int *)(base_ptr + I2C_ENABLE)) = 0x1; + write32(base_ptr + I2C_ENABLE, 0x1); printk(BIOS_INFO, "I2C: Controller %d enabled.\n", bus); return I2C_SUCCESS; @@ -177,20 +178,20 @@ int i2c_read(unsigned bus, unsigned chip, unsigned addr, if (stat != I2C_SUCCESS) return stat; /* Now we can program the desired slave address and start transfer */ - *((unsigned int *)(base_ptr + I2C_TARGET_ADR)) = (chip & 0xff); + write32(base_ptr + I2C_TARGET_ADR, chip & 0xff); /* Send address inside slave to read from */ - *((unsigned int *)(base_ptr + I2C_DATA_CMD)) = (addr & 0xff); + write32(base_ptr + I2C_DATA_CMD, addr & 0xff); /* For the next byte we need a repeated start condition */ val = I2C_RW_CMD | I2C_RESTART; /* Now we can read desired amount of data over I2C */ for (i = 0; i < len; i++) { /* A read is initiated by writing dummy data to the DATA-register */ - *((unsigned int *)(base_ptr + I2C_DATA_CMD)) = val; + write32(base_ptr + I2C_DATA_CMD, val); stat = wait_rx_fifo(base_ptr); if (stat) return stat; - buf[i] = (*((unsigned int *)(base_ptr + I2C_DATA_CMD))) & 0xff; + buf[i] = read32(base_ptr + I2C_DATA_CMD) & 0xff; val = I2C_RW_CMD; if (i == (len - 2)) { /* For the last byte we need a stop condition to be generated */ @@ -232,10 +233,10 @@ int i2c_write(unsigned bus, unsigned chip, unsigned addr, return stat; } /* Program slave address to use for this transfer */ - *((unsigned int *)(base_ptr + I2C_TARGET_ADR)) = (chip & 0xff); + write32(base_ptr + I2C_TARGET_ADR, chip & 0xff); /* Send address inside slave to write data to */ - *((unsigned int *)(base_ptr + I2C_DATA_CMD)) = (addr & 0xff); + write32(base_ptr + I2C_DATA_CMD, addr & 0xff); for (i = 0; i < len; i++) { val = (unsigned int)(buf[i] & 0xff); /* Take only 8 bits */ @@ -247,7 +248,7 @@ int i2c_write(unsigned bus, unsigned chip, unsigned addr, if (stat) { return stat; } - *((unsigned int *)(base_ptr + I2C_DATA_CMD)) = val; + write32(base_ptr + I2C_DATA_CMD, val); } return I2C_SUCCESS; }

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Patch set updated for coreboot: buildgcc: support pigz and lbzip2 decpmpressors if installed.
by Martin Roth 24 Mar '16

24 Mar '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14146 -gerrit commit dd484d6b09be5c2ba25592c0e592d0e03233368c Author: Martin Roth <martinroth(a)google.com> Date: Sun Mar 20 12:38:48 2016 -0600 buildgcc: support pigz and lbzip2 decpmpressors if installed. These are multi-threaded decompressors for .gz and .bz2 compressed files. If they're installed, use them to decompress, if they're not, use the standard single-threaded decompressors. Change-Id: I397740817e6b234a43b62075899964bdab14f121 Signed-off-by: Martin Roth <martinroth(a)google.com> --- util/crossgcc/buildgcc | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index 2e7505b..2b586c7 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -243,10 +243,13 @@ unpack_and_patch() { printf " * $(basename $archive)\n" FLAGS=zxf suffix=$(echo $archive | sed 's,.*\.,,') - test "$suffix" = "gz" && FLAGS=zxf - test "$suffix" = "bz2" && FLAGS=jxf - test "$suffix" = "xz" && FLAGS="--xz -xf" - test "$suffix" = "lzma" && FLAGS="--lzma -xf" + if [ "$suffix" = "gz" ] && [ -n "$PIGZ" ]; then FLAGS="-I pigz -xf" + elif [ "$suffix" = "gz" ]; then FLAGS=zxf + elif [ "$suffix" = "bz2" ] && [ -n "$LBZIP2" ]; then FLAGS="-I lbzip2 -xf" + elif [ "$suffix" = "bz2" ]; then FLAGS=jxf + elif [ "$suffix" = "xz" ]; then FLAGS="--xz -xf" + elif [ "$suffix" = "lzma" ]; then FLAGS="--lzma -xf" + fi $TAR $FLAGS tarballs/$(basename $archive) for patch in patches/${dir}_*.patch; do test -r $patch || continue @@ -675,6 +678,8 @@ MAKE=$(searchtool make) || exit $? SHA1SUM=$(searchtool sha1sum) SHA512SUM=$(searchtool sha512sum) CHECKSUM=$SHA1SUM +LBZIP2=$(searchtool lbzip2 "" nofail) +PIGZ=$(searchtool pigz "" nofail) searchtool m4 > /dev/null searchtool bison > /dev/null

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Patch set updated for coreboot: buildgcc: Fix help text formatting
by Martin Roth 24 Mar '16

24 Mar '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14145 -gerrit commit 67ff5220474aabd5d8981cf407a7edb74e5b2d99 Author: Martin Roth <martinroth(a)google.com> Date: Sun Mar 20 12:03:20 2016 -0600 buildgcc: Fix help text formatting Add a newline after the supported version text. Move $TARGETDIR left so that longer paths print better. Change-Id: If520e1b8657a526dee27763aee62cb78777d020d Signed-off-by: Martin Roth <martinroth(a)google.com> --- util/crossgcc/buildgcc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index f88c09c..2e7505b 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -326,9 +326,9 @@ myhelp() printf " [--nocolor] don't print color codes in output\n" printf " [--urls] print the urls for all packages\n" printf " [-j|--jobs <num>] run <num> jobs in parallel in make\n" - printf " [-s]--supported <tool> print supported version of a tool" + printf " [-s]--supported <tool> print supported version of a tool\n" printf " [-d|--directory <target dir>] target directory to install cross compiler to\n" - printf " (defaults to $TARGETDIR)\n\n" + printf " (defaults to $TARGETDIR)\n\n" printf " [-D|--destdir <dest dir>] destination directory to install cross compiler to\n" printf " (for RPM builds, default unset)\n" printf " [-P|--package <package>] Build a specific package: GCC, CLANG, IASL, GDB\n"

1 0

New patch to review for coreboot: libpayload: update junit.xml target, clean up output
by Martin Roth 23 Mar '16

23 Mar '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14164 -gerrit commit 6557004a18e238f62d7a83f562abb77bc35579d3 Author: Martin Roth <martinroth(a)google.com> Date: Wed Mar 23 16:07:54 2016 -0600 libpayload: update junit.xml target, clean up output - Copy each config in configs/ to the junit_config, update each, in turn, and clean up when done. This avoids updating the saved config files and creating dirty files in git. - Use 'make olddefconfig' instead of 'yes "" | make oldconfig' - Update clean target to remove junit_config file - Update distclean target to remove junit.xml Change-Id: Ib023eb3197f2d8806c73c9c18464157ce3de958f Signed-off-by: Martin Roth <martinroth(a)google.com> --- payloads/libpayload/Makefile | 4 ++-- payloads/libpayload/Makefile.inc | 5 +++-- 2 files changed, 5 insertions(+), 4 deletions(-) diff --git a/payloads/libpayload/Makefile b/payloads/libpayload/Makefile index 1b42e29..00fb537 100644 --- a/payloads/libpayload/Makefile +++ b/payloads/libpayload/Makefile @@ -303,13 +303,13 @@ clean-for-update: doxygen-clean clean-for-update-target rmdir -p $(alldirs) 2>/dev/null >/dev/null || true clean: clean-for-update clean-target - rm -f .ccwrap + rm -f .ccwrap junit_config junit_config.old clean-cscope: rm -f cscope.out distclean: clean-cscope rm -rf $(obj) - rm -f .config .config.old ..config.tmp .kconfig.d .tmpconfig* .ccwrap .xcompile + rm -f .config .config.old ..config.tmp .kconfig.d .tmpconfig* .ccwrap .xcompile junit.xml .PHONY: $(PHONY) clean clean-cscope cscope distclean doxygen doxy diff --git a/payloads/libpayload/Makefile.inc b/payloads/libpayload/Makefile.inc index a449f7a..b88cd20 100644 --- a/payloads/libpayload/Makefile.inc +++ b/payloads/libpayload/Makefile.inc @@ -130,9 +130,10 @@ junit.xml: echo '<?xml version="1.0" encoding="utf-8"?><testsuite>' > $@.tmp for i in $(filter-out %.old,$(wildcard configs/*)); do \ $(MAKE) clean; \ - yes "" | $(MAKE) oldconfig DOTCONFIG=$$i V=$(V) Q=$(Q) 2>/dev/null >/dev/null; \ + cp "$$i" junit_config; \ + $(MAKE) olddefconfig DOTCONFIG=junit_config V=$(V) Q=$(Q) 2>/dev/null >/dev/null; \ echo "<testcase classname='libpayload' name='$$i'>" >> $@.tmp; \ - $(MAKE) V=$(V) Q=$(Q) CONFIG_LP_CCACHE=$(CONFIG_LP_CCACHE) DOTCONFIG=$$i >> $@.tmp.2 2>&1 && type="system-out" || type="failure"; \ + $(MAKE) V=$(V) Q=$(Q) CONFIG_LP_CCACHE=$(CONFIG_LP_CCACHE) DOTCONFIG=junit_config >> $@.tmp.2 2>&1 && type="system-out" || type="failure"; \ if [ $$type = "failure" ]; then \ echo "<failure type='buildFailed'>" >> $@.tmp; \ else \

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Patch set updated for coreboot: nb/amd/mct_ddr3: Set the NBP0 read latency from P0 trained values
by Timothy Pearson 23 Mar '16

23 Mar '16

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14150 -gerrit commit 30a51a4a956b0873b11e357c7824c7efd27fe0ce Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Mon Mar 21 13:22:37 2016 -0500 nb/amd/mct_ddr3: Set the NBP0 read latency from P0 trained values During maximum read latency training on Family 15h processors, the maximum read latency was incorrectly set from the NBP1 value instead of the correct NBP0 value. Modify maximimum read latency training to explicitly operate on the NBP0 value, and store the previously calculated NBP1 value for reference by other portions of the training algorithm. Change-Id: I5d4a6c2def83df3e23f1a4c598314c31a0172cd7 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 4 ++-- src/northbridge/amd/amdmct/mct_ddr3/mct_d.h | 4 ++-- src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c | 7 ++++--- src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c | 20 ++++++++++---------- src/northbridge/amd/amdmct/mct_ddr3/mcttmrl.c | 6 +++--- 5 files changed, 21 insertions(+), 20 deletions(-) diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c index 4615dd2..c530848 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c @@ -3798,7 +3798,7 @@ static void LoadDQSSigTmgRegs_D(struct MCTStatStruc *pMCTstat, reg = 0x78; val = Get_NB32_DCT(dev, Channel, reg); val &= ~(0x3ff<<22); - val |= ((u32) pDCTstat->CH_MaxRdLat[Channel] << 22); + val |= ((u32) pDCTstat->CH_MaxRdLat[Channel][0] << 22); val &= ~(1<<DqsRcvEnTrain); Set_NB32_DCT(dev, Channel, reg, val); /* program MaxRdLatency to correspond with current delay*/ } @@ -7391,7 +7391,7 @@ static void mct_ResetDataStruct_D(struct MCTStatStruc *pMCTstat, p = (u8 *) pDCTstat; start = 0; - stop = ((u32) &((struct DCTStatStruc *)0)->CH_MaxRdLat[2]); + stop = ((u32) &((struct DCTStatStruc *)0)->CH_MaxRdLat[2][2]); for (i = start; i < stop ; i++) { p[i] = 0; } diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h index 654acc0..fd35f9c 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering + * Copyright (C) 2015-2016 Raptor Engineering, LLC * Copyright (C) 2010 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify @@ -498,7 +498,7 @@ struct DCTStatStruc { /* A per Node structure*/ u16 CSUsrTestFail; /* Chip selects excluded by user */ /* DCTStatStruct_F - end */ - u16 CH_MaxRdLat[2]; /* Max Read Latency (ns) for DCT 0*/ + u16 CH_MaxRdLat[2][2]; /* Max Read Latency (nclks) [dct][pstate] */ /* Max Read Latency (ns) for DCT 1*/ u8 CH_D_DIR_B_DQS[2][4][2][9]; /* [A/B] [DIMM1-4] [R/W] [DQS] */ /* CHA DIMM0 Byte 0 - 7 and Check Write DQS Delay*/ diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c index 5d75fb0..a9097ea 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c @@ -877,7 +877,8 @@ static void Calc_SetMaxRdLatency_D_Fam15(struct MCTStatStruc *pMCTstat, mem_clk = Get_NB32_DCT(dev, dct, 0x94) & 0x1f; if (fam15h_freq_tab[mem_clk] == 0) { - pDCTstat->CH_MaxRdLat[dct] = 0x55; + pDCTstat->CH_MaxRdLat[dct][0] = 0x55; + pDCTstat->CH_MaxRdLat[dct][1] = 0x55; return; } @@ -947,10 +948,10 @@ static void Calc_SetMaxRdLatency_D_Fam15(struct MCTStatStruc *pMCTstat, } /* Save result for later use */ - pDCTstat->CH_MaxRdLat[dct] = n - 1; + pDCTstat->CH_MaxRdLat[dct][nb_pstate] = n - 1; #if DQS_TRAIN_DEBUG > 0 - printk(BIOS_DEBUG, "%s: CH_MaxRdLat[%d]: %03x\n", __func__, dct, pDCTstat->CH_MaxRdLat[dct]); + printk(BIOS_DEBUG, "%s: CH_MaxRdLat[%d][%d]: %03x\n", __func__, dct, nb_pstate, pDCTstat->CH_MaxRdLat[dct][nb_pstate]); #endif } diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c index 9a0d372..524bea0 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c @@ -998,7 +998,7 @@ static void dqsTrainRcvrEn_SW_Fam10(struct MCTStatStruc *pMCTstat, printk(BIOS_DEBUG, "TrainRcvrEn: CH_MaxRdLat:\n"); for(ChannelDTD = 0; ChannelDTD<2; ChannelDTD++) { printk(BIOS_DEBUG, "Channel:%x: %x\n", - ChannelDTD, pDCTstat->CH_MaxRdLat[ChannelDTD]); + ChannelDTD, pDCTstat->CH_MaxRdLat[ChannelDTD][0]); } } #endif @@ -1498,7 +1498,7 @@ static void dqsTrainRcvrEn_SW_Fam15(struct MCTStatStruc *pMCTstat, printk(BIOS_DEBUG, "TrainRcvrEn: CH_MaxRdLat:\n"); for(ChannelDTD = 0; ChannelDTD<2; ChannelDTD++) { printk(BIOS_DEBUG, "Channel:%x: %x\n", - ChannelDTD, pDCTstat->CH_MaxRdLat[ChannelDTD]); + ChannelDTD, pDCTstat->CH_MaxRdLat[ChannelDTD][0]); } } #endif @@ -1533,7 +1533,7 @@ static void dqsTrainRcvrEn_SW_Fam15(struct MCTStatStruc *pMCTstat, } static void write_max_read_latency_to_registers(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, uint8_t dct, uint16_t latency) + struct DCTStatStruc *pDCTstat, uint8_t dct, uint16_t *latency) { uint32_t dword; uint8_t nb_pstate; @@ -1541,7 +1541,7 @@ static void write_max_read_latency_to_registers(struct MCTStatStruc *pMCTstat, for (nb_pstate = 0; nb_pstate < 2; nb_pstate++) { dword = Get_NB32_DCT_NBPstate(pDCTstat->dev_dct, dct, nb_pstate, 0x210); dword &= ~(0x3ff << 22); - dword |= ((latency & 0x3ff) << 22); + dword |= ((latency[nb_pstate] & 0x3ff) << 22); Set_NB32_DCT_NBPstate(pDCTstat->dev_dct, dct, nb_pstate, 0x210, dword); } } @@ -1665,7 +1665,7 @@ static void dqsTrainMaxRdLatency_SW_Fam15(struct MCTStatStruc *pMCTstat, /* 2.10.5.8.5.1.4 * Incrementally test each MaxRdLatency candidate */ - for (; pDCTstat->CH_MaxRdLat[Channel] < 0x3ff; pDCTstat->CH_MaxRdLat[Channel]++) { + for (; pDCTstat->CH_MaxRdLat[Channel][0] < 0x3ff; pDCTstat->CH_MaxRdLat[Channel][0]++) { write_max_read_latency_to_registers(pMCTstat, pDCTstat, Channel, pDCTstat->CH_MaxRdLat[Channel]); read_dram_dqs_training_pattern_fam15(pMCTstat, pDCTstat, Channel, current_worst_case_total_delay_dimm << 1, 0xff, 0); dword = Get_NB32_DCT(dev, Channel, 0x268) & 0x3ffff; @@ -1683,8 +1683,8 @@ static void dqsTrainMaxRdLatency_SW_Fam15(struct MCTStatStruc *pMCTstat, dword = Get_NB32(pDCTstat->dev_nbctl, (0x160 + (nb_pstate * 4))); /* Retrieve NbDid, NbFid */ nb_clk = (200 * (((dword >> 1) & 0x1f) + 0x4)) / (((dword >> 7) & 0x1)?2:1); - pDCTstat->CH_MaxRdLat[Channel]++; - pDCTstat->CH_MaxRdLat[Channel] += ((((uint64_t)15 * 100000000000ULL) / ((uint64_t)fam15h_freq_tab[mem_clk] * 1000000ULL)) + pDCTstat->CH_MaxRdLat[Channel][0]++; + pDCTstat->CH_MaxRdLat[Channel][0] += ((((uint64_t)15 * 100000000000ULL) / ((uint64_t)fam15h_freq_tab[mem_clk] * 1000000ULL)) * ((uint64_t)nb_clk * 1000)) / 1000000000ULL; write_max_read_latency_to_registers(pMCTstat, pDCTstat, Channel, pDCTstat->CH_MaxRdLat[Channel]); @@ -1712,7 +1712,7 @@ static void dqsTrainMaxRdLatency_SW_Fam15(struct MCTStatStruc *pMCTstat, printk(BIOS_DEBUG, "TrainMaxRdLatency: CH_MaxRdLat:\n"); for(ChannelDTD = 0; ChannelDTD<2; ChannelDTD++) { printk(BIOS_DEBUG, "Channel:%x: %x\n", - ChannelDTD, pDCTstat->CH_MaxRdLat[ChannelDTD]); + ChannelDTD, pDCTstat->CH_MaxRdLat[ChannelDTD][0]); } } #endif @@ -1904,9 +1904,9 @@ static void mct_SetMaxLatency_D(struct DCTStatStruc *pDCTstat, u8 Channel, u16 D */ SubTotal += (cpu_val_n) / 2; - pDCTstat->CH_MaxRdLat[Channel] = SubTotal; + pDCTstat->CH_MaxRdLat[Channel][0] = SubTotal; if(pDCTstat->GangedMode) { - pDCTstat->CH_MaxRdLat[1] = SubTotal; + pDCTstat->CH_MaxRdLat[1][0] = SubTotal; } /* Program the F2x[1, 0]78[MaxRdLatency] register with diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mcttmrl.c b/src/northbridge/amd/amdmct/mct_ddr3/mcttmrl.c index 1b18efa..8cda2f8 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mcttmrl.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mcttmrl.c @@ -191,7 +191,7 @@ static void maxRdLatencyTrain_D(struct MCTStatStruc *pMCTstat, u8 ChannelDTD; printk(BIOS_DEBUG, "maxRdLatencyTrain: CH_MaxRdLat:\n"); for(ChannelDTD = 0; ChannelDTD<2; ChannelDTD++) { - printk(BIOS_DEBUG, "Channel: %02x: %02x\n", ChannelDTD, pDCTstat->CH_MaxRdLat[ChannelDTD]); + printk(BIOS_DEBUG, "Channel: %02x: %02x\n", ChannelDTD, pDCTstat->CH_MaxRdLat[ChannelDTD][0]); } } #endif @@ -208,9 +208,9 @@ static void mct_setMaxRdLatTrnVal_D(struct DCTStatStruc *pDCTstat, if (pDCTstat->GangedMode) { Channel = 0; /* for safe */ for (i=0; i<2; i++) - pDCTstat->CH_MaxRdLat[i] = MaxRdLatVal; + pDCTstat->CH_MaxRdLat[i][0] = MaxRdLatVal; } else { - pDCTstat->CH_MaxRdLat[Channel] = MaxRdLatVal; + pDCTstat->CH_MaxRdLat[Channel][0] = MaxRdLatVal; } dev = pDCTstat->dev_dct;

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Patch merged into coreboot/master: nb/amd/mct_ddr3: Remove spurious Addl_Index variable in dqsTrainMaxRdLatency_SW_Fam15()
by gerrit＠coreboot.org 23 Mar '16

23 Mar '16

the following patch was just integrated into master: commit f1d807c5c603e9a77cf3ddd54e4aa3ceebcc3ae9 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Mon Mar 21 02:14:50 2016 -0500 nb/amd/mct_ddr3: Remove spurious Addl_Index variable in dqsTrainMaxRdLatency_SW_Fam15() Change-Id: Ic3f636983cf6ba2796ee56e2a25b56513a4343c1 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/14148 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See https://review.coreboot.org/14148 for details. -gerrit

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New patch to review for coreboot: crossgcc: Enable multiple targets for a platform
by Patrick Georgi 23 Mar '16

23 Mar '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14163 -gerrit commit d1691390f1853406da4ac30686b426baf1d27c3f Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Wed Mar 23 21:44:43 2016 +0100 crossgcc: Enable multiple targets for a platform This is required on powerpc64 to build both little endian and big endian libgcc. Change-Id: I295c8ee5e8131d4108e98d1bfd53abb8bd8982b2 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> --- util/crossgcc/buildgcc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index 245211d..49dcf24 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -450,7 +450,7 @@ build_GCC() { --disable-libssp --disable-bootstrap --disable-nls \ --disable-libquadmath --without-headers \ --disable-threads \ - --enable-interwork --enable-multilib \ + --enable-interwork --enable-multilib --enable-targets=all \ --disable-libatomic --disable-libcc1 --disable-decimal-float \ ${GCC_OPTIONS} --enable-languages="${LANGUAGES}" \ --with-system-zlib \

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Patch set updated for coreboot: crossgcc: Switch POWER8 to big endian mode
by Patrick Georgi 23 Mar '16

23 Mar '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14161 -gerrit commit b78d8d9a147d79048ba866a65467f572866bf88f Author: Martin Roth <martinroth(a)google.com> Date: Wed Mar 23 09:00:11 2016 -0600 crossgcc: Switch POWER8 to big endian mode Change-Id: If8c07fb3bee4bf0b531e52fae29890af99f924b4 Signed-off-by: Martin Roth <martinroth(a)google.com> --- util/crossgcc/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/util/crossgcc/Makefile b/util/crossgcc/Makefile index 917301c..24fe942 100644 --- a/util/crossgcc/Makefile +++ b/util/crossgcc/Makefile @@ -64,7 +64,7 @@ build-riscv: @$(MAKE) build_gcc BUILD_PLATFORM=riscv-elf build-power8: - @$(MAKE) build_tools BUILD_PLATFORM=powerpc64le-linux-gnu + @$(MAKE) build_tools BUILD_PLATFORM=powerpc64-linux-gnu build-nds32le: @$(MAKE) build_tools BUILD_PLATFORM=nds32le-elf

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Patch set updated for coreboot: buildgcc: Update coreboot's IASL version to 20160318
by Patrick Georgi 23 Mar '16

23 Mar '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12817 -gerrit commit 82271b3903240b1bb6758a1303f2c3f5cff916e1 Author: Martin Roth <gaumless(a)gmail.com> Date: Wed Dec 30 15:10:13 2015 -0700 buildgcc: Update coreboot's IASL version to 20160318 Update IASL from 20150619 to 20160318 See release notes at acpica.org Change-Id: Ic7e7b3956378ad611069e984d5a59c78e4cb08b1 Signed-off-by: Martin Roth <gaumless(a)gmail.com> --- util/crossgcc/buildgcc | 6 ++--- .../patches/acpica-unix2-20150619_iasl.patch | 12 ---------- .../patches/acpica-unix2-20160318_iasl.patch | 27 ++++++++++++++++++++++ .../sum/acpica-unix2-20150619.tar.gz.cksum | 1 - .../sum/acpica-unix2-20160318.tar.gz.cksum | 1 + 5 files changed, 31 insertions(+), 16 deletions(-) diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index f88c09c..245211d 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -18,8 +18,8 @@ cd $(dirname $0) -CROSSGCC_DATE="March 1st, 2016" -CROSSGCC_VERSION="1.36" +CROSSGCC_DATE="March 21st, 2016" +CROSSGCC_VERSION="1.37" # default settings PACKAGE=GCC @@ -39,7 +39,7 @@ GCC_VERSION=5.2.0 GCC_AUTOCONF_VERSION=2.69 BINUTILS_VERSION=2.25 GDB_VERSION=7.9.1 -IASL_VERSION=20150619 +IASL_VERSION=20160318 PYTHON_VERSION=3.4.3 EXPAT_VERSION=2.1.0 # CLANG version number diff --git a/util/crossgcc/patches/acpica-unix2-20150619_iasl.patch b/util/crossgcc/patches/acpica-unix2-20150619_iasl.patch deleted file mode 100644 index 2c754c9..0000000 --- a/util/crossgcc/patches/acpica-unix2-20150619_iasl.patch +++ /dev/null @@ -1,12 +0,0 @@ -diff -urN acpica-unix-20150619/source/compiler/asloptions.c acpica-unix-20150619/source/compiler/asloptions.c ---- acpica-unix2-20150619/source/compiler/asloptions.c 2015-06-19 08:56:19.000000000 -0600 -+++ acpica-unix2-20150619/source/compiler/asloptions.c 2015-12-08 10:44:58.816669240 -0700 -@@ -717,6 +717,7 @@ - case '^': - - printf (ACPI_COMMON_SIGNON (ASL_COMPILER_NAME)); -+ printf ("%s\n", COREBOOT_TOOLCHAIN_VERSION); - exit (0); - - case 'a': - diff --git a/util/crossgcc/patches/acpica-unix2-20160318_iasl.patch b/util/crossgcc/patches/acpica-unix2-20160318_iasl.patch new file mode 100644 index 0000000..6c73d5a --- /dev/null +++ b/util/crossgcc/patches/acpica-unix2-20160318_iasl.patch @@ -0,0 +1,27 @@ +Add coreboot toolchain version string +--- acpica-unix2-20160318/source/compiler/asloptions.c ++++ acpica-unix2-20160318/source/compiler/asloptions.c +@@ -169,6 +169,7 @@ + if (argc < 2) + { + printf (ACPI_COMMON_SIGNON (ASL_COMPILER_NAME)); ++ printf ("%s\n", COREBOOT_TOOLCHAIN_VERSION); + Usage (); + exit (1); + } +@@ -199,6 +200,7 @@ + if (Gbl_DoSignon) + { + printf (ACPI_COMMON_SIGNON (ASL_COMPILER_NAME)); ++ printf ("%s\n", COREBOOT_TOOLCHAIN_VERSION); + if (Gbl_IgnoreErrors) + { + printf ("Ignoring all errors, forcing AML file generation\n\n"); +@@ -743,6 +745,7 @@ + case '^': + + printf (ACPI_COMMON_SIGNON (ASL_COMPILER_NAME)); ++ printf ("%s\n", COREBOOT_TOOLCHAIN_VERSION); + exit (0); + + case 'a': diff --git a/util/crossgcc/sum/acpica-unix2-20150619.tar.gz.cksum b/util/crossgcc/sum/acpica-unix2-20150619.tar.gz.cksum deleted file mode 100644 index 523e6da..0000000 --- a/util/crossgcc/sum/acpica-unix2-20150619.tar.gz.cksum +++ /dev/null @@ -1 +0,0 @@ -283c594c4b89db8e3bef8fca25021c52938987ad tarballs/acpica-unix2-20150619.tar.gz diff --git a/util/crossgcc/sum/acpica-unix2-20160318.tar.gz.cksum b/util/crossgcc/sum/acpica-unix2-20160318.tar.gz.cksum new file mode 100644 index 0000000..2f9b331 --- /dev/null +++ b/util/crossgcc/sum/acpica-unix2-20160318.tar.gz.cksum @@ -0,0 +1 @@ +786811c1501b9cc90c988293a1c3afefa33b60cc tarballs/acpica-unix2-20160318.tar.gz

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Patch merged into coreboot/master: armv7: Word-sized/half-word-sized memory operations for 32/16 bit read/write
by gerrit＠coreboot.org 23 Mar '16

23 Mar '16

the following patch was just integrated into master: commit 263522db97b5b16d2408fa11c5c158f88539bc8c Author: Paul Kocialkowski <contact(a)paulk.fr> Date: Tue Sep 22 22:16:33 2015 +0200 armv7: Word-sized/half-word-sized memory operations for 32/16 bit read/write As a follow up to Change-Id: I1fb3fc139e0a813acf9d70f14386a9603c9f9ede, use as builtin compiler hint instead of inline assembly to allow the compiler to generate more efficient code. Change-Id: I690514ac6d8988a6494ad3a77690709d932802b0 Signed-off-by: Paul Kocialkowski <contact(a)paulk.fr> Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> Reviewed-on: https://review.coreboot.org/12083 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Reviewed-by: Julius Werner <jwerner(a)chromium.org> Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See https://review.coreboot.org/12083 for details. -gerrit

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