coreboot-gerrit March 2016

coreboot-gerrit@coreboot.org

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Patch merged into coreboot/master: arch/x86: introduce postcar stage/phase
by gerrit＠coreboot.org 23 Mar '16

23 Mar '16

the following patch was just integrated into master: commit 7f8afe063139f6fc7076a3e4edf6093a953792dc Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Mar 18 12:21:23 2016 -0500 arch/x86: introduce postcar stage/phase Certain chipsets don't have a memory-mapped boot media so their code execution for stages prior to DRAM initialization is backed by SRAM or cache-as-ram. The postcar stage/phase handles the cache-as-ram situation where in order to tear down cache-as-ram one needs to be executing out of a backing store that isn't transient. By current definition, cache-as-ram is volatile and tearing it down leads to its contents disappearing. Therefore provide a shim layer, postcar, that's loaded into memory and executed which does 2 things: 1. Tears down cache-as-ram with a chipset helper function. 2. Loads and runs ramstage. Because those 2 things are executed out of ram there's no issue of the code's backing store while executing the code that tears down cache-as-ram. The current implementation makes no assumption regarding cacheability of the DRAM itself. If the chipset code wishes to cache DRAM for loading of the postcar stage/phase then it's also up to the chipset to handle any coherency issues pertaining to cache-as-ram destruction. Change-Id: Ia58efdadd0b48f20cfe7de2f49ab462306c3a19b Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://review.coreboot.org/14140 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> Reviewed-by: Furquan Shaikh <furquan(a)google.com> See https://review.coreboot.org/14140 for details. -gerrit

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Patch set updated for coreboot: edid: Add helper function to calculate bits-per-pixel dependent values
by Julius Werner 23 Mar '16

23 Mar '16

Julius Werner (jwerner(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14158 -gerrit commit 85c2f3608d7a58587677c2473615b904bb7ba023 Author: Julius Werner <jwerner(a)chromium.org> Date: Mon Mar 14 17:29:55 2016 -0700 edid: Add helper function to calculate bits-per-pixel dependent values Coreboot and most payloads support three basic pixel widths for the framebuffer. It assumes 32 by default, but several chipsets need to override that value with whatever else they're supporting. Our struct edid contains multiple convenience values that are directly derived from this (and other properties), so changing the bits per pixel always requires recalculating all those dependents in the chipset code. This patch provides a small convenience wrapper that can be used to consistently update the whole struct edid with a new pixel width instead, so we no longer need to duplicate those calculations everywhere. BUG=None TEST=Booted Oak in all three pixel widths (which it conveniently all supports), confirmed that images looked good. Change-Id: I5376dd4e28cf107ac2fba1dc418f5e1c5a2e2de6 Signed-off-by: Julius Werner <jwerner(a)chromium.org> --- src/drivers/emulation/qemu/bochs.c | 5 +---- src/drivers/emulation/qemu/cirrus.c | 5 +---- src/include/edid.h | 1 + src/lib/edid.c | 45 +++++++++++++++++-------------------- src/soc/nvidia/tegra124/display.c | 9 ++++---- src/soc/nvidia/tegra132/dc.c | 12 +++++----- src/soc/nvidia/tegra210/dc.c | 12 +++++----- src/soc/rockchip/rk3288/display.c | 6 ++--- 8 files changed, 40 insertions(+), 55 deletions(-) diff --git a/src/drivers/emulation/qemu/bochs.c b/src/drivers/emulation/qemu/bochs.c index ae2975d..f32fee0 100644 --- a/src/drivers/emulation/qemu/bochs.c +++ b/src/drivers/emulation/qemu/bochs.c @@ -111,12 +111,9 @@ static void bochs_init(struct device *dev) /* setup coreboot framebuffer */ edid.mode.ha = width; edid.mode.va = height; - edid.x_resolution = width; - edid.y_resolution = height; - edid.bytes_per_line = width * 4; - edid.framebuffer_bits_per_pixel = 32; edid.panel_bits_per_color = 8; edid.panel_bits_per_pixel = 24; + edid_set_framebuffer_bits_per_pixel(&edid, 32); set_vbe_mode_info_valid(&edid, addr); #else vga_misc_write(0x1); diff --git a/src/drivers/emulation/qemu/cirrus.c b/src/drivers/emulation/qemu/cirrus.c index 42cc120..84c2958 100644 --- a/src/drivers/emulation/qemu/cirrus.c +++ b/src/drivers/emulation/qemu/cirrus.c @@ -330,12 +330,9 @@ static void cirrus_init(struct device *dev) struct edid edid; edid.mode.ha = width; edid.mode.va = height; - edid.x_resolution = width; - edid.y_resolution = height; - edid.bytes_per_line = width * 4; - edid.framebuffer_bits_per_pixel = 32; edid.panel_bits_per_color = 8; edid.panel_bits_per_pixel = 24; + edid_set_framebuffer_bits_per_pixel(&edid, 32); set_vbe_mode_info_valid(&edid, addr); #else vga_misc_write(0x1); diff --git a/src/include/edid.h b/src/include/edid.h index d3cab17..f46c761 100644 --- a/src/include/edid.h +++ b/src/include/edid.h @@ -93,6 +93,7 @@ struct edid { /* Defined in src/lib/edid.c */ int decode_edid(unsigned char *edid, int size, struct edid *out); +void edid_set_framebuffer_bits_per_pixel(struct edid *edid, int fb_bpp); void set_vbe_mode_info_valid(struct edid *edid, uintptr_t fb_addr); int set_display_mode(struct edid *edid, enum edid_modes mode); diff --git a/src/lib/edid.c b/src/lib/edid.c index 3aebc65..52898fb 100644 --- a/src/lib/edid.c +++ b/src/lib/edid.c @@ -28,6 +28,7 @@ * at present. */ +#include <assert.h> #include <stddef.h> #include <console/console.h> #include <arch/io.h> @@ -478,30 +479,12 @@ detailed_block(struct edid *result_edid, unsigned char *x, int in_extension, out->mode.vso = ((x[10] >> 4) + ((x[11] & 0x0C) << 2)); out->mode.vspw = ((x[10] & 0x0F) + ((x[11] & 0x03) << 4)); out->mode.vborder = x[16]; - /* set up some reasonable defaults for payloads. - * We observe that most modern chipsets we work with - * tend to support rgb888 without regard to the - * panel bits per color or other settings. The rgb888 - * is a convenient layout for software because - * it avoids the messy bit stuffing of rgb565 or rgb444. - * It makes a reasonable trade of memory for speed. - * So, set up the default for - * 32 bits per pixel - * rgb888 (i.e. no alpha, but pixels on 32-bit boundaries) - * The mainboard can modify these if needed, though - * we have yet to see a case where that will happen. - * The existing ARM mainboards don't even call this function - * so this will not affect them. - */ - out->framebuffer_bits_per_pixel = 32; - - out->x_resolution = ALIGN(out->mode.ha * - ((out->framebuffer_bits_per_pixel + 7) / 8), - 64) / (out->framebuffer_bits_per_pixel/8); - out->y_resolution = out->mode.va; - out->bytes_per_line = ALIGN(out->mode.ha * - ((out->framebuffer_bits_per_pixel + 7)/8), - 64); + + /* We assume rgb888 (32 bits per pixel) framebuffers by default. + * Chipsets that want something else will need to override this + * with another call to edid_set_framebuffer_bits_per_pixel(). */ + edid_set_framebuffer_bits_per_pixel(out, 32); + switch ((x[17] & 0x18) >> 3) { case 0x00: extra_info.syncmethod = " analog composite"; @@ -1539,6 +1522,20 @@ int decode_edid(unsigned char *edid, int size, struct edid *out) * SPWG also says something strange about the LSB of detailed descriptor 1: * "LSB is set to "1" if panel is DE-timing only. H/V can be ignored." */ + +/* Set the framebuffer bits-per-pixel, recalculating all dependent values. */ +void edid_set_framebuffer_bits_per_pixel(struct edid *edid, int fb_bpp) +{ + /* Caller should pass a supported value, everything else is BUG(). */ + assert(fb_bpp == 32 || fb_bpp == 24 || fb_bpp == 16); + + edid->framebuffer_bits_per_pixel = fb_bpp; + edid->bytes_per_line = ALIGN_UP(edid->mode.ha * + div_round_up(fb_bpp, 8), 64); + edid->x_resolution = edid->bytes_per_line / (fb_bpp / 8); + edid->y_resolution = edid->mode.va; +} + /* * Take an edid, and create a framebuffer. Set vbe_valid to 1. */ diff --git a/src/soc/nvidia/tegra124/display.c b/src/soc/nvidia/tegra124/display.c index ac1b950..74202ba 100644 --- a/src/soc/nvidia/tegra124/display.c +++ b/src/soc/nvidia/tegra124/display.c @@ -331,10 +331,9 @@ void display_startup(device_t dev) /* tell depthcharge ... */ struct edid edid; - edid.bytes_per_line = ((config->xres * config->framebuffer_bits_per_pixel / 8 + 31) / - 32 * 32); - edid.x_resolution = edid.bytes_per_line / (config->framebuffer_bits_per_pixel / 8); - edid.y_resolution = config->yres; - edid.framebuffer_bits_per_pixel = config->framebuffer_bits_per_pixel; + edid.mode.va = config->yres; + edid.mode.ha = config->xres; + edid_set_framebuffer_bits_per_pixel(&edid, + config->framebuffer_bits_per_pixel); set_vbe_mode_info_valid(&edid, (uintptr_t)(framebuffer_base_mb*MiB)); } diff --git a/src/soc/nvidia/tegra132/dc.c b/src/soc/nvidia/tegra132/dc.c index 2b1687b..562061a 100644 --- a/src/soc/nvidia/tegra132/dc.c +++ b/src/soc/nvidia/tegra132/dc.c @@ -226,13 +226,11 @@ void pass_mode_info_to_payload( struct soc_nvidia_tegra132_config *config) { struct edid edid; - /* Align bytes_per_line to 64 bytes as required by dc */ - edid.bytes_per_line = ALIGN_UP((config->display_xres * - config->framebuffer_bits_per_pixel / 8), 64); - edid.x_resolution = edid.bytes_per_line / - (config->framebuffer_bits_per_pixel / 8); - edid.y_resolution = config->display_yres; - edid.framebuffer_bits_per_pixel = config->framebuffer_bits_per_pixel; + + edid.mode.va = config->display_yres; + edid.mode.ha = config->display_xres; + edid_set_framebuffer_bits_per_pixel(&edid, + config->framebuffer_bits_per_pixel); printk(BIOS_INFO, "%s: bytes_per_line: %d, bits_per_pixel: %d\n " " x_res x y_res: %d x %d, size: %d\n", diff --git a/src/soc/nvidia/tegra210/dc.c b/src/soc/nvidia/tegra210/dc.c index 5dad92e..72f1bcb 100644 --- a/src/soc/nvidia/tegra210/dc.c +++ b/src/soc/nvidia/tegra210/dc.c @@ -226,13 +226,11 @@ void pass_mode_info_to_payload( struct soc_nvidia_tegra210_config *config) { struct edid edid; - /* Align bytes_per_line to 64 bytes as required by dc */ - edid.bytes_per_line = ALIGN_UP((config->display_xres * - config->framebuffer_bits_per_pixel / 8), 64); - edid.x_resolution = edid.bytes_per_line / - (config->framebuffer_bits_per_pixel / 8); - edid.y_resolution = config->display_yres; - edid.framebuffer_bits_per_pixel = config->framebuffer_bits_per_pixel; + + edid.mode.va = config->display_yres; + edid.mode.ha = config->display_xres; + edid_set_framebuffer_bits_per_pixel(&edid, + config->framebuffer_bits_per_pixel); printk(BIOS_INFO, "%s: bytes_per_line: %d, bits_per_pixel: %d\n " " x_res x y_res: %d x %d, size: %d\n", diff --git a/src/soc/rockchip/rk3288/display.c b/src/soc/rockchip/rk3288/display.c index 56eea07..66b2edc 100644 --- a/src/soc/rockchip/rk3288/display.c +++ b/src/soc/rockchip/rk3288/display.c @@ -94,10 +94,8 @@ void rk_display_init(device_t dev, u32 lcdbase, return; } - edid.framebuffer_bits_per_pixel = conf->framebuffer_bits_per_pixel; - edid.bytes_per_line = edid.mode.ha * conf->framebuffer_bits_per_pixel / 8; - edid.x_resolution = edid.mode.ha; - edid.y_resolution = edid.mode.va; + edid_set_framebuffer_bits_per_pixel(&edid, + conf->framebuffer_bits_per_pixel); rkvop_mode_set(conf->vop_id, &edid, detected_mode); rkvop_enable(conf->vop_id, lcdbase, &edid);

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New patch to review for coreboot: edid: Add helper function to calculate bits-per-pixel dependent values
by Julius Werner 23 Mar '16

23 Mar '16

Julius Werner (jwerner(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14158 -gerrit commit 56a6d3a48a64a97e6057f4c8e91a54760423e98c Author: Julius Werner <jwerner(a)chromium.org> Date: Mon Mar 14 17:29:55 2016 -0700 edid: Add helper function to calculate bits-per-pixel dependent values Coreboot and most payloads support three basic pixel widths for the framebuffer. It assumes 32 by default, but several chipsets need to override that value with whatever else they're supporting. Our struct edid contains multiple convenience values that are directly derived from this (and other properties), so changing the bits per pixel always requires recalculating all those dependents in the chipset code. This patch provides a small convenience wrapper that can be used to consistently update the whole struct edid with a new pixel width instead, so we no longer need to duplicate those calculations everywhere. BUG=None TEST=Booted Oak in all three pixel widths (which it conveniently all supports), confirmed that images looked good. Change-Id: I5376dd4e28cf107ac2fba1dc418f5e1c5a2e2de6 Signed-off-by: Julius Werner <jwerner(a)chromium.org> --- src/drivers/emulation/qemu/bochs.c | 5 +---- src/drivers/emulation/qemu/cirrus.c | 5 +---- src/include/edid.h | 1 + src/lib/edid.c | 45 +++++++++++++++++-------------------- src/soc/nvidia/tegra124/display.c | 9 ++++---- src/soc/nvidia/tegra132/dc.c | 12 +++++----- src/soc/nvidia/tegra210/dc.c | 12 +++++----- src/soc/rockchip/rk3288/display.c | 6 ++--- 8 files changed, 40 insertions(+), 55 deletions(-) diff --git a/src/drivers/emulation/qemu/bochs.c b/src/drivers/emulation/qemu/bochs.c index ae2975d..7166378 100644 --- a/src/drivers/emulation/qemu/bochs.c +++ b/src/drivers/emulation/qemu/bochs.c @@ -111,12 +111,9 @@ static void bochs_init(struct device *dev) /* setup coreboot framebuffer */ edid.mode.ha = width; edid.mode.va = height; - edid.x_resolution = width; - edid.y_resolution = height; - edid.bytes_per_line = width * 4; - edid.framebuffer_bits_per_pixel = 32; edid.panel_bits_per_color = 8; edid.panel_bits_per_pixel = 24; + edid_set_framebuffer_bits_per_pixel(edid, 32); set_vbe_mode_info_valid(&edid, addr); #else vga_misc_write(0x1); diff --git a/src/drivers/emulation/qemu/cirrus.c b/src/drivers/emulation/qemu/cirrus.c index 42cc120..0b5316e 100644 --- a/src/drivers/emulation/qemu/cirrus.c +++ b/src/drivers/emulation/qemu/cirrus.c @@ -330,12 +330,9 @@ static void cirrus_init(struct device *dev) struct edid edid; edid.mode.ha = width; edid.mode.va = height; - edid.x_resolution = width; - edid.y_resolution = height; - edid.bytes_per_line = width * 4; - edid.framebuffer_bits_per_pixel = 32; edid.panel_bits_per_color = 8; edid.panel_bits_per_pixel = 24; + edid_set_framebuffer_bits_per_pixel(edid, 32); set_vbe_mode_info_valid(&edid, addr); #else vga_misc_write(0x1); diff --git a/src/include/edid.h b/src/include/edid.h index d3cab17..f46c761 100644 --- a/src/include/edid.h +++ b/src/include/edid.h @@ -93,6 +93,7 @@ struct edid { /* Defined in src/lib/edid.c */ int decode_edid(unsigned char *edid, int size, struct edid *out); +void edid_set_framebuffer_bits_per_pixel(struct edid *edid, int fb_bpp); void set_vbe_mode_info_valid(struct edid *edid, uintptr_t fb_addr); int set_display_mode(struct edid *edid, enum edid_modes mode); diff --git a/src/lib/edid.c b/src/lib/edid.c index 3aebc65..52898fb 100644 --- a/src/lib/edid.c +++ b/src/lib/edid.c @@ -28,6 +28,7 @@ * at present. */ +#include <assert.h> #include <stddef.h> #include <console/console.h> #include <arch/io.h> @@ -478,30 +479,12 @@ detailed_block(struct edid *result_edid, unsigned char *x, int in_extension, out->mode.vso = ((x[10] >> 4) + ((x[11] & 0x0C) << 2)); out->mode.vspw = ((x[10] & 0x0F) + ((x[11] & 0x03) << 4)); out->mode.vborder = x[16]; - /* set up some reasonable defaults for payloads. - * We observe that most modern chipsets we work with - * tend to support rgb888 without regard to the - * panel bits per color or other settings. The rgb888 - * is a convenient layout for software because - * it avoids the messy bit stuffing of rgb565 or rgb444. - * It makes a reasonable trade of memory for speed. - * So, set up the default for - * 32 bits per pixel - * rgb888 (i.e. no alpha, but pixels on 32-bit boundaries) - * The mainboard can modify these if needed, though - * we have yet to see a case where that will happen. - * The existing ARM mainboards don't even call this function - * so this will not affect them. - */ - out->framebuffer_bits_per_pixel = 32; - - out->x_resolution = ALIGN(out->mode.ha * - ((out->framebuffer_bits_per_pixel + 7) / 8), - 64) / (out->framebuffer_bits_per_pixel/8); - out->y_resolution = out->mode.va; - out->bytes_per_line = ALIGN(out->mode.ha * - ((out->framebuffer_bits_per_pixel + 7)/8), - 64); + + /* We assume rgb888 (32 bits per pixel) framebuffers by default. + * Chipsets that want something else will need to override this + * with another call to edid_set_framebuffer_bits_per_pixel(). */ + edid_set_framebuffer_bits_per_pixel(out, 32); + switch ((x[17] & 0x18) >> 3) { case 0x00: extra_info.syncmethod = " analog composite"; @@ -1539,6 +1522,20 @@ int decode_edid(unsigned char *edid, int size, struct edid *out) * SPWG also says something strange about the LSB of detailed descriptor 1: * "LSB is set to "1" if panel is DE-timing only. H/V can be ignored." */ + +/* Set the framebuffer bits-per-pixel, recalculating all dependent values. */ +void edid_set_framebuffer_bits_per_pixel(struct edid *edid, int fb_bpp) +{ + /* Caller should pass a supported value, everything else is BUG(). */ + assert(fb_bpp == 32 || fb_bpp == 24 || fb_bpp == 16); + + edid->framebuffer_bits_per_pixel = fb_bpp; + edid->bytes_per_line = ALIGN_UP(edid->mode.ha * + div_round_up(fb_bpp, 8), 64); + edid->x_resolution = edid->bytes_per_line / (fb_bpp / 8); + edid->y_resolution = edid->mode.va; +} + /* * Take an edid, and create a framebuffer. Set vbe_valid to 1. */ diff --git a/src/soc/nvidia/tegra124/display.c b/src/soc/nvidia/tegra124/display.c index ac1b950..3108a74 100644 --- a/src/soc/nvidia/tegra124/display.c +++ b/src/soc/nvidia/tegra124/display.c @@ -331,10 +331,9 @@ void display_startup(device_t dev) /* tell depthcharge ... */ struct edid edid; - edid.bytes_per_line = ((config->xres * config->framebuffer_bits_per_pixel / 8 + 31) / - 32 * 32); - edid.x_resolution = edid.bytes_per_line / (config->framebuffer_bits_per_pixel / 8); - edid.y_resolution = config->yres; - edid.framebuffer_bits_per_pixel = config->framebuffer_bits_per_pixel; + edid.mode.va = config->yres; + edid.mode.ha = config->xres; + edid_set_framebuffer_bits_per_pixel(edid, + config->framebuffer_bits_per_pixel); set_vbe_mode_info_valid(&edid, (uintptr_t)(framebuffer_base_mb*MiB)); } diff --git a/src/soc/nvidia/tegra132/dc.c b/src/soc/nvidia/tegra132/dc.c index 2b1687b..9ab278c 100644 --- a/src/soc/nvidia/tegra132/dc.c +++ b/src/soc/nvidia/tegra132/dc.c @@ -226,13 +226,11 @@ void pass_mode_info_to_payload( struct soc_nvidia_tegra132_config *config) { struct edid edid; - /* Align bytes_per_line to 64 bytes as required by dc */ - edid.bytes_per_line = ALIGN_UP((config->display_xres * - config->framebuffer_bits_per_pixel / 8), 64); - edid.x_resolution = edid.bytes_per_line / - (config->framebuffer_bits_per_pixel / 8); - edid.y_resolution = config->display_yres; - edid.framebuffer_bits_per_pixel = config->framebuffer_bits_per_pixel; + + edid.mode.va = config->display_yres; + edid.mode.ha = config->display_xres; + edid_set_framebuffer_bits_per_pixel(edid, + config->framebuffer_bits_per_pixel); printk(BIOS_INFO, "%s: bytes_per_line: %d, bits_per_pixel: %d\n " " x_res x y_res: %d x %d, size: %d\n", diff --git a/src/soc/nvidia/tegra210/dc.c b/src/soc/nvidia/tegra210/dc.c index 5dad92e..7d44349 100644 --- a/src/soc/nvidia/tegra210/dc.c +++ b/src/soc/nvidia/tegra210/dc.c @@ -226,13 +226,11 @@ void pass_mode_info_to_payload( struct soc_nvidia_tegra210_config *config) { struct edid edid; - /* Align bytes_per_line to 64 bytes as required by dc */ - edid.bytes_per_line = ALIGN_UP((config->display_xres * - config->framebuffer_bits_per_pixel / 8), 64); - edid.x_resolution = edid.bytes_per_line / - (config->framebuffer_bits_per_pixel / 8); - edid.y_resolution = config->display_yres; - edid.framebuffer_bits_per_pixel = config->framebuffer_bits_per_pixel; + + edid.mode.va = config->display_yres; + edid.mode.ha = config->display_xres; + edid_set_framebuffer_bits_per_pixel(edid, + config->framebuffer_bits_per_pixel); printk(BIOS_INFO, "%s: bytes_per_line: %d, bits_per_pixel: %d\n " " x_res x y_res: %d x %d, size: %d\n", diff --git a/src/soc/rockchip/rk3288/display.c b/src/soc/rockchip/rk3288/display.c index 56eea07..6083363 100644 --- a/src/soc/rockchip/rk3288/display.c +++ b/src/soc/rockchip/rk3288/display.c @@ -94,10 +94,8 @@ void rk_display_init(device_t dev, u32 lcdbase, return; } - edid.framebuffer_bits_per_pixel = conf->framebuffer_bits_per_pixel; - edid.bytes_per_line = edid.mode.ha * conf->framebuffer_bits_per_pixel / 8; - edid.x_resolution = edid.mode.ha; - edid.y_resolution = edid.mode.va; + edid_set_framebuffer_bits_per_pixel(edid, + conf->framebuffer_bits_per_pixel); rkvop_mode_set(conf->vop_id, &edid, detected_mode); rkvop_enable(conf->vop_id, lcdbase, &edid);

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Patch set updated for coreboot: MAINTAINERS: Add maintainer for the intelmetool
by Philipp Deppenwiese 23 Mar '16

23 Mar '16

Philipp Deppenwiese (zaolin.daisuki(a)googlemail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14157 -gerrit commit 34b6914b905b32ff7c9a01507c839a6d80b4064d Author: Philipp Deppenwiese <zaolin(a)das-labor.org> Date: Wed Mar 23 00:02:40 2016 +0100 MAINTAINERS: Add maintainer for the intelmetool If you want to be a maintainer Damien just add yourself to the list. Change-Id: I15c646fc23d0804a8172da66d9297ab7977e6e6a --- MAINTAINERS | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index a3b6762..28628ff 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -337,6 +337,10 @@ INTELTOOL M: Stefan Reinauer <stefan.reinauer(a)coreboot.org> F: util/inteltool/ +INTELMETOOL +M: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> +F: util/intelmetool/ + IFDTOOL M: Stefan Reinauer <stefan.reinauer(a)coreboot.org> F: util/ifdtool/

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New patch to review for coreboot: MAINTAINERS: Add maintainer for the intelmetool
by Philipp Deppenwiese 23 Mar '16

23 Mar '16

Philipp Deppenwiese (zaolin.daisuki(a)googlemail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14157 -gerrit commit 207f3cd49020278554fae75294f98b287ac2a798 Author: Philipp Deppenwiese <zaolin(a)das-labor.org> Date: Wed Mar 23 00:02:40 2016 +0100 MAINTAINERS: Add maintainer for the intelmetool Change-Id: I15c646fc23d0804a8172da66d9297ab7977e6e6a --- MAINTAINERS | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index a3b6762..28628ff 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -337,6 +337,10 @@ INTELTOOL M: Stefan Reinauer <stefan.reinauer(a)coreboot.org> F: util/inteltool/ +INTELMETOOL +M: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> +F: util/intelmetool/ + IFDTOOL M: Stefan Reinauer <stefan.reinauer(a)coreboot.org> F: util/ifdtool/

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Patch merged into coreboot/master: gpio: Add support for binary_first base3 number system
by gerrit＠coreboot.org 22 Mar '16

22 Mar '16

the following patch was just integrated into master: commit 2b239485358ec063a4803f248c88378076810e24 Author: Julius Werner <jwerner(a)chromium.org> Date: Wed Mar 16 17:11:55 2016 -0700 gpio: Add support for binary_first base3 number system This patch adds support for an alternative ternary number system in which group of GPIOs can be interpreted. In this system, the digit combinations that would form a binary number (i.e. that contain no 'Z' state) are used to represent the lower values in the way they're used in the normal binary system, and all the combinations that do contain a 'Z' are used to represent values above those. We can use this for boards that originally get strapped with binary board IDs but eventually require more revisions than that representation allows. We can switch their code to binary_first base3 and all old revisions with already produced boards will still get read as the correct numbers. Credit for the algorithm idea goes to Haran Talmon. BRANCH=None BUG=None TEST=Stubbed out the actual GPIO reading and simulated all combinations of 4 ternary digits for both number systems. Change-Id: Ib5127656455f97f890ce2999ba5ac5f58a20cf93 Signed-off-by: Julius Werner <jwerner(a)chromium.org> Reviewed-on: https://review.coreboot.org/14116 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix(a)chromium.org> Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See https://review.coreboot.org/14116 for details. -gerrit

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Patch set updated for coreboot: crossgcc: Switch POWER8 to big endian mode and fix compiler detect
by Martin Roth 22 Mar '16

22 Mar '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14018 -gerrit commit 4b257515546f2519a853f6ea9730b92d55328b3d Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Wed Mar 9 17:20:26 2016 -0600 crossgcc: Switch POWER8 to big endian mode and fix compiler detect Change-Id: I7afb35fd5bc971a2c4d63e3a084ce7473f7a66fa Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- util/crossgcc/Makefile | 2 +- util/xcompile/xcompile | 9 +++++---- 2 files changed, 6 insertions(+), 5 deletions(-) diff --git a/util/crossgcc/Makefile b/util/crossgcc/Makefile index 917301c..24fe942 100644 --- a/util/crossgcc/Makefile +++ b/util/crossgcc/Makefile @@ -64,7 +64,7 @@ build-riscv: @$(MAKE) build_gcc BUILD_PLATFORM=riscv-elf build-power8: - @$(MAKE) build_tools BUILD_PLATFORM=powerpc64le-linux-gnu + @$(MAKE) build_tools BUILD_PLATFORM=powerpc64-linux-gnu build-nds32le: @$(MAKE) build_tools BUILD_PLATFORM=nds32le-elf diff --git a/util/xcompile/xcompile b/util/xcompile/xcompile index 53f0a85..2b9b818 100755 --- a/util/xcompile/xcompile +++ b/util/xcompile/xcompile @@ -4,6 +4,7 @@ # # Copyright (C) 2007-2010 coresystems GmbH # Copyright (C) 2012 Google Inc +# Copyright (C) 2016 Raptor Engineering, LLC # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by @@ -367,12 +368,12 @@ arch_config_mipsel() { arch_config_power8() { TARCH="power8" - TBFDARCHS="powerpcle" - TCLIST="powerpc64 powerpc64le" + TBFDARCHS="powerpc" + TCLIST="powerpc64" TWIDTH="64" TSUPP="power8" - TABI="linux" # there is no generic ABI on ppc64 - CC_RT_EXTRA_GCC="-mcpu=power8 -mlittle-endian" + TABI="linux-gnu" # there is no generic ABI on ppc64 + CC_RT_EXTRA_GCC="-mcpu=power8 -mbig-endian" } test_architecture() {

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Patch set updated for coreboot: buildgcc: Update coreboot's IASL version to 20160318
by Martin Roth 22 Mar '16

22 Mar '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12817 -gerrit commit 7cc6479531d42a48d82bf106280ab78126a18ac9 Author: Martin Roth <gaumless(a)gmail.com> Date: Wed Dec 30 15:10:13 2015 -0700 buildgcc: Update coreboot's IASL version to 20160318 Update IASL from 20150619 to 20160318 See release notes at acpica.org Change-Id: Ic7e7b3956378ad611069e984d5a59c78e4cb08b1 Signed-off-by: Martin Roth <gaumless(a)gmail.com> --- util/crossgcc/buildgcc | 6 ++--- .../patches/acpica-unix2-20150619_iasl.patch | 12 ---------- .../patches/acpica-unix2-20160318_iasl.patch | 27 ++++++++++++++++++++++ .../sum/acpica-unix2-20150619.tar.gz.cksum | 1 - .../sum/acpica-unix2-20160318.tar.gz.cksum | 1 + 5 files changed, 31 insertions(+), 16 deletions(-) diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index f88c09c..245211d 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -18,8 +18,8 @@ cd $(dirname $0) -CROSSGCC_DATE="March 1st, 2016" -CROSSGCC_VERSION="1.36" +CROSSGCC_DATE="March 21st, 2016" +CROSSGCC_VERSION="1.37" # default settings PACKAGE=GCC @@ -39,7 +39,7 @@ GCC_VERSION=5.2.0 GCC_AUTOCONF_VERSION=2.69 BINUTILS_VERSION=2.25 GDB_VERSION=7.9.1 -IASL_VERSION=20150619 +IASL_VERSION=20160318 PYTHON_VERSION=3.4.3 EXPAT_VERSION=2.1.0 # CLANG version number diff --git a/util/crossgcc/patches/acpica-unix2-20150619_iasl.patch b/util/crossgcc/patches/acpica-unix2-20150619_iasl.patch deleted file mode 100644 index 2c754c9..0000000 --- a/util/crossgcc/patches/acpica-unix2-20150619_iasl.patch +++ /dev/null @@ -1,12 +0,0 @@ -diff -urN acpica-unix-20150619/source/compiler/asloptions.c acpica-unix-20150619/source/compiler/asloptions.c ---- acpica-unix2-20150619/source/compiler/asloptions.c 2015-06-19 08:56:19.000000000 -0600 -+++ acpica-unix2-20150619/source/compiler/asloptions.c 2015-12-08 10:44:58.816669240 -0700 -@@ -717,6 +717,7 @@ - case '^': - - printf (ACPI_COMMON_SIGNON (ASL_COMPILER_NAME)); -+ printf ("%s\n", COREBOOT_TOOLCHAIN_VERSION); - exit (0); - - case 'a': - diff --git a/util/crossgcc/patches/acpica-unix2-20160318_iasl.patch b/util/crossgcc/patches/acpica-unix2-20160318_iasl.patch new file mode 100644 index 0000000..6c73d5a --- /dev/null +++ b/util/crossgcc/patches/acpica-unix2-20160318_iasl.patch @@ -0,0 +1,27 @@ +Add coreboot toolchain version string +--- acpica-unix2-20160318/source/compiler/asloptions.c ++++ acpica-unix2-20160318/source/compiler/asloptions.c +@@ -169,6 +169,7 @@ + if (argc < 2) + { + printf (ACPI_COMMON_SIGNON (ASL_COMPILER_NAME)); ++ printf ("%s\n", COREBOOT_TOOLCHAIN_VERSION); + Usage (); + exit (1); + } +@@ -199,6 +200,7 @@ + if (Gbl_DoSignon) + { + printf (ACPI_COMMON_SIGNON (ASL_COMPILER_NAME)); ++ printf ("%s\n", COREBOOT_TOOLCHAIN_VERSION); + if (Gbl_IgnoreErrors) + { + printf ("Ignoring all errors, forcing AML file generation\n\n"); +@@ -743,6 +745,7 @@ + case '^': + + printf (ACPI_COMMON_SIGNON (ASL_COMPILER_NAME)); ++ printf ("%s\n", COREBOOT_TOOLCHAIN_VERSION); + exit (0); + + case 'a': diff --git a/util/crossgcc/sum/acpica-unix2-20150619.tar.gz.cksum b/util/crossgcc/sum/acpica-unix2-20150619.tar.gz.cksum deleted file mode 100644 index 523e6da..0000000 --- a/util/crossgcc/sum/acpica-unix2-20150619.tar.gz.cksum +++ /dev/null @@ -1 +0,0 @@ -283c594c4b89db8e3bef8fca25021c52938987ad tarballs/acpica-unix2-20150619.tar.gz diff --git a/util/crossgcc/sum/acpica-unix2-20160318.tar.gz.cksum b/util/crossgcc/sum/acpica-unix2-20160318.tar.gz.cksum new file mode 100644 index 0000000..2f9b331 --- /dev/null +++ b/util/crossgcc/sum/acpica-unix2-20160318.tar.gz.cksum @@ -0,0 +1 @@ +786811c1501b9cc90c988293a1c3afefa33b60cc tarballs/acpica-unix2-20160318.tar.gz

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New patch to review for coreboot: Makefile: Update jenkins-build-toolchain to run built tests
by Martin Roth 22 Mar '16

22 Mar '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14156 -gerrit commit af980314e9e1ac5448e12bb63e26d2437bcae784 Author: Martin Roth <martinroth(a)google.com> Date: Tue Mar 22 13:05:42 2016 -0600 Makefile: Update jenkins-build-toolchain to run built tests Add coreboot build tests after running the toolchain build. This verifies that everything still builds with the new toolchain. Change-Id: Ifa51db897925c0b77791c83bbcbfd75045c907b5 Signed-off-by: Martin Roth <martinroth(a)google.com> --- util/crossgcc/Makefile.inc | 1 + 1 file changed, 1 insertion(+) diff --git a/util/crossgcc/Makefile.inc b/util/crossgcc/Makefile.inc index dfa1ec8..767b35c 100644 --- a/util/crossgcc/Makefile.inc +++ b/util/crossgcc/Makefile.inc @@ -71,3 +71,4 @@ endif # ifeq ($(COMPILER_OUT_OF_DATE),1) jenkins-build-toolchain: $(MAKE) crosstools clang \ BUILDGCC_OPTIONS='-y --nocolor' + $(MAKE) what-jenkins-does

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Patch merged into coreboot/master: MAINTAINERS: Add maintainer for Braswell SOC & Reference board
by gerrit＠coreboot.org 22 Mar '16

22 Mar '16

the following patch was just integrated into master: commit 4a1c69aa34cec4a959bc3318d68c287ed4eafbb0 Author: Martin Roth <martinroth(a)google.com> Date: Thu Mar 17 12:02:12 2016 -0600 MAINTAINERS: Add maintainer for Braswell SOC & Reference board Change-Id: If3b49c3056abe6e1c1a14578d6c62a866bc6834d Signed-off-by: Martin Roth <martinroth(a)google.com> Reviewed-on: https://review.coreboot.org/14127 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Reviewed-by: Hannah Williams <hannah.williams(a)intel.com> See https://review.coreboot.org/14127 for details. -gerrit

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