March 2016 - coreboot-gerrit - mail.coreboot.org

Patch set updated for coreboot: crossgcc: Switch POWER8 to big endian mode
by Martin Roth March 23, 2016

March 23, 2016

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14161 -gerrit commit 23409f3596e08fd7f93b176a2751d142b2110c2e Author: Martin Roth <martinroth(a)google.com> Date: Wed Mar 23 09:00:11 2016 -0600 crossgcc: Switch POWER8 to big endian mode Change-Id: If8c07fb3bee4bf0b531e52fae29890af99f924b4 Signed-off-by: Martin Roth <martinroth(a)google.com> --- util/crossgcc/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/util/crossgcc/Makefile b/util/crossgcc/Makefile index 917301c..24fe942 100644 --- a/util/crossgcc/Makefile +++ b/util/crossgcc/Makefile @@ -64,7 +64,7 @@ build-riscv: @$(MAKE) build_gcc BUILD_PLATFORM=riscv-elf build-power8: - @$(MAKE) build_tools BUILD_PLATFORM=powerpc64le-linux-gnu + @$(MAKE) build_tools BUILD_PLATFORM=powerpc64-linux-gnu build-nds32le: @$(MAKE) build_tools BUILD_PLATFORM=nds32le-elf

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Patch set updated for coreboot: crossgcc: Switch POWER8 to big endian mode and fix compiler detect
by Martin Roth March 23, 2016

March 23, 2016

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14018 -gerrit commit beffe7756d7b69137fec2258f8609c4ae801475d Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Wed Mar 9 17:20:26 2016 -0600 crossgcc: Switch POWER8 to big endian mode and fix compiler detect Change-Id: I7afb35fd5bc971a2c4d63e3a084ce7473f7a66fa Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- util/crossgcc/Makefile | 2 +- util/xcompile/xcompile | 9 +++++---- 2 files changed, 6 insertions(+), 5 deletions(-) diff --git a/util/crossgcc/Makefile b/util/crossgcc/Makefile index 917301c..24fe942 100644 --- a/util/crossgcc/Makefile +++ b/util/crossgcc/Makefile @@ -64,7 +64,7 @@ build-riscv: @$(MAKE) build_gcc BUILD_PLATFORM=riscv-elf build-power8: - @$(MAKE) build_tools BUILD_PLATFORM=powerpc64le-linux-gnu + @$(MAKE) build_tools BUILD_PLATFORM=powerpc64-linux-gnu build-nds32le: @$(MAKE) build_tools BUILD_PLATFORM=nds32le-elf diff --git a/util/xcompile/xcompile b/util/xcompile/xcompile index 53f0a85..2b9b818 100755 --- a/util/xcompile/xcompile +++ b/util/xcompile/xcompile @@ -4,6 +4,7 @@ # # Copyright (C) 2007-2010 coresystems GmbH # Copyright (C) 2012 Google Inc +# Copyright (C) 2016 Raptor Engineering, LLC # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by @@ -367,12 +368,12 @@ arch_config_mipsel() { arch_config_power8() { TARCH="power8" - TBFDARCHS="powerpcle" - TCLIST="powerpc64 powerpc64le" + TBFDARCHS="powerpc" + TCLIST="powerpc64" TWIDTH="64" TSUPP="power8" - TABI="linux" # there is no generic ABI on ppc64 - CC_RT_EXTRA_GCC="-mcpu=power8 -mlittle-endian" + TABI="linux-gnu" # there is no generic ABI on ppc64 + CC_RT_EXTRA_GCC="-mcpu=power8 -mbig-endian" } test_architecture() {

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Patch set updated for coreboot: intel/fsp_baytrail: Use read32() and write32() in i2c.c
by Ben Gardner March 23, 2016

March 23, 2016

Ben Gardner (gardner.ben(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14162 -gerrit commit 0401ee2f21771f79caf9d005e71c0409ee3852c2 Author: Ben Gardner <gardner.ben(a)gmail.com> Date: Wed Mar 23 10:11:24 2016 -0500 intel/fsp_baytrail: Use read32() and write32() in i2c.c i2c.c uses "*(volatile unsigned int *)" constructs where it could use read32() and write32(). Switch to using read32() and write32(). The remaining instances in wait_tx_fifo() and wait_rx_fifo() are fixed in https://review.coreboot.org/#/c/14160/ I also fixed a few minor white space issues. Change-Id: I587551272ac171ef1f42c7eb26daf877dc56646b Signed-off-by: Ben Gardner <gardner.ben(a)gmail.com> --- src/soc/intel/fsp_baytrail/i2c.c | 47 ++++++++++++++++++++-------------------- 1 file changed, 24 insertions(+), 23 deletions(-) diff --git a/src/soc/intel/fsp_baytrail/i2c.c b/src/soc/intel/fsp_baytrail/i2c.c index c6c8f65..5a0d59d 100644 --- a/src/soc/intel/fsp_baytrail/i2c.c +++ b/src/soc/intel/fsp_baytrail/i2c.c @@ -23,7 +23,8 @@ /* Wait for the transmit FIFO till there is at least one slot empty. * FIFO stall due to transmit abort will be checked and resolved */ -static int wait_tx_fifo(char *base_adr) { +static int wait_tx_fifo(char *base_adr) +{ int i; if (read32(base_adr + I2C_ABORT_SOURCE) & 0x1ffff) { @@ -35,7 +36,7 @@ static int wait_tx_fifo(char *base_adr) { /* Wait here for a free slot in TX-FIFO */ i = I2C_TIMEOUT_US; - while ((!(*((volatile unsigned int *)(base_adr + I2C_STATUS)) & I2C_TFNF))) { + while (!(read32(base_adr + I2C_STATUS) & I2C_TFNF)) { udelay(1); if (!--i) return I2C_ERR_TIMEOUT; @@ -47,7 +48,8 @@ static int wait_tx_fifo(char *base_adr) { /* Wait for the receive FIFO till there is at least one valid entry to read. * FIFO stall due to transmit abort will be checked and resolved */ -static int wait_rx_fifo(char *base_adr) { +static int wait_rx_fifo(char *base_adr) +{ int i; if (read32(base_adr + I2C_ABORT_SOURCE) & 0x1ffff) { /* Reading back I2C_CLR_TX_ABRT resets abort lock on TX FIFO */ @@ -58,7 +60,7 @@ static int wait_rx_fifo(char *base_adr) { /* Wait here for a received entry in RX-FIFO */ i = I2C_TIMEOUT_US; - while ((!(*((volatile unsigned int *)(base_adr + I2C_STATUS)) & I2C_RFNE))) { + while (!(read32(base_adr + I2C_STATUS) & I2C_RFNE)) { udelay(1); if (!--i) return I2C_ERR_TIMEOUT; @@ -74,20 +76,19 @@ static int wait_rx_fifo(char *base_adr) { static int wait_for_idle(char *base_adr) { int i; - volatile int status; + int status; /* For IDLE, increase timeout by ten times */ i = I2C_TIMEOUT_US * 10; - status = *((volatile unsigned int *)(base_adr + I2C_STATUS)); + status = read32(base_adr + I2C_STATUS); while (((status & I2C_MST_ACTIVITY) || (!(status & I2C_TFE)))) { - status = *((volatile unsigned int *)(base_adr + I2C_STATUS)); + status = read32(base_adr + I2C_STATUS); udelay(1); if (!--i) return I2C_ERR_TIMEOUT; } return I2C_SUCCESS; - } /** \brief Enables I2C-controller, sets up BAR and timing parameters @@ -101,6 +102,7 @@ int i2c_init(unsigned bus) I2C3_MEM_BASE, I2C4_MEM_BASE, I2C5_MEM_BASE, I2C6_MEM_BASE}; char *base_ptr; + /* Ensure the desired device is valid */ if (bus >= ARRAY_SIZE(base_adr)) { printk(BIOS_ERR, "I2C: Only I2C controllers 0...6 are available.\n"); @@ -126,20 +128,19 @@ int i2c_init(unsigned bus) (pci_read_config32(dev, PCI_COMMAND) | 0x2)); /* Set up some settings of I2C controller */ - *((unsigned int *)(base_ptr + I2C_CTRL)) = (I2C_RESTART_EN | - (I2C_STANDARD_MODE << 1) | - I2C_MASTER_ENABLE); + write32(base_ptr + I2C_CTRL, + I2C_RESTART_EN | (I2C_STANDARD_MODE << 1) | I2C_MASTER_ENABLE); /* Adjust frequency for standard mode to 100 kHz */ /* The counter value can be computed by N=100MHz/2/I2C_CLK */ /* Thus, for 100 kHz I2C_CLK, N is 0x1F4 */ - *((unsigned int *)(base_ptr + I2C_SS_SCL_HCNT)) = 0x1f4; - *((unsigned int *)(base_ptr + I2C_SS_SCL_LCNT)) = 0x1f4; + write32(base_ptr + I2C_SS_SCL_HCNT, 0x1f4); + write32(base_ptr + I2C_SS_SCL_LCNT, 0x1f4); /* For 400 kHz, the counter value is 0x7d */ - *((unsigned int *)(base_ptr + I2C_FS_SCL_HCNT)) = 0x7d; - *((unsigned int *)(base_ptr + I2C_FS_SCL_LCNT)) = 0x7d; + write32(base_ptr + I2C_FS_SCL_HCNT, 0x7d); + write32(base_ptr + I2C_FS_SCL_LCNT, 0x7d); /* Enable the I2C controller for operation */ - *((unsigned int *)(base_ptr + I2C_ENABLE)) = 0x1; + write32(base_ptr + I2C_ENABLE, 0x1); printk(BIOS_INFO, "I2C: Controller %d enabled.\n", bus); return I2C_SUCCESS; @@ -177,20 +178,20 @@ int i2c_read(unsigned bus, unsigned chip, unsigned addr, if (stat != I2C_SUCCESS) return stat; /* Now we can program the desired slave address and start transfer */ - *((unsigned int *)(base_ptr + I2C_TARGET_ADR)) = (chip & 0xff); + write32(base_ptr + I2C_TARGET_ADR, chip & 0xff); /* Send address inside slave to read from */ - *((unsigned int *)(base_ptr + I2C_DATA_CMD)) = (addr & 0xff); + write32(base_ptr + I2C_DATA_CMD, addr & 0xff); /* For the next byte we need a repeated start condition */ val = I2C_RW_CMD | I2C_RESTART; /* Now we can read desired amount of data over I2C */ for (i = 0; i < len; i++) { /* A read is initiated by writing dummy data to the DATA-register */ - *((unsigned int *)(base_ptr + I2C_DATA_CMD)) = val; + write32(base_ptr + I2C_DATA_CMD, val); stat = wait_rx_fifo(base_ptr); if (stat) return stat; - buf[i] = (*((unsigned int *)(base_ptr + I2C_DATA_CMD))) & 0xff; + buf[i] = read32(base_ptr + I2C_DATA_CMD) & 0xff; val = I2C_RW_CMD; if (i == (len - 2)) { /* For the last byte we need a stop condition to be generated */ @@ -232,10 +233,10 @@ int i2c_write(unsigned bus, unsigned chip, unsigned addr, return stat; } /* Program slave address to use for this transfer */ - *((unsigned int *)(base_ptr + I2C_TARGET_ADR)) = (chip & 0xff); + write32(base_ptr + I2C_TARGET_ADR, chip & 0xff); /* Send address inside slave to write data to */ - *((unsigned int *)(base_ptr + I2C_DATA_CMD)) = (addr & 0xff); + write32(base_ptr + I2C_DATA_CMD, addr & 0xff); for (i = 0; i < len; i++) { val = (unsigned int)(buf[i] & 0xff); /* Take only 8 bits */ @@ -247,7 +248,7 @@ int i2c_write(unsigned bus, unsigned chip, unsigned addr, if (stat) { return stat; } - *((unsigned int *)(base_ptr + I2C_DATA_CMD)) = val; + write32(base_ptr + I2C_DATA_CMD, val); } return I2C_SUCCESS; }

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New patch to review for coreboot: intel/fsp_baytrail: Switch to using read32() and write32() in i2c.c
by Ben Gardner March 23, 2016

March 23, 2016

Ben Gardner (gardner.ben(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14162 -gerrit commit 25e898834cc2cf2d136189fe579cf2a3fecb8f48 Author: Ben Gardner <gardner.ben(a)gmail.com> Date: Wed Mar 23 10:11:24 2016 -0500 intel/fsp_baytrail: Switch to using read32() and write32() in i2c.c i2c.c uses "*(volatile unsigned int *)" constructs where it could use read32() and write32(). Switch to using read32() and write32(). The remaining instances in wait_tx_fifo() and wait_rx_fifo() are fixed in https://review.coreboot.org/#/c/14160/ I also fixed a few minor white space issues. Change-Id: I587551272ac171ef1f42c7eb26daf877dc56646b Signed-off-by: Ben Gardner <gardner.ben(a)gmail.com> --- src/soc/intel/fsp_baytrail/i2c.c | 47 ++++++++++++++++++++-------------------- 1 file changed, 24 insertions(+), 23 deletions(-) diff --git a/src/soc/intel/fsp_baytrail/i2c.c b/src/soc/intel/fsp_baytrail/i2c.c index c6c8f65..5a0d59d 100644 --- a/src/soc/intel/fsp_baytrail/i2c.c +++ b/src/soc/intel/fsp_baytrail/i2c.c @@ -23,7 +23,8 @@ /* Wait for the transmit FIFO till there is at least one slot empty. * FIFO stall due to transmit abort will be checked and resolved */ -static int wait_tx_fifo(char *base_adr) { +static int wait_tx_fifo(char *base_adr) +{ int i; if (read32(base_adr + I2C_ABORT_SOURCE) & 0x1ffff) { @@ -35,7 +36,7 @@ static int wait_tx_fifo(char *base_adr) { /* Wait here for a free slot in TX-FIFO */ i = I2C_TIMEOUT_US; - while ((!(*((volatile unsigned int *)(base_adr + I2C_STATUS)) & I2C_TFNF))) { + while (!(read32(base_adr + I2C_STATUS) & I2C_TFNF)) { udelay(1); if (!--i) return I2C_ERR_TIMEOUT; @@ -47,7 +48,8 @@ static int wait_tx_fifo(char *base_adr) { /* Wait for the receive FIFO till there is at least one valid entry to read. * FIFO stall due to transmit abort will be checked and resolved */ -static int wait_rx_fifo(char *base_adr) { +static int wait_rx_fifo(char *base_adr) +{ int i; if (read32(base_adr + I2C_ABORT_SOURCE) & 0x1ffff) { /* Reading back I2C_CLR_TX_ABRT resets abort lock on TX FIFO */ @@ -58,7 +60,7 @@ static int wait_rx_fifo(char *base_adr) { /* Wait here for a received entry in RX-FIFO */ i = I2C_TIMEOUT_US; - while ((!(*((volatile unsigned int *)(base_adr + I2C_STATUS)) & I2C_RFNE))) { + while (!(read32(base_adr + I2C_STATUS) & I2C_RFNE)) { udelay(1); if (!--i) return I2C_ERR_TIMEOUT; @@ -74,20 +76,19 @@ static int wait_rx_fifo(char *base_adr) { static int wait_for_idle(char *base_adr) { int i; - volatile int status; + int status; /* For IDLE, increase timeout by ten times */ i = I2C_TIMEOUT_US * 10; - status = *((volatile unsigned int *)(base_adr + I2C_STATUS)); + status = read32(base_adr + I2C_STATUS); while (((status & I2C_MST_ACTIVITY) || (!(status & I2C_TFE)))) { - status = *((volatile unsigned int *)(base_adr + I2C_STATUS)); + status = read32(base_adr + I2C_STATUS); udelay(1); if (!--i) return I2C_ERR_TIMEOUT; } return I2C_SUCCESS; - } /** \brief Enables I2C-controller, sets up BAR and timing parameters @@ -101,6 +102,7 @@ int i2c_init(unsigned bus) I2C3_MEM_BASE, I2C4_MEM_BASE, I2C5_MEM_BASE, I2C6_MEM_BASE}; char *base_ptr; + /* Ensure the desired device is valid */ if (bus >= ARRAY_SIZE(base_adr)) { printk(BIOS_ERR, "I2C: Only I2C controllers 0...6 are available.\n"); @@ -126,20 +128,19 @@ int i2c_init(unsigned bus) (pci_read_config32(dev, PCI_COMMAND) | 0x2)); /* Set up some settings of I2C controller */ - *((unsigned int *)(base_ptr + I2C_CTRL)) = (I2C_RESTART_EN | - (I2C_STANDARD_MODE << 1) | - I2C_MASTER_ENABLE); + write32(base_ptr + I2C_CTRL, + I2C_RESTART_EN | (I2C_STANDARD_MODE << 1) | I2C_MASTER_ENABLE); /* Adjust frequency for standard mode to 100 kHz */ /* The counter value can be computed by N=100MHz/2/I2C_CLK */ /* Thus, for 100 kHz I2C_CLK, N is 0x1F4 */ - *((unsigned int *)(base_ptr + I2C_SS_SCL_HCNT)) = 0x1f4; - *((unsigned int *)(base_ptr + I2C_SS_SCL_LCNT)) = 0x1f4; + write32(base_ptr + I2C_SS_SCL_HCNT, 0x1f4); + write32(base_ptr + I2C_SS_SCL_LCNT, 0x1f4); /* For 400 kHz, the counter value is 0x7d */ - *((unsigned int *)(base_ptr + I2C_FS_SCL_HCNT)) = 0x7d; - *((unsigned int *)(base_ptr + I2C_FS_SCL_LCNT)) = 0x7d; + write32(base_ptr + I2C_FS_SCL_HCNT, 0x7d); + write32(base_ptr + I2C_FS_SCL_LCNT, 0x7d); /* Enable the I2C controller for operation */ - *((unsigned int *)(base_ptr + I2C_ENABLE)) = 0x1; + write32(base_ptr + I2C_ENABLE, 0x1); printk(BIOS_INFO, "I2C: Controller %d enabled.\n", bus); return I2C_SUCCESS; @@ -177,20 +178,20 @@ int i2c_read(unsigned bus, unsigned chip, unsigned addr, if (stat != I2C_SUCCESS) return stat; /* Now we can program the desired slave address and start transfer */ - *((unsigned int *)(base_ptr + I2C_TARGET_ADR)) = (chip & 0xff); + write32(base_ptr + I2C_TARGET_ADR, chip & 0xff); /* Send address inside slave to read from */ - *((unsigned int *)(base_ptr + I2C_DATA_CMD)) = (addr & 0xff); + write32(base_ptr + I2C_DATA_CMD, addr & 0xff); /* For the next byte we need a repeated start condition */ val = I2C_RW_CMD | I2C_RESTART; /* Now we can read desired amount of data over I2C */ for (i = 0; i < len; i++) { /* A read is initiated by writing dummy data to the DATA-register */ - *((unsigned int *)(base_ptr + I2C_DATA_CMD)) = val; + write32(base_ptr + I2C_DATA_CMD, val); stat = wait_rx_fifo(base_ptr); if (stat) return stat; - buf[i] = (*((unsigned int *)(base_ptr + I2C_DATA_CMD))) & 0xff; + buf[i] = read32(base_ptr + I2C_DATA_CMD) & 0xff; val = I2C_RW_CMD; if (i == (len - 2)) { /* For the last byte we need a stop condition to be generated */ @@ -232,10 +233,10 @@ int i2c_write(unsigned bus, unsigned chip, unsigned addr, return stat; } /* Program slave address to use for this transfer */ - *((unsigned int *)(base_ptr + I2C_TARGET_ADR)) = (chip & 0xff); + write32(base_ptr + I2C_TARGET_ADR, chip & 0xff); /* Send address inside slave to write data to */ - *((unsigned int *)(base_ptr + I2C_DATA_CMD)) = (addr & 0xff); + write32(base_ptr + I2C_DATA_CMD, addr & 0xff); for (i = 0; i < len; i++) { val = (unsigned int)(buf[i] & 0xff); /* Take only 8 bits */ @@ -247,7 +248,7 @@ int i2c_write(unsigned bus, unsigned chip, unsigned addr, if (stat) { return stat; } - *((unsigned int *)(base_ptr + I2C_DATA_CMD)) = val; + write32(base_ptr + I2C_DATA_CMD, val); } return I2C_SUCCESS; }

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New patch to review for coreboot: crossgcc: Switch POWER8 to big endian mode
by Martin Roth March 23, 2016

March 23, 2016

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14161 -gerrit commit f03e0674984ad895fd529ba4919c450323f933f5 Author: Martin Roth <martinroth(a)google.com> Date: Wed Mar 23 09:00:11 2016 -0600 crossgcc: Switch POWER8 to big endian mode Change-Id: If8c07fb3bee4bf0b531e52fae29890af99f924b4 Signed-off-by: Martin Roth <martinroth(a)google.com> --- util/crossgcc/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/util/crossgcc/Makefile b/util/crossgcc/Makefile index 917301c..24fe942 100644 --- a/util/crossgcc/Makefile +++ b/util/crossgcc/Makefile @@ -64,7 +64,7 @@ build-riscv: @$(MAKE) build_gcc BUILD_PLATFORM=riscv-elf build-power8: - @$(MAKE) build_tools BUILD_PLATFORM=powerpc64le-linux-gnu + @$(MAKE) build_tools BUILD_PLATFORM=powerpc64-linux-gnu build-nds32le: @$(MAKE) build_tools BUILD_PLATFORM=nds32le-elf

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Patch set updated for coreboot: Makefile: Update jenkins-build-toolchain to run built tests
by Martin Roth March 23, 2016

March 23, 2016

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14156 -gerrit commit 587e5d14d84e04ae8d919bd6e6777bb919ab3104 Author: Martin Roth <martinroth(a)google.com> Date: Tue Mar 22 13:05:42 2016 -0600 Makefile: Update jenkins-build-toolchain to run built tests Add coreboot build tests after running the toolchain build. This verifies that everything still builds with the new toolchain. Change-Id: Ifa51db897925c0b77791c83bbcbfd75045c907b5 Signed-off-by: Martin Roth <martinroth(a)google.com> --- util/crossgcc/Makefile.inc | 1 + 1 file changed, 1 insertion(+) diff --git a/util/crossgcc/Makefile.inc b/util/crossgcc/Makefile.inc index dfa1ec8..767b35c 100644 --- a/util/crossgcc/Makefile.inc +++ b/util/crossgcc/Makefile.inc @@ -71,3 +71,4 @@ endif # ifeq ($(COMPILER_OUT_OF_DATE),1) jenkins-build-toolchain: $(MAKE) crosstools clang \ BUILDGCC_OPTIONS='-y --nocolor' + $(MAKE) what-jenkins-does

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Patch set updated for coreboot: Makefile: Update jenkins-build-toolchain to run built tests
by Martin Roth March 23, 2016

March 23, 2016

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14156 -gerrit commit 8b7672205b337c3ba65007badb0cbd1a964d3ddb Author: Martin Roth <martinroth(a)google.com> Date: Tue Mar 22 13:05:42 2016 -0600 Makefile: Update jenkins-build-toolchain to run built tests Add coreboot build tests after running the toolchain build. This verifies that everything still builds with the new toolchain. Change-Id: Ifa51db897925c0b77791c83bbcbfd75045c907b5 Signed-off-by: Martin Roth <martinroth(a)google.com> --- util/crossgcc/Makefile.inc | 1 + 1 file changed, 1 insertion(+) diff --git a/util/crossgcc/Makefile.inc b/util/crossgcc/Makefile.inc index dfa1ec8..767b35c 100644 --- a/util/crossgcc/Makefile.inc +++ b/util/crossgcc/Makefile.inc @@ -71,3 +71,4 @@ endif # ifeq ($(COMPILER_OUT_OF_DATE),1) jenkins-build-toolchain: $(MAKE) crosstools clang \ BUILDGCC_OPTIONS='-y --nocolor' + $(MAKE) what-jenkins-does

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New patch to review for coreboot: intel/fsp_baytrail: Fix I2C abort logic
by Ben Gardner March 23, 2016

March 23, 2016

Ben Gardner (gardner.ben(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14160 -gerrit commit 2d6743ece3b3c5021568602e0acd8e9d77c1b09a Author: Ben Gardner <gardner.ben(a)gmail.com> Date: Wed Mar 23 09:40:37 2016 -0500 intel/fsp_baytrail: Fix I2C abort logic A call to i2c_read() for a non-existent address followed by an i2c_read() to a valid address results in a false abort status for the 2nd call. i2c_read(1, 0x40, 0, buf, sizeof(buf)) => 0x2000000 (I2C_ERR_TIMEOUT) i2c_read(1, 0x74, 0, buf, sizeof(buf)) => 0x4000000 (I2C_ERR_ABORT) Because the abort status register is cleared on read and wait_tx_fifo() reads it twice, the returned status does not contain the abort status. Fixing that changed the 2nd read to reflect the abort status. i2c_read(1, 0x40, 0, buf, sizeof(buf)) => 0x2000000 (I2C_ERR_TIMEOUT) i2c_read(1, 0x74, 0, buf, sizeof(buf)) => 0x4000001 (I2C_ERR_ABORT) Bit 0 indicates that the address was not acknowledged by any slave. That's the abort status from the previous transaction. So I added a read of the abort status before starting a transaction in both i2c_read() and i2c_write(). i2c_read(1, 0x40, 0, buf, sizeof(buf)) => 0x2000000 (I2C_ERR_TIMEOUT) i2c_read(1, 0x74, 0, buf, sizeof(buf)) => 0 (I2C_SUCCESS) Tested on a Bay Trail E3845 SoC. Change-Id: I39e4ff4206587267b6fceef58f4a567bf162fbbe Signed-off-by: Ben Gardner <gardner.ben(a)gmail.com> --- src/soc/intel/fsp_baytrail/i2c.c | 27 +++++++++++++++++++-------- 1 file changed, 19 insertions(+), 8 deletions(-) diff --git a/src/soc/intel/fsp_baytrail/i2c.c b/src/soc/intel/fsp_baytrail/i2c.c index c6c8f65..38ac451 100644 --- a/src/soc/intel/fsp_baytrail/i2c.c +++ b/src/soc/intel/fsp_baytrail/i2c.c @@ -25,12 +25,13 @@ */ static int wait_tx_fifo(char *base_adr) { int i; + u32 as; - if (read32(base_adr + I2C_ABORT_SOURCE) & 0x1ffff) { + as = read32(base_adr + I2C_ABORT_SOURCE) & 0x1ffff; + if (as) { /* Reading back I2C_CLR_TX_ABRT resets abort lock on TX FIFO */ - i = *((volatile unsigned int *)(base_adr + I2C_CLR_TX_ABRT)); - return I2C_ERR_ABORT | - (*((unsigned int *)(base_adr + I2C_ABORT_SOURCE)) & 0x1ffff); + i = read32(base_adr + I2C_CLR_TX_ABRT); + return I2C_ERR_ABORT | as; } /* Wait here for a free slot in TX-FIFO */ @@ -49,11 +50,13 @@ static int wait_tx_fifo(char *base_adr) { */ static int wait_rx_fifo(char *base_adr) { int i; - if (read32(base_adr + I2C_ABORT_SOURCE) & 0x1ffff) { + u32 as; + + as = read32(base_adr + I2C_ABORT_SOURCE) & 0x1ffff; + if (as) { /* Reading back I2C_CLR_TX_ABRT resets abort lock on TX FIFO */ - i = *((volatile unsigned int *)(base_adr + I2C_CLR_TX_ABRT)); - return I2C_ERR_ABORT | - (*((unsigned int *)(base_adr + I2C_ABORT_SOURCE)) & 0x1ffff); + i = read32(base_adr + I2C_CLR_TX_ABRT); + return I2C_ERR_ABORT | as; } /* Wait here for a received entry in RX-FIFO */ @@ -176,6 +179,10 @@ int i2c_read(unsigned bus, unsigned chip, unsigned addr, stat = wait_for_idle(base_ptr); if (stat != I2C_SUCCESS) return stat; + + /* clear any abort status from a previous transaction */ + read32(base_ptr + I2C_CLR_TX_ABRT); + /* Now we can program the desired slave address and start transfer */ *((unsigned int *)(base_ptr + I2C_TARGET_ADR)) = (chip & 0xff); /* Send address inside slave to read from */ @@ -231,6 +238,10 @@ int i2c_write(unsigned bus, unsigned chip, unsigned addr, if (stat) { return stat; } + + /* clear any abort status from a previous transaction */ + read32(base_ptr + I2C_CLR_TX_ABRT); + /* Program slave address to use for this transfer */ *((unsigned int *)(base_ptr + I2C_TARGET_ADR)) = (chip & 0xff);

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Patch set updated for coreboot: Makefile: Update jenkins-build-toolchain to run built tests
by Martin Roth March 23, 2016

March 23, 2016

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14156 -gerrit commit 8722497c5cf440f3a6128a0f78790e9b65b64066 Author: Martin Roth <martinroth(a)google.com> Date: Tue Mar 22 13:05:42 2016 -0600 Makefile: Update jenkins-build-toolchain to run built tests Add coreboot build tests after running the toolchain build. This verifies that everything still builds with the new toolchain. Change-Id: Ifa51db897925c0b77791c83bbcbfd75045c907b5 Signed-off-by: Martin Roth <martinroth(a)google.com> --- util/crossgcc/Makefile.inc | 1 + 1 file changed, 1 insertion(+) diff --git a/util/crossgcc/Makefile.inc b/util/crossgcc/Makefile.inc index dfa1ec8..767b35c 100644 --- a/util/crossgcc/Makefile.inc +++ b/util/crossgcc/Makefile.inc @@ -71,3 +71,4 @@ endif # ifeq ($(COMPILER_OUT_OF_DATE),1) jenkins-build-toolchain: $(MAKE) crosstools clang \ BUILDGCC_OPTIONS='-y --nocolor' + $(MAKE) what-jenkins-does

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Patch merged into coreboot/master: soc/intel/apollolake: utilize postcar phase/stage
by gerrit＠coreboot.org March 23, 2016

March 23, 2016

the following patch was just integrated into master: commit eebe0e0db14476dde980896b8eb8a97129436af3 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Mar 18 11:19:38 2016 -0500 soc/intel/apollolake: utilize postcar phase/stage The current Apollolake flow has its code executing out of cache-as-ram for the pre-DRAM stages. This is different from past platforms where they were just executing-in-place against the memory-mapped SPI flash boot media. The implication is that when cache-as-ram needs to be torn down one needs to be executing out of DRAM since the act of cache-as-ram going away means the code disappears out from under the processor. Therefore load and use the postcar infrastructure to bootstrap this process for tearing down cache-as-ram and subsequently loading ramstage. Change-Id: I856f4b992dd2609b95375767bfa4fe64a267d89e Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://review.coreboot.org/14141 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> Reviewed-by: Furquan Shaikh <furquan(a)google.com> See https://review.coreboot.org/14141 for details. -gerrit

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