coreboot-gerrit March 2016

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Patch set updated for coreboot: google/intel mainboards: Add missing board_info.txt files
by Martin Roth 25 Mar '16

25 Mar '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14117 -gerrit commit 5a53a6896e06d52bbba1bd172d4691a23b37c136 Author: Martin Roth <martinroth(a)google.com> Date: Wed Mar 16 18:36:35 2016 -0600 google/intel mainboards: Add missing board_info.txt files The lint script didn't catch that these mainboard directories didn't have board_info files. Add all missing board_info.txt files Change-Id: Ib1d61a3c04e91b22480527885faf60c22093d98a Signed-off-by: Martin Roth <martinroth(a)google.com> --- src/mainboard/google/auron_paine/board_info.txt | 6 ++++++ src/mainboard/google/chell/board_info.txt | 6 ++++++ src/mainboard/google/cosmos/board_info.txt | 5 +++++ src/mainboard/google/cyan/board_info.txt | 6 ++++++ src/mainboard/google/foster/board_info.txt | 6 ++++++ src/mainboard/google/glados/board_info.txt | 6 ++++++ src/mainboard/google/jecht/board_info.txt | 6 ++++++ src/mainboard/google/lars/board_info.txt | 6 ++++++ src/mainboard/google/nyan_blaze/board_info.txt | 6 ++++++ src/mainboard/google/oak/board_info.txt | 6 ++++++ src/mainboard/google/purin/board_info.txt | 6 ++++++ src/mainboard/google/rush/board_info.txt | 6 ++++++ src/mainboard/google/rush_ryu/board_info.txt | 6 ++++++ src/mainboard/google/smaug/board_info.txt | 6 ++++++ src/mainboard/google/storm/board_info.txt | 6 ++++++ src/mainboard/google/urara/board_info.txt | 5 +++++ src/mainboard/google/veyron/board_info.txt | 6 ++++++ src/mainboard/google/veyron_brain/board_info.txt | 6 ++++++ src/mainboard/google/veyron_danger/board_info.txt | 6 ++++++ src/mainboard/google/veyron_emile/board_info.txt | 6 ++++++ src/mainboard/google/veyron_mickey/board_info.txt | 6 ++++++ src/mainboard/google/veyron_rialto/board_info.txt | 6 ++++++ src/mainboard/google/veyron_romy/board_info.txt | 6 ++++++ src/mainboard/intel/apollolake_rvp/board_info.txt | 6 ++++++ src/mainboard/intel/kunimitsu/board_info.txt | 6 ++++++ src/mainboard/intel/strago/board_info.txt | 6 ++++++ 26 files changed, 154 insertions(+) diff --git a/src/mainboard/google/auron_paine/board_info.txt b/src/mainboard/google/auron_paine/board_info.txt new file mode 100644 index 0000000..2c6971b --- /dev/null +++ b/src/mainboard/google/auron_paine/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: Google +Board name: Auron Paine Broadwell chromebook +Category: laptop +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/google/chell/board_info.txt b/src/mainboard/google/chell/board_info.txt new file mode 100644 index 0000000..be33f44 --- /dev/null +++ b/src/mainboard/google/chell/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: Google +Board name: Chell Skylake Reference Board +Category: laptop +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/google/cosmos/board_info.txt b/src/mainboard/google/cosmos/board_info.txt new file mode 100644 index 0000000..15e52fd --- /dev/null +++ b/src/mainboard/google/cosmos/board_info.txt @@ -0,0 +1,5 @@ +Vendor name: Google +Board name: Cosmos Marvell BG4CD reference board +Category: eval +ROM protocol: SPI +ROM socketed: n diff --git a/src/mainboard/google/cyan/board_info.txt b/src/mainboard/google/cyan/board_info.txt new file mode 100644 index 0000000..8815b36 --- /dev/null +++ b/src/mainboard/google/cyan/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: Google +Board name: Cyan Braswell reference board +Category: laptop +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/google/foster/board_info.txt b/src/mainboard/google/foster/board_info.txt new file mode 100644 index 0000000..1a4f42d --- /dev/null +++ b/src/mainboard/google/foster/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: Google +Board name: Foster Nvidia Tegra210 reference board +Category: eval +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/google/glados/board_info.txt b/src/mainboard/google/glados/board_info.txt new file mode 100644 index 0000000..958df10 --- /dev/null +++ b/src/mainboard/google/glados/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: Google +Board name: Glados Skylake Reference Board +Category: laptop +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/google/jecht/board_info.txt b/src/mainboard/google/jecht/board_info.txt new file mode 100644 index 0000000..67697e0 --- /dev/null +++ b/src/mainboard/google/jecht/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: Google +Board name: Jecht Broadwell Chromebox +Category: settop +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/google/lars/board_info.txt b/src/mainboard/google/lars/board_info.txt new file mode 100644 index 0000000..8547dda --- /dev/null +++ b/src/mainboard/google/lars/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: Google +Board name: Lars Skylake chromebook +Category: laptop +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/google/nyan_blaze/board_info.txt b/src/mainboard/google/nyan_blaze/board_info.txt new file mode 100644 index 0000000..79a250a --- /dev/null +++ b/src/mainboard/google/nyan_blaze/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: Google +Board name: Nyan Blaze Nvidia Tegra T124 Chromebook +Category: laptop +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/google/oak/board_info.txt b/src/mainboard/google/oak/board_info.txt new file mode 100644 index 0000000..ddd05bc --- /dev/null +++ b/src/mainboard/google/oak/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: Google +Board name: Oak MediaTek MT8173 reference board +Category: laptop +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/google/purin/board_info.txt b/src/mainboard/google/purin/board_info.txt new file mode 100644 index 0000000..878db18 --- /dev/null +++ b/src/mainboard/google/purin/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: Google +Board name: Purin Broadcom Cygnus reference board +Category: eval +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/google/rush/board_info.txt b/src/mainboard/google/rush/board_info.txt new file mode 100644 index 0000000..7be004d --- /dev/null +++ b/src/mainboard/google/rush/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: Google +Board name: Rush Nvidia Tegra132 reference board +Category: eval +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/google/rush_ryu/board_info.txt b/src/mainboard/google/rush_ryu/board_info.txt new file mode 100644 index 0000000..dd52e9c --- /dev/null +++ b/src/mainboard/google/rush_ryu/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: Google +Board name: Rush Ryu Nvidia Tegra132 board +Category: eval +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/google/smaug/board_info.txt b/src/mainboard/google/smaug/board_info.txt new file mode 100644 index 0000000..fbca4ab --- /dev/null +++ b/src/mainboard/google/smaug/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: Google +Board name: Smaug Nvidia Tegra210 tablet +Category: misc +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/google/storm/board_info.txt b/src/mainboard/google/storm/board_info.txt new file mode 100644 index 0000000..edc4b32 --- /dev/null +++ b/src/mainboard/google/storm/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: Google +Board name: Storm Qualcomm IPQ806X board +Category: settop +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/google/urara/board_info.txt b/src/mainboard/google/urara/board_info.txt new file mode 100644 index 0000000..0458abd --- /dev/null +++ b/src/mainboard/google/urara/board_info.txt @@ -0,0 +1,5 @@ +Vendor name: Google +Board name: Urara Imgtec Pistachio reference board +Category: eval +ROM protocol: SPI +ROM socketed: n diff --git a/src/mainboard/google/veyron/board_info.txt b/src/mainboard/google/veyron/board_info.txt new file mode 100644 index 0000000..5ee07fb --- /dev/null +++ b/src/mainboard/google/veyron/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: Google +Board name: Veyron Rockchip RK3288 boards +Category: misc +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/google/veyron_brain/board_info.txt b/src/mainboard/google/veyron_brain/board_info.txt new file mode 100644 index 0000000..c82b566 --- /dev/null +++ b/src/mainboard/google/veyron_brain/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: Google +Board name: Veyron Brain Rockchip RK3288 chromebox +Category: settop +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/google/veyron_danger/board_info.txt b/src/mainboard/google/veyron_danger/board_info.txt new file mode 100644 index 0000000..a2077a2 --- /dev/null +++ b/src/mainboard/google/veyron_danger/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: Google +Board name: Veyron Danger Rockchip RK3288 board +Category: misc +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/google/veyron_emile/board_info.txt b/src/mainboard/google/veyron_emile/board_info.txt new file mode 100644 index 0000000..bc7b70d --- /dev/null +++ b/src/mainboard/google/veyron_emile/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: Google +Board name: Veyron Emile Rockchip RK3288 board +Category: misc +ROM protocol: SPI +ROM socketed: n +Flashrom support: ? diff --git a/src/mainboard/google/veyron_mickey/board_info.txt b/src/mainboard/google/veyron_mickey/board_info.txt new file mode 100644 index 0000000..1a15387 --- /dev/null +++ b/src/mainboard/google/veyron_mickey/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: Google +Board name: Veyron Mickey Rockchip RK3288 board +Category: misc +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/google/veyron_rialto/board_info.txt b/src/mainboard/google/veyron_rialto/board_info.txt new file mode 100644 index 0000000..7a5402f --- /dev/null +++ b/src/mainboard/google/veyron_rialto/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: Google +Board name: Veyron Rialto Rockchip RK3288 board +Category: misc +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/google/veyron_romy/board_info.txt b/src/mainboard/google/veyron_romy/board_info.txt new file mode 100644 index 0000000..a1ae42d --- /dev/null +++ b/src/mainboard/google/veyron_romy/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: Google +Board name: Veyron Romy Rockchip RK3288 board +Category: misc +ROM protocol: SPI +ROM socketed: n +Flashrom support: ? diff --git a/src/mainboard/intel/apollolake_rvp/board_info.txt b/src/mainboard/intel/apollolake_rvp/board_info.txt new file mode 100644 index 0000000..eb95944 --- /dev/null +++ b/src/mainboard/intel/apollolake_rvp/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: Intel +Board name: Apollolake RVP Reference Board +Category: eval +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/intel/kunimitsu/board_info.txt b/src/mainboard/intel/kunimitsu/board_info.txt new file mode 100644 index 0000000..acf033c --- /dev/null +++ b/src/mainboard/intel/kunimitsu/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: Intel +Board name: Kunimitsu Skylake Reference Board +Category: laptop +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/intel/strago/board_info.txt b/src/mainboard/intel/strago/board_info.txt new file mode 100644 index 0000000..3da4aa9 --- /dev/null +++ b/src/mainboard/intel/strago/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: Intel +Board name: Strago Braswell Reference Board +Category: laptop +ROM protocol: SPI +ROM socketed: n +Flashrom support: y

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Patch set updated for coreboot: lint: Update board status script to look at the whole tree
by Martin Roth 25 Mar '16

25 Mar '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14118 -gerrit commit 41624eb9a2acc0b6e6c9f2d330563faf9c3afb1f Author: Martin Roth <martinroth(a)google.com> Date: Wed Mar 16 15:58:23 2016 -0600 lint: Update board status script to look at the whole tree The board status script wasn't checking the entire tree to make sure that all boards had board_info.txt files. Also it would only print out the first issue that was found. Change-Id: I5f2fa9e564c805c6dbee7a35cab80c1c342567a5 Signed-off-by: Martin Roth <martinroth(a)google.com> --- util/lint/lint-stable-005-board-status | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/util/lint/lint-stable-005-board-status b/util/lint/lint-stable-005-board-status index 61813ea..952a9b5 100755 --- a/util/lint/lint-stable-005-board-status +++ b/util/lint/lint-stable-005-board-status @@ -16,11 +16,11 @@ # DESCR: Check that every board has a meaningful board_info.txt LC_ALL=C export LC_ALL -for mobodir in $(git diff --diff-filter ACMR --name-only src/mainboard | sed -n 's,^$src/mainboard/[^/]*/[^/]*$/.*$,\1,p'|sort|uniq); do +for mobodir in $(git ls-files src/mainboard | sed -n 's,^$src/mainboard/[^/]*/[^/]*$/.*$,\1,p'|sort|uniq); do board_info="$mobodir/board_info.txt" if ! [ -f "$board_info" ]; then echo "No $board_info found" - exit 1 + continue fi category="$(sed -n 's#^Category: $.*$$#\1#p' < "$board_info")" case "$category" in @@ -28,11 +28,11 @@ for mobodir in $(git diff --diff-filter ACMR --name-only src/mainboard | sed -n ;; "") echo "$board_info doesn't contain 'Category' tag" - exit 1 + continue ;; *) echo "$board_info specifies unknown category '$category'" - exit 1 + continue ;; esac done

1 0

Patch set updated for coreboot: crossgcc: Fix compiler detect for POWER8 big endian mode switch.
by Timothy Pearson 25 Mar '16

25 Mar '16

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14018 -gerrit commit 107e0e700edc70e0f8e32999315da238f36334cf Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Wed Mar 9 17:20:26 2016 -0600 crossgcc: Fix compiler detect for POWER8 big endian mode switch. Change-Id: I7afb35fd5bc971a2c4d63e3a084ce7473f7a66fa Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- util/xcompile/xcompile | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/util/xcompile/xcompile b/util/xcompile/xcompile index 53f0a85..2b9b818 100755 --- a/util/xcompile/xcompile +++ b/util/xcompile/xcompile @@ -4,6 +4,7 @@ # # Copyright (C) 2007-2010 coresystems GmbH # Copyright (C) 2012 Google Inc +# Copyright (C) 2016 Raptor Engineering, LLC # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by @@ -367,12 +368,12 @@ arch_config_mipsel() { arch_config_power8() { TARCH="power8" - TBFDARCHS="powerpcle" - TCLIST="powerpc64 powerpc64le" + TBFDARCHS="powerpc" + TCLIST="powerpc64" TWIDTH="64" TSUPP="power8" - TABI="linux" # there is no generic ABI on ppc64 - CC_RT_EXTRA_GCC="-mcpu=power8 -mlittle-endian" + TABI="linux-gnu" # there is no generic ABI on ppc64 + CC_RT_EXTRA_GCC="-mcpu=power8 -mbig-endian" } test_architecture() {

1 0

Patch merged into coreboot/master: util/intelmetool: Add intelmetool from Damien Zammit
by gerrit＠coreboot.org 25 Mar '16

25 Mar '16

the following patch was just integrated into master: commit d8fe4431ec7e158be1267ecece8d7d338a4b9703 Author: Philipp Deppenwiese <zaolin(a)das-labor.org> Date: Fri Mar 18 00:52:54 2016 +0100 util/intelmetool: Add intelmetool from Damien Zammit The intelmetool shows information about the Intel Management Engine for different platforms. Original source code can be found under following link: https://github.com/zamaudio/intelmetool.git Change-Id: I0eb17833a21eb04cf9245a7312289a4102bec1a9 Signed-off-by: Philipp Deppenwiese <zaolin(a)das-labor.org> Reviewed-on: https://review.coreboot.org/14136 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/14136 for details. -gerrit

1 0

Patch merged into coreboot/master: intel/fsp_baytrail: Fix I2C abort logic
by gerrit＠coreboot.org 25 Mar '16

25 Mar '16

the following patch was just integrated into master: commit 77e351d9d17cf8e8ad1c70200192ac59285b3096 Author: Ben Gardner <gardner.ben(a)gmail.com> Date: Wed Mar 23 09:40:37 2016 -0500 intel/fsp_baytrail: Fix I2C abort logic A call to i2c_read() for a non-existent address followed by an i2c_read() to a valid address results in a false abort status for the 2nd call. i2c_read(1, 0x40, 0, buf, sizeof(buf)) => 0x2000000 (I2C_ERR_TIMEOUT) i2c_read(1, 0x74, 0, buf, sizeof(buf)) => 0x4000000 (I2C_ERR_ABORT) Because the abort status register is cleared on read and wait_tx_fifo() reads it twice, the returned status does not contain the abort status. Fixing that changed the 2nd read to reflect the abort status. i2c_read(1, 0x40, 0, buf, sizeof(buf)) => 0x2000000 (I2C_ERR_TIMEOUT) i2c_read(1, 0x74, 0, buf, sizeof(buf)) => 0x4000001 (I2C_ERR_ABORT) Bit 0 indicates that the address was not acknowledged by any slave. That's the abort status from the previous transaction. So I added a read of the abort status before starting a transaction in both i2c_read() and i2c_write(). i2c_read(1, 0x40, 0, buf, sizeof(buf)) => 0x2000000 (I2C_ERR_TIMEOUT) i2c_read(1, 0x74, 0, buf, sizeof(buf)) => 0 (I2C_SUCCESS) Tested on a Bay Trail E3845 SoC. Change-Id: I39e4ff4206587267b6fceef58f4a567bf162fbbe Signed-off-by: Ben Gardner <gardner.ben(a)gmail.com> Reviewed-on: https://review.coreboot.org/14160 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> Reviewed-by: Werner Zeh <werner.zeh(a)siemens.com> See https://review.coreboot.org/14160 for details. -gerrit

1 0

Patch merged into coreboot/master: intel/fsp_baytrail: Use read32() and write32() in i2c.c
by gerrit＠coreboot.org 25 Mar '16

25 Mar '16

the following patch was just integrated into master: commit 5aecd0e533fe8e7dd5fee0a3c10ee8aabe6c8803 Author: Ben Gardner <gardner.ben(a)gmail.com> Date: Wed Mar 23 10:11:24 2016 -0500 intel/fsp_baytrail: Use read32() and write32() in i2c.c i2c.c uses "*(volatile unsigned int *)" constructs where it could use read32() and write32(). Switch to using read32() and write32(). The remaining instances in wait_tx_fifo() and wait_rx_fifo() are fixed in https://review.coreboot.org/#/c/14160/ Change-Id: I39e4ff4206587267b6fceef58f4a567bf162fbbe (intel/fsp_baytrail: Fix I2C abort logic) I also fixed a few minor white space issues. Change-Id: I587551272ac171ef1f42c7eb26daf877dc56646b Signed-off-by: Ben Gardner <gardner.ben(a)gmail.com> Reviewed-on: https://review.coreboot.org/14162 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> Reviewed-by: Werner Zeh <werner.zeh(a)siemens.com> See https://review.coreboot.org/14162 for details. -gerrit

1 0

Patch set updated for coreboot: intel/fsp_baytrail: Use read32() and write32() in i2c.c
by Ben Gardner 25 Mar '16

25 Mar '16

Ben Gardner (gardner.ben(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14162 -gerrit commit 0e573d3962c5082118c825ae3681e490d2221333 Author: Ben Gardner <gardner.ben(a)gmail.com> Date: Wed Mar 23 10:11:24 2016 -0500 intel/fsp_baytrail: Use read32() and write32() in i2c.c i2c.c uses "*(volatile unsigned int *)" constructs where it could use read32() and write32(). Switch to using read32() and write32(). The remaining instances in wait_tx_fifo() and wait_rx_fifo() are fixed in https://review.coreboot.org/#/c/14160/ Change-Id: I39e4ff4206587267b6fceef58f4a567bf162fbbe (intel/fsp_baytrail: Fix I2C abort logic) I also fixed a few minor white space issues. Change-Id: I587551272ac171ef1f42c7eb26daf877dc56646b Signed-off-by: Ben Gardner <gardner.ben(a)gmail.com> --- src/soc/intel/fsp_baytrail/i2c.c | 47 ++++++++++++++++++++-------------------- 1 file changed, 24 insertions(+), 23 deletions(-) diff --git a/src/soc/intel/fsp_baytrail/i2c.c b/src/soc/intel/fsp_baytrail/i2c.c index c6c8f65..5a0d59d 100644 --- a/src/soc/intel/fsp_baytrail/i2c.c +++ b/src/soc/intel/fsp_baytrail/i2c.c @@ -23,7 +23,8 @@ /* Wait for the transmit FIFO till there is at least one slot empty. * FIFO stall due to transmit abort will be checked and resolved */ -static int wait_tx_fifo(char *base_adr) { +static int wait_tx_fifo(char *base_adr) +{ int i; if (read32(base_adr + I2C_ABORT_SOURCE) & 0x1ffff) { @@ -35,7 +36,7 @@ static int wait_tx_fifo(char *base_adr) { /* Wait here for a free slot in TX-FIFO */ i = I2C_TIMEOUT_US; - while ((!(*((volatile unsigned int *)(base_adr + I2C_STATUS)) & I2C_TFNF))) { + while (!(read32(base_adr + I2C_STATUS) & I2C_TFNF)) { udelay(1); if (!--i) return I2C_ERR_TIMEOUT; @@ -47,7 +48,8 @@ static int wait_tx_fifo(char *base_adr) { /* Wait for the receive FIFO till there is at least one valid entry to read. * FIFO stall due to transmit abort will be checked and resolved */ -static int wait_rx_fifo(char *base_adr) { +static int wait_rx_fifo(char *base_adr) +{ int i; if (read32(base_adr + I2C_ABORT_SOURCE) & 0x1ffff) { /* Reading back I2C_CLR_TX_ABRT resets abort lock on TX FIFO */ @@ -58,7 +60,7 @@ static int wait_rx_fifo(char *base_adr) { /* Wait here for a received entry in RX-FIFO */ i = I2C_TIMEOUT_US; - while ((!(*((volatile unsigned int *)(base_adr + I2C_STATUS)) & I2C_RFNE))) { + while (!(read32(base_adr + I2C_STATUS) & I2C_RFNE)) { udelay(1); if (!--i) return I2C_ERR_TIMEOUT; @@ -74,20 +76,19 @@ static int wait_rx_fifo(char *base_adr) { static int wait_for_idle(char *base_adr) { int i; - volatile int status; + int status; /* For IDLE, increase timeout by ten times */ i = I2C_TIMEOUT_US * 10; - status = *((volatile unsigned int *)(base_adr + I2C_STATUS)); + status = read32(base_adr + I2C_STATUS); while (((status & I2C_MST_ACTIVITY) || (!(status & I2C_TFE)))) { - status = *((volatile unsigned int *)(base_adr + I2C_STATUS)); + status = read32(base_adr + I2C_STATUS); udelay(1); if (!--i) return I2C_ERR_TIMEOUT; } return I2C_SUCCESS; - } /** \brief Enables I2C-controller, sets up BAR and timing parameters @@ -101,6 +102,7 @@ int i2c_init(unsigned bus) I2C3_MEM_BASE, I2C4_MEM_BASE, I2C5_MEM_BASE, I2C6_MEM_BASE}; char *base_ptr; + /* Ensure the desired device is valid */ if (bus >= ARRAY_SIZE(base_adr)) { printk(BIOS_ERR, "I2C: Only I2C controllers 0...6 are available.\n"); @@ -126,20 +128,19 @@ int i2c_init(unsigned bus) (pci_read_config32(dev, PCI_COMMAND) | 0x2)); /* Set up some settings of I2C controller */ - *((unsigned int *)(base_ptr + I2C_CTRL)) = (I2C_RESTART_EN | - (I2C_STANDARD_MODE << 1) | - I2C_MASTER_ENABLE); + write32(base_ptr + I2C_CTRL, + I2C_RESTART_EN | (I2C_STANDARD_MODE << 1) | I2C_MASTER_ENABLE); /* Adjust frequency for standard mode to 100 kHz */ /* The counter value can be computed by N=100MHz/2/I2C_CLK */ /* Thus, for 100 kHz I2C_CLK, N is 0x1F4 */ - *((unsigned int *)(base_ptr + I2C_SS_SCL_HCNT)) = 0x1f4; - *((unsigned int *)(base_ptr + I2C_SS_SCL_LCNT)) = 0x1f4; + write32(base_ptr + I2C_SS_SCL_HCNT, 0x1f4); + write32(base_ptr + I2C_SS_SCL_LCNT, 0x1f4); /* For 400 kHz, the counter value is 0x7d */ - *((unsigned int *)(base_ptr + I2C_FS_SCL_HCNT)) = 0x7d; - *((unsigned int *)(base_ptr + I2C_FS_SCL_LCNT)) = 0x7d; + write32(base_ptr + I2C_FS_SCL_HCNT, 0x7d); + write32(base_ptr + I2C_FS_SCL_LCNT, 0x7d); /* Enable the I2C controller for operation */ - *((unsigned int *)(base_ptr + I2C_ENABLE)) = 0x1; + write32(base_ptr + I2C_ENABLE, 0x1); printk(BIOS_INFO, "I2C: Controller %d enabled.\n", bus); return I2C_SUCCESS; @@ -177,20 +178,20 @@ int i2c_read(unsigned bus, unsigned chip, unsigned addr, if (stat != I2C_SUCCESS) return stat; /* Now we can program the desired slave address and start transfer */ - *((unsigned int *)(base_ptr + I2C_TARGET_ADR)) = (chip & 0xff); + write32(base_ptr + I2C_TARGET_ADR, chip & 0xff); /* Send address inside slave to read from */ - *((unsigned int *)(base_ptr + I2C_DATA_CMD)) = (addr & 0xff); + write32(base_ptr + I2C_DATA_CMD, addr & 0xff); /* For the next byte we need a repeated start condition */ val = I2C_RW_CMD | I2C_RESTART; /* Now we can read desired amount of data over I2C */ for (i = 0; i < len; i++) { /* A read is initiated by writing dummy data to the DATA-register */ - *((unsigned int *)(base_ptr + I2C_DATA_CMD)) = val; + write32(base_ptr + I2C_DATA_CMD, val); stat = wait_rx_fifo(base_ptr); if (stat) return stat; - buf[i] = (*((unsigned int *)(base_ptr + I2C_DATA_CMD))) & 0xff; + buf[i] = read32(base_ptr + I2C_DATA_CMD) & 0xff; val = I2C_RW_CMD; if (i == (len - 2)) { /* For the last byte we need a stop condition to be generated */ @@ -232,10 +233,10 @@ int i2c_write(unsigned bus, unsigned chip, unsigned addr, return stat; } /* Program slave address to use for this transfer */ - *((unsigned int *)(base_ptr + I2C_TARGET_ADR)) = (chip & 0xff); + write32(base_ptr + I2C_TARGET_ADR, chip & 0xff); /* Send address inside slave to write data to */ - *((unsigned int *)(base_ptr + I2C_DATA_CMD)) = (addr & 0xff); + write32(base_ptr + I2C_DATA_CMD, addr & 0xff); for (i = 0; i < len; i++) { val = (unsigned int)(buf[i] & 0xff); /* Take only 8 bits */ @@ -247,7 +248,7 @@ int i2c_write(unsigned bus, unsigned chip, unsigned addr, if (stat) { return stat; } - *((unsigned int *)(base_ptr + I2C_DATA_CMD)) = val; + write32(base_ptr + I2C_DATA_CMD, val); } return I2C_SUCCESS; }

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Patch merged into coreboot/master: libpayload: update junit.xml target, clean up output
by gerrit＠coreboot.org 25 Mar '16

25 Mar '16

the following patch was just integrated into master: commit 6959f5c915e8455ae7bc84aef7250cde62fa2637 Author: Martin Roth <martinroth(a)google.com> Date: Wed Mar 23 16:07:54 2016 -0600 libpayload: update junit.xml target, clean up output - Copy each config in configs/ to the junit_config, update each, in turn, and clean up when done. This avoids updating the saved config files and creating dirty files in git. - Use 'make olddefconfig' instead of 'yes "" | make oldconfig' - Update clean target to remove junit_config file - Update distclean target to remove junit.xml Change-Id: Ib023eb3197f2d8806c73c9c18464157ce3de958f Signed-off-by: Martin Roth <martinroth(a)google.com> Reviewed-on: https://review.coreboot.org/14164 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See https://review.coreboot.org/14164 for details. -gerrit

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Patch merged into coreboot/master: buildgcc: Add check for missing libraries and test for zlib
by gerrit＠coreboot.org 25 Mar '16

25 Mar '16

the following patch was just integrated into master: commit 591790fca5f3e2ce0b1e4fa6099f59aaf9546c95 Author: Martin Roth <martinroth(a)google.com> Date: Sun Mar 20 20:39:04 2016 -0600 buildgcc: Add check for missing libraries and test for zlib - Add check_for_library routine to test for missing libraries. - Add a check for zlib. - Remove 'utility' text from please_install() routine since we can test for libraries or utilities now. - Remove incorrect 'solution' text from alternate install since I was updating that line. Change-Id: Id5ef28f8bde114cbf4e5a91fc119d42593ea6ab2 Signed-off-by: Martin Roth <martinroth(a)google.com> Reviewed-on: https://review.coreboot.org/14147 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See https://review.coreboot.org/14147 for details. -gerrit

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Patch merged into coreboot/master: buildgcc: support pigz and lbzip2 decpmpressors if installed.
by gerrit＠coreboot.org 25 Mar '16

25 Mar '16

the following patch was just integrated into master: commit 95f7b22dc4e0db2e27fab615c6e9c42bf7898ce4 Author: Martin Roth <martinroth(a)google.com> Date: Sun Mar 20 12:38:48 2016 -0600 buildgcc: support pigz and lbzip2 decpmpressors if installed. These are multi-threaded decompressors for .gz and .bz2 compressed files. If they're installed, use them to decompress, if they're not, use the standard single-threaded decompressors. Change-Id: I397740817e6b234a43b62075899964bdab14f121 Signed-off-by: Martin Roth <martinroth(a)google.com> Reviewed-on: https://review.coreboot.org/14146 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See https://review.coreboot.org/14146 for details. -gerrit

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coreboot-gerrit March 2016