coreboot-gerrit March 2016

coreboot-gerrit@coreboot.org

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Patch merged into coreboot/master: nb/amd/amdmct: Select max_lanes based on ECC presence or absence
by gerrit＠coreboot.org 26 Mar '16

26 Mar '16

the following patch was just integrated into master: commit ec38c3d956ed2c34f6ae7783d45cfbf4cab3c2df Author: Damien Zammit <damien(a)zamaudio.com> Date: Wed Feb 17 14:14:47 2016 +1100 nb/amd/amdmct: Select max_lanes based on ECC presence or absence Change-Id: Ic5482dc13ab7b53ec4df408bbe32d20888ae2e12 Signed-off-by: Damien Zammit <damien(a)zamaudio.com> Reviewed-on: https://review.coreboot.org/13725 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply(a)raptorengineeringinc.com> Reviewed-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/13725 for details. -gerrit

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Patch merged into coreboot/master: MAINTAINERS: Add maintainer for the intelmetool
by gerrit＠coreboot.org 26 Mar '16

26 Mar '16

the following patch was just integrated into master: commit 4cd9a11477c08b7e0392d79e20686e72cbdbc327 Author: Philipp Deppenwiese <zaolin(a)das-labor.org> Date: Wed Mar 23 00:02:40 2016 +0100 MAINTAINERS: Add maintainer for the intelmetool If you want to be a maintainer Damien just add yourself to the list. Change-Id: I15c646fc23d0804a8172da66d9297ab7977e6e6a Reviewed-on: https://review.coreboot.org/14157 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/14157 for details. -gerrit

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Patch set updated for coreboot: lint: Update board status script to look at the whole tree
by Martin Roth 26 Mar '16

26 Mar '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14118 -gerrit commit b0f61f7dadb05ee4ce763f54ace83c6b40082da1 Author: Martin Roth <martinroth(a)google.com> Date: Wed Mar 16 15:58:23 2016 -0600 lint: Update board status script to look at the whole tree The board status script wasn't checking the entire tree to make sure that all boards had board_info.txt files. Also it would only print out the first issue that was found. Change-Id: I5f2fa9e564c805c6dbee7a35cab80c1c342567a5 Signed-off-by: Martin Roth <martinroth(a)google.com> --- util/lint/lint-stable-005-board-status | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/util/lint/lint-stable-005-board-status b/util/lint/lint-stable-005-board-status index 61813ea..952a9b5 100755 --- a/util/lint/lint-stable-005-board-status +++ b/util/lint/lint-stable-005-board-status @@ -16,11 +16,11 @@ # DESCR: Check that every board has a meaningful board_info.txt LC_ALL=C export LC_ALL -for mobodir in $(git diff --diff-filter ACMR --name-only src/mainboard | sed -n 's,^$src/mainboard/[^/]*/[^/]*$/.*$,\1,p'|sort|uniq); do +for mobodir in $(git ls-files src/mainboard | sed -n 's,^$src/mainboard/[^/]*/[^/]*$/.*$,\1,p'|sort|uniq); do board_info="$mobodir/board_info.txt" if ! [ -f "$board_info" ]; then echo "No $board_info found" - exit 1 + continue fi category="$(sed -n 's#^Category: $.*$$#\1#p' < "$board_info")" case "$category" in @@ -28,11 +28,11 @@ for mobodir in $(git diff --diff-filter ACMR --name-only src/mainboard | sed -n ;; "") echo "$board_info doesn't contain 'Category' tag" - exit 1 + continue ;; *) echo "$board_info specifies unknown category '$category'" - exit 1 + continue ;; esac done

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Patch merged into coreboot/master: Makefile: Update jenkins-build-toolchain to run build tests
by gerrit＠coreboot.org 26 Mar '16

26 Mar '16

the following patch was just integrated into master: commit 4c3b156a26311fb178a8f0b0c03167dfe403c075 Author: Martin Roth <martinroth(a)google.com> Date: Tue Mar 22 13:05:42 2016 -0600 Makefile: Update jenkins-build-toolchain to run build tests Add coreboot build tests after running the toolchain build. This verifies that everything still builds with the new toolchain. Change-Id: Ifa51db897925c0b77791c83bbcbfd75045c907b5 Signed-off-by: Martin Roth <martinroth(a)google.com> Reviewed-on: https://review.coreboot.org/14156 Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Tested-by: build bot (Jenkins) See https://review.coreboot.org/14156 for details. -gerrit

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New patch to review for coreboot: nb/intel/sandybridge/raminit: support calling dram_freq multiple times
by Patrick Rudolph 26 Mar '16

26 Mar '16

Patrick Rudolph (siro(a)das-labor.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14174 -gerrit commit 7d39de9348d5faab015f27879dbb078a834b6922 Author: Patrick Rudolph <siro(a)das-labor.org> Date: Sat Mar 26 17:20:02 2016 +0100 nb/intel/sandybridge/raminit: support calling dram_freq multiple times The PLL will never lock if the requested frequency is already set. As the fallback may request the same frequency again exit early to prevent a hang. Test system: * Gigabyte GA-B75M-D3H * Intel Pentium CPU G2130 Change-Id: I625b2956346d8c50cca84def6190c076bf99dbec Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- src/northbridge/intel/sandybridge/raminit.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index f6d082f..d0b48e2 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -810,6 +810,17 @@ static void dram_freq(ramctr_timing * ctrl) /* Frequency mulitplier. */ u32 FRQ = get_FRQ(ctrl->tCK); + /* The PLL will never lock if the required frequency is + * already set. Exit early to prevent a system hang. + */ + reg1 = MCHBAR32(0x5e04); + val2 = (u8) reg1; + if (val2 >= FRQ) { + printk(BIOS_DEBUG, "MCU frequency is set at : %d MHz\n", + (1000 << 8) / ctrl->tCK); + return; + } + /* Step 2 - Select frequency in the MCU */ reg1 = FRQ; reg1 |= 0x80000000; // set running bit

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Patch set updated for coreboot: nb/intel/sandybridge/raminit: add additional fallbacks
by Patrick Rudolph 26 Mar '16

26 Mar '16

Patrick Rudolph (siro(a)das-labor.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14173 -gerrit commit 29f99886c7b3d4fa91790b944a18da054fba6d85 Author: Patrick Rudolph <siro(a)das-labor.org> Date: Sat Mar 26 12:16:29 2016 +0100 nb/intel/sandybridge/raminit: add additional fallbacks Add the following fallbacks: * Try decreasing clock frequency. In case of DDR1600 the next possible value of DDR1333 is being used. * Try decreasing clock frequency. In case of DDR1333 the next possible value of DDR1066 is being used. * Disable failing channel. The system may be able to boot with a single channel enabled. The fallbacks are untested. Change-Id: I3be7034ad25312b3ebf47a54f335a3893f8d7cc1 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- src/northbridge/intel/sandybridge/raminit.c | 45 +++++++++++++++++++++++++++++ 1 file changed, 45 insertions(+) diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index b980ff8..f6d082f 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -201,6 +201,7 @@ typedef struct ramctr_timing_st { #define MAX_TIMA 127 #define MAKE_ERR ((channel<<16)|(slotrank<<8)|1) +#define GET_ERR_CHANNEL(x) (x>>16) static void program_timings(ramctr_timing * ctrl, int channel); @@ -241,6 +242,18 @@ static void toggle_io_reset(void) { } /* + * Disable a channel in ramctr_timing. + */ +static void disable_channel(ramctr_timing *ctrl, int channel) { + ctrl->rankmap[channel] = 0; + memset(&ctrl->rank_mirror[channel][0], 0, sizeof(ctrl->rank_mirror[0])); + ctrl->channel_size_mb[channel] = 0; + ctrl->cmd_stretch[channel] = 0; + ctrl->mad_dimm[channel] = 0; + memset(&ctrl->timings[channel][0], 0, sizeof(ctrl->timings[0])); +} + +/* * Fill cbmem with information for SMBIOS type 17. */ static void fill_smbios17(ramctr_timing *ctrl) @@ -4242,6 +4255,38 @@ void init_dram_ddr3(spd_raw_data *spds, int mobile, int min_tck, } err = try_init_dram_ddr3(&ctrl, fast_boot, me_uma_size); + if (!err) + goto done; + + /* fallback: lower clock frequency */ + printk(BIOS_ERR, "RAM training failed, trying fallback.\n"); + printram("Decreasing clock frequency.\n"); + ctrl.tCK++; + + err = try_init_dram_ddr3(&ctrl, fast_boot, me_uma_size); + if (!err) + goto done; + + /* fallback: lower clock frequency */ + printk(BIOS_ERR, "RAM training failed, trying fallback.\n"); + printram("Decreasing clock frequency.\n"); + ctrl.tCK++; + + err = try_init_dram_ddr3(&ctrl, fast_boot, me_uma_size); + if (!err) + goto done; + + /* fallback: disable failing channel */ + printk(BIOS_ERR, "RAM training failed, trying fallback.\n"); + printram("Disable failing channel.\n"); + + /* Reset DDR3 frequency */ + dram_find_spds_ddr3(spds, &ctrl); + + /* disable failing channel */ + disable_channel(&ctrl, GET_ERR_CHANNEL(err)); + + err = try_init_dram_ddr3(&ctrl, fast_boot, me_uma_size); if (err) die("raminit failed");

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Patch set updated for coreboot: nb/intel/sandybridge/raminit: always use mrccache
by Patrick Rudolph 26 Mar '16

26 Mar '16

Patrick Rudolph (siro(a)das-labor.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14172 -gerrit commit a2b6ad580d2e2c45b9a30718f47303d7daacd698 Author: Patrick Rudolph <siro(a)das-labor.org> Date: Sun Mar 13 11:07:45 2016 +0100 nb/intel/sandybridge/raminit: always use mrccache Always use MRC cache if possible. Added a CRC16 array to make sure the DIMMs haven't been replaced. In case one of the CRC's doesn't match, start normal RAM training. Use new fallback in case of broken mrc cache. Test system: * Gigabyte GA-B75M-D3H * Intel Pentium CPU G2130 Test result: The system boots a lot faster using the MRC cache. On swapping DIMMs the CRC16 doesn't match and normal ram training is started. Change-Id: Ib48fe8380446846df17d37b22968f7d4fd6b9b13 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- src/northbridge/intel/sandybridge/raminit.c | 98 ++++++++++++++++++++++------- 1 file changed, 74 insertions(+), 24 deletions(-) diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index 48ec5b5..b980ff8 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -135,6 +135,7 @@ struct ram_rank_timings { struct ramctr_timing_st; typedef struct ramctr_timing_st { + u16 spd_crc[NUM_CHANNELS][NUM_SLOTS]; int mobile; u16 cas_supported; @@ -324,6 +325,24 @@ static void report_memory_config(void) } } +/* + * Return CRC16 match for all SPDs. + */ +static int verify_crc16_spds_ddr3(spd_raw_data *spd, ramctr_timing *ctrl) +{ + int channel, slot, spd_slot; + int match = 1; + + FOR_ALL_CHANNELS { + for (slot = 0; slot < NUM_SLOTS; slot++) { + spd_slot = 2 * channel + slot; + match &= ctrl->spd_crc[channel][slot] == + spd_ddr3_calc_crc(spd[spd_slot], sizeof(spd_raw_data)); + } + } + return match; +} + void read_spd(spd_raw_data * spd, u8 addr) { int j; @@ -376,6 +395,10 @@ static void dram_find_spds_ddr3(spd_raw_data *spd, ramctr_timing *ctrl) spd_decode_ddr3(&dimm->dimm[channel][slot], spd[spd_slot]); } + /* fill in CRC16 for MRC cache */ + ctrl->spd_crc[channel][slot] = + spd_ddr3_calc_crc(spd[spd_slot], sizeof(spd_raw_data)); + if (dimm->dimm[channel][slot].dram_type != SPD_MEMORY_TYPE_SDRAM_DDR3) { // set dimm invalid dimm->dimm[channel][slot].ranks = 0; @@ -4014,12 +4037,14 @@ static void restore_timings(ramctr_timing * ctrl) write32(DEFAULT_MCHBAR + 0x4ea8, 0); } -static int try_init_dram_ddr3(ramctr_timing *ctrl, int s3resume, +static int try_init_dram_ddr3(ramctr_timing *ctrl, int fast_boot, int me_uma_size) { int err; - if (!s3resume) { + printk(BIOS_DEBUG, "Starting RAM training.\n"); + + if (!fast_boot) { /* Find fastest common supported parameters */ dram_find_common_params(ctrl); @@ -4029,7 +4054,7 @@ static int try_init_dram_ddr3(ramctr_timing *ctrl, int s3resume, /* Set MCU frequency */ dram_freq(ctrl); - if (!s3resume) { + if (!fast_boot) { /* Calculate timings */ dram_timing(ctrl); } @@ -4072,7 +4097,7 @@ static int try_init_dram_ddr3(ramctr_timing *ctrl, int s3resume, udelay(1); - if (s3resume) { + if (fast_boot) { restore_timings(ctrl); } else { /* Do jedec ddr3 reset sequence */ @@ -4123,11 +4148,9 @@ static int try_init_dram_ddr3(ramctr_timing *ctrl, int s3resume, write_controller_mr(ctrl); - if (!s3resume) { - err = channel_test(ctrl); - if (err) - return err; - } + err = channel_test(ctrl); + if (err) + return err; return 0; } @@ -4138,6 +4161,9 @@ void init_dram_ddr3(spd_raw_data *spds, int mobile, int min_tck, int me_uma_size; int cbmem_was_inited; ramctr_timing ctrl; + int fast_boot; + struct mrc_data_container *mrc_cache; + ramctr_timing *ctrl_cached; int err; MCHBAR32(0x5f00) |= 1; @@ -4171,31 +4197,55 @@ void init_dram_ddr3(spd_raw_data *spds, int mobile, int min_tck, early_pch_init_native(); early_thermal_init(); - ctrl.mobile = mobile; - ctrl.tCK = min_tck; - - /* FIXME: for non-S3 we should be able to use timing caching with - proper verification. Right now we use timings only for S3 case. - */ - if (s3resume) { - struct mrc_data_container *mrc_cache; - - mrc_cache = find_current_mrc_cache(); - if (!mrc_cache || (mrc_cache->mrc_data_size < sizeof(ctrl))) { + /* try to find timings in MRC cache */ + mrc_cache = find_current_mrc_cache(); + if (!mrc_cache || (mrc_cache->mrc_data_size < sizeof(ctrl))) { + if (s3resume) { /* Failed S3 resume, reset to come up cleanly */ outb(0x6, 0xcf9); halt(); } - memcpy(&ctrl, mrc_cache->mrc_data, sizeof(ctrl)); + ctrl_cached = NULL; } else { + ctrl_cached = (ramctr_timing *)mrc_cache->mrc_data; + } + + /* verify MRC cache for fast boot */ + if (ctrl_cached) { + /* check SPD CRC16 to make sure the DIMMs haven't been replaced */ + fast_boot = verify_crc16_spds_ddr3(spds, ctrl_cached); + if (!fast_boot) + printk(BIOS_DEBUG, "Stored timings CRC16 mismatch.\n"); + } else + fast_boot = 0; + + if (fast_boot) { + printk(BIOS_DEBUG, "Trying stored timings.\n"); + memcpy(&ctrl, ctrl_cached, sizeof(ctrl)); + + err = try_init_dram_ddr3(&ctrl, fast_boot, me_uma_size); + if (err) { + /* no need to erase bad mrc cache here, it gets overritten on + * successful boot. */ + printk(BIOS_ERR, "Stored timings are invalid !\n"); + fast_boot = 0; + } else + goto done; + + } + if (!fast_boot) { + ctrl.mobile = mobile; + ctrl.tCK = min_tck; + /* Get DDR3 SPD data */ dram_find_spds_ddr3(spds, &ctrl); } - err = try_init_dram_ddr3(&ctrl, s3resume, me_uma_size); + err = try_init_dram_ddr3(&ctrl, fast_boot, me_uma_size); if (err) die("raminit failed"); +done: /* FIXME: should be hardware revision-dependent. */ write32(DEFAULT_MCHBAR + 0x5024, 0x00a030ce); @@ -4208,7 +4258,7 @@ void init_dram_ddr3(spd_raw_data *spds, int mobile, int min_tck, /* Zone config */ dram_zones(&ctrl, 0); - if (!s3resume) + if (!fast_boot) quick_ram_check(); intel_early_me_status(); @@ -4218,7 +4268,7 @@ void init_dram_ddr3(spd_raw_data *spds, int mobile, int min_tck, report_memory_config(); cbmem_was_inited = !cbmem_recovery(s3resume); - if (!s3resume) + if (!fast_boot) save_timings(&ctrl); if (s3resume && !cbmem_was_inited) { /* Failed S3 resume, reset to come up cleanly */

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Patch set updated for coreboot: nb/intel/sandybridge/raminit: add additional fallbacks
by Patrick Rudolph 26 Mar '16

26 Mar '16

Patrick Rudolph (siro(a)das-labor.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14173 -gerrit commit 516d3bdfab807c71a6633665dbb354429a14770c Author: Patrick Rudolph <siro(a)das-labor.org> Date: Sat Mar 26 12:16:29 2016 +0100 nb/intel/sandybridge/raminit: add additional fallbacks Try decreasing clock frequency twice. Disable failing channel. The system may be able to boot with a single channel enabled. Change-Id: I3be7034ad25312b3ebf47a54f335a3893f8d7cc1 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- src/northbridge/intel/sandybridge/raminit.c | 50 +++++++++++++++++++++++++++-- 1 file changed, 48 insertions(+), 2 deletions(-) diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index 3bfb900..d370da4 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -201,6 +201,7 @@ typedef struct ramctr_timing_st { #define MAX_TIMA 127 #define MAKE_ERR ((channel<<16)|(slotrank<<8)|1) +#define GET_ERR_CHANNEL(x) (x>>16) static void program_timings(ramctr_timing * ctrl, int channel); @@ -241,6 +242,18 @@ static void toggle_io_reset(void) { } /* + * Disable a channel in ramctr_timing. + */ +static void disable_channel(ramctr_timing *ctrl, int channel) { + ctrl->rankmap[channel] = 0; + memset(&ctrl->rank_mirror[channel][0], 0, sizeof(ctrl->rank_mirror[0])); + ctrl->channel_size_mb[channel] = 0; + ctrl->cmd_stretch[channel] = 0; + ctrl->mad_dimm[channel] = 0; + memset(&ctrl->timings[channel][0], 0, sizeof(ctrl->timings[0])); +} + +/* * Fill cbmem with information for SMBIOS type 17. */ static void fill_smbios17(ramctr_timing *ctrl) @@ -4042,6 +4055,8 @@ static int try_init_dram_ddr3(ramctr_timing *ctrl, int fast_boot, { int err; + printk(BIOS_DEBUG, "Starting RAM training.\n"); + if (!fast_boot) { /* Find fastest common supported parameters */ dram_find_common_params(ctrl); @@ -4233,16 +4248,47 @@ void init_dram_ddr3(spd_raw_data *spds, int mobile, int min_tck, ctrl.mobile = mobile; ctrl.tCK = min_tck; - printk(BIOS_DEBUG, "Starting RAM training.\n"); - /* Get DDR3 SPD data */ dram_find_spds_ddr3(spds, &ctrl); } err = try_init_dram_ddr3(&ctrl, fast_boot, me_uma_size); + if (!err) + goto done; + + /* fallback: lower clock frequency */ + printk(BIOS_ERR, "RAM training failed, trying fallback.\n"); + printram("Decreasing clock frequency.\n"); + ctrl.tCK++; + + err = try_init_dram_ddr3(&ctrl, fast_boot, me_uma_size); + if (!err) + goto done; + + /* fallback: lower clock frequency */ + printk(BIOS_ERR, "RAM training failed, trying fallback.\n"); + printram("Decreasing clock frequency.\n"); + ctrl.tCK++; + + err = try_init_dram_ddr3(&ctrl, fast_boot, me_uma_size); + if (!err) + goto done; + + /* fallback: disable failing channel */ + printk(BIOS_ERR, "RAM training failed, trying fallback.\n"); + printram("Disable failing channel.\n"); + + /* Reset DDR3 frequency */ + dram_find_spds_ddr3(spds, &ctrl); + + /* disable failing channel */ + disable_channel(&ctrl, GET_ERR_CHANNEL(err)); + + err = try_init_dram_ddr3(&ctrl, fast_boot, me_uma_size); if (err) die("raminit failed"); +done: /* FIXME: should be hardware revision-dependent. */ write32(DEFAULT_MCHBAR + 0x5024, 0x00a030ce);

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Patch set updated for coreboot: nb/intel/sandybridge/raminit: always use mrccache
by Patrick Rudolph 26 Mar '16

26 Mar '16

Patrick Rudolph (siro(a)das-labor.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14172 -gerrit commit 1d721562202a752a22f2cf08a6d674402aa103fd Author: Patrick Rudolph <siro(a)das-labor.org> Date: Sun Mar 13 11:07:45 2016 +0100 nb/intel/sandybridge/raminit: always use mrccache Always use MRC cache if possible. Added a CRC16 array to make sure the DIMMs haven't been replaced. In case one of the CRC's doesn't match, start normal RAM training. Use new fallback in case of broken mrc cache. Test system: * Gigabyte GA-B75M-D3H * Intel Pentium CPU G2130 Change-Id: Ib48fe8380446846df17d37b22968f7d4fd6b9b13 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- src/northbridge/intel/sandybridge/raminit.c | 95 +++++++++++++++++++++-------- 1 file changed, 71 insertions(+), 24 deletions(-) diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index 48ec5b5..3bfb900 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -135,6 +135,7 @@ struct ram_rank_timings { struct ramctr_timing_st; typedef struct ramctr_timing_st { + u16 spd_crc[NUM_CHANNELS][NUM_SLOTS]; int mobile; u16 cas_supported; @@ -324,6 +325,24 @@ static void report_memory_config(void) } } +/* + * Return CRC16 match for all SPDs. + */ +static int verify_crc16_spds_ddr3(spd_raw_data *spd, ramctr_timing *ctrl) +{ + int channel, slot, spd_slot; + int match = 1; + + FOR_ALL_CHANNELS { + for (slot = 0; slot < NUM_SLOTS; slot++) { + spd_slot = 2 * channel + slot; + match &= ctrl->spd_crc[channel][slot] == + spd_ddr3_calc_crc(spd[spd_slot], sizeof(spd_raw_data)); + } + } + return match; +} + void read_spd(spd_raw_data * spd, u8 addr) { int j; @@ -376,6 +395,10 @@ static void dram_find_spds_ddr3(spd_raw_data *spd, ramctr_timing *ctrl) spd_decode_ddr3(&dimm->dimm[channel][slot], spd[spd_slot]); } + /* fill in CRC16 for MRC cache */ + ctrl->spd_crc[channel][slot] = + spd_ddr3_calc_crc(spd[spd_slot], sizeof(spd_raw_data)); + if (dimm->dimm[channel][slot].dram_type != SPD_MEMORY_TYPE_SDRAM_DDR3) { // set dimm invalid dimm->dimm[channel][slot].ranks = 0; @@ -4014,12 +4037,12 @@ static void restore_timings(ramctr_timing * ctrl) write32(DEFAULT_MCHBAR + 0x4ea8, 0); } -static int try_init_dram_ddr3(ramctr_timing *ctrl, int s3resume, +static int try_init_dram_ddr3(ramctr_timing *ctrl, int fast_boot, int me_uma_size) { int err; - if (!s3resume) { + if (!fast_boot) { /* Find fastest common supported parameters */ dram_find_common_params(ctrl); @@ -4029,7 +4052,7 @@ static int try_init_dram_ddr3(ramctr_timing *ctrl, int s3resume, /* Set MCU frequency */ dram_freq(ctrl); - if (!s3resume) { + if (!fast_boot) { /* Calculate timings */ dram_timing(ctrl); } @@ -4072,7 +4095,7 @@ static int try_init_dram_ddr3(ramctr_timing *ctrl, int s3resume, udelay(1); - if (s3resume) { + if (fast_boot) { restore_timings(ctrl); } else { /* Do jedec ddr3 reset sequence */ @@ -4123,11 +4146,9 @@ static int try_init_dram_ddr3(ramctr_timing *ctrl, int s3resume, write_controller_mr(ctrl); - if (!s3resume) { - err = channel_test(ctrl); - if (err) - return err; - } + err = channel_test(ctrl); + if (err) + return err; return 0; } @@ -4138,6 +4159,9 @@ void init_dram_ddr3(spd_raw_data *spds, int mobile, int min_tck, int me_uma_size; int cbmem_was_inited; ramctr_timing ctrl; + int fast_boot; + struct mrc_data_container *mrc_cache; + ramctr_timing *ctrl_cached; int err; MCHBAR32(0x5f00) |= 1; @@ -4171,28 +4195,51 @@ void init_dram_ddr3(spd_raw_data *spds, int mobile, int min_tck, early_pch_init_native(); early_thermal_init(); - ctrl.mobile = mobile; - ctrl.tCK = min_tck; - - /* FIXME: for non-S3 we should be able to use timing caching with - proper verification. Right now we use timings only for S3 case. - */ - if (s3resume) { - struct mrc_data_container *mrc_cache; - - mrc_cache = find_current_mrc_cache(); - if (!mrc_cache || (mrc_cache->mrc_data_size < sizeof(ctrl))) { + /* try to find timings in MRC cache */ + mrc_cache = find_current_mrc_cache(); + if (!mrc_cache || (mrc_cache->mrc_data_size < sizeof(ctrl))) { + if (s3resume) { /* Failed S3 resume, reset to come up cleanly */ outb(0x6, 0xcf9); halt(); } - memcpy(&ctrl, mrc_cache->mrc_data, sizeof(ctrl)); + ctrl_cached = NULL; } else { + ctrl_cached = (ramctr_timing *)mrc_cache->mrc_data; + } + + /* verify MRC cache for fast boot */ + if (ctrl_cached) { + /* check SPD CRC16 to make sure the DIMMs haven't been replaced */ + fast_boot = verify_crc16_spds_ddr3(spds, ctrl_cached); + if (!fast_boot) + printk(BIOS_DEBUG, "Stored timings CRC16 mismatch.\n"); + } else + fast_boot = 0; + + if (fast_boot) { + printk(BIOS_DEBUG, "Trying stored timings.\n"); + memcpy(&ctrl, ctrl_cached, sizeof(ctrl)); + + err = try_init_dram_ddr3(&ctrl, fast_boot, me_uma_size); + if (err) { + printk(BIOS_ERR, "Stored timings are invalid !\n"); + fast_boot = 0; + /* no need to erase bad mrc cache here, it gets overritten on + * successful boot. */ + } + } + if (!fast_boot) { + ctrl.mobile = mobile; + ctrl.tCK = min_tck; + + printk(BIOS_DEBUG, "Starting RAM training.\n"); + /* Get DDR3 SPD data */ dram_find_spds_ddr3(spds, &ctrl); } - err = try_init_dram_ddr3(&ctrl, s3resume, me_uma_size); + err = try_init_dram_ddr3(&ctrl, fast_boot, me_uma_size); if (err) die("raminit failed"); @@ -4208,7 +4255,7 @@ void init_dram_ddr3(spd_raw_data *spds, int mobile, int min_tck, /* Zone config */ dram_zones(&ctrl, 0); - if (!s3resume) + if (!fast_boot) quick_ram_check(); intel_early_me_status(); @@ -4218,7 +4265,7 @@ void init_dram_ddr3(spd_raw_data *spds, int mobile, int min_tck, report_memory_config(); cbmem_was_inited = !cbmem_recovery(s3resume); - if (!s3resume) + if (!fast_boot) save_timings(&ctrl); if (s3resume && !cbmem_was_inited) { /* Failed S3 resume, reset to come up cleanly */

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Patch set updated for coreboot: nb/intel/sandybridge/raminit: die in toplevel function
by Patrick Rudolph 26 Mar '16

26 Mar '16

Patrick Rudolph (siro(a)das-labor.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14171 -gerrit commit 98c8cfd85b3e3794a8d40ed8cec3a1d227a882ed Author: Patrick Rudolph <siro(a)das-labor.org> Date: Sat Mar 26 12:22:34 2016 +0100 nb/intel/sandybridge/raminit: die in toplevel function In error case die in top level function. No functionality is changed. Change-Id: Ie15b01184d40bdbce20d49dcab2f9fb607068c7a Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- src/northbridge/intel/sandybridge/raminit.c | 15 ++++----------- 1 file changed, 4 insertions(+), 11 deletions(-) diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index cf096a2..48ec5b5 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -1902,7 +1902,6 @@ static int discover_402x(ramctr_timing *ctrl, int channel, int slotrank, if (ctrl->timings[channel][slotrank].val_4024 < 2) { printk(BIOS_EMERG, "402x discovery failed (1): %d, %d\n", channel, slotrank); - halt(); return MAKE_ERR; } ctrl->timings[channel][slotrank].val_4024 -= 2; @@ -1914,7 +1913,6 @@ static int discover_402x(ramctr_timing *ctrl, int channel, int slotrank, if (ctrl->timings[channel][slotrank].val_4028 >= 0x10) { printk(BIOS_EMERG, "402x discovery failed (2): %d, %d\n", channel, slotrank); - halt(); return MAKE_ERR; } FOR_ALL_LANES if (works[lane]) { @@ -2222,7 +2220,6 @@ static int discover_timC(ramctr_timing *ctrl, int channel, int slotrank) if (rn.all) { printk(BIOS_EMERG, "timC discovery failed: %d, %d, %d\n", channel, slotrank, lane); - halt(); return MAKE_ERR; } printram("Cval: %d, %d, %d: %x\n", channel, slotrank, @@ -2468,7 +2465,6 @@ static int discover_timB(ramctr_timing *ctrl, int channel, int slotrank) if (rn.all) { printk(BIOS_EMERG, "timB discovery failed: %d, %d, %d\n", channel, slotrank, lane); - halt(); return MAKE_ERR; } printram("Bval: %d, %d, %d: %x\n", channel, slotrank, @@ -3000,7 +2996,6 @@ static int command_training(ramctr_timing *ctrl) err = try_cmd_stretch(ctrl, 2); if (err) { printk(BIOS_EMERG, "c320c discovery failed\n"); - halt(); return err; } } @@ -3089,7 +3084,6 @@ static int discover_edges_real(ramctr_timing *ctrl, int channel, int slotrank, if (rn.all) { printk(BIOS_EMERG, "edge discovery failed: %d, %d, %d\n", channel, slotrank, lane); - halt(); return MAKE_ERR; } printram("eval %d, %d, %d: %02x\n", channel, slotrank, @@ -3409,7 +3403,6 @@ static int discover_edges_write_real(ramctr_timing *ctrl, int channel, if (rn.all || (lower[lane] > upper[lane])) { printk(BIOS_EMERG, "edge write discovery failed: %d, %d, %d\n", channel, slotrank, lane); - halt(); return MAKE_ERR; } } @@ -3575,7 +3568,6 @@ static int discover_timC_write(ramctr_timing *ctrl) if (rn.all) { printk(BIOS_EMERG, "timC write discovery failed: %d, %d, %d\n", channel, slotrank, lane); - halt(); return MAKE_ERR; } printram("timC: %d, %d, %d: 0x%02x-0x%02x-0x%02x, 0x%02x-0x%02x\n", @@ -3662,7 +3654,6 @@ static int channel_test(ramctr_timing *ctrl) if (read32(DEFAULT_MCHBAR + 0x42a0 + (channel << 10)) & 0xa000) { printk(BIOS_EMERG, "Mini channel test failed (1): %d\n", channel); - halt(); return MAKE_ERR; } FOR_ALL_POPULATED_CHANNELS { @@ -3709,7 +3700,6 @@ static int channel_test(ramctr_timing *ctrl) if (read32(DEFAULT_MCHBAR + 0x4340 + (channel << 10) + 4 * lane)) { printk(BIOS_EMERG, "Mini channel test failed (2): %d, %d, %d\n", channel, slotrank, lane); - halt(); return MAKE_ERR; } } @@ -4148,6 +4138,7 @@ void init_dram_ddr3(spd_raw_data *spds, int mobile, int min_tck, int me_uma_size; int cbmem_was_inited; ramctr_timing ctrl; + int err; MCHBAR32(0x5f00) |= 1; @@ -4201,7 +4192,9 @@ void init_dram_ddr3(spd_raw_data *spds, int mobile, int min_tck, dram_find_spds_ddr3(spds, &ctrl); } - try_init_dram_ddr3(&ctrl, s3resume, me_uma_size); + err = try_init_dram_ddr3(&ctrl, s3resume, me_uma_size); + if (err) + die("raminit failed"); /* FIXME: should be hardware revision-dependent. */ write32(DEFAULT_MCHBAR + 0x5024, 0x00a030ce);

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coreboot-gerrit March 2016