coreboot-gerrit March 2016

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Patch set updated for coreboot: nb/amd/mct_ddr3: Disable MCE framework during DRAM training
by Timothy Pearson 30 Mar '16

30 Mar '16

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14186 -gerrit commit a5799251fdeae57380f2ab72d8314a3fb2dcb1db Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Tue Mar 29 20:37:36 2016 -0500 nb/amd/mct_ddr3: Disable MCE framework during DRAM training On Family 15h processors, with certain RDIMMs, MCEs are generated as a normal part of DCT startup / DRAM training. Disable sync flood on parity or UC data error until ECC has been enabled. Change-Id: Ife54751ff127ffd59baaad35d3fea14ea01ef505 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 13 ++++++++++++ src/northbridge/amd/amdmct/mct_ddr3/mct_d.h | 5 +++++ src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c | 28 ++++++++++---------------- 3 files changed, 29 insertions(+), 17 deletions(-) diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c index 32964bd..30c511b 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c @@ -8014,14 +8014,27 @@ void mct_SetDramConfigHi_D(struct MCTStatStruc *pMCTstat, printk(BIOS_DEBUG, "mct_SetDramConfigHi_D: DramConfigHi: %08x\n", DramConfigHi); + /* Prevent lockups on parity errors during initial DCT startup */ + if (!pDCTstat->mca_config_backed_up) { + dword = Get_NB32(pDCTstat->dev_nbmisc, 0x44); + pDCTstat->sync_flood_on_dram_err = (dword >> 30) & 0x1; + pDCTstat->sync_flood_on_any_uc_err = (dword >> 21) & 0x1; + dword &= ~(0x1 << 30); + dword &= ~(0x1 << 21); + Set_NB32(pDCTstat->dev_nbmisc, 0x44, dword); + pDCTstat->mca_config_backed_up = 1; + } + /* Program the DRAM Configuration High register */ Set_NB32_DCT(dev, dct, 0x94, DramConfigHi); if (is_fam15h()) { /* Wait until F2x[1, 0]94[FreqChgInProg]=0. */ do { + printk(BIOS_DEBUG, "*"); dword = Get_NB32_DCT(pDCTstat->dev_dct, dct, 0x94); } while (dword & (1 << FreqChgInProg)); + printk(BIOS_DEBUG, "\n"); /* Program D18F2x9C_x0D0F_E006_dct[1:0][PllLockTime] = 0xf */ dword = Get_NB32_index_wait_DCT(pDCTstat->dev_dct, dct, index_reg, 0x0d0fe006); diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h index fd35f9c..6031239 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h @@ -580,6 +580,11 @@ struct DCTStatStruc { /* A per Node structure*/ uint8_t NbPstateThreshold; uint8_t NbPstateHi; + /* MCA backup variables */ + uint8_t mca_config_backed_up; + uint8_t sync_flood_on_dram_err; + uint8_t sync_flood_on_any_uc_err; + /* New for LB Support */ u8 NodePresent; u32 dev_host; diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c index be63149..2ebd093 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c @@ -85,8 +85,6 @@ u8 ECCInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) u16 nvbits; uint32_t dword; - uint8_t sync_flood_on_dram_err[MAX_NODES_SUPPORTED]; - uint8_t sync_flood_on_any_uc_err[MAX_NODES_SUPPORTED]; mctHookBeforeECC(); @@ -120,17 +118,6 @@ u8 ECCInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) pDCTstat = pDCTstatA + Node; if (NodePresent_D(Node)) { - dword = Get_NB32(pDCTstat->dev_nbmisc, 0x44); - sync_flood_on_dram_err[Node] = (dword >> 30) & 0x1; - sync_flood_on_any_uc_err[Node] = (dword >> 21) & 0x1; - dword &= ~(0x1 << 30); - dword &= ~(0x1 << 21); - Set_NB32(pDCTstat->dev_nbmisc, 0x44, dword); - - /* Clear MC4 error status */ - pci_write_config32(pDCTstat->dev_nbmisc, 0x48, 0x0); - pci_write_config32(pDCTstat->dev_nbmisc, 0x4c, 0x0); - /* Clear the RAM before enabling ECC to prevent MCE-related lockups */ DCTMemClr_Init_D(pMCTstat, pDCTstat); DCTMemClr_Sync_D(pMCTstat, pDCTstat); @@ -263,10 +250,17 @@ u8 ECCInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) pDCTstat = pDCTstatA + Node; if (NodePresent_D(Node)) { - dword = Get_NB32(pDCTstat->dev_nbmisc, 0x44); - dword |= (sync_flood_on_dram_err[Node] & 0x1) << 30; - dword |= (sync_flood_on_any_uc_err[Node] & 0x1) << 21; - Set_NB32(pDCTstat->dev_nbmisc, 0x44, dword); + /* Clear MC4 error status */ + pci_write_config32(pDCTstat->dev_nbmisc, 0x48, 0x0); + pci_write_config32(pDCTstat->dev_nbmisc, 0x4c, 0x0); + + /* Restore previous MCA error handling settings */ + if (pDCTstat->mca_config_backed_up) { + dword = Get_NB32(pDCTstat->dev_nbmisc, 0x44); + dword |= (pDCTstat->sync_flood_on_dram_err & 0x1) << 30; + dword |= (pDCTstat->sync_flood_on_any_uc_err & 0x1) << 21; + Set_NB32(pDCTstat->dev_nbmisc, 0x44, dword); + } } }

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New patch to review for coreboot: nb/amd/mcd_ddr3: Disable MCE framework during DRAM training
by Timothy Pearson 30 Mar '16

30 Mar '16

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14186 -gerrit commit a5e9e5516ea482ae22208b6558916c3e62b50cb9 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Tue Mar 29 20:37:36 2016 -0500 nb/amd/mcd_ddr3: Disable MCE framework during DRAM training On Family 15h processors, with certain RDIMMs, MCEs are generated as a normal part of DCT startup / DRAM training. Disable sync flood on parity or UC data error until ECC has been enabled. Change-Id: Ife54751ff127ffd59baaad35d3fea14ea01ef505 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 13 ++++++++++++ src/northbridge/amd/amdmct/mct_ddr3/mct_d.h | 5 +++++ src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c | 28 ++++++++++---------------- 3 files changed, 29 insertions(+), 17 deletions(-) diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c index 32964bd..30c511b 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c @@ -8014,14 +8014,27 @@ void mct_SetDramConfigHi_D(struct MCTStatStruc *pMCTstat, printk(BIOS_DEBUG, "mct_SetDramConfigHi_D: DramConfigHi: %08x\n", DramConfigHi); + /* Prevent lockups on parity errors during initial DCT startup */ + if (!pDCTstat->mca_config_backed_up) { + dword = Get_NB32(pDCTstat->dev_nbmisc, 0x44); + pDCTstat->sync_flood_on_dram_err = (dword >> 30) & 0x1; + pDCTstat->sync_flood_on_any_uc_err = (dword >> 21) & 0x1; + dword &= ~(0x1 << 30); + dword &= ~(0x1 << 21); + Set_NB32(pDCTstat->dev_nbmisc, 0x44, dword); + pDCTstat->mca_config_backed_up = 1; + } + /* Program the DRAM Configuration High register */ Set_NB32_DCT(dev, dct, 0x94, DramConfigHi); if (is_fam15h()) { /* Wait until F2x[1, 0]94[FreqChgInProg]=0. */ do { + printk(BIOS_DEBUG, "*"); dword = Get_NB32_DCT(pDCTstat->dev_dct, dct, 0x94); } while (dword & (1 << FreqChgInProg)); + printk(BIOS_DEBUG, "\n"); /* Program D18F2x9C_x0D0F_E006_dct[1:0][PllLockTime] = 0xf */ dword = Get_NB32_index_wait_DCT(pDCTstat->dev_dct, dct, index_reg, 0x0d0fe006); diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h index fd35f9c..6031239 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h @@ -580,6 +580,11 @@ struct DCTStatStruc { /* A per Node structure*/ uint8_t NbPstateThreshold; uint8_t NbPstateHi; + /* MCA backup variables */ + uint8_t mca_config_backed_up; + uint8_t sync_flood_on_dram_err; + uint8_t sync_flood_on_any_uc_err; + /* New for LB Support */ u8 NodePresent; u32 dev_host; diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c index be63149..2ebd093 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c @@ -85,8 +85,6 @@ u8 ECCInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) u16 nvbits; uint32_t dword; - uint8_t sync_flood_on_dram_err[MAX_NODES_SUPPORTED]; - uint8_t sync_flood_on_any_uc_err[MAX_NODES_SUPPORTED]; mctHookBeforeECC(); @@ -120,17 +118,6 @@ u8 ECCInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) pDCTstat = pDCTstatA + Node; if (NodePresent_D(Node)) { - dword = Get_NB32(pDCTstat->dev_nbmisc, 0x44); - sync_flood_on_dram_err[Node] = (dword >> 30) & 0x1; - sync_flood_on_any_uc_err[Node] = (dword >> 21) & 0x1; - dword &= ~(0x1 << 30); - dword &= ~(0x1 << 21); - Set_NB32(pDCTstat->dev_nbmisc, 0x44, dword); - - /* Clear MC4 error status */ - pci_write_config32(pDCTstat->dev_nbmisc, 0x48, 0x0); - pci_write_config32(pDCTstat->dev_nbmisc, 0x4c, 0x0); - /* Clear the RAM before enabling ECC to prevent MCE-related lockups */ DCTMemClr_Init_D(pMCTstat, pDCTstat); DCTMemClr_Sync_D(pMCTstat, pDCTstat); @@ -263,10 +250,17 @@ u8 ECCInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) pDCTstat = pDCTstatA + Node; if (NodePresent_D(Node)) { - dword = Get_NB32(pDCTstat->dev_nbmisc, 0x44); - dword |= (sync_flood_on_dram_err[Node] & 0x1) << 30; - dword |= (sync_flood_on_any_uc_err[Node] & 0x1) << 21; - Set_NB32(pDCTstat->dev_nbmisc, 0x44, dword); + /* Clear MC4 error status */ + pci_write_config32(pDCTstat->dev_nbmisc, 0x48, 0x0); + pci_write_config32(pDCTstat->dev_nbmisc, 0x4c, 0x0); + + /* Restore previous MCA error handling settings */ + if (pDCTstat->mca_config_backed_up) { + dword = Get_NB32(pDCTstat->dev_nbmisc, 0x44); + dword |= (pDCTstat->sync_flood_on_dram_err & 0x1) << 30; + dword |= (pDCTstat->sync_flood_on_any_uc_err & 0x1) << 21; + Set_NB32(pDCTstat->dev_nbmisc, 0x44, dword); + } } }

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Patch merged into coreboot/master: storm: Fix compilation error
by gerrit＠coreboot.org 30 Mar '16

30 Mar '16

the following patch was just integrated into master: commit e9e7b20f43617880d1d0300257bb88595bea4e35 Author: Furquan Shaikh <furquan(a)google.com> Date: Tue Mar 29 16:48:04 2016 -0700 storm: Fix compilation error Somehow the missing header file in https://review.coreboot.org/#/c/14182 did not trigger compilation errors before. Add the required header file to enable proper compilation of storm. Change-Id: I83c8f2b5fc41e38c1385ff405370753e6eba2abc Signed-off-by: Furquan Shaikh <furquan(a)google.com> Reviewed-on: https://review.coreboot.org/14185 Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Tested-by: build bot (Jenkins) See https://review.coreboot.org/14185 for details. -gerrit

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Patch set updated for coreboot: storm: Fix compilation error
by Furquan Shaikh 30 Mar '16

30 Mar '16

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14185 -gerrit commit 381461463ec2646928f5b6797a27c8a1b52e0493 Author: Furquan Shaikh <furquan(a)google.com> Date: Tue Mar 29 16:48:04 2016 -0700 storm: Fix compilation error Somehow the missing header file in https://review.coreboot.org/#/c/14182 did not trigger compilation errors before. Add the required header file to enable proper compilation of storm. Change-Id: I83c8f2b5fc41e38c1385ff405370753e6eba2abc Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- src/mainboard/google/storm/mmu.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/mainboard/google/storm/mmu.c b/src/mainboard/google/storm/mmu.c index fcea8e2..da15795 100644 --- a/src/mainboard/google/storm/mmu.c +++ b/src/mainboard/google/storm/mmu.c @@ -11,6 +11,8 @@ */ #include <arch/cache.h> +#include <rules.h> +#include <soc/soc_services.h> #include <symbols.h> #include "mmu.h" @@ -34,8 +36,10 @@ void setup_dram_mappings(enum dram_state dram) mmu_config_range(DRAM_START, DRAM_SIZE, DCACHE_WRITEBACK); /* Map DMA memory */ mmu_config_range(DMA_START, DMA_SIZE, DCACHE_OFF); +#if ENV_ROMSTAGE /* Mark cbmem backing store as ready. */ ipq_cbmem_backing_store_ready(); +#endif } else { mmu_disable_range(DRAM_START, DRAM_SIZE); /* Map DMA memory */

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New patch to review for coreboot: storm: Fix compilation error
by Furquan Shaikh 30 Mar '16

30 Mar '16

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14185 -gerrit commit 89dd1932ed211e0fa88ed4fe47801a5639dce72c Author: Furquan Shaikh <furquan(a)google.com> Date: Tue Mar 29 16:48:04 2016 -0700 storm: Fix compilation error Somehow the missing header file in https://review.coreboot.org/#/c/14182 did not trigger compilation errors before. Add the required header file to enable proper compilation of storm. Change-Id: I83c8f2b5fc41e38c1385ff405370753e6eba2abc Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- 3rdparty/blobs | 2 +- src/mainboard/google/storm/mmu.c | 4 ++++ 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/3rdparty/blobs b/3rdparty/blobs index b0eeddd..832bc6f 160000 --- a/3rdparty/blobs +++ b/3rdparty/blobs @@ -1 +1 @@ -Subproject commit b0eeddd4f5c583818e66521f2552cd3448b357b2 +Subproject commit 832bc6f1f8ffafc5ff397fd95616fdae988f224f diff --git a/src/mainboard/google/storm/mmu.c b/src/mainboard/google/storm/mmu.c index fcea8e2..da15795 100644 --- a/src/mainboard/google/storm/mmu.c +++ b/src/mainboard/google/storm/mmu.c @@ -11,6 +11,8 @@ */ #include <arch/cache.h> +#include <rules.h> +#include <soc/soc_services.h> #include <symbols.h> #include "mmu.h" @@ -34,8 +36,10 @@ void setup_dram_mappings(enum dram_state dram) mmu_config_range(DRAM_START, DRAM_SIZE, DCACHE_WRITEBACK); /* Map DMA memory */ mmu_config_range(DMA_START, DMA_SIZE, DCACHE_OFF); +#if ENV_ROMSTAGE /* Mark cbmem backing store as ready. */ ipq_cbmem_backing_store_ready(); +#endif } else { mmu_disable_range(DRAM_START, DRAM_SIZE); /* Map DMA memory */

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Patch merged into coreboot/master: intel/skylake: Enable PROCHOT
by gerrit＠coreboot.org 29 Mar '16

29 Mar '16

the following patch was just integrated into master: commit 79cfcde4589f4ab07a721c509b9fa59060e091cc Author: Pratik Prajapati <pratikkumar.v.prajapati(a)intel.com> Date: Tue Mar 8 12:34:06 2016 -0800 intel/skylake: Enable PROCHOT This patch would enable PROCHOT feature in skylake. Asserting PROCHOT line would throttle the GPU/CPU. BUG=chrome-os-partner:51142 BRANCH=glados TEST=manually tested on lars. asserting PROCTHOT by EC reduces FSP in fish-tank from approx 40 to 20. (50 fish setting), also CPU freq. drops to from 1600000 to 400000 Change-Id: I8fc0c015ea2c26d20bbbfc619f720f231d540feb Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 1b88b1f183df9c7362d7e58acb0a1fa0b076d56e Original-Change-Id: Ida8636efc3d8da56ebd3931144d31ab1b88fe806 Original-Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati(a)intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/331690 Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Original-(cherry picked from commit d091a999c3827179182b62a1274a9b3581f7f006) Original-Reviewed-on: https://chromium-review.googlesource.com/333073 Original-Commit-Ready: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Original-Tested-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Original-Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Reviewed-on: https://review.coreboot.org/14120 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/14120 for details. -gerrit

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Patch merged into coreboot/master: google/chell: Update DPTF thermal parameters
by gerrit＠coreboot.org 29 Mar '16

29 Mar '16

the following patch was just integrated into master: commit 89cc9ce399845382c2180cd6ee8d2482521aeed1 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Tue Mar 15 16:42:07 2016 -0700 google/chell: Update DPTF thermal parameters MinPL1: 2.5W MaxPL1: 7W StepPL1: 0.25W _PSV(TSR2): 51C _TRT(TSR2): 9 second BUG=chrome-os-partner:49859 BRANCH=glados TEST=build and boot on chell Change-Id: I69de1d66fb0d52ad0ad77eb51ca56f50fc44c255 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 845f1d046a5143057d683b2bd9cf5dab2ab2ef34 Original-Change-Id: I8a161c979a22621f5f854926677cb7835f8ce88b Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/332857 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-(cherry picked from commit 4d5023524591fc6b651a199874ed990bd5be1d50) Original-Reviewed-on: https://chromium-review.googlesource.com/333071 Reviewed-on: https://review.coreboot.org/14119 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/14119 for details. -gerrit

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Patch merged into coreboot/master: intel/kunimitsu: configure native mode for GPP_E21
by gerrit＠coreboot.org 29 Mar '16

29 Mar '16

the following patch was just integrated into master: commit 2dfdc7746d0f1b688bb2213e96fcb92e8abaf827 Author: Youvedeep Singh <youvedeep.singh(a)intel.com> Date: Fri Mar 11 11:08:38 2016 +0530 intel/kunimitsu: configure native mode for GPP_E21 GPP_E_21_DDPC_CTRLDATA is pulled low by default. This causes 2.5mW leakage from 3.3S to GND via R877. So configuring GPP_E21 in native mode. BUG=chrome-os-partner:50958 BRANCH=glados TEST=Build and boot. Measure Power at 3P3S(R955). Change-Id: I2bdcb698d0b0cd3228c2e59653ac3fb3b1a26951 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: d01f932cda44b0b44c5494b316aefc43c8b84c52 Original-Change-Id: Ifd13ea4b16108ef98d09891365f0d17831ab5f65 Original-Signed-off-by: Youvedeep Singh <youvedeep.singh(a)intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/332369 Original-Commit-Ready: Rajneesh Bhardwaj <rajneesh.bhardwaj(a)intel.com> Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://review.coreboot.org/14108 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/14108 for details. -gerrit

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Patch merged into coreboot/master: vboot: Handle S3 resume path for TPM initialization
by gerrit＠coreboot.org 29 Mar '16

29 Mar '16

the following patch was just integrated into master: commit a613a311b230d4ecfabd8860d207c286347f9393 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Mon Mar 14 09:32:08 2016 -0700 vboot: Handle S3 resume path for TPM initialization When doing verification of memory init code in verstage vboot should issue a TPM_Startup(ST_STATE) instead of TPM_Startup(ST_CLEAR) in order to preserve the flags in TPM_STCLEAR_FLAGS which include things like physical presence. In doing so we can also skip the rest of the TPM init work in this function in the S3 resume path. BUG=chrome-os-partner:50633 BRANCH=glados TEST=S3 resume on chell and ensure TPM is resumed instead of being cleared and that 'tpmc getvf|getpf|getf' does not show any difference in flags between boot and resume. Change-Id: I7a48eaf7f57d2bc6ebc182178cbe60ceb2ad8863 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: f059f39a0f5c2f21e564b9554efacf26a41ad794 Original-Change-Id: I647869202d2f04328764155d3de4cad9edf10ae4 Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Previous-Reviewed-on: https://chromium-review.googlesource.com/332434 Original-(cherry picked from commit 5fc7792e4104523569140cd84ce313da721ec34b) Original-Reviewed-on: https://chromium-review.googlesource.com/332542 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://review.coreboot.org/14107 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/14107 for details. -gerrit

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Patch merged into coreboot/master: intel/fsp1_1: Do not re-init TPM in romstage if already setup in verstage
by gerrit＠coreboot.org 29 Mar '16

29 Mar '16

the following patch was just integrated into master: commit fe4983e5aa0a9d3228d3634116be88e361ec23c3 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Mon Mar 14 09:29:09 2016 -0700 intel/fsp1_1: Do not re-init TPM in romstage if already setup in verstage For platforms that do verification of memory init (and have verstage execute before romstage) FSP should not attempt to re-initialize the TPM again in romstage as it has already been done. BUG=chrome-os-partner:50633 BRANCH=glados TEST=boot and resume on chell and ensure TPM is not re-initialized Change-Id: Ied6f39dc8dacdbc3d76070b6135de2308196ff53 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: fefd4d4b3fde4c7fe4b6de304790914b7a2f87d8 Original-Change-Id: I60a2e4e2d73270697218f094527e09d444e6ab56 Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Previous-Reviewed-on: https://chromium-review.googlesource.com/332433 Original-(cherry picked from commit 2de1fd57fe1db7960e0bb86c64dccf827fa55742) Original-Reviewed-on: https://chromium-review.googlesource.com/332299 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://review.coreboot.org/14106 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/14106 for details. -gerrit

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coreboot-gerrit March 2016