coreboot-gerrit March 2016

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: LINT TEST: Do not submit
by Martin Roth 30 Mar '16

30 Mar '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14197 -gerrit commit 8519f0ed797fe61a393e437cc2d7a4155452a092 Author: Martin Roth <martinroth(a)google.com> Date: Wed Mar 30 14:08:52 2016 -0600 LINT TEST: Do not submit This should cause all of the lint-stable tests to fail. Change-Id: I38db15c4d169bfebc443007da883e17a08fadc01 Signed-off-by: Martin Roth <martinroth(a)google.com> --- site-local/tmp.b6e9i3VnEc | 0 src/acpi/sata.c | 18 +++++++++--------- src/arch/power8/misc.c | 2 +- src/arch/x86/bootblock_romcc.S | 1 + src/arch/x86/thread.c | 18 +++++++++--------- src/lib/libgcc.c | 0 src/mainboard/aaeon/pfm-540i_revb/board_info.txt | 2 +- src/mainboard/amd/bettong/Kconfig.name | 2 -- src/mainboard/google/storm/board_info.txt | 6 ------ src/soc/nvidia/tegra124/spi.c | 4 ++-- src/superio/common/conf_mode.c | 3 +++ 11 files changed, 26 insertions(+), 30 deletions(-) diff --git a/site-local/tmp.b6e9i3VnEc b/site-local/tmp.b6e9i3VnEc new file mode 100644 index 0000000..e69de29 diff --git a/src/acpi/sata.c b/src/acpi/sata.c index ec0d505..aab9c0d 100644 --- a/src/acpi/sata.c +++ b/src/acpi/sata.c @@ -10,12 +10,12 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ - + #include "sata.h" - + #include <arch/acpi.h> #include <arch/acpigen.h> - + /* e.g. * generate_sata_ssdt_ports("\_SB.PCI0.SATA", 0x3); * generates: @@ -38,23 +38,23 @@ void generate_sata_ssdt_ports(const char *scope, uint32_t enable_map) int i; uint32_t bit; char port_name[4] = "PR00"; - + acpigen_write_scope(scope); - + /* generate a device for every enabled port */ for (i = 0; i < 32; i++) { bit = 1 << i; if (!(bit & enable_map)) continue; - + port_name[2] = '0' + i / 10; port_name[3] = '0' + i % 10; - + acpigen_write_device(port_name); - + acpigen_write_name_dword("_ADR", 0xffff + i * 0x10000); acpigen_pop_len(); /* close PRT%d */ } - + acpigen_pop_len(); /* close scope */ } diff --git a/src/arch/power8/misc.c b/src/arch/power8/misc.c index 65b8ecf..fbc5678 100644 --- a/src/arch/power8/misc.c +++ b/src/arch/power8/misc.c @@ -6,7 +6,7 @@ * the Free Software Foundation; version 2 of the License. * * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of + without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ diff --git a/src/arch/x86/bootblock_romcc.S b/src/arch/x86/bootblock_romcc.S index 6c1723a..0d7d759 100644 --- a/src/arch/x86/bootblock_romcc.S +++ b/src/arch/x86/bootblock_romcc.S @@ -1,3 +1,4 @@ +.att_syntax noprefix /* * This file is part of the coreboot project. * diff --git a/src/arch/x86/thread.c b/src/arch/x86/thread.c index 993577d..f2dae2d 100644 --- a/src/arch/x86/thread.c +++ b/src/arch/x86/thread.c @@ -1,16 +1,16 @@ /* - * This file is part of the coreboot project. + * - * Copyright (C) 2013 Google, Inc. + * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. + + + * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. + + + + */ #include <thread.h> diff --git a/src/lib/libgcc.c b/src/lib/libgcc.c old mode 100644 new mode 100755 diff --git a/src/mainboard/aaeon/pfm-540i_revb/board_info.txt b/src/mainboard/aaeon/pfm-540i_revb/board_info.txt index 76246af..a8db96f 100644 --- a/src/mainboard/aaeon/pfm-540i_revb/board_info.txt +++ b/src/mainboard/aaeon/pfm-540i_revb/board_info.txt @@ -1,3 +1,3 @@ Board name: PFM-540I Rev.B -Category: half +Category: lint Board URL: http://www.aaeonusa.com/products/details/?item_id=1043 diff --git a/src/mainboard/amd/bettong/Kconfig.name b/src/mainboard/amd/bettong/Kconfig.name deleted file mode 100644 index 09201b5..0000000 --- a/src/mainboard/amd/bettong/Kconfig.name +++ /dev/null @@ -1,2 +0,0 @@ -config BOARD_AMD_BETTONG - bool "Bettong" diff --git a/src/mainboard/google/storm/board_info.txt b/src/mainboard/google/storm/board_info.txt deleted file mode 100644 index edc4b32..0000000 --- a/src/mainboard/google/storm/board_info.txt +++ /dev/null @@ -1,6 +0,0 @@ -Vendor name: Google -Board name: Storm Qualcomm IPQ806X board -Category: settop -ROM protocol: SPI -ROM socketed: n -Flashrom support: y diff --git a/src/soc/nvidia/tegra124/spi.c b/src/soc/nvidia/tegra124/spi.c index d5be4a6..3d659d7 100644 --- a/src/soc/nvidia/tegra124/spi.c +++ b/src/soc/nvidia/tegra124/spi.c @@ -580,7 +580,7 @@ static int tegra_spi_dma_finish(struct tegra_spi_channel *spi) } ret = 0; -done: + done: spi->dma_in = NULL; spi->dma_out = NULL; return ret; @@ -684,7 +684,7 @@ static int xfer_setup(struct tegra_spi_channel *spi, void *buf, goto done; } -done: + done: return ret; } diff --git a/src/superio/common/conf_mode.c b/src/superio/common/conf_mode.c index cbe1a9e..423f127 100644 --- a/src/superio/common/conf_mode.c +++ b/src/superio/common/conf_mode.c @@ -11,6 +11,9 @@ * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. */ #include <arch/io.h>

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New patch to review for coreboot: LINT TEST: Do not submit
by Martin Roth 30 Mar '16

30 Mar '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14197 -gerrit commit a0d2dcfa9b30616d109d090329c9ab49b8848f7a Author: Martin Roth <martinroth(a)google.com> Date: Wed Mar 30 14:08:52 2016 -0600 LINT TEST: Do not submit This should cause all of the lint-stable tests to fail. Change-Id: I38db15c4d169bfebc443007da883e17a08fadc01 Signed-off-by: Martin Roth <martinroth(a)google.com> --- site-local/tmp.b6e9i3VnEc | 0 src/acpi/sata.c | 18 +++++++++--------- src/arch/power8/misc.c | 2 +- src/arch/x86/bootblock_romcc.S | 1 + src/arch/x86/thread.c | 18 +++++++++--------- src/lib/libgcc.c | 0 src/mainboard/aaeon/pfm-540i_revb/board_info.txt | 2 +- src/mainboard/amd/bettong/Kconfig.name | 2 -- src/mainboard/google/storm/board_info.txt | 6 ------ src/soc/nvidia/tegra124/spi.c | 4 ++-- src/superio/common/conf_mode.c | 3 +++ 11 files changed, 26 insertions(+), 30 deletions(-) diff --git a/site-local/tmp.b6e9i3VnEc b/site-local/tmp.b6e9i3VnEc new file mode 100644 index 0000000..e69de29 diff --git a/src/acpi/sata.c b/src/acpi/sata.c index ec0d505..aab9c0d 100644 --- a/src/acpi/sata.c +++ b/src/acpi/sata.c @@ -10,12 +10,12 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ - + #include "sata.h" - + #include <arch/acpi.h> #include <arch/acpigen.h> - + /* e.g. * generate_sata_ssdt_ports("\_SB.PCI0.SATA", 0x3); * generates: @@ -38,23 +38,23 @@ void generate_sata_ssdt_ports(const char *scope, uint32_t enable_map) int i; uint32_t bit; char port_name[4] = "PR00"; - + acpigen_write_scope(scope); - + /* generate a device for every enabled port */ for (i = 0; i < 32; i++) { bit = 1 << i; if (!(bit & enable_map)) continue; - + port_name[2] = '0' + i / 10; port_name[3] = '0' + i % 10; - + acpigen_write_device(port_name); - + acpigen_write_name_dword("_ADR", 0xffff + i * 0x10000); acpigen_pop_len(); /* close PRT%d */ } - + acpigen_pop_len(); /* close scope */ } diff --git a/src/arch/power8/misc.c b/src/arch/power8/misc.c index 65b8ecf..fbc5678 100644 --- a/src/arch/power8/misc.c +++ b/src/arch/power8/misc.c @@ -6,7 +6,7 @@ * the Free Software Foundation; version 2 of the License. * * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of + without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ diff --git a/src/arch/x86/bootblock_romcc.S b/src/arch/x86/bootblock_romcc.S index 6c1723a..0d7d759 100644 --- a/src/arch/x86/bootblock_romcc.S +++ b/src/arch/x86/bootblock_romcc.S @@ -1,3 +1,4 @@ +.att_syntax noprefix /* * This file is part of the coreboot project. * diff --git a/src/arch/x86/thread.c b/src/arch/x86/thread.c index 993577d..f2dae2d 100644 --- a/src/arch/x86/thread.c +++ b/src/arch/x86/thread.c @@ -1,16 +1,16 @@ /* - * This file is part of the coreboot project. + * - * Copyright (C) 2013 Google, Inc. + * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. + + + * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. + + + + */ #include <thread.h> diff --git a/src/lib/libgcc.c b/src/lib/libgcc.c old mode 100644 new mode 100755 diff --git a/src/mainboard/aaeon/pfm-540i_revb/board_info.txt b/src/mainboard/aaeon/pfm-540i_revb/board_info.txt index 76246af..a8db96f 100644 --- a/src/mainboard/aaeon/pfm-540i_revb/board_info.txt +++ b/src/mainboard/aaeon/pfm-540i_revb/board_info.txt @@ -1,3 +1,3 @@ Board name: PFM-540I Rev.B -Category: half +Category: lint Board URL: http://www.aaeonusa.com/products/details/?item_id=1043 diff --git a/src/mainboard/amd/bettong/Kconfig.name b/src/mainboard/amd/bettong/Kconfig.name deleted file mode 100644 index 09201b5..0000000 --- a/src/mainboard/amd/bettong/Kconfig.name +++ /dev/null @@ -1,2 +0,0 @@ -config BOARD_AMD_BETTONG - bool "Bettong" diff --git a/src/mainboard/google/storm/board_info.txt b/src/mainboard/google/storm/board_info.txt deleted file mode 100644 index edc4b32..0000000 --- a/src/mainboard/google/storm/board_info.txt +++ /dev/null @@ -1,6 +0,0 @@ -Vendor name: Google -Board name: Storm Qualcomm IPQ806X board -Category: settop -ROM protocol: SPI -ROM socketed: n -Flashrom support: y diff --git a/src/soc/nvidia/tegra124/spi.c b/src/soc/nvidia/tegra124/spi.c index d5be4a6..3d659d7 100644 --- a/src/soc/nvidia/tegra124/spi.c +++ b/src/soc/nvidia/tegra124/spi.c @@ -580,7 +580,7 @@ static int tegra_spi_dma_finish(struct tegra_spi_channel *spi) } ret = 0; -done: + done: spi->dma_in = NULL; spi->dma_out = NULL; return ret; @@ -684,7 +684,7 @@ static int xfer_setup(struct tegra_spi_channel *spi, void *buf, goto done; } -done: + done: return ret; } diff --git a/src/superio/common/conf_mode.c b/src/superio/common/conf_mode.c index cbe1a9e..423f127 100644 --- a/src/superio/common/conf_mode.c +++ b/src/superio/common/conf_mode.c @@ -11,6 +11,9 @@ * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. */ #include <arch/io.h>

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New patch to review for coreboot: lint/lint-stable-004-style-labels: Update script
by Martin Roth 30 Mar '16

30 Mar '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14194 -gerrit commit 1c4607911c3e4c5a38d9fd56bb45784615b39be1 Author: Martin Roth <martinroth(a)google.com> Date: Wed Mar 30 13:56:23 2016 -0600 lint/lint-stable-004-style-labels: Update script - Look at entire tree instead of just the current commit. This was causing the test to overlook some issues that were already in the tree. - Use find instead of git to get the list of files so this check will work on new files as well. - Wrap the command so it's easier to read. Change-Id: I3dce219a29ffb1ae56a31318b995e3ba8ea43e70 Signed-off-by: Martin Roth <martinroth(a)google.com> --- util/lint/lint-stable-004-style-labels | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/util/lint/lint-stable-004-style-labels b/util/lint/lint-stable-004-style-labels index f024ca1..35814d8 100755 --- a/util/lint/lint-stable-004-style-labels +++ b/util/lint/lint-stable-004-style-labels @@ -2,6 +2,7 @@ # This file is part of the coreboot project. # # Copyright (C) 2012 Patrick Georgi <patrick(a)georgi-clan.de> +# Copyright (C) 2016 Google Inc. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by @@ -15,4 +16,8 @@ # DESCR: Check that C labels begin at start-of-line LC_ALL=C export LC_ALL -git diff --name-status |grep -v "^D" |cut -c3- |grep "^src/.*\.[csS]" | xargs grep -Hn '^[[:space:]][[:space:]]*[a-z][a-z]*:[[:space:]]*$' |grep -v "[^a-z_]default:" + +find src | \ + grep "^src/.*\.[csS]" | \ + xargs grep -Hn '^[[:space:]][[:space:]]*[a-z][a-z]*:[[:space:]]*$' | \ + grep -v "[^a-z_]default:"

1 0

New patch to review for coreboot: src/: Fix lint style-labels warnings
by Martin Roth 30 Mar '16

30 Mar '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14193 -gerrit commit cb7a4b550accd238e7985cf8f1543ff1b5ca272e Author: Martin Roth <martinroth(a)google.com> Date: Wed Mar 30 13:30:12 2016 -0600 src/: Fix lint style-labels warnings The lint-stable-004-style-labels check tries to verify that labels in c and asm files start at the first column, and don't have whitespace in front of them. - Fix 2 actual violations of the lint check. - Update a comment that was showing up as a violation. Change-Id: Ia11a90d7301e62a116c7a9ef9b4c2bc3f982b308 Signed-off-by: Martin Roth <martinroth(a)google.com> --- src/commonlib/lz4.c.inc | 64 +++++++++++----------- src/cpu/allwinner/a10/raminit.c | 2 +- src/cpu/amd/family_10h-family_15h/processor_name.c | 2 +- 3 files changed, 34 insertions(+), 34 deletions(-) diff --git a/src/commonlib/lz4.c.inc b/src/commonlib/lz4.c.inc index b3be4e5..e8f6e59 100644 --- a/src/commonlib/lz4.c.inc +++ b/src/commonlib/lz4.c.inc @@ -1,36 +1,36 @@ /* - LZ4 - Fast LZ compression algorithm - Copyright (C) 2011-2015, Yann Collet. - - BSD 2-Clause License (http://www.opensource.org/licenses/bsd-license.php) - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are - met: - - * Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - * Redistributions in binary form must reproduce the above - copyright notice, this list of conditions and the following disclaimer - in the documentation and/or other materials provided with the - distribution. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - - You can contact the author at : - - LZ4 source repository : https://github.com/Cyan4973/lz4 - - LZ4 public forum : https://groups.google.com/forum/#!forum/lz4c -*/ + * LZ4 - Fast LZ compression algorithm + * Copyright (C) 2011-2015, Yann Collet. + * + * BSD 2-Clause License (http://www.opensource.org/licenses/bsd-license.php) + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following disclaimer + * in the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You can contact the author at : + * - LZ4 source repository : https://github.com/Cyan4973/lz4 + * - LZ4 public forum : https://groups.google.com/forum/#!forum/lz4c + */ /************************************** diff --git a/src/cpu/allwinner/a10/raminit.c b/src/cpu/allwinner/a10/raminit.c index e917e6e..f3b39cb 100644 --- a/src/cpu/allwinner/a10/raminit.c +++ b/src/cpu/allwinner/a10/raminit.c @@ -317,7 +317,7 @@ static int dramc_scan_dll_para(void) return dramc_scan_readpipe(); } - fail: +fail: clrbits_le32(&dram->dllcr[0], 0x3f << 6); for (cr_i = 1; cr_i < 5; cr_i++) clrbits_le32(&dram->dllcr[cr_i], 0x4f << 14); diff --git a/src/cpu/amd/family_10h-family_15h/processor_name.c b/src/cpu/amd/family_10h-family_15h/processor_name.c index ac0392b..3d92ee2 100644 --- a/src/cpu/amd/family_10h-family_15h/processor_name.c +++ b/src/cpu/amd/family_10h-family_15h/processor_name.c @@ -340,7 +340,7 @@ int init_processor_name(void) } } - done: +done: strcpymax(&program_string[j], processor_name_string, sizeof(program_string) - j); }

1 0

Patch set updated for coreboot: nb/amd_mct_ddr3: Move DRAM MCE sync flood enable to ramstage
by Timothy Pearson 30 Mar '16

30 Mar '16

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14192 -gerrit commit c7a7bff3c75989d8927162a133bdd95249f4c479 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Wed Mar 30 13:48:24 2016 -0500 nb/amd_mct_ddr3: Move DRAM MCE sync flood enable to ramstage Enabling sync flood on DRAM MCE directly after ECC clear can lead to a system hang with no way to determine the offending DRAM module. Clear MCEs after ECC setup, but do not enable sync flood until NB setup in ramstage to allow time for any MCEs to accumulate in the status registers. Before enabling sync flood on MCE, determine if any MCEs were logged during ramstage execution and display them on the serial console. Change-Id: Ibd93801be2eed06d89c8d306c14aef5558dd5a15 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/northbridge/amd/amdfam10/misc_control.c | 45 ++++++++++++++++++++++++++ src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c | 10 ------ 2 files changed, 45 insertions(+), 10 deletions(-) diff --git a/src/northbridge/amd/amdfam10/misc_control.c b/src/northbridge/amd/amdfam10/misc_control.c index d6f9fd9..2fe715c 100644 --- a/src/northbridge/amd/amdfam10/misc_control.c +++ b/src/northbridge/amd/amdfam10/misc_control.c @@ -30,6 +30,7 @@ #include <device/pci_ops.h> #include <pc80/mc146818rtc.h> #include <lib.h> +#include <cbmem.h> #include <cpu/amd/model_10xxx_rev.h> #include "amdfam10.h" @@ -152,6 +153,50 @@ static void misc_control_init(struct device *dev) printk(BIOS_DEBUG, "NB: Function 3 Misc Control.. "); +#if IS_ENABLED(CONFIG_DIMM_DDR3) && !IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_AGESA) + uint8_t node; + uint8_t slot; + uint8_t dimm_present; + + /* Restore DRAM MCA registers */ + struct amdmct_memory_info *mem_info; + mem_info = cbmem_find(CBMEM_ID_AMDMCT_MEMINFO); + if (mem_info) { + node = PCI_SLOT(dev->path.pci.devfn) - 0x18; + + /* Check node for installed DIMMs */ + dimm_present = 0; + + /* Check all slots for installed DIMMs */ + for (slot = 0; slot < MAX_DIMMS_SUPPORTED; slot++) { + if (mem_info->dct_stat[node].DIMMPresent & (1 << slot)) { + dimm_present = 1; + break; + } + } + + if (dimm_present) { + uint32_t mc4_status_high = pci_read_config32(dev, 0x4c); + uint32_t mc4_status_low = pci_read_config32(dev, 0x48); + if (mc4_status_high != 0) { + printk(BIOS_WARNING, "\nWARNING: MC4 Machine Check Exception detected on node %d!\n" + "Signature: %08x%08x\n", node, mc4_status_high, mc4_status_low); + } + + /* Clear MC4 error status */ + pci_write_config32(dev, 0x48, 0x0); + pci_write_config32(dev, 0x4c, 0x0); + + if (mem_info->dct_stat[node].mca_config_backed_up) { + dword = pci_read_config32(dev, 0x44); + dword |= (mem_info->dct_stat[node].sync_flood_on_dram_err & 0x1) << 30; + dword |= (mem_info->dct_stat[node].sync_flood_on_any_uc_err & 0x1) << 21; + pci_write_config32(dev, 0x44, dword); + } + } + } +#endif + /* Disable Machine checks from Invalid Locations. * This is needed for PC backwards compatibility. */ diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c index 07eb0bd..1077cb8 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c @@ -84,8 +84,6 @@ u8 ECCInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) u32 val; u16 nvbits; - uint32_t dword; - mctHookBeforeECC(); /* Construct these booleans, based on setup options, for easy handling @@ -266,14 +264,6 @@ u8 ECCInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) /* Clear MC4 error status */ pci_write_config32(pDCTstat->dev_nbmisc, 0x48, 0x0); pci_write_config32(pDCTstat->dev_nbmisc, 0x4c, 0x0); - - /* Restore previous MCA error handling settings */ - if (pDCTstat->mca_config_backed_up) { - dword = Get_NB32(pDCTstat->dev_nbmisc, 0x44); - dword |= (pDCTstat->sync_flood_on_dram_err & 0x1) << 30; - dword |= (pDCTstat->sync_flood_on_any_uc_err & 0x1) << 21; - Set_NB32(pDCTstat->dev_nbmisc, 0x44, dword); - } } } }

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Patch set updated for coreboot: nb/amd_mct_ddr3: Move DRAM MCE sync flood enable to ramstage
by Timothy Pearson 30 Mar '16

30 Mar '16

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14192 -gerrit commit 938afea76b006d16dc4da203dca657659db71679 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Wed Mar 30 13:48:24 2016 -0500 nb/amd_mct_ddr3: Move DRAM MCE sync flood enable to ramstage Enabling sync flood on DRAM MCE directly after ECC clear can lead to a system hang with no way to determine the offending DRAM module. Clear MCEs after ECC setup, but do not enable sync flood until NB setup in ramstage to allow time for any MCEs to accumulate in the status registers. Before enabling sync flood on MCE, determine if any MCEs were logged during ramstage execution and display them on the serial console. Change-Id: Ibd93801be2eed06d89c8d306c14aef5558dd5a15 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/northbridge/amd/amdfam10/misc_control.c | 45 ++++++++++++++++++++++++++ src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c | 10 ------ 2 files changed, 45 insertions(+), 10 deletions(-) diff --git a/src/northbridge/amd/amdfam10/misc_control.c b/src/northbridge/amd/amdfam10/misc_control.c index d6f9fd9..568d146 100644 --- a/src/northbridge/amd/amdfam10/misc_control.c +++ b/src/northbridge/amd/amdfam10/misc_control.c @@ -30,6 +30,7 @@ #include <device/pci_ops.h> #include <pc80/mc146818rtc.h> #include <lib.h> +#include <cbmem.h> #include <cpu/amd/model_10xxx_rev.h> #include "amdfam10.h" @@ -152,6 +153,50 @@ static void misc_control_init(struct device *dev) printk(BIOS_DEBUG, "NB: Function 3 Misc Control.. "); +#if !IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_AGESA) + uint8_t node; + uint8_t slot; + uint8_t dimm_present; + + /* Restore DRAM MCA registers */ + struct amdmct_memory_info *mem_info; + mem_info = cbmem_find(CBMEM_ID_AMDMCT_MEMINFO); + if (mem_info) { + node = PCI_SLOT(dev->path.pci.devfn) - 0x18; + + /* Check node for installed DIMMs */ + dimm_present = 0; + + /* Check all slots for installed DIMMs */ + for (slot = 0; slot < MAX_DIMMS_SUPPORTED; slot++) { + if (mem_info->dct_stat[node].DIMMPresent & (1 << slot)) { + dimm_present = 1; + break; + } + } + + if (dimm_present) { + uint32_t mc4_status_high = pci_read_config32(dev, 0x4c); + uint32_t mc4_status_low = pci_read_config32(dev, 0x48); + if (mc4_status_high != 0) { + printk(BIOS_WARNING, "\nWARNING: MC4 Machine Check Exception detected on node %d!\n" + "Signature: %08x%08x\n", node, mc4_status_high, mc4_status_low); + } + + /* Clear MC4 error status */ + pci_write_config32(dev, 0x48, 0x0); + pci_write_config32(dev, 0x4c, 0x0); + + if (mem_info->dct_stat[node].mca_config_backed_up) { + dword = pci_read_config32(dev, 0x44); + dword |= (mem_info->dct_stat[node].sync_flood_on_dram_err & 0x1) << 30; + dword |= (mem_info->dct_stat[node].sync_flood_on_any_uc_err & 0x1) << 21; + pci_write_config32(dev, 0x44, dword); + } + } + } +#endif + /* Disable Machine checks from Invalid Locations. * This is needed for PC backwards compatibility. */ diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c index 07eb0bd..1077cb8 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c @@ -84,8 +84,6 @@ u8 ECCInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) u32 val; u16 nvbits; - uint32_t dword; - mctHookBeforeECC(); /* Construct these booleans, based on setup options, for easy handling @@ -266,14 +264,6 @@ u8 ECCInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) /* Clear MC4 error status */ pci_write_config32(pDCTstat->dev_nbmisc, 0x48, 0x0); pci_write_config32(pDCTstat->dev_nbmisc, 0x4c, 0x0); - - /* Restore previous MCA error handling settings */ - if (pDCTstat->mca_config_backed_up) { - dword = Get_NB32(pDCTstat->dev_nbmisc, 0x44); - dword |= (pDCTstat->sync_flood_on_dram_err & 0x1) << 30; - dword |= (pDCTstat->sync_flood_on_any_uc_err & 0x1) << 21; - Set_NB32(pDCTstat->dev_nbmisc, 0x44, dword); - } } } }

1 0

Patch set updated for coreboot: nb/amd_mct_ddr3: Move DRAM MCE sync flood enable to ramstage
by Timothy Pearson 30 Mar '16

30 Mar '16

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14192 -gerrit commit a30bfab66f343045a0aca46fbaa4302f0ff553b7 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Wed Mar 30 13:48:24 2016 -0500 nb/amd_mct_ddr3: Move DRAM MCE sync flood enable to ramstage Enabling sync flood on DRAM MCE directly after ECC clear can lead to a system hang with no way to determine the offending DRAM module. Clear MCEs after ECC setup, but do not enable sync flood until NB setup in ramstage to allow time for any MCEs to accumulate in the status registers. Before enabling sync flood on MCE, determine if any MCEs were logged during ramstage execution and display them on the serial console. Change-Id: Ibd93801be2eed06d89c8d306c14aef5558dd5a15 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/northbridge/amd/amdfam10/misc_control.c | 45 ++++++++++++++++++++++++++ src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c | 10 ------ 2 files changed, 45 insertions(+), 10 deletions(-) diff --git a/src/northbridge/amd/amdfam10/misc_control.c b/src/northbridge/amd/amdfam10/misc_control.c index d6f9fd9..56999e6 100644 --- a/src/northbridge/amd/amdfam10/misc_control.c +++ b/src/northbridge/amd/amdfam10/misc_control.c @@ -30,6 +30,7 @@ #include <device/pci_ops.h> #include <pc80/mc146818rtc.h> #include <lib.h> +#include <cbmem.h> #include <cpu/amd/model_10xxx_rev.h> #include "amdfam10.h" @@ -147,11 +148,55 @@ static void misc_control_init(struct device *dev) { uint32_t dword; uint8_t nvram; + uint8_t dimm_present; uint8_t boost_limit; uint8_t current_boost; printk(BIOS_DEBUG, "NB: Function 3 Misc Control.. "); +#if !IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_AGESA) + uint8_t node; + uint8_t slot; + + /* Restore DRAM MCA registers */ + struct amdmct_memory_info *mem_info; + mem_info = cbmem_find(CBMEM_ID_AMDMCT_MEMINFO); + if (mem_info) { + node = PCI_SLOT(dev->path.pci.devfn) - 0x18; + + /* Check node for installed DIMMs */ + dimm_present = 0; + + /* Check all slots for installed DIMMs */ + for (slot = 0; slot < MAX_DIMMS_SUPPORTED; slot++) { + if (mem_info->dct_stat[node].DIMMPresent & (1 << slot)) { + dimm_present = 1; + break; + } + } + + if (dimm_present) { + uint32_t mc4_status_high = pci_read_config32(dev, 0x4c); + uint32_t mc4_status_low = pci_read_config32(dev, 0x48); + if (mc4_status_high != 0) { + printk(BIOS_WARNING, "\nWARNING: MC4 Machine Check Exception detected on node %d!\n" + "Signature: %08x%08x\n", node, mc4_status_high, mc4_status_low); + } + + /* Clear MC4 error status */ + pci_write_config32(dev, 0x48, 0x0); + pci_write_config32(dev, 0x4c, 0x0); + + if (mem_info->dct_stat[node].mca_config_backed_up) { + dword = pci_read_config32(dev, 0x44); + dword |= (mem_info->dct_stat[node].sync_flood_on_dram_err & 0x1) << 30; + dword |= (mem_info->dct_stat[node].sync_flood_on_any_uc_err & 0x1) << 21; + pci_write_config32(dev, 0x44, dword); + } + } + } +#endif + /* Disable Machine checks from Invalid Locations. * This is needed for PC backwards compatibility. */ diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c index 07eb0bd..1077cb8 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c @@ -84,8 +84,6 @@ u8 ECCInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) u32 val; u16 nvbits; - uint32_t dword; - mctHookBeforeECC(); /* Construct these booleans, based on setup options, for easy handling @@ -266,14 +264,6 @@ u8 ECCInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) /* Clear MC4 error status */ pci_write_config32(pDCTstat->dev_nbmisc, 0x48, 0x0); pci_write_config32(pDCTstat->dev_nbmisc, 0x4c, 0x0); - - /* Restore previous MCA error handling settings */ - if (pDCTstat->mca_config_backed_up) { - dword = Get_NB32(pDCTstat->dev_nbmisc, 0x44); - dword |= (pDCTstat->sync_flood_on_dram_err & 0x1) << 30; - dword |= (pDCTstat->sync_flood_on_any_uc_err & 0x1) << 21; - Set_NB32(pDCTstat->dev_nbmisc, 0x44, dword); - } } } }

1 0

Patch set updated for coreboot: nb/amd/mct_ddr3: Clear early MCEs and report DRAM MCEs
by Timothy Pearson 30 Mar '16

30 Mar '16

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14191 -gerrit commit c37f56a5033eff98e84ea5a5eab8260dd0ac876b Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Wed Mar 30 13:07:47 2016 -0500 nb/amd/mct_ddr3: Clear early MCEs and report DRAM MCEs During power on from cold (S5) state, numerous MCEs are generated before DRAM training starts, e.g. during HT link training. Clear these MCEs before DRAM training start, and report any MCEs generated during DRAM training. Change-Id: I7d047571242e5bd041e4aac22c1ec1d7d26ef0e6 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 4 +++ src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c | 34 ++++++++++++++++++-------- 2 files changed, 28 insertions(+), 10 deletions(-) diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c index 6292f0b..2de7521 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c @@ -8048,6 +8048,10 @@ void mct_SetDramConfigHi_D(struct MCTStatStruc *pMCTstat, Set_NB32_index_wait_DCT(pDCTstat->dev_dct, dct, index_reg, 0x0d0fe006, dword); } + /* Clear MC4 error status */ + pci_write_config32(pDCTstat->dev_nbmisc, 0x48, 0x0); + pci_write_config32(pDCTstat->dev_nbmisc, 0x4c, 0x0); + printk(BIOS_DEBUG, "%s: Done\n", __func__); } diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c index 2ebd093..07eb0bd 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c @@ -250,16 +250,30 @@ u8 ECCInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) pDCTstat = pDCTstatA + Node; if (NodePresent_D(Node)) { - /* Clear MC4 error status */ - pci_write_config32(pDCTstat->dev_nbmisc, 0x48, 0x0); - pci_write_config32(pDCTstat->dev_nbmisc, 0x4c, 0x0); - - /* Restore previous MCA error handling settings */ - if (pDCTstat->mca_config_backed_up) { - dword = Get_NB32(pDCTstat->dev_nbmisc, 0x44); - dword |= (pDCTstat->sync_flood_on_dram_err & 0x1) << 30; - dword |= (pDCTstat->sync_flood_on_any_uc_err & 0x1) << 21; - Set_NB32(pDCTstat->dev_nbmisc, 0x44, dword); + dev = pDCTstat->dev_map; + reg = 0x40 + (Node << 3); /* Dram Base Node 0 + index */ + val = Get_NB32(dev, reg); + + /* WE/RE is checked */ + if ((val & 0x3) == 0x3) { /* Node has dram populated */ + uint32_t mc4_status_high = pci_read_config32(pDCTstat->dev_nbmisc, 0x4c); + uint32_t mc4_status_low = pci_read_config32(pDCTstat->dev_nbmisc, 0x48); + if (mc4_status_high != 0) { + printk(BIOS_WARNING, "WARNING: MC4 Machine Check Exception detected!\n" + "Signature: %08x%08x\n", mc4_status_high, mc4_status_low); + } + + /* Clear MC4 error status */ + pci_write_config32(pDCTstat->dev_nbmisc, 0x48, 0x0); + pci_write_config32(pDCTstat->dev_nbmisc, 0x4c, 0x0); + + /* Restore previous MCA error handling settings */ + if (pDCTstat->mca_config_backed_up) { + dword = Get_NB32(pDCTstat->dev_nbmisc, 0x44); + dword |= (pDCTstat->sync_flood_on_dram_err & 0x1) << 30; + dword |= (pDCTstat->sync_flood_on_any_uc_err & 0x1) << 21; + Set_NB32(pDCTstat->dev_nbmisc, 0x44, dword); + } } } }

1 0

Patch set updated for coreboot: nb/amd/mct_ddr3: Disable MCE framework during DRAM training
by Timothy Pearson 30 Mar '16

30 Mar '16

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14186 -gerrit commit ac1641503508e2908235dee7e413c3c25ff6310c Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Tue Mar 29 20:37:36 2016 -0500 nb/amd/mct_ddr3: Disable MCE framework during DRAM training On Family 15h processors, with certain RDIMMs, MCEs are generated as a normal part of DCT startup / DRAM training. Disable sync flood on parity or UC data error until ECC has been enabled. Change-Id: Ife54751ff127ffd59baaad35d3fea14ea01ef505 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 13 ++++++++++++ src/northbridge/amd/amdmct/mct_ddr3/mct_d.h | 5 +++++ src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c | 28 ++++++++++---------------- 3 files changed, 29 insertions(+), 17 deletions(-) diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c index f144f8a..6292f0b 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c @@ -8019,14 +8019,27 @@ void mct_SetDramConfigHi_D(struct MCTStatStruc *pMCTstat, printk(BIOS_DEBUG, "mct_SetDramConfigHi_D: DramConfigHi: %08x\n", DramConfigHi); + /* Prevent lockups on parity errors during initial DCT startup */ + if (!pDCTstat->mca_config_backed_up) { + dword = Get_NB32(pDCTstat->dev_nbmisc, 0x44); + pDCTstat->sync_flood_on_dram_err = (dword >> 30) & 0x1; + pDCTstat->sync_flood_on_any_uc_err = (dword >> 21) & 0x1; + dword &= ~(0x1 << 30); + dword &= ~(0x1 << 21); + Set_NB32(pDCTstat->dev_nbmisc, 0x44, dword); + pDCTstat->mca_config_backed_up = 1; + } + /* Program the DRAM Configuration High register */ Set_NB32_DCT(dev, dct, 0x94, DramConfigHi); if (is_fam15h()) { /* Wait until F2x[1, 0]94[FreqChgInProg]=0. */ do { + printk(BIOS_DEBUG, "*"); dword = Get_NB32_DCT(pDCTstat->dev_dct, dct, 0x94); } while (dword & (1 << FreqChgInProg)); + printk(BIOS_DEBUG, "\n"); /* Program D18F2x9C_x0D0F_E006_dct[1:0][PllLockTime] = 0xf */ dword = Get_NB32_index_wait_DCT(pDCTstat->dev_dct, dct, index_reg, 0x0d0fe006); diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h index fd35f9c..6031239 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h @@ -580,6 +580,11 @@ struct DCTStatStruc { /* A per Node structure*/ uint8_t NbPstateThreshold; uint8_t NbPstateHi; + /* MCA backup variables */ + uint8_t mca_config_backed_up; + uint8_t sync_flood_on_dram_err; + uint8_t sync_flood_on_any_uc_err; + /* New for LB Support */ u8 NodePresent; u32 dev_host; diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c index be63149..2ebd093 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c @@ -85,8 +85,6 @@ u8 ECCInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) u16 nvbits; uint32_t dword; - uint8_t sync_flood_on_dram_err[MAX_NODES_SUPPORTED]; - uint8_t sync_flood_on_any_uc_err[MAX_NODES_SUPPORTED]; mctHookBeforeECC(); @@ -120,17 +118,6 @@ u8 ECCInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) pDCTstat = pDCTstatA + Node; if (NodePresent_D(Node)) { - dword = Get_NB32(pDCTstat->dev_nbmisc, 0x44); - sync_flood_on_dram_err[Node] = (dword >> 30) & 0x1; - sync_flood_on_any_uc_err[Node] = (dword >> 21) & 0x1; - dword &= ~(0x1 << 30); - dword &= ~(0x1 << 21); - Set_NB32(pDCTstat->dev_nbmisc, 0x44, dword); - - /* Clear MC4 error status */ - pci_write_config32(pDCTstat->dev_nbmisc, 0x48, 0x0); - pci_write_config32(pDCTstat->dev_nbmisc, 0x4c, 0x0); - /* Clear the RAM before enabling ECC to prevent MCE-related lockups */ DCTMemClr_Init_D(pMCTstat, pDCTstat); DCTMemClr_Sync_D(pMCTstat, pDCTstat); @@ -263,10 +250,17 @@ u8 ECCInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) pDCTstat = pDCTstatA + Node; if (NodePresent_D(Node)) { - dword = Get_NB32(pDCTstat->dev_nbmisc, 0x44); - dword |= (sync_flood_on_dram_err[Node] & 0x1) << 30; - dword |= (sync_flood_on_any_uc_err[Node] & 0x1) << 21; - Set_NB32(pDCTstat->dev_nbmisc, 0x44, dword); + /* Clear MC4 error status */ + pci_write_config32(pDCTstat->dev_nbmisc, 0x48, 0x0); + pci_write_config32(pDCTstat->dev_nbmisc, 0x4c, 0x0); + + /* Restore previous MCA error handling settings */ + if (pDCTstat->mca_config_backed_up) { + dword = Get_NB32(pDCTstat->dev_nbmisc, 0x44); + dword |= (pDCTstat->sync_flood_on_dram_err & 0x1) << 30; + dword |= (pDCTstat->sync_flood_on_any_uc_err & 0x1) << 21; + Set_NB32(pDCTstat->dev_nbmisc, 0x44, dword); + } } }

1 0

New patch to review for coreboot: nb/amd_mct_ddr3: Move DRAM MCE sync flood enable to ramstage
by Timothy Pearson 30 Mar '16

30 Mar '16

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14192 -gerrit commit a989e41ec446eb06c8a9074d4087351e30500667 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Wed Mar 30 13:48:24 2016 -0500 nb/amd_mct_ddr3: Move DRAM MCE sync flood enable to ramstage Enabling sync flood on DRAM MCE directly after ECC clear can lead to a system hang with no way to determine the offending DRAM module. Clear MCEs after ECC setup, but do not enable sync flood until NB setup in ramstage to allow time for any MCEs to accumulate in the status registers. Before enabling sync flood on MCE, determine if any MCEs were logged during ramstage execution and display them on the serial console. Change-Id: Ibd93801be2eed06d89c8d306c14aef5558dd5a15 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/northbridge/amd/amdfam10/misc_control.c | 42 ++++++++++++++++++++++++++ src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c | 10 ------ 2 files changed, 42 insertions(+), 10 deletions(-) diff --git a/src/northbridge/amd/amdfam10/misc_control.c b/src/northbridge/amd/amdfam10/misc_control.c index 4c65bca..cc415cd 100644 --- a/src/northbridge/amd/amdfam10/misc_control.c +++ b/src/northbridge/amd/amdfam10/misc_control.c @@ -29,6 +29,7 @@ #include <device/pci_ops.h> #include <pc80/mc146818rtc.h> #include <lib.h> +#include <cbmem.h> #include <cpu/amd/model_10xxx_rev.h> #include "amdfam10.h" @@ -136,12 +137,53 @@ static void mcf3_set_resources_fam15h(device_t dev) static void misc_control_init(struct device *dev) { uint32_t dword; + uint8_t node; + uint8_t slot; uint8_t nvram; + uint8_t dimm_present; uint8_t boost_limit; uint8_t current_boost; printk(BIOS_DEBUG, "NB: Function 3 Misc Control.. "); + /* Restore DRAM MCA registers */ + struct amdmct_memory_info *mem_info; + mem_info = cbmem_find(CBMEM_ID_AMDMCT_MEMINFO); + if (mem_info) { + node = PCI_SLOT(dev->path.pci.devfn) - 0x18; + + /* Check node for installed DIMMs */ + dimm_present = 0; + + /* Check all slots for installed DIMMs */ + for (slot = 0; slot < MAX_DIMMS_SUPPORTED; slot++) { + if (mem_info->dct_stat[node].DIMMPresent & (1 << slot)) { + dimm_present = 1; + break; + } + } + + if (dimm_present) { + uint32_t mc4_status_high = pci_read_config32(dev, 0x4c); + uint32_t mc4_status_low = pci_read_config32(dev, 0x48); + if (mc4_status_high != 0) { + printk(BIOS_WARNING, "WARNING: MC4 Machine Check Exception detected on node %d!\n" + "Signature: %08x%08x\n", node, mc4_status_high, mc4_status_low); + } + + /* Clear MC4 error status */ + pci_write_config32(dev, 0x48, 0x0); + pci_write_config32(dev, 0x4c, 0x0); + + if (mem_info->dct_stat[node].mca_config_backed_up) { + dword = pci_read_config32(dev, 0x44); + dword |= (mem_info->dct_stat[node].sync_flood_on_dram_err & 0x1) << 30; + dword |= (mem_info->dct_stat[node].sync_flood_on_any_uc_err & 0x1) << 21; + pci_write_config32(dev, 0x44, dword); + } + } + } + /* Disable Machine checks from Invalid Locations. * This is needed for PC backwards compatibility. */ diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c index 07eb0bd..1077cb8 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c @@ -84,8 +84,6 @@ u8 ECCInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) u32 val; u16 nvbits; - uint32_t dword; - mctHookBeforeECC(); /* Construct these booleans, based on setup options, for easy handling @@ -266,14 +264,6 @@ u8 ECCInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) /* Clear MC4 error status */ pci_write_config32(pDCTstat->dev_nbmisc, 0x48, 0x0); pci_write_config32(pDCTstat->dev_nbmisc, 0x4c, 0x0); - - /* Restore previous MCA error handling settings */ - if (pDCTstat->mca_config_backed_up) { - dword = Get_NB32(pDCTstat->dev_nbmisc, 0x44); - dword |= (pDCTstat->sync_flood_on_dram_err & 0x1) << 30; - dword |= (pDCTstat->sync_flood_on_any_uc_err & 0x1) << 21; - Set_NB32(pDCTstat->dev_nbmisc, 0x44, dword); - } } } }

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coreboot-gerrit March 2016