coreboot-gerrit March 2016

coreboot-gerrit@coreboot.org

1 participants
1119 discussions

Patch merged into coreboot/master: nb/amd_mct_ddr3: Move DRAM MCE sync flood enable to ramstage
by gerrit＠coreboot.org 31 Mar '16

31 Mar '16

the following patch was just integrated into master: commit b3ddf83a118a7b1ae374ec00cd98420331f36cb1 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Wed Mar 30 13:48:24 2016 -0500 nb/amd_mct_ddr3: Move DRAM MCE sync flood enable to ramstage Enabling sync flood on DRAM MCE directly after ECC clear can lead to a system hang with no way to determine the offending DRAM module. Clear MCEs after ECC setup, but do not enable sync flood until NB setup in ramstage to allow time for any MCEs to accumulate in the status registers. Before enabling sync flood on MCE, determine if any MCEs were logged during ramstage execution and display them on the serial console. Also clear the DRAM ECC sync flood bits during DRAM training and initial ramstage execution. Change-Id: Ibd93801be2eed06d89c8d306c14aef5558dd5a15 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/14192 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply(a)raptorengineeringinc.com> Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/14192 for details. -gerrit

1 0

Patch merged into coreboot/master: src/: Fix lint style-labels warnings
by gerrit＠coreboot.org 31 Mar '16

31 Mar '16

the following patch was just integrated into master: commit e35db2c6eb66945d443f60ad2ba6e0e0fed27ad1 Author: Martin Roth <martinroth(a)google.com> Date: Wed Mar 30 13:30:12 2016 -0600 src/: Fix lint style-labels warnings The lint-stable-004-style-labels check tries to verify that labels in c and asm files start at the first column, and don't have whitespace in front of them. This fixes the 2 actual violations of the lint check. Change-Id: Ia11a90d7301e62a116c7a9ef9b4c2bc3f982b308 Signed-off-by: Martin Roth <martinroth(a)google.com> Reviewed-on: https://review.coreboot.org/14193 Reviewed-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Reviewed-by: Julius Werner <jwerner(a)chromium.org> Tested-by: build bot (Jenkins) See https://review.coreboot.org/14193 for details. -gerrit

1 0

Patch set updated for coreboot: vendorcode/amd/agesa/*/AGESA.h: Correct "ne" to "be" in comment
by Martin Roth 31 Mar '16

31 Mar '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/5543 -gerrit commit d0d964515df4441c1cef59387f695de5a33efd05 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Fri Mar 15 10:47:50 2013 +0100 vendorcode/amd/agesa/*/AGESA.h: Correct "ne" to "be" in comment The typo is not present anymore in Family 16h (Kabini), so fix it for the older families (Family 10h, 12h, 14h, 15h, 15h Trinity) too using the command below. $ git grep -l ' ne ' src/vendorcode/amd/agesa | xargs sed -i 's/ ne / be /g' Change-Id: I9cb419251eeec79925f48a5832fac339d40f01d1 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/vendorcode/amd/agesa/f10/AGESA.h | 2 +- src/vendorcode/amd/agesa/f12/AGESA.h | 2 +- src/vendorcode/amd/agesa/f14/AGESA.h | 2 +- src/vendorcode/amd/agesa/f15/AGESA.h | 2 +- src/vendorcode/amd/agesa/f15tn/AGESA.h | 2 +- 5 files changed, 5 insertions(+), 5 deletions(-) diff --git a/src/vendorcode/amd/agesa/f10/AGESA.h b/src/vendorcode/amd/agesa/f10/AGESA.h index a128116..a6a8d07 100644 --- a/src/vendorcode/amd/agesa/f10/AGESA.h +++ b/src/vendorcode/amd/agesa/f10/AGESA.h @@ -764,7 +764,7 @@ typedef enum { /// GNB configuration info typedef struct { IN PCIe_COMPLEX_DESCRIPTOR *PcieComplexList; /**< Pointer to array of structures describe PCIe topology on each processor package or NULL. - * Last element of array must ne terminated with DESCRIPTOR_TERMINATE_LIST + * Last element of array must be terminated with DESCRIPTOR_TERMINATE_LIST * Example of topology definition for single socket system: * @code * PCIe_PORT_DESCRIPTOR PortList [] = { diff --git a/src/vendorcode/amd/agesa/f12/AGESA.h b/src/vendorcode/amd/agesa/f12/AGESA.h index abe72b6..feb8397 100644 --- a/src/vendorcode/amd/agesa/f12/AGESA.h +++ b/src/vendorcode/amd/agesa/f12/AGESA.h @@ -1022,7 +1022,7 @@ typedef struct { /// GNB configuration info typedef struct { IN PCIe_COMPLEX_DESCRIPTOR *PcieComplexList; /**< Pointer to array of structures describe PCIe topology on each processor package or NULL. - * Last element of array must ne terminated with DESCRIPTOR_TERMINATE_LIST + * Last element of array must be terminated with DESCRIPTOR_TERMINATE_LIST * Example of topology definition for single socket system: * @code * PCIe_PORT_DESCRIPTOR PortList [] = { diff --git a/src/vendorcode/amd/agesa/f14/AGESA.h b/src/vendorcode/amd/agesa/f14/AGESA.h index d997ad1..2dc234b 100644 --- a/src/vendorcode/amd/agesa/f14/AGESA.h +++ b/src/vendorcode/amd/agesa/f14/AGESA.h @@ -877,7 +877,7 @@ typedef struct { /// GNB configuration info typedef struct { IN PCIe_COMPLEX_DESCRIPTOR *PcieComplexList; /**< Pointer to array of structures describe PCIe topology on each processor package or NULL. - * Last element of array must ne terminated with DESCRIPTOR_TERMINATE_LIST + * Last element of array must be terminated with DESCRIPTOR_TERMINATE_LIST * Example of topology definition for single socket system: * @code * PCIe_PORT_DESCRIPTOR PortList [] = { diff --git a/src/vendorcode/amd/agesa/f15/AGESA.h b/src/vendorcode/amd/agesa/f15/AGESA.h index ffa37ae..1a0c1f6 100644 --- a/src/vendorcode/amd/agesa/f15/AGESA.h +++ b/src/vendorcode/amd/agesa/f15/AGESA.h @@ -1145,7 +1145,7 @@ typedef struct { /// GNB configuration info typedef struct { IN PCIe_COMPLEX_DESCRIPTOR *PcieComplexList; /**< Pointer to array of structures describe PCIe topology on each processor package or NULL. - * Last element of array must ne terminated with DESCRIPTOR_TERMINATE_LIST + * Last element of array must be terminated with DESCRIPTOR_TERMINATE_LIST * Example of topology definition for single socket system: * @code * PCIe_PORT_DESCRIPTOR PortList [] = { diff --git a/src/vendorcode/amd/agesa/f15tn/AGESA.h b/src/vendorcode/amd/agesa/f15tn/AGESA.h index a709274..1392810 100644 --- a/src/vendorcode/amd/agesa/f15tn/AGESA.h +++ b/src/vendorcode/amd/agesa/f15tn/AGESA.h @@ -1244,7 +1244,7 @@ typedef struct { /// GNB configuration info typedef struct { IN PCIe_COMPLEX_DESCRIPTOR *PcieComplexList; /**< Pointer to array of structures describe PCIe topology on each processor package or NULL. - * Last element of array must ne terminated with DESCRIPTOR_TERMINATE_LIST + * Last element of array must be terminated with DESCRIPTOR_TERMINATE_LIST * Example of topology definition for single socket system: * @code * PCIe_PORT_DESCRIPTOR PortList [] = {

1 0

Patch set updated for coreboot: southbridge: Remove trailing space in `dump_south()` output
by Martin Roth 31 Mar '16

31 Mar '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/5179 -gerrit commit 4eb99ef7efb4834af5d77179fca02652401f13af Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Mon Feb 10 11:46:52 2014 +0100 southbridge: Remove trailing space in `dump_south()` output Change-Id: I4df9f8ce1058a2bb219508d0c8d04e153d37131c Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/southbridge/amd/cs5535/cs5535.c | 4 ++-- src/southbridge/via/vt8237r/vt8237r.c | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/src/southbridge/amd/cs5535/cs5535.c b/src/southbridge/amd/cs5535/cs5535.c index 70b8386..606bcb7 100644 --- a/src/southbridge/amd/cs5535/cs5535.c +++ b/src/southbridge/amd/cs5535/cs5535.c @@ -57,9 +57,9 @@ static void dump_south(struct device *dev) int i, j; for(i=0; i<256; i+=16) { - printk(BIOS_DEBUG, "0x%02x: ", i); + printk(BIOS_DEBUG, "0x%02x:", i); for(j=0; j<16; j++) - printk(BIOS_DEBUG, "%02x ", pci_read_config8(dev, i+j)); + printk(BIOS_DEBUG, " %02x", pci_read_config8(dev, i+j)); printk(BIOS_DEBUG, "\n"); } } diff --git a/src/southbridge/via/vt8237r/vt8237r.c b/src/southbridge/via/vt8237r/vt8237r.c index f32aa3f..e1a0e35 100644 --- a/src/southbridge/via/vt8237r/vt8237r.c +++ b/src/southbridge/via/vt8237r/vt8237r.c @@ -49,9 +49,9 @@ void dump_south(device_t dev) int i, j; for (i = 0; i < 256; i += 16) { - printk(BIOS_DEBUG, "%02x: ", i); + printk(BIOS_DEBUG, "%02x:", i); for (j = 0; j < 16; j++) - printk(BIOS_DEBUG, "%02x ", pci_read_config8(dev, i + j)); + printk(BIOS_DEBUG, " %02x", pci_read_config8(dev, i + j)); printk(BIOS_DEBUG, "\n"); } }

1 0

Patch set updated for coreboot: nb/amd/mct_ddr3: Fix revision mask for DR processors
by Timothy Pearson 31 Mar '16

31 Mar '16

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14216 -gerrit commit d1d57b14ce76131b4a7328dc4a3c530badaa770b Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Thu Mar 31 15:25:27 2016 -0500 nb/amd/mct_ddr3: Fix revision mask for DR processors The revision mask for all DR-* series processors was incorrectly set to only include the DR-B revision mask. Include all DR-* series prcessors in the DR_ALL revision mask. Change-Id: Iceda96aa6267b24abcbf78d39f4848d2be8053b8 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Found-by: Coverity, CID 1229627 (#1 of 1): Logically dead code (DEADCODE) --- src/northbridge/amd/amdmct/amddefs.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/northbridge/amd/amdmct/amddefs.h b/src/northbridge/amd/amdmct/amddefs.h index 9193a04..bbdd2ed 100644 --- a/src/northbridge/amd/amdmct/amddefs.h +++ b/src/northbridge/amd/amdmct/amddefs.h @@ -67,7 +67,7 @@ #define AMD_DR_GT_B0 (AMD_DR_ALL & ~(AMD_DR_B0)) #define AMD_DR_GT_Bx (AMD_DR_ALL & ~(AMD_DR_Ax | AMD_DR_Bx)) #define AMD_DR_GT_D0 ((AMD_DR_Dx & ~(AMD_HY_D0)) | AMD_DR_Ex) -#define AMD_DR_ALL (AMD_DR_Bx) +#define AMD_DR_ALL (AMD_DR_Ax | AMD_DR_Bx | AMD_DR_Cx | AMD_DR_Dx | AMD_DR_Ex) #define AMD_FAM10_ALL (AMD_DR_ALL | AMD_RB_C2 | AMD_HY_D0 | AMD_DA_C3 | AMD_DA_C2 | AMD_RB_C3 | AMD_HY_D1 | AMD_PH_E0) #define AMD_FAM10_LT_D (AMD_FAM10_ALL & ~(AMD_HY_D0)) #define AMD_FAM10_GT_B0 (AMD_FAM10_ALL & ~(AMD_DR_B0))

1 0

New patch to review for coreboot: nb/amd/mct_ddr3: Fix revision mask for DR processors
by Timothy Pearson 31 Mar '16

31 Mar '16

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14216 -gerrit commit e696b6938c71b09362e4233bdc226d32e10c4878 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Thu Mar 31 15:25:27 2016 -0500 nb/amd/mct_ddr3: Fix revision mask for DR processors The revision mask for all DR-* series processors was incorrectly set to only include the DR-A revision mask. Include all DR-* series prcessors in the DR_ALL revision mask. Change-Id: Iceda96aa6267b24abcbf78d39f4848d2be8053b8 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Found-by: Coverity, CID 1229627 (#1 of 1): Logically dead code (DEADCODE) --- src/northbridge/amd/amdmct/amddefs.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/northbridge/amd/amdmct/amddefs.h b/src/northbridge/amd/amdmct/amddefs.h index 9193a04..bbdd2ed 100644 --- a/src/northbridge/amd/amdmct/amddefs.h +++ b/src/northbridge/amd/amdmct/amddefs.h @@ -67,7 +67,7 @@ #define AMD_DR_GT_B0 (AMD_DR_ALL & ~(AMD_DR_B0)) #define AMD_DR_GT_Bx (AMD_DR_ALL & ~(AMD_DR_Ax | AMD_DR_Bx)) #define AMD_DR_GT_D0 ((AMD_DR_Dx & ~(AMD_HY_D0)) | AMD_DR_Ex) -#define AMD_DR_ALL (AMD_DR_Bx) +#define AMD_DR_ALL (AMD_DR_Ax | AMD_DR_Bx | AMD_DR_Cx | AMD_DR_Dx | AMD_DR_Ex) #define AMD_FAM10_ALL (AMD_DR_ALL | AMD_RB_C2 | AMD_HY_D0 | AMD_DA_C3 | AMD_DA_C2 | AMD_RB_C3 | AMD_HY_D1 | AMD_PH_E0) #define AMD_FAM10_LT_D (AMD_FAM10_ALL & ~(AMD_HY_D0)) #define AMD_FAM10_GT_B0 (AMD_FAM10_ALL & ~(AMD_DR_B0))

1 0

New patch to review for coreboot: soc/intel/apollolake: use platform_segment_loaded() for CAR coherency
by Aaron Durbin 31 Mar '16

31 Mar '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14215 -gerrit commit 07a329398dba288f329a771ece5067533fc1ffad Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Mar 31 14:00:47 2016 -0500 soc/intel/apollolake: use platform_segment_loaded() for CAR coherency Instead of using arch_segment_loaded() implement platform_segment_loaded() so as not to tangle the notion of arch and the chipset. Lastly, add a TODO to allow filtering of the L1D to L2 flush depending on the region loaded. Change-Id: I52e7cd2ae6e2d95f21bdd2fe1a471a10565309cb Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/soc/intel/apollolake/car.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/soc/intel/apollolake/car.c b/src/soc/intel/apollolake/car.c index c49d7ef..b0a5b45 100644 --- a/src/soc/intel/apollolake/car.c +++ b/src/soc/intel/apollolake/car.c @@ -26,8 +26,10 @@ static void flush_l1d_to_l2(void) wrmsr(MSR_POWER_MISC, msr); } -void arch_segment_loaded(uintptr_t start, size_t size, int flags) +void platform_segment_loaded(uintptr_t start, size_t size, int flags) { + /* TODO: filter on address to see if L1D flushing required. */ + /* Flush L1D cache to L2 on final segment loaded */ if (flags & SEG_FINAL) flush_l1d_to_l2();

1 0

New patch to review for coreboot: lib/prog_loading: introduce prog_segment_loaded()
by Aaron Durbin 31 Mar '16

31 Mar '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14214 -gerrit commit 198b08ee65c5ca90f4b86bbbafd1bcb1b84d272a Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Mar 31 13:49:00 2016 -0500 lib/prog_loading: introduce prog_segment_loaded() In order to not muddle arch vs chipset implementations provide a generic prog_segment_loaded() which calls platform_segment_loaded() and arch_segment_loaded() in that order. This allows the arch variants to live in src/arch while the chipset/platform code can implement their own. Change-Id: I17b6497219ec904d92bd286f18c9ec96b2b7af25 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/arch/x86/postcar_loader.c | 2 +- src/drivers/intel/fsp2_0/util.c | 2 +- src/include/program_loading.h | 11 +++++++++-- src/lib/cbfs.c | 2 +- src/lib/prog_ops.c | 12 ++++++++++++ src/lib/rmodule.c | 2 +- src/lib/selfboot.c | 2 +- 7 files changed, 26 insertions(+), 7 deletions(-) diff --git a/src/arch/x86/postcar_loader.c b/src/arch/x86/postcar_loader.c index eba90d4..cc1d460 100644 --- a/src/arch/x86/postcar_loader.c +++ b/src/arch/x86/postcar_loader.c @@ -115,7 +115,7 @@ void run_postcar_phase(struct postcar_frame *pcf) * Signal to rest of system that another update was made to the * postcar program prior to running it. */ - arch_segment_loaded((uintptr_t)rsl.params, sizeof(uintptr_t), + prog_segment_loaded((uintptr_t)rsl.params, sizeof(uintptr_t), SEG_FINAL); prog_run(&prog); diff --git a/src/drivers/intel/fsp2_0/util.c b/src/drivers/intel/fsp2_0/util.c index c4fe8dc..743bc9a 100644 --- a/src/drivers/intel/fsp2_0/util.c +++ b/src/drivers/intel/fsp2_0/util.c @@ -132,7 +132,7 @@ enum cb_err fsp_load_binary(struct fsp_header *hdr, return CB_ERR; /* Signal that FSP component has been loaded. */ - arch_segment_loaded(hdr->image_base, hdr->image_size, SEG_FINAL); + prog_segment_loaded(hdr->image_base, hdr->image_size, SEG_FINAL); return CB_SUCCESS; } diff --git a/src/include/program_loading.h b/src/include/program_loading.h index 8ac73dd..42addb8 100644 --- a/src/include/program_loading.h +++ b/src/include/program_loading.h @@ -37,8 +37,15 @@ enum prog_type { PROG_BL32, }; -/* Called for each segment of a program loaded. The SEG_FINAL flag will be - * set on the last segment loaded. */ +/* + * prog_segment_loaded() is called for each segment of a program loaded. The + * SEG_FINAL flag will be set on the last segment loaded. The following two + * functions, platform_segment_loaded() and arch_segment_loaded(), are called + * in that order within prog_segment_loaded(). In short, rely on + * prog_segment_loaded() to perform the proper dispatch sequence. + */ +void prog_segment_loaded(uintptr_t start, size_t size, int flags); +void platform_segment_loaded(uintptr_t start, size_t size, int flags); void arch_segment_loaded(uintptr_t start, size_t size, int flags); /* Return true if arch supports bounce buffer. */ diff --git a/src/lib/cbfs.c b/src/lib/cbfs.c index 82bfa2d..e1626d7 100644 --- a/src/lib/cbfs.c +++ b/src/lib/cbfs.c @@ -206,7 +206,7 @@ int cbfs_prog_stage_load(struct prog *pstage) /* Clear area not covered by file. */ memset(&load[fsize], 0, stage.memlen - fsize); - arch_segment_loaded((uintptr_t)load, stage.memlen, SEG_FINAL); + prog_segment_loaded((uintptr_t)load, stage.memlen, SEG_FINAL); out: prog_set_area(pstage, load, stage.memlen); diff --git a/src/lib/prog_ops.c b/src/lib/prog_ops.c index 67bdcc0..bc889fc 100644 --- a/src/lib/prog_ops.c +++ b/src/lib/prog_ops.c @@ -17,6 +17,18 @@ #include <program_loading.h> /* For each segment of a program loaded this function is called*/ +void prog_segment_loaded(uintptr_t start, size_t size, int flags) +{ + platform_segment_loaded(start, size, flags); + arch_segment_loaded(start, size, flags); +} + +void __attribute__ ((weak)) platform_segment_loaded(uintptr_t start, + size_t size, int flags) +{ + /* do nothing */ +} + void __attribute__ ((weak)) arch_segment_loaded(uintptr_t start, size_t size, int flags) { diff --git a/src/lib/rmodule.c b/src/lib/rmodule.c index 9825e6a..7043157 100644 --- a/src/lib/rmodule.c +++ b/src/lib/rmodule.c @@ -197,7 +197,7 @@ int rmodule_load(void *base, struct rmodule *module) return -1; rmodule_clear_bss(module); - arch_segment_loaded((uintptr_t)module->location, + prog_segment_loaded((uintptr_t)module->location, rmodule_memory_size(module), SEG_FINAL); return 0; diff --git a/src/lib/selfboot.c b/src/lib/selfboot.c index 7d3e2dd..23eda14 100644 --- a/src/lib/selfboot.c +++ b/src/lib/selfboot.c @@ -452,7 +452,7 @@ static int load_self_segments( * Each architecture can perform additonal operations * on the loaded segment */ - arch_segment_loaded((uintptr_t)dest, ptr->s_memsz, + prog_segment_loaded((uintptr_t)dest, ptr->s_memsz, last_non_empty == ptr ? SEG_FINAL : 0); } }

1 0

New patch to review for coreboot: arch/x86: notify the system when the postcar parameter was updated
by Aaron Durbin 31 Mar '16

31 Mar '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14213 -gerrit commit be3dc834fabb77d034ba35f71c5619931538bea1 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Mar 31 13:36:33 2016 -0500 arch/x86: notify the system when the postcar parameter was updated While rmodule_load() calls arch_segment_loaded() when it's done loading any pieces of code which further modify it, like changing parameters within the program itself, need to notify the rest of the system. Change-Id: Ia3374b58488120ba6279592a77d7f9c6217f1215 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/arch/x86/postcar_loader.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/src/arch/x86/postcar_loader.c b/src/arch/x86/postcar_loader.c index 580cc45..eba90d4 100644 --- a/src/arch/x86/postcar_loader.c +++ b/src/arch/x86/postcar_loader.c @@ -111,5 +111,12 @@ void run_postcar_phase(struct postcar_frame *pcf) *(uintptr_t *)rsl.params = pcf->stack; + /* + * Signal to rest of system that another update was made to the + * postcar program prior to running it. + */ + arch_segment_loaded((uintptr_t)rsl.params, sizeof(uintptr_t), + SEG_FINAL); + prog_run(&prog); }

1 0

New patch to review for coreboot: soc/intel/apollolake: use arch_segment_loaded() for CAR code coherency
by Aaron Durbin 31 Mar '16

31 Mar '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14212 -gerrit commit 72c7fb459d8e9f62abe9af9769a8c0956a77f7a3 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Mar 31 13:26:46 2016 -0500 soc/intel/apollolake: use arch_segment_loaded() for CAR code coherency Instead of using platform_prog_run() for flushing programs from L1D to L2 for code coherency purposes use arch_segment_loaded() instead as that it's primary purpose. The arch_segment_loaded() is called within the infrastructure at the appropriate places when loading programs. Therefore use that to perform the L1D flush instead of when something is just about to run. Change-Id: Ib0a6be6f676dcf2c946ef5702471af65d89133e9 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/soc/intel/apollolake/car.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/src/soc/intel/apollolake/car.c b/src/soc/intel/apollolake/car.c index 7646865..c49d7ef 100644 --- a/src/soc/intel/apollolake/car.c +++ b/src/soc/intel/apollolake/car.c @@ -26,8 +26,9 @@ static void flush_l1d_to_l2(void) wrmsr(MSR_POWER_MISC, msr); } -void platform_prog_run(struct prog *prog) +void arch_segment_loaded(uintptr_t start, size_t size, int flags) { - /* Flush L1D cache to L2 */ - flush_l1d_to_l2(); + /* Flush L1D cache to L2 on final segment loaded */ + if (flags & SEG_FINAL) + flush_l1d_to_l2(); }

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit March 2016