Patch merged into coreboot/master: nb/amd_mct_ddr3: Move DRAM MCE sync flood enable to ramstage

the following patch was just integrated into master:
commit b3ddf83a118a7b1ae374ec00cd98420331f36cb1
Author: Timothy Pearson <[e-mail]>
Date:   Wed Mar 30 13:48:24 2016 -0500

    nb/amd_mct_ddr3: Move DRAM MCE sync flood enable to ramstage
    
    Enabling sync flood on DRAM MCE directly after ECC clear can
    lead to a system hang with no way to determine the offending
    DRAM module.  Clear MCEs after ECC setup, but do not enable
    sync flood until NB setup in ramstage to allow time for any
    MCEs to accumulate in the status registers.  Before enabling
    sync flood on MCE, determine if any MCEs were logged during
    ramstage execution and display them on the serial console.
    
    Also clear the DRAM ECC sync flood bits during DRAM training
    and initial ramstage execution.
    
    Change-Id: Ibd93801be2eed06d89c8d306c14aef5558dd5a15
    Signed-off-by: Timothy Pearson <[e-mail]>
    Reviewed-on: https://review.coreboot.org/14192
    Tested-by: build bot (Jenkins)
    Tested-by: Raptor Engineering Automated Test Stand <[e-mail]>
    Reviewed-by: Martin Roth <[e-mail]>


See https://review.coreboot.org/14192 for details.

-gerrit