March 2016 - coreboot-gerrit - mail.coreboot.org

New patch to review for coreboot: soc/intel/apollolake: use CAR code coherency for all CAR stages

by Aaron Durbin

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14210 -gerrit commit 5ad0a02a16fe04f240db9eb3a6932eaca3a455c7 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Mar 31 11:38:13 2016 -0500 soc/intel/apollolake: use CAR code coherency for all CAR stages The flush L1D to L2 operation was only being used when loading romstage from bootblock. However, when the FSP-M component is loaded no code coherency actions are taken. I suspect this is because the FSP-M component is larger than the 24KiB L1D and the entry point is early in the image. Thus, when loading the FSP-M component the earlier part of the image if flushed out to L2 in the process of loading the latter part of the component. Also, once verstage is introduced the same code coherency actions need to be taken as well. Therefore, position the apollolake code to handle all these cases. Change-Id: Ie71764f1b420a6072c4f149ad3e37278b6cb70e1 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/soc/intel/apollolake/Makefile.inc | 2 ++ src/soc/intel/apollolake/bootblock/bootblock.c | 9 ------- src/soc/intel/apollolake/car.c | 33 ++++++++++++++++++++++++++ 3 files changed, 35 insertions(+), 9 deletions(-) diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index 41ac847..70ab515 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -11,6 +11,7 @@ subdirs-y += ../../../cpu/x86/cache bootblock-y += bootblock/bootblock.c bootblock-y += bootblock/cache_as_ram.S bootblock-y += bootblock/bootblock.c +bootblock-y += car.c bootblock-y += gpio.c bootblock-y += mmap_boot.c bootblock-y += placeholders.c @@ -18,6 +19,7 @@ bootblock-y += tsc_freq.c bootblock-$(CONFIG_SOC_UART_DEBUG) += uart_early.c romstage-y += placeholders.c +romstage-y += car.c romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += romstage.c romstage-y += gpio.c romstage-$(CONFIG_SOC_UART_DEBUG) += uart_early.c diff --git a/src/soc/intel/apollolake/bootblock/bootblock.c b/src/soc/intel/apollolake/bootblock/bootblock.c index 4ea3f70..a9258e1 100644 --- a/src/soc/intel/apollolake/bootblock/bootblock.c +++ b/src/soc/intel/apollolake/bootblock/bootblock.c @@ -12,7 +12,6 @@ #include <arch/cpu.h> #include <bootblock_common.h> #include <device/pci.h> -#include <program_loading.h> #include <soc/bootblock.h> #include <soc/cpu.h> #include <soc/northbridge.h> @@ -36,14 +35,6 @@ void asmlinkage bootblock_c_entry(void) main(); } -void platform_prog_run(struct prog *prog) -{ - /* Flush L1D cache to L2 */ - msr_t msr = rdmsr(MSR_POWER_MISC); - msr.lo |= (1 << 8); - wrmsr(MSR_POWER_MISC, msr); -} - void bootblock_soc_early_init(void) { /* Prepare UART for serial console. */ diff --git a/src/soc/intel/apollolake/car.c b/src/soc/intel/apollolake/car.c new file mode 100644 index 0000000..7646865 --- /dev/null +++ b/src/soc/intel/apollolake/car.c @@ -0,0 +1,33 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corp. + * Copyright 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include <arch/cpu.h> +#include <program_loading.h> +#include <soc/cpu.h> + +/* + * This file supports the necessary hoops one needs to jump through since + * early FSP component and early stages are running from cache-as-ram. + */ + +static void flush_l1d_to_l2(void) +{ + msr_t msr = rdmsr(MSR_POWER_MISC); + msr.lo |= (1 << 8); + wrmsr(MSR_POWER_MISC, msr); +} + +void platform_prog_run(struct prog *prog) +{ + /* Flush L1D cache to L2 */ + flush_l1d_to_l2(); +}

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New patch to review for coreboot: drivers/intel/fsp2_0: signal that FSP components are loaded

by Aaron Durbin

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14211 -gerrit commit c4c122713bfccd2b425e5fd0d0b69fa5e8e01ad3 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Mar 31 12:48:30 2016 -0500 drivers/intel/fsp2_0: signal that FSP components are loaded In order for the platform code to handle situations where special actions are required after a piece of code is loaded use arch_segment_loaded() to signal to the platform code that the compoment is fully loaded into memory. Change-Id: I119cfc9913f15eb4968fe5bf6a56589e2c53f2d1 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/drivers/intel/fsp2_0/util.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/drivers/intel/fsp2_0/util.c b/src/drivers/intel/fsp2_0/util.c index a234a7c..c4fe8dc 100644 --- a/src/drivers/intel/fsp2_0/util.c +++ b/src/drivers/intel/fsp2_0/util.c @@ -17,6 +17,7 @@ #include <fsp/util.h> #include <lib.h> #include <memrange.h> +#include <program_loading.h> #include <string.h> static bool looks_like_fsp_header(const uint8_t *raw_hdr) @@ -130,5 +131,8 @@ enum cb_err fsp_load_binary(struct fsp_header *hdr, if (rdev_readat(&file_data, (void *)hdr->image_base, 0, hdr->image_size) < 0) return CB_ERR; + /* Signal that FSP component has been loaded. */ + arch_segment_loaded(hdr->image_base, hdr->image_size, SEG_FINAL); + return CB_SUCCESS; }

5 years, 5 months

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Patch set updated for coreboot: nb/amd_mct_ddr3: Move DRAM MCE sync flood enable to ramstage

by Timothy Pearson

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14192 -gerrit commit 1c5418422f4e891ddc1814ef4d78a1d1b1bff3b3 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Wed Mar 30 13:48:24 2016 -0500 nb/amd_mct_ddr3: Move DRAM MCE sync flood enable to ramstage Enabling sync flood on DRAM MCE directly after ECC clear can lead to a system hang with no way to determine the offending DRAM module. Clear MCEs after ECC setup, but do not enable sync flood until NB setup in ramstage to allow time for any MCEs to accumulate in the status registers. Before enabling sync flood on MCE, determine if any MCEs were logged during ramstage execution and display them on the serial console. Also clear the DRAM ECC sync flood bits during DRAM training and initial ramstage execution. Change-Id: Ibd93801be2eed06d89c8d306c14aef5558dd5a15 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/northbridge/amd/amdfam10/misc_control.c | 46 ++++++++++++++++++++++++++ src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 2 ++ src/northbridge/amd/amdmct/mct_ddr3/mct_d.h | 1 + src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c | 10 ------ 4 files changed, 49 insertions(+), 10 deletions(-) diff --git a/src/northbridge/amd/amdfam10/misc_control.c b/src/northbridge/amd/amdfam10/misc_control.c index d6f9fd9..de9f342 100644 --- a/src/northbridge/amd/amdfam10/misc_control.c +++ b/src/northbridge/amd/amdfam10/misc_control.c @@ -30,6 +30,7 @@ #include <device/pci_ops.h> #include <pc80/mc146818rtc.h> #include <lib.h> +#include <cbmem.h> #include <cpu/amd/model_10xxx_rev.h> #include "amdfam10.h" @@ -152,6 +153,51 @@ static void misc_control_init(struct device *dev) printk(BIOS_DEBUG, "NB: Function 3 Misc Control.. "); +#if IS_ENABLED(CONFIG_DIMM_DDR3) && !IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_AGESA) + uint8_t node; + uint8_t slot; + uint8_t dimm_present; + + /* Restore DRAM MCA registers */ + struct amdmct_memory_info *mem_info; + mem_info = cbmem_find(CBMEM_ID_AMDMCT_MEMINFO); + if (mem_info) { + node = PCI_SLOT(dev->path.pci.devfn) - 0x18; + + /* Check node for installed DIMMs */ + dimm_present = 0; + + /* Check all slots for installed DIMMs */ + for (slot = 0; slot < MAX_DIMMS_SUPPORTED; slot++) { + if (mem_info->dct_stat[node].DIMMPresent & (1 << slot)) { + dimm_present = 1; + break; + } + } + + if (dimm_present) { + uint32_t mc4_status_high = pci_read_config32(dev, 0x4c); + uint32_t mc4_status_low = pci_read_config32(dev, 0x48); + if (mc4_status_high != 0) { + printk(BIOS_WARNING, "\nWARNING: MC4 Machine Check Exception detected on node %d!\n" + "Signature: %08x%08x\n", node, mc4_status_high, mc4_status_low); + } + + /* Clear MC4 error status */ + pci_write_config32(dev, 0x48, 0x0); + pci_write_config32(dev, 0x4c, 0x0); + + if (mem_info->dct_stat[node].mca_config_backed_up) { + dword = pci_read_config32(dev, 0x44); + dword |= (mem_info->dct_stat[node].sync_flood_on_dram_err & 0x1) << 30; + dword |= (mem_info->dct_stat[node].sync_flood_on_any_uc_err & 0x1) << 21; + dword |= (mem_info->dct_stat[node].sync_flood_on_uc_dram_ecc_err & 0x1) << 2; + pci_write_config32(dev, 0x44, dword); + } + } + } +#endif + /* Disable Machine checks from Invalid Locations. * This is needed for PC backwards compatibility. */ diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c index 2de7521..0b88331 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c @@ -8024,8 +8024,10 @@ void mct_SetDramConfigHi_D(struct MCTStatStruc *pMCTstat, dword = Get_NB32(pDCTstat->dev_nbmisc, 0x44); pDCTstat->sync_flood_on_dram_err = (dword >> 30) & 0x1; pDCTstat->sync_flood_on_any_uc_err = (dword >> 21) & 0x1; + pDCTstat->sync_flood_on_uc_dram_ecc_err = (dword >> 2) & 0x1; dword &= ~(0x1 << 30); dword &= ~(0x1 << 21); + dword &= ~(0x1 << 2); Set_NB32(pDCTstat->dev_nbmisc, 0x44, dword); pDCTstat->mca_config_backed_up = 1; } diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h index 6031239..67eb2b4 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h @@ -584,6 +584,7 @@ struct DCTStatStruc { /* A per Node structure*/ uint8_t mca_config_backed_up; uint8_t sync_flood_on_dram_err; uint8_t sync_flood_on_any_uc_err; + uint8_t sync_flood_on_uc_dram_ecc_err; /* New for LB Support */ u8 NodePresent; diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c index 07eb0bd..1077cb8 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c @@ -84,8 +84,6 @@ u8 ECCInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) u32 val; u16 nvbits; - uint32_t dword; - mctHookBeforeECC(); /* Construct these booleans, based on setup options, for easy handling @@ -266,14 +264,6 @@ u8 ECCInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) /* Clear MC4 error status */ pci_write_config32(pDCTstat->dev_nbmisc, 0x48, 0x0); pci_write_config32(pDCTstat->dev_nbmisc, 0x4c, 0x0); - - /* Restore previous MCA error handling settings */ - if (pDCTstat->mca_config_backed_up) { - dword = Get_NB32(pDCTstat->dev_nbmisc, 0x44); - dword |= (pDCTstat->sync_flood_on_dram_err & 0x1) << 30; - dword |= (pDCTstat->sync_flood_on_any_uc_err & 0x1) << 21; - Set_NB32(pDCTstat->dev_nbmisc, 0x44, dword); - } } } }

5 years, 5 months

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Patch merged into coreboot/master: nb/amd/mct_ddr3: Clear early MCEs and report DRAM MCEs

by gerrit＠coreboot.org

the following patch was just integrated into master: commit c00f4d669dd03bf5a4ee8c255bb71fc86f229239 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Wed Mar 30 13:07:47 2016 -0500 nb/amd/mct_ddr3: Clear early MCEs and report DRAM MCEs During power on from cold (S5) state, numerous MCEs are generated before DRAM training starts, e.g. during HT link training. Clear these MCEs before DRAM training start, and report any MCEs generated during DRAM training. Change-Id: I7d047571242e5bd041e4aac22c1ec1d7d26ef0e6 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/14191 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> Tested-by: Raptor Engineering Automated Test Stand <noreply(a)raptorengineeringinc.com> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See https://review.coreboot.org/14191 for details. -gerrit

5 years, 5 months

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Patch set updated for coreboot: lint/lint-stable-004-style-labels: Update script

by Martin Roth

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14194 -gerrit commit 2e7b942c0b887110bf654f315e994af995732ddd Author: Martin Roth <martinroth(a)google.com> Date: Wed Mar 30 13:56:23 2016 -0600 lint/lint-stable-004-style-labels: Update script - Look at entire tree instead of just the current commit. This was causing the test to overlook some issues that were already in the tree. - If git is on the system, and the code is in a git repo, use the 'git ls-files' command to find the files to examine. If those conditions aren't met, fall back to using the find command. - Wrap the command so it's easier to read. Change-Id: I3dce219a29ffb1ae56a31318b995e3ba8ea43e70 Signed-off-by: Martin Roth <martinroth(a)google.com> --- util/lint/lint-stable-004-style-labels | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/util/lint/lint-stable-004-style-labels b/util/lint/lint-stable-004-style-labels index f024ca1..7b68b4a 100755 --- a/util/lint/lint-stable-004-style-labels +++ b/util/lint/lint-stable-004-style-labels @@ -2,6 +2,7 @@ # This file is part of the coreboot project. # # Copyright (C) 2012 Patrick Georgi <patrick(a)georgi-clan.de> +# Copyright (C) 2016 Google Inc. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by @@ -15,4 +16,15 @@ # DESCR: Check that C labels begin at start-of-line LC_ALL=C export LC_ALL -git diff --name-status |grep -v "^D" |cut -c3- |grep "^src/.*\.[csS]" | xargs grep -Hn '^[[:space:]][[:space:]]*[a-z][a-z]*:[[:space:]]*$' |grep -v "[^a-z_]default:" + +# Use git ls-files if the code is in a git repo, otherwise use find. +if [ -n "$(command -v git)" ] && [ -d .git ]; then + FIND_FILES="git ls-files" +else + FIND_FILES="find src" +fi + +${FIND_FILES} | \ + grep "^src/.*\.[csS]$" | \ + xargs grep -Hn '^[[:space:]][[:space:]]*[a-z][a-z]*:[[:space:]]*$' | \ + grep -v "[^a-z_]default:"

5 years, 5 months

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Patch set updated for coreboot: src/: Fix lint style-labels warnings

by Martin Roth

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14193 -gerrit commit 2df8c503085095b6b17f3ff97e8b71d0ed7245e9 Author: Martin Roth <martinroth(a)google.com> Date: Wed Mar 30 13:30:12 2016 -0600 src/: Fix lint style-labels warnings The lint-stable-004-style-labels check tries to verify that labels in c and asm files start at the first column, and don't have whitespace in front of them. This fixes the 2 actual violations of the lint check. Change-Id: Ia11a90d7301e62a116c7a9ef9b4c2bc3f982b308 Signed-off-by: Martin Roth <martinroth(a)google.com> --- src/cpu/allwinner/a10/raminit.c | 2 +- src/cpu/amd/family_10h-family_15h/processor_name.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/cpu/allwinner/a10/raminit.c b/src/cpu/allwinner/a10/raminit.c index e917e6e..f3b39cb 100644 --- a/src/cpu/allwinner/a10/raminit.c +++ b/src/cpu/allwinner/a10/raminit.c @@ -317,7 +317,7 @@ static int dramc_scan_dll_para(void) return dramc_scan_readpipe(); } - fail: +fail: clrbits_le32(&dram->dllcr[0], 0x3f << 6); for (cr_i = 1; cr_i < 5; cr_i++) clrbits_le32(&dram->dllcr[cr_i], 0x4f << 14); diff --git a/src/cpu/amd/family_10h-family_15h/processor_name.c b/src/cpu/amd/family_10h-family_15h/processor_name.c index ac0392b..3d92ee2 100644 --- a/src/cpu/amd/family_10h-family_15h/processor_name.c +++ b/src/cpu/amd/family_10h-family_15h/processor_name.c @@ -340,7 +340,7 @@ int init_processor_name(void) } } - done: +done: strcpymax(&program_string[j], processor_name_string, sizeof(program_string) - j); }

5 years, 5 months

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Patch merged into coreboot/master: nb/amd/mct_ddr3: Disable MCE framework during DRAM training

by gerrit＠coreboot.org

the following patch was just integrated into master: commit c094d9961144871c472698c41ce634e58abb6a32 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Tue Mar 29 20:37:36 2016 -0500 nb/amd/mct_ddr3: Disable MCE framework during DRAM training On Family 15h processors, with certain RDIMMs, MCEs are generated as a normal part of DCT startup / DRAM training. Disable sync flood on parity or UC data error until ECC has been enabled. Change-Id: Ife54751ff127ffd59baaad35d3fea14ea01ef505 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/14186 Tested-by: Raptor Engineering Automated Test Stand <noreply(a)raptorengineeringinc.com> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/14186 for details. -gerrit

5 years, 5 months

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Patch set updated for coreboot: src/mainboard: Disable power_on_after_fail CMOS option for laptop's

by Philipp Deppenwiese

Philipp Deppenwiese (zaolin.daisuki(a)googlemail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13884 -gerrit commit 29415bfcd168e445eede707b72df64b3eb7085d5 Author: Philipp Deppenwiese <zaolin(a)das-labor.org> Date: Thu Mar 3 01:14:03 2016 +0100 src/mainboard: Disable power_on_after_fail CMOS option for laptop's power_on_after_fail=Enable in cmos.default leads to wake on AC behaviour on mobile systems. Therefore set cmos.default entry to "Disable" in order to improve user experience. Change-Id: I977a4e6bc028c8c4c7fc1c2f5fdd74a59e951c60 Signed-off-by: Philipp Deppenwiese <zaolin(a)das-labor.org> --- src/mainboard/lenovo/t420s/cmos.default | 4 ++-- src/mainboard/lenovo/t430s/cmos.default | 4 ++-- src/mainboard/lenovo/t520/cmos.default | 4 ++-- src/mainboard/lenovo/t530/cmos.default | 4 ++-- src/mainboard/lenovo/x201/cmos.default | 2 +- src/mainboard/lenovo/x220/cmos.default | 2 +- src/mainboard/lenovo/x230/cmos.default | 4 ++-- src/mainboard/packardbell/ms2290/cmos.default | 2 +- 8 files changed, 13 insertions(+), 13 deletions(-) diff --git a/src/mainboard/lenovo/t420s/cmos.default b/src/mainboard/lenovo/t420s/cmos.default index 6f3f75d..1b8e212 100644 --- a/src/mainboard/lenovo/t420s/cmos.default +++ b/src/mainboard/lenovo/t420s/cmos.default @@ -1,7 +1,7 @@ boot_option=Fallback baud_rate=115200 debug_level=Spew -power_on_after_fail=Enable +power_on_after_fail=Disable nmi=Enable volume=0x3 first_battery=Primary @@ -13,4 +13,4 @@ sata_mode=AHCI fn_ctrl_swap=Disable sticky_fn=Disable trackpoint=Enable -hyper_threading=Enable \ No newline at end of file +hyper_threading=Enable diff --git a/src/mainboard/lenovo/t430s/cmos.default b/src/mainboard/lenovo/t430s/cmos.default index 99a0f1a..00e8863 100644 --- a/src/mainboard/lenovo/t430s/cmos.default +++ b/src/mainboard/lenovo/t430s/cmos.default @@ -1,7 +1,7 @@ boot_option=Fallback baud_rate=115200 debug_level=Spew -power_on_after_fail=Enable +power_on_after_fail=Disable nmi=Enable volume=0x3 first_battery=Primary @@ -14,4 +14,4 @@ fn_ctrl_swap=Disable sticky_fn=Disable trackpoint=Enable hyper_threading=Enable -backlight=Both \ No newline at end of file +backlight=Both diff --git a/src/mainboard/lenovo/t520/cmos.default b/src/mainboard/lenovo/t520/cmos.default index 99a0f1a..00e8863 100644 --- a/src/mainboard/lenovo/t520/cmos.default +++ b/src/mainboard/lenovo/t520/cmos.default @@ -1,7 +1,7 @@ boot_option=Fallback baud_rate=115200 debug_level=Spew -power_on_after_fail=Enable +power_on_after_fail=Disable nmi=Enable volume=0x3 first_battery=Primary @@ -14,4 +14,4 @@ fn_ctrl_swap=Disable sticky_fn=Disable trackpoint=Enable hyper_threading=Enable -backlight=Both \ No newline at end of file +backlight=Both diff --git a/src/mainboard/lenovo/t530/cmos.default b/src/mainboard/lenovo/t530/cmos.default index 99a0f1a..00e8863 100644 --- a/src/mainboard/lenovo/t530/cmos.default +++ b/src/mainboard/lenovo/t530/cmos.default @@ -1,7 +1,7 @@ boot_option=Fallback baud_rate=115200 debug_level=Spew -power_on_after_fail=Enable +power_on_after_fail=Disable nmi=Enable volume=0x3 first_battery=Primary @@ -14,4 +14,4 @@ fn_ctrl_swap=Disable sticky_fn=Disable trackpoint=Enable hyper_threading=Enable -backlight=Both \ No newline at end of file +backlight=Both diff --git a/src/mainboard/lenovo/x201/cmos.default b/src/mainboard/lenovo/x201/cmos.default index 710edfc..50d17ae 100644 --- a/src/mainboard/lenovo/x201/cmos.default +++ b/src/mainboard/lenovo/x201/cmos.default @@ -1,7 +1,7 @@ boot_option=Fallback baud_rate=115200 debug_level=Spew -power_on_after_fail=Enable +power_on_after_fail=Disable nmi=Enable volume=0x3 first_battery=Primary diff --git a/src/mainboard/lenovo/x220/cmos.default b/src/mainboard/lenovo/x220/cmos.default index 8038d64..1b8e212 100644 --- a/src/mainboard/lenovo/x220/cmos.default +++ b/src/mainboard/lenovo/x220/cmos.default @@ -1,7 +1,7 @@ boot_option=Fallback baud_rate=115200 debug_level=Spew -power_on_after_fail=Enable +power_on_after_fail=Disable nmi=Enable volume=0x3 first_battery=Primary diff --git a/src/mainboard/lenovo/x230/cmos.default b/src/mainboard/lenovo/x230/cmos.default index 99a0f1a..00e8863 100644 --- a/src/mainboard/lenovo/x230/cmos.default +++ b/src/mainboard/lenovo/x230/cmos.default @@ -1,7 +1,7 @@ boot_option=Fallback baud_rate=115200 debug_level=Spew -power_on_after_fail=Enable +power_on_after_fail=Disable nmi=Enable volume=0x3 first_battery=Primary @@ -14,4 +14,4 @@ fn_ctrl_swap=Disable sticky_fn=Disable trackpoint=Enable hyper_threading=Enable -backlight=Both \ No newline at end of file +backlight=Both diff --git a/src/mainboard/packardbell/ms2290/cmos.default b/src/mainboard/packardbell/ms2290/cmos.default index aef840c..43c09e8 100644 --- a/src/mainboard/packardbell/ms2290/cmos.default +++ b/src/mainboard/packardbell/ms2290/cmos.default @@ -1,6 +1,6 @@ boot_option=Fallback baud_rate=115200 debug_level=Spew -power_on_after_fail=Enable +power_on_after_fail=Disable nmi=Enable sata_mode=AHCI

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New patch to review for coreboot: superiotool: Fix some whitespace issues

by Roberto Muñoz Gómez

Roberto Muñoz Gómez (roberto(a)gul.es) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14207 -gerrit commit 5d4a3b8dfb7ce6af22ad918f837438aa7edd55f7 Author: Roberto Muñoz Gómez <munoz.roberto(a)gmail.com> Date: Thu Mar 31 17:34:15 2016 +0200 superiotool: Fix some whitespace issues Fix some whitespace issues Change-Id: I7732ddd0f8622c09e416bdde16e04d4d6410d10e Signed-off-by: Roberto Muñoz Gómez <munoz.roberto(a)gmail.com> --- util/superiotool/nuvoton.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/util/superiotool/nuvoton.c b/util/superiotool/nuvoton.c index 83f461d..7c95615 100644 --- a/util/superiotool/nuvoton.c +++ b/util/superiotool/nuvoton.c @@ -490,7 +490,7 @@ static const struct superio_registers reg_table[] = { {0x30,0xe0,0xe1,0xe2,0xe3,0xe4,0xe5,0xe6,0xe7,0xe8,0xe9,0xea,0xeb,0xec,0xed,0xee,0xef,0xf0,0xf1,0xf2,0xf3,0xf4,0xf5,0xf6,0xf7,0xf8,0xf9,0xfa,0xfb,0xfc,0xfd,0xfe,0xff,EOT}, {0xdf,0xff,0x00,0x00,0x00,0xef,0x00,0x00,0x00,0xff,0x00,0x00,0x00,0xff,0x00,0x00,0x00,0xff,0xff,0x00,0x00,0xff,0x00,0x00,0x00,0xff,0x00,0x00,0x00,0x02,0x00,0x00,0x00,EOT}}, {0x08, "GPIO,WDT1", - {0x30,0x60,0x61,0xe0,0xe1,0xe2,0xe3,0xe4,0xe5,0xe6,0xe7,0xf0,0xf1,0xf2,EOT}, + {0x30,0x60,0x61,0xe0,0xe1,0xe2,0xe3,0xe4,0xe5,0xe6,0xe7,0xf0,0xf1,0xf2,EOT}, {0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x04,0x00,EOT}}, {0x09, "GPIO", {0xe0,0xe1,0xe2,EOT}, @@ -514,7 +514,7 @@ static const struct superio_registers reg_table[] = { {0x30,0x60,0x61,0x70,0xf0,0xf2,0xf3,0xf4,0xf5,0xf6,0xf7,0xf8,EOT}, {0x00,0x03,0x00,0x04,0x00,0x00,0x00,0xff,0xff,0x02,0x00,0x00,EOT}}, {0x11, "UARTD", - {0x30,0x60,0x61,0x70,0xf0,0xf2,0xf3,0xf4,0xf5,0xf6,0xf7,0xf8,EOT}, + {0x30,0x60,0x61,0x70,0xf0,0xf2,0xf3,0xf4,0xf5,0xf6,0xf7,0xf8,EOT}, {0x00,0x02,0x00,0x03,0x00,0x00,0x00,0xff,0xff,0x02,0x00,0x00,EOT}}, {0x12, "UARTE", {0x30,0x60,0x61,0x70,0xf0,0xf2,0xf3,0xf4,0xf5,0xf6,0xf7,0xf8,EOT}, @@ -526,7 +526,7 @@ static const struct superio_registers reg_table[] = { {0x30,0x60,0x61,0x70,0xe0,0xe1,0xe2,0xe3,0xe4,0xf0,0xf1,EOT}, {0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x10,0x00,0x00,0x00,EOT}}, {0x15, "FADING LED", - {0xe0,0xe1,0xe2,0xe3,0xe4,0xe5,0xe6,0xe7,0xe8,0xe9,EOT}, + {0xe0,0xe1,0xe2,0xe3,0xe4,0xe5,0xe6,0xe7,0xe8,0xe9,EOT}, {0x00,0x3f,0x01,0x11,0x11,0x02,0x00,0x00,0x01,0x00,EOT}}, {0x16, "Deep Sleep", {0x30,0xe0,0xe1,0xe2,EOT},

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Patch set updated for coreboot: superiotool: Add support for chip NCT6102D / NCT6106D

by Roberto Muñoz Gómez

Roberto Muñoz Gómez (roberto(a)gul.es) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14206 -gerrit commit 8f0f53483e47f4c37e5cd5e62693f4f908e5118d Author: Roberto Muñoz Gómez <munoz.roberto(a)gmail.com> Date: Thu Mar 31 17:03:53 2016 +0200 superiotool: Add support for chip NCT6102D / NCT6106D Add support of chip NCT6102D / NCT6106D in superiotool Change-Id: I689ff8e796f43a5aac144e9898df750407588b1f Signed-off-by: Roberto Muñoz Gómez <munoz.roberto(a)gmail.com> --- util/superiotool/nuvoton.c | 68 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 68 insertions(+) diff --git a/util/superiotool/nuvoton.c b/util/superiotool/nuvoton.c index 7135f25..83f461d 100644 --- a/util/superiotool/nuvoton.c +++ b/util/superiotool/nuvoton.c @@ -464,6 +464,74 @@ static const struct superio_registers reg_table[] = { {0x30,0xe0,0xe1,0xe2,EOT}, {0x20,0x20,0x04,0x05,EOT}}, {EOT}}}, + {0xc452, "NCT6102D / NCT6106D", { + {NOLDN, NULL, + {0x07,0x10,0x11,0x13,0x14,0x1a,0x1b,0x20,0x21,0x22,0x24,0x25,0x26,0x27,0x28,0x29,0x2a,0x2f,EOT}, + {0x00,0xff,0xff,0x00,0x00,0xcc,0x03,0x10,0x61,0x7F,0x00,0x00,MISC,0x00,0x00,0xf0,0x00,MISC,EOT}}, + {0x00, "FDC", + {0x30,0x60,0x61,0x70,0x74,0xf0,0xf1,0xf2,0xf4,0xf5,EOT}, + {0x01,0x03,0xf0,0x06,0x02,0x0e,0x00,0xff,0x00,0x00,EOT}}, + {0x01, "PRT", + {0x30,0x60,0x61,0x70,0x74,0xf0,EOT}, + {0x01,0x03,0x78,0x07,0x04,0x3f,EOT}}, + {0x02, "UART A", + {0x30,0x60,0x61,0x70,0xf0,0xf2,0xf3,0xf4,0xf5,0xf6,0xf7,0xf8,EOT}, + {0x01,0x03,0xf8,0x04,0x00,0x00,0x00,0xff,0xff,0x02,0x00,0x00,EOT}}, + {0x03, "UART B", + {0x30,0x60,0x61,0x70,0xf0,0xf2,0xf3,0xf4,0xf5,0xf6,0xf7,0xf8,EOT}, + {0x01,0x02,0xf8,0x03,0x00,0x00,0x00,0xff,0xff,0x02,0x00,0x00,EOT}}, + {0x05, "Keyboard Controller (KBC)", + {0x30,0x60,0x61,0x62,0x63,0x70,0x72,0xf0,EOT}, + {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x83,EOT}}, + {0x06, "CIR", + {0x30,0x60,0x61,0x70,0xf0,0xf1,0xf2,0xf3,EOT}, + {0x00,0x00,0x00,0x00,0x08,0x09,0x32,0x00,EOT}}, + {0x07, "GPIO", + {0x30,0xe0,0xe1,0xe2,0xe3,0xe4,0xe5,0xe6,0xe7,0xe8,0xe9,0xea,0xeb,0xec,0xed,0xee,0xef,0xf0,0xf1,0xf2,0xf3,0xf4,0xf5,0xf6,0xf7,0xf8,0xf9,0xfa,0xfb,0xfc,0xfd,0xfe,0xff,EOT}, + {0xdf,0xff,0x00,0x00,0x00,0xef,0x00,0x00,0x00,0xff,0x00,0x00,0x00,0xff,0x00,0x00,0x00,0xff,0xff,0x00,0x00,0xff,0x00,0x00,0x00,0xff,0x00,0x00,0x00,0x02,0x00,0x00,0x00,EOT}}, + {0x08, "GPIO,WDT1", + {0x30,0x60,0x61,0xe0,0xe1,0xe2,0xe3,0xe4,0xe5,0xe6,0xe7,0xf0,0xf1,0xf2,EOT}, + {0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x04,0x00,EOT}}, + {0x09, "GPIO", + {0xe0,0xe1,0xe2,EOT}, + {0x00,0x00,0x00,EOT}}, + {0x0a, "ACPI", + {0xe0,0xe1,0xe2,0xe3,0xe4,0xe5,0xe6,0xe7,0xf0,0xf1,0xf2,0xf3,0xf4,0xf5,0xf6,0xf7,0xf8,0xfa,EOT}, + {0x01,0x00,0x00,0x00,0x00,0x02,0x1c,0x00,0x80,0x00,0x40,0x00,0x00,0x00,0x00,0xc0,0x00,0x00,EOT}}, + {0x0b, "Hardware Monitor, Front Panel LED", + {0x30,0x60,0x61,0x62,0x63,0x70,0xe0,0xe1,0xe2,0xf0,0xf1,0xf2,0xf3,0xf4,0xf5,0xf6,0xf7,EOT}, + {0x00,0x00,0x00,0x00,0x00,0x00,0x7f,0x7f,0xff,0x00,0x00,0x00,0x00,0x00,0x87,0x47,0x00,EOT}}, + {0x0d, "WDT2", + {0xe0,0xe1,0xe2,0xe3,0xe4,EOT}, + {0x00,0x32,0x14,0x00,0x00,EOT}}, + {0x0e, "CIR WAKE-UP", + {0x30,0x60,0x61,0x70,0xe0,0xe1,EOT}, + {0x00,0x00,0x00,0x00,0x25,0x00,EOT}}, + {0x0f, "GPIO Push-Pull or Open-drain", + {0xe0,0xe1,0xe2,0xe3,0xe4,0xe5,0xe6,0xe7,0xf0,0xf1,0xf2,EOT}, + {0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x03,0x9d,0x00,0x00,EOT}}, + {0x10, "UARTC", + {0x30,0x60,0x61,0x70,0xf0,0xf2,0xf3,0xf4,0xf5,0xf6,0xf7,0xf8,EOT}, + {0x00,0x03,0x00,0x04,0x00,0x00,0x00,0xff,0xff,0x02,0x00,0x00,EOT}}, + {0x11, "UARTD", + {0x30,0x60,0x61,0x70,0xf0,0xf2,0xf3,0xf4,0xf5,0xf6,0xf7,0xf8,EOT}, + {0x00,0x02,0x00,0x03,0x00,0x00,0x00,0xff,0xff,0x02,0x00,0x00,EOT}}, + {0x12, "UARTE", + {0x30,0x60,0x61,0x70,0xf0,0xf2,0xf3,0xf4,0xf5,0xf6,0xf7,0xf8,EOT}, + {0x00,0x03,0xe8,0x04,0x00,0x00,0x00,0xff,0xff,0x02,0x00,0x00,EOT}}, + {0x13, "UARTF", + {0x30,0x60,0x61,0x70,0xf0,0xf2,0xf3,0xf4,0xf5,0xf6,0xf7,0xf8,EOT}, + {0x00,0x02,0xe8,0x03,0x00,0x00,0x00,0xff,0xff,0x02,0x00,0x00,EOT}}, + {0x14, "PORT80 IR", + {0x30,0x60,0x61,0x70,0xe0,0xe1,0xe2,0xe3,0xe4,0xf0,0xf1,EOT}, + {0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x10,0x00,0x00,0x00,EOT}}, + {0x15, "FADING LED", + {0xe0,0xe1,0xe2,0xe3,0xe4,0xe5,0xe6,0xe7,0xe8,0xe9,EOT}, + {0x00,0x3f,0x01,0x11,0x11,0x02,0x00,0x00,0x01,0x00,EOT}}, + {0x16, "Deep Sleep", + {0x30,0xe0,0xe1,0xe2,EOT}, + {0x20,0x20,0x04,0x05,EOT}}, + {EOT}}}, {EOT} };

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coreboot-gerrit March 2016