coreboot-gerrit March 2016

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Patch merged into coreboot/master: nb/amd/mct_ddr3: Enable DIMM parity when RDIMMs installed
by gerrit＠coreboot.org 30 Mar '16

30 Mar '16

the following patch was just integrated into master: commit f961becc433bf23fc8744fdfd757f0cdb75c2c62 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Tue Mar 29 13:17:02 2016 -0500 nb/amd/mct_ddr3: Enable DIMM parity when RDIMMs installed This resolves a long-standing issue with RDIMM control word configuration failure, likely due to random parity failure. Change-Id: If8b8dc5b8b99f4c2fe29b3a133b064631e4693be Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/14184 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply(a)raptorengineeringinc.com> Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/14184 for details. -gerrit

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Patch set updated for coreboot: nb/amd/mct_ddr3: Clear early MCEs and report DRAM MCEs
by Timothy Pearson 30 Mar '16

30 Mar '16

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14191 -gerrit commit c44f9696fd23a1fc70f08f8809e502865d1671d3 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Wed Mar 30 13:07:47 2016 -0500 nb/amd/mct_ddr3: Clear early MCEs and report DRAM MCEs During power on from cold (S5) state, numerous MCEs are generated before DRAM training starts, e.g. during HT link training. Clear these MCEs before DRAM training start, and report any MCEs generated during DRAM training. Change-Id: I7d047571242e5bd041e4aac22c1ec1d7d26ef0e6 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 4 +++ src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c | 34 ++++++++++++++++++-------- 2 files changed, 28 insertions(+), 10 deletions(-) diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c index 30c511b..b32a2f7 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c @@ -8043,6 +8043,10 @@ void mct_SetDramConfigHi_D(struct MCTStatStruc *pMCTstat, Set_NB32_index_wait_DCT(pDCTstat->dev_dct, dct, index_reg, 0x0d0fe006, dword); } + /* Clear MC4 error status */ + pci_write_config32(pDCTstat->dev_nbmisc, 0x48, 0x0); + pci_write_config32(pDCTstat->dev_nbmisc, 0x4c, 0x0); + printk(BIOS_DEBUG, "%s: Done\n", __func__); } diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c index 2ebd093..07eb0bd 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c @@ -250,16 +250,30 @@ u8 ECCInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) pDCTstat = pDCTstatA + Node; if (NodePresent_D(Node)) { - /* Clear MC4 error status */ - pci_write_config32(pDCTstat->dev_nbmisc, 0x48, 0x0); - pci_write_config32(pDCTstat->dev_nbmisc, 0x4c, 0x0); - - /* Restore previous MCA error handling settings */ - if (pDCTstat->mca_config_backed_up) { - dword = Get_NB32(pDCTstat->dev_nbmisc, 0x44); - dword |= (pDCTstat->sync_flood_on_dram_err & 0x1) << 30; - dword |= (pDCTstat->sync_flood_on_any_uc_err & 0x1) << 21; - Set_NB32(pDCTstat->dev_nbmisc, 0x44, dword); + dev = pDCTstat->dev_map; + reg = 0x40 + (Node << 3); /* Dram Base Node 0 + index */ + val = Get_NB32(dev, reg); + + /* WE/RE is checked */ + if ((val & 0x3) == 0x3) { /* Node has dram populated */ + uint32_t mc4_status_high = pci_read_config32(pDCTstat->dev_nbmisc, 0x4c); + uint32_t mc4_status_low = pci_read_config32(pDCTstat->dev_nbmisc, 0x48); + if (mc4_status_high != 0) { + printk(BIOS_WARNING, "WARNING: MC4 Machine Check Exception detected!\n" + "Signature: %08x%08x\n", mc4_status_high, mc4_status_low); + } + + /* Clear MC4 error status */ + pci_write_config32(pDCTstat->dev_nbmisc, 0x48, 0x0); + pci_write_config32(pDCTstat->dev_nbmisc, 0x4c, 0x0); + + /* Restore previous MCA error handling settings */ + if (pDCTstat->mca_config_backed_up) { + dword = Get_NB32(pDCTstat->dev_nbmisc, 0x44); + dword |= (pDCTstat->sync_flood_on_dram_err & 0x1) << 30; + dword |= (pDCTstat->sync_flood_on_any_uc_err & 0x1) << 21; + Set_NB32(pDCTstat->dev_nbmisc, 0x44, dword); + } } } }

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New patch to review for coreboot: nb/amd/mct_ddr3: Clear early MCEs and report DRAM MCEs
by Timothy Pearson 30 Mar '16

30 Mar '16

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14191 -gerrit commit d0f67fcad15fd3cf5d1dc7903f397dbaed102a00 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Wed Mar 30 13:07:47 2016 -0500 nb/amd/mct_ddr3: Clear early MCEs and report DRAM MCEs During power on from cold (S5) state, numerous MCEs are generated before DRAM training starts, e.g. during HT link training. Clear these MCEs before DRAM training start, and report any MCEs generated during DRAM training. Change-Id: I7d047571242e5bd041e4aac22c1ec1d7d26ef0e6 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 4 +++ src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c | 34 ++++++++++++++++++-------- 2 files changed, 28 insertions(+), 10 deletions(-) diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c index 30c511b..b32a2f7 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c @@ -8043,6 +8043,10 @@ void mct_SetDramConfigHi_D(struct MCTStatStruc *pMCTstat, Set_NB32_index_wait_DCT(pDCTstat->dev_dct, dct, index_reg, 0x0d0fe006, dword); } + /* Clear MC4 error status */ + pci_write_config32(pDCTstat->dev_nbmisc, 0x48, 0x0); + pci_write_config32(pDCTstat->dev_nbmisc, 0x4c, 0x0); + printk(BIOS_DEBUG, "%s: Done\n", __func__); } diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c index 2ebd093..07eb0bd 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c @@ -250,16 +250,30 @@ u8 ECCInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) pDCTstat = pDCTstatA + Node; if (NodePresent_D(Node)) { - /* Clear MC4 error status */ - pci_write_config32(pDCTstat->dev_nbmisc, 0x48, 0x0); - pci_write_config32(pDCTstat->dev_nbmisc, 0x4c, 0x0); - - /* Restore previous MCA error handling settings */ - if (pDCTstat->mca_config_backed_up) { - dword = Get_NB32(pDCTstat->dev_nbmisc, 0x44); - dword |= (pDCTstat->sync_flood_on_dram_err & 0x1) << 30; - dword |= (pDCTstat->sync_flood_on_any_uc_err & 0x1) << 21; - Set_NB32(pDCTstat->dev_nbmisc, 0x44, dword); + dev = pDCTstat->dev_map; + reg = 0x40 + (Node << 3); /* Dram Base Node 0 + index */ + val = Get_NB32(dev, reg); + + /* WE/RE is checked */ + if ((val & 0x3) == 0x3) { /* Node has dram populated */ + uint32_t mc4_status_high = pci_read_config32(pDCTstat->dev_nbmisc, 0x4c); + uint32_t mc4_status_low = pci_read_config32(pDCTstat->dev_nbmisc, 0x48); + if (mc4_status_high != 0) { + printk(BIOS_WARNING, "WARNING: MC4 Machine Check Exception detected!\n" + "Signature: %08x%08x\n", mc4_status_high, mc4_status_low); + } + + /* Clear MC4 error status */ + pci_write_config32(pDCTstat->dev_nbmisc, 0x48, 0x0); + pci_write_config32(pDCTstat->dev_nbmisc, 0x4c, 0x0); + + /* Restore previous MCA error handling settings */ + if (pDCTstat->mca_config_backed_up) { + dword = Get_NB32(pDCTstat->dev_nbmisc, 0x44); + dword |= (pDCTstat->sync_flood_on_dram_err & 0x1) << 30; + dword |= (pDCTstat->sync_flood_on_any_uc_err & 0x1) << 21; + Set_NB32(pDCTstat->dev_nbmisc, 0x44, dword); + } } } }

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New patch to review for coreboot: do not submit: jenkins test 2
by Martin Roth 30 Mar '16

30 Mar '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14190 -gerrit commit ca2ce7c62185af53ae139cb6b924703da06a4945 Author: Martin Roth <martinroth(a)google.com> Date: Wed Mar 30 10:53:35 2016 -0600 do not submit: jenkins test 2 Change-Id: I3e5fb3bd1bbb4b9ac0ec40ef2720cd485108477f Signed-off-by: Martin Roth <martinroth(a)google.com> --- src/mainboard/google/storm/romstage.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mainboard/google/storm/romstage.c b/src/mainboard/google/storm/romstage.c index efebc95..9b50072 100644 --- a/src/mainboard/google/storm/romstage.c +++ b/src/mainboard/google/storm/romstage.c @@ -23,6 +23,7 @@ void main(void) { THIS WILL BREAK THE BUILDS + SO WILL THIS. console_init(); initialize_dram();

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Patch set updated for coreboot: intel/gma: Fix VBT generation
by Patrick Rudolph 30 Mar '16

30 Mar '16

Patrick Rudolph (siro(a)das-labor.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14188 -gerrit commit a08650a1919918655013aac9a7584624b0b194c0 Author: Patrick Rudolph <siro(a)das-labor.org> Date: Wed Mar 30 17:59:09 2016 +0200 intel/gma: Fix VBT generation The log shows the following error on systems that use the native gfx init. The error isn't shown using the VBIOS blob: GET_VBIOS: aa55 8086 0 3 0 VBIOS not found. Don't shift the class-code, as it's already shifted by the PCI layer. Not tested using native gfx init. Change-Id: I69018940dd51966b45774e0576a1380f90716dce Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- src/drivers/intel/gma/vbt.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/drivers/intel/gma/vbt.c b/src/drivers/intel/gma/vbt.c index 1993793..e768402 100644 --- a/src/drivers/intel/gma/vbt.c +++ b/src/drivers/intel/gma/vbt.c @@ -93,9 +93,9 @@ generate_fake_intel_oprom(const struct i915_gpu_controller_info *conf, pcir->device = dev->device; pcir->length = sizeof(*pcir); pcir->revision = dev->class; - pcir->classcode[0] = dev->class >> 8; - pcir->classcode[1] = dev->class >> 16; - pcir->classcode[2] = dev->class >> 24; + pcir->classcode[0] = dev->class; + pcir->classcode[1] = dev->class >> 8; + pcir->classcode[2] = dev->class >> 16; pcir->indicator = 0x80; vbt_size = generate_vbt (conf, (void *)(PCI_VGA_RAM_IMAGE_START + 0x80), idstr);

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New patch to review for coreboot: do not submit - jenkins test
by Martin Roth 30 Mar '16

30 Mar '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14189 -gerrit commit 6d317b8a5150fa5e3ad766b98788f871912c1037 Author: Martin Roth <martinroth(a)google.com> Date: Wed Mar 30 10:23:57 2016 -0600 do not submit - jenkins test Change-Id: I57346486d1b543fae293655950c6a29da11b7032 Signed-off-by: Martin Roth <martinroth(a)google.com> --- src/mainboard/google/storm/romstage.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/mainboard/google/storm/romstage.c b/src/mainboard/google/storm/romstage.c index c1b8654..efebc95 100644 --- a/src/mainboard/google/storm/romstage.c +++ b/src/mainboard/google/storm/romstage.c @@ -22,6 +22,8 @@ void main(void) { + THIS WILL BREAK THE BUILDS + console_init(); initialize_dram();

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New patch to review for coreboot: intel/gma: Fix vbt generation
by Patrick Rudolph 30 Mar '16

30 Mar '16

Patrick Rudolph (siro(a)das-labor.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14188 -gerrit commit 98924c613d729b89073c5bcd59b3c452c59164b8 Author: Patrick Rudolph <siro(a)das-labor.org> Date: Wed Mar 30 17:59:09 2016 +0200 intel/gma: Fix vbt generation The log shows the following error on systems that use the native gfx init. The error isn't show using VBIOS blob: GET_VBIOS: aa55 8086 0 3 0 VBIOS not found. Don't shift the class-code, as it's already shifted by the PCI layer. Not tested using native gfx init. Change-Id: I69018940dd51966b45774e0576a1380f90716dce Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- src/drivers/intel/gma/vbt.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/drivers/intel/gma/vbt.c b/src/drivers/intel/gma/vbt.c index 1993793..e768402 100644 --- a/src/drivers/intel/gma/vbt.c +++ b/src/drivers/intel/gma/vbt.c @@ -93,9 +93,9 @@ generate_fake_intel_oprom(const struct i915_gpu_controller_info *conf, pcir->device = dev->device; pcir->length = sizeof(*pcir); pcir->revision = dev->class; - pcir->classcode[0] = dev->class >> 8; - pcir->classcode[1] = dev->class >> 16; - pcir->classcode[2] = dev->class >> 24; + pcir->classcode[0] = dev->class; + pcir->classcode[1] = dev->class >> 8; + pcir->classcode[2] = dev->class >> 16; pcir->indicator = 0x80; vbt_size = generate_vbt (conf, (void *)(PCI_VGA_RAM_IMAGE_START + 0x80), idstr);

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Patch merged into coreboot/master: northbridge/amd/amdfam10: Add family15h model10h-1fh (Trinity)
by gerrit＠coreboot.org 30 Mar '16

30 Mar '16

the following patch was just integrated into master: commit 33aaa921f7538761816900652e186b610d2ab35b Author: Damien Zammit <damien(a)zamaudio.com> Date: Wed Feb 10 14:01:36 2016 +1100 northbridge/amd/amdfam10: Add family15h model10h-1fh (Trinity) Change-Id: I96d695ed10176276116fcf3a2b77605fb3f2d5db Signed-off-by: Damien Zammit <damien(a)zamaudio.com> Reviewed-on: https://review.coreboot.org/13710 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply(a)raptorengineeringinc.com> Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/13710 for details. -gerrit

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Patch merged into coreboot/master: nb/intel/sandybridge/raminit: move ram training into seperate function
by gerrit＠coreboot.org 30 Mar '16

30 Mar '16

the following patch was just integrated into master: commit 27e085a8eea7f34ed4987b83c513d2f1818b33a1 Author: Patrick Rudolph <siro(a)das-labor.org> Date: Sat Mar 26 10:59:02 2016 +0100 nb/intel/sandybridge/raminit: move ram training into seperate function In order to add a fallback mechanism, move the ram training code into a new function. This function will be called multiple times and must return error or success to the calling function. Change-Id: I5ee1b3a528290d8252d236b9152b81291736958a Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> Reviewed-on: https://review.coreboot.org/14169 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/14169 for details. -gerrit

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Patch set updated for coreboot: ec/lenovo/h8: do not reset volume on s3 wakeup
by Christopher Spinrath 30 Mar '16

30 Mar '16

Christopher Spinrath (christopher.spinrath(a)rwth-aachen.de) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14183 -gerrit commit 2f85bbb47aedff1b35494c29493c5b3ac92d3c0d Author: Christopher Spinrath <christopher.spinrath(a)rwth-aachen.de> Date: Thu Mar 24 20:45:13 2016 +0100 ec/lenovo/h8: do not reset volume on s3 wakeup On s3 wakeup h8_enable is called which resets the (audio) volume. But the volume should be the same as before the s3 state. In particular, userland programs (e.g. pulseaudio) may be out of sync, if the volume can be changed by hardware buttons also emitting acpi events. Hence, do not reset the volume on s3 wakeup. Tested on a Lenovo ThinkPad X220. Change-Id: I2af08dea1a3f14a40734d67d372e845cc18c5e09 Signed-off-by: Christopher Spinrath <christopher.spinrath(a)rwth-aachen.de> --- src/ec/lenovo/h8/h8.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/ec/lenovo/h8/h8.c b/src/ec/lenovo/h8/h8.c index 4f882c1..943bdd4 100644 --- a/src/ec/lenovo/h8/h8.c +++ b/src/ec/lenovo/h8/h8.c @@ -13,6 +13,7 @@ * GNU General Public License for more details. */ +#include <arch/acpi.h> #include <arch/io.h> #include <console/console.h> #include <device/device.h> @@ -258,7 +259,7 @@ static void h8_enable(struct device *dev) h8_trackpoint_enable(1); h8_usb_power_enable(1); - if (get_option(&val, "volume") == CB_SUCCESS) + if (get_option(&val, "volume") == CB_SUCCESS && !acpi_is_wakeup_s3()) ec_write(H8_VOLUME_CONTROL, val); if (get_option(&val, "bluetooth") != CB_SUCCESS)

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coreboot-gerrit March 2016