March 2016 - coreboot-gerrit - mail.coreboot.org

Patch merged into coreboot/master: lint: Update board status script to look at the whole tree
by gerrit＠coreboot.org March 29, 2016

March 29, 2016

the following patch was just integrated into master: commit 92658db3ca00b230a7effd5408d0492a44f9b3f3 Author: Martin Roth <martinroth(a)google.com> Date: Wed Mar 16 15:58:23 2016 -0600 lint: Update board status script to look at the whole tree The board status script wasn't checking the entire tree to make sure that all boards had board_info.txt files. Also it would only print out the first issue that was found. Change-Id: I5f2fa9e564c805c6dbee7a35cab80c1c342567a5 Signed-off-by: Martin Roth <martinroth(a)google.com> Reviewed-on: https://review.coreboot.org/14118 Tested-by: build bot (Jenkins) Reviewed-by: Vladimir Serbinenko <phcoder(a)gmail.com> See https://review.coreboot.org/14118 for details. -gerrit

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Patch set updated for coreboot: nb/intel/sandybridge/raminit: move ram training into seperate function
by Martin Roth March 29, 2016

March 29, 2016

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14169 -gerrit commit d199bb713e9448d82a6b40166ac55781b1126935 Author: Patrick Rudolph <siro(a)das-labor.org> Date: Sat Mar 26 10:59:02 2016 +0100 nb/intel/sandybridge/raminit: move ram training into seperate function In order to add a fallback mechanism, move the ram training code into a new function. This function will be called multiple times and must return error or success to the calling function. Change-Id: I5ee1b3a528290d8252d236b9152b81291736958a Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- src/northbridge/intel/sandybridge/raminit.c | 172 +++++++++++++++------------- 1 file changed, 90 insertions(+), 82 deletions(-) diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index 7d946af..dbec9fb 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -3946,88 +3946,32 @@ static void restore_timings(ramctr_timing * ctrl) write32(DEFAULT_MCHBAR + 0x4ea8, 0); } -void init_dram_ddr3(spd_raw_data * spds, int mobile, int min_tck, - int s3resume) +static int try_init_dram_ddr3(ramctr_timing *ctrl, int s3resume, + int me_uma_size) { - int me_uma_size; - int cbmem_was_inited; - ramctr_timing ctrl; - - MCHBAR32(0x5f00) |= 1; - - report_platform_info(); - - /* Wait for ME to be ready */ - intel_early_me_init(); - me_uma_size = intel_early_me_uma_size(); - - printk(BIOS_DEBUG, "Starting native Platform init\n"); - - u32 reg_5d10; - - wait_txt_clear(); - - wrmsr(0x000002e6, (msr_t) { .lo = 0, .hi = 0 }); - - reg_5d10 = read32(DEFAULT_MCHBAR + 0x5d10); // !!! = 0x00000000 - if ((pcie_read_config16(SOUTHBRIDGE, 0xa2) & 0xa0) == 0x20 /* 0x0004 */ - && reg_5d10 && !s3resume) { - write32(DEFAULT_MCHBAR + 0x5d10, 0); - /* Need reset. */ - outb(0x6, 0xcf9); - - halt(); - } - - memset(&ctrl, 0, sizeof (ctrl)); - - early_pch_init_native(); - early_thermal_init(); - - ctrl.mobile = mobile; - ctrl.tCK = min_tck; - - /* FIXME: for non-S3 we should be able to use timing caching with - proper verification. Right now we use timings only for S3 case. - */ - if (s3resume) { - struct mrc_data_container *mrc_cache; - - mrc_cache = find_current_mrc_cache(); - if (!mrc_cache || mrc_cache->mrc_data_size < sizeof (ctrl)) { - /* Failed S3 resume, reset to come up cleanly */ - outb(0x6, 0xcf9); - halt(); - } - memcpy(&ctrl, mrc_cache->mrc_data, sizeof (ctrl)); - } - if (!s3resume) { - /* Get DDR3 SPD data */ - dram_find_spds_ddr3(spds, &ctrl); - /* Find fastest common supported parameters */ - dram_find_common_params(&ctrl); + dram_find_common_params(ctrl); - dram_dimm_mapping(&ctrl); + dram_dimm_mapping(ctrl); } /* Set MCU frequency */ - dram_freq(&ctrl); + dram_freq(ctrl); if (!s3resume) { /* Calculate timings */ - dram_timing(&ctrl); + dram_timing(ctrl); } /* Set version register */ MCHBAR32(0x5034) = 0xC04EB002; /* Enable crossover */ - dram_xover(&ctrl); + dram_xover(ctrl); /* Set timing and refresh registers */ - dram_timing_regs(&ctrl); + dram_timing_regs(ctrl); /* Power mode preset */ MCHBAR32(0x4e80) = 0x5500; @@ -4042,64 +3986,128 @@ void init_dram_ddr3(spd_raw_data * spds, int mobile, int min_tck, MCHBAR32(0x5030) &= ~0x20; /* Set MAD-DIMM registers */ - dram_dimm_set_mapping(&ctrl); + dram_dimm_set_mapping(ctrl); printk(BIOS_DEBUG, "Done dimm mapping\n"); /* Zone config */ - dram_zones(&ctrl, 1); + dram_zones(ctrl, 1); /* Set memory map */ - dram_memorymap(&ctrl, me_uma_size); + dram_memorymap(ctrl, me_uma_size); printk(BIOS_DEBUG, "Done memory map\n"); /* Set IO registers */ - dram_ioregs(&ctrl); + dram_ioregs(ctrl); printk(BIOS_DEBUG, "Done io registers\n"); udelay(1); if (s3resume) { - restore_timings(&ctrl); + restore_timings(ctrl); } else { /* Do jedec ddr3 reset sequence */ - dram_jedecreset(&ctrl); + dram_jedecreset(ctrl); printk(BIOS_DEBUG, "Done jedec reset\n"); /* MRS commands */ - dram_mrscommands(&ctrl); + dram_mrscommands(ctrl); printk(BIOS_DEBUG, "Done MRS commands\n"); /* Prepare for memory training */ - prepare_training(&ctrl); + prepare_training(ctrl); - read_training(&ctrl); - write_training(&ctrl); + read_training(ctrl); + write_training(ctrl); printram("CP5a\n"); - discover_edges(&ctrl); + discover_edges(ctrl); printram("CP5b\n"); - command_training(&ctrl); + command_training(ctrl); printram("CP5c\n"); - discover_edges_write(&ctrl); + discover_edges_write(ctrl); - discover_timC_write(&ctrl); + discover_timC_write(ctrl); - normalize_training(&ctrl); + normalize_training(ctrl); } - set_4008c(&ctrl); + set_4008c(ctrl); - write_controller_mr(&ctrl); + write_controller_mr(ctrl); if (!s3resume) { - channel_test(&ctrl); + channel_test(ctrl); + } + + return 0; +} + +void init_dram_ddr3(spd_raw_data *spds, int mobile, int min_tck, + int s3resume) +{ + int me_uma_size; + int cbmem_was_inited; + ramctr_timing ctrl; + + MCHBAR32(0x5f00) |= 1; + + report_platform_info(); + + /* Wait for ME to be ready */ + intel_early_me_init(); + me_uma_size = intel_early_me_uma_size(); + + printk(BIOS_DEBUG, "Starting native Platform init\n"); + + u32 reg_5d10; + + wait_txt_clear(); + + wrmsr(0x000002e6, (msr_t) { .lo = 0, .hi = 0 }); + + reg_5d10 = read32(DEFAULT_MCHBAR + 0x5d10); // !!! = 0x00000000 + if ((pcie_read_config16(SOUTHBRIDGE, 0xa2) & 0xa0) == 0x20 /* 0x0004 */ + && reg_5d10 && !s3resume) { + write32(DEFAULT_MCHBAR + 0x5d10, 0); + /* Need reset. */ + outb(0x6, 0xcf9); + + halt(); + } + + memset(&ctrl, 0, sizeof (ctrl)); + + early_pch_init_native(); + early_thermal_init(); + + ctrl.mobile = mobile; + ctrl.tCK = min_tck; + + /* FIXME: for non-S3 we should be able to use timing caching with + proper verification. Right now we use timings only for S3 case. + */ + if (s3resume) { + struct mrc_data_container *mrc_cache; + + mrc_cache = find_current_mrc_cache(); + if (!mrc_cache || (mrc_cache->mrc_data_size < sizeof(ctrl))) { + /* Failed S3 resume, reset to come up cleanly */ + outb(0x6, 0xcf9); + halt(); + } + memcpy(&ctrl, mrc_cache->mrc_data, sizeof(ctrl)); + } else { + /* Get DDR3 SPD data */ + dram_find_spds_ddr3(spds, &ctrl); } + try_init_dram_ddr3(&ctrl, s3resume, me_uma_size); + /* FIXME: should be hardware revision-dependent. */ write32(DEFAULT_MCHBAR + 0x5024, 0x00a030ce);

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Patch merged into coreboot/master: nb/intel/sandybridge/raminit: move dimm_info into ramctr_timing
by gerrit＠coreboot.org March 29, 2016

March 29, 2016

the following patch was just integrated into master: commit 735eccea4af0395bf19bc1c54bd765ec2b474f41 Author: Patrick Rudolph <siro(a)das-labor.org> Date: Sat Mar 26 10:42:27 2016 +0100 nb/intel/sandybridge/raminit: move dimm_info into ramctr_timing It's required to store the dimm_info in ramctr_timing as only ramctr_timing is written to mrc cache. Allows to fill SMBIOS type 17 if mrc cache is used. Change-Id: I7634b05069df307d471938d9854997a018de81b3 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> Reviewed-on: https://review.coreboot.org/14168 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/14168 for details. -gerrit

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Patch set updated for coreboot: lint: Update board status script to look at the whole tree
by Martin Roth March 29, 2016

March 29, 2016

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14118 -gerrit commit 7e4f4bbf326d34f5d6e41e060cbfd633f713ca0a Author: Martin Roth <martinroth(a)google.com> Date: Wed Mar 16 15:58:23 2016 -0600 lint: Update board status script to look at the whole tree The board status script wasn't checking the entire tree to make sure that all boards had board_info.txt files. Also it would only print out the first issue that was found. Change-Id: I5f2fa9e564c805c6dbee7a35cab80c1c342567a5 Signed-off-by: Martin Roth <martinroth(a)google.com> --- util/lint/lint-stable-005-board-status | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/util/lint/lint-stable-005-board-status b/util/lint/lint-stable-005-board-status index 61813ea..952a9b5 100755 --- a/util/lint/lint-stable-005-board-status +++ b/util/lint/lint-stable-005-board-status @@ -16,11 +16,11 @@ # DESCR: Check that every board has a meaningful board_info.txt LC_ALL=C export LC_ALL -for mobodir in $(git diff --diff-filter ACMR --name-only src/mainboard | sed -n 's,^$src/mainboard/[^/]*/[^/]*$/.*$,\1,p'|sort|uniq); do +for mobodir in $(git ls-files src/mainboard | sed -n 's,^$src/mainboard/[^/]*/[^/]*$/.*$,\1,p'|sort|uniq); do board_info="$mobodir/board_info.txt" if ! [ -f "$board_info" ]; then echo "No $board_info found" - exit 1 + continue fi category="$(sed -n 's#^Category: $.*$$#\1#p' < "$board_info")" case "$category" in @@ -28,11 +28,11 @@ for mobodir in $(git diff --diff-filter ACMR --name-only src/mainboard | sed -n ;; "") echo "$board_info doesn't contain 'Category' tag" - exit 1 + continue ;; *) echo "$board_info specifies unknown category '$category'" - exit 1 + continue ;; esac done

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Patch merged into coreboot/master: ipq806x/storm: Return NULL for cbmem_top if DRAM is not initialized
by gerrit＠coreboot.org March 29, 2016

March 29, 2016

the following patch was just integrated into master: commit cf9e0bc6a62b38a3046fa898b04720ae2572c116 Author: Furquan Shaikh <furquan(a)google.com> Date: Mon Mar 28 13:29:33 2016 -0700 ipq806x/storm: Return NULL for cbmem_top if DRAM is not initialized DRAM initialization on storm requires ipq blobs to be loaded from cbfs. vboot_locator first checks cbmem_find to see if cbmem is initialized and contains selected region info, else it falls back to vboot work buffer. Since cbmem_find calls into cbmem_top to identify the location of cbmem area, board/chipset is expected to return NULL until the backing store is ready, which in this case until DRAM is initialized in romstage, return NULL for cbmem_top. Change-Id: I1880ce61dcfdabaa527d7a6dcc3482dfe5d5fd17 Signed-off-by: Furquan Shaikh <furquan(a)google.com> Reviewed-on: https://review.coreboot.org/14182 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Tested-by: build bot (Jenkins) See https://review.coreboot.org/14182 for details. -gerrit

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New patch to review for coreboot: nb/amd/mct_ddr3: Enable DIMM parity when RDIMMs installed
by Timothy Pearson March 29, 2016

March 29, 2016

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14184 -gerrit commit f8e0c0a973010b978768f7d8e63cd7ccafa7ed0a Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Tue Mar 29 13:17:02 2016 -0500 nb/amd/mct_ddr3: Enable DIMM parity when RDIMMs installed This resolves a long-standing issue with RDIMM control word configuration failure, likely due to random parity failure. Change-Id: If8b8dc5b8b99f4c2fe29b3a133b064631e4693be Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c index 4d9bc58..32964bd 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c @@ -5124,9 +5124,7 @@ static u8 AutoConfig_D(struct MCTStatStruc *pMCTstat, if (Status & (1 << SB_Registered)) { /* Registered DIMMs */ - if (!is_fam15h()) { - DramConfigLo |= 1 << ParEn; - } + DramConfigLo |= 1 << ParEn; } else { /* Unbuffered DIMMs */ DramConfigLo |= 1 << UnBuffDimm;

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Patch merged into coreboot/master: cbmem: Add comment for cbmem_top returning NULL if backing store is not ready
by gerrit＠coreboot.org March 29, 2016

March 29, 2016

the following patch was just integrated into master: commit 6f009dc485e8bfb0a9f316c1e831938cf46b0c3a Author: Furquan Shaikh <furquan(a)google.com> Date: Mon Mar 28 13:23:13 2016 -0700 cbmem: Add comment for cbmem_top returning NULL if backing store is not ready Board or chipset needs to ensure that cbmem backing store is ready when returning the cbmem top address. cbmem infrastructure has no support for checking the validity of the backing store/address. E.g.: If romstage handles cbmem coming online, chipset or board need to ensure that call to cbmem_top in romstage returns NULL if the backing store is not yet initialized. Add a comment to ensure that developers know this requirement while implementing cbmem_top for future chipsets/boards. Change-Id: I0086b8e528f65190b764a84365cf9bf970b69c3f Signed-off-by: Furquan Shaikh <furquan(a)google.com> Reviewed-on: https://review.coreboot.org/14181 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h(a)gmx.de> Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See https://review.coreboot.org/14181 for details. -gerrit

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Patch set updated for coreboot: ipq806x/storm: Return NULL for cbmem_top if DRAM is not initialized
by Furquan Shaikh March 29, 2016

March 29, 2016

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14182 -gerrit commit 745fb0135b903dd7f031e185e719880c91974a69 Author: Furquan Shaikh <furquan(a)google.com> Date: Mon Mar 28 13:29:33 2016 -0700 ipq806x/storm: Return NULL for cbmem_top if DRAM is not initialized DRAM initialization on storm requires ipq blobs to be loaded from cbfs. vboot_locator first checks cbmem_find to see if cbmem is initialized and contains selected region info, else it falls back to vboot work buffer. Since cbmem_find calls into cbmem_top to identify the location of cbmem area, board/chipset is expected to return NULL until the backing store is ready, which in this case until DRAM is initialized in romstage, return NULL for cbmem_top. Change-Id: I1880ce61dcfdabaa527d7a6dcc3482dfe5d5fd17 Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- src/mainboard/google/storm/mmu.c | 2 ++ src/soc/qualcomm/ipq806x/cbmem.c | 17 +++++++++++++++++ src/soc/qualcomm/ipq806x/include/soc/soc_services.h | 3 +++ 3 files changed, 22 insertions(+) diff --git a/src/mainboard/google/storm/mmu.c b/src/mainboard/google/storm/mmu.c index 4d2e9a0..fcea8e2 100644 --- a/src/mainboard/google/storm/mmu.c +++ b/src/mainboard/google/storm/mmu.c @@ -34,6 +34,8 @@ void setup_dram_mappings(enum dram_state dram) mmu_config_range(DRAM_START, DRAM_SIZE, DCACHE_WRITEBACK); /* Map DMA memory */ mmu_config_range(DMA_START, DMA_SIZE, DCACHE_OFF); + /* Mark cbmem backing store as ready. */ + ipq_cbmem_backing_store_ready(); } else { mmu_disable_range(DRAM_START, DRAM_SIZE); /* Map DMA memory */ diff --git a/src/soc/qualcomm/ipq806x/cbmem.c b/src/soc/qualcomm/ipq806x/cbmem.c index 7aff231..9674db6 100644 --- a/src/soc/qualcomm/ipq806x/cbmem.c +++ b/src/soc/qualcomm/ipq806x/cbmem.c @@ -16,7 +16,24 @@ #include <cbmem.h> #include <soc/soc_services.h> +static int cbmem_backing_store_ready; + +void ipq_cbmem_backing_store_ready(void) +{ + cbmem_backing_store_ready = 1; +} + void *cbmem_top(void) { + /* + * In romstage, make sure that cbmem backing store is ready before + * returning the pointer to cbmem top. Otherwise, it could lead to + * issues with components that utilize cbmem in romstage + * (e.g. vboot_locator for loading ipq blobs before DRAM is + * initialized). + */ + if (ENV_ROMSTAGE && (cbmem_backing_store_ready == 0)) + return NULL; + return _memlayout_cbmem_top; } diff --git a/src/soc/qualcomm/ipq806x/include/soc/soc_services.h b/src/soc/qualcomm/ipq806x/include/soc/soc_services.h index 7006b82..e7a6d68 100644 --- a/src/soc/qualcomm/ipq806x/include/soc/soc_services.h +++ b/src/soc/qualcomm/ipq806x/include/soc/soc_services.h @@ -32,4 +32,7 @@ int tz_init_wrapper(int, int, void *); /* Load RPM code into memory and trigger its execution. */ void start_rpm(void); +/* Mark cbmem backing store as ready. */ +void ipq_cbmem_backing_store_ready(void); + #endif

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New patch to review for coreboot: ec/lenovo/h8: do not reset volume on s3 wakeup
by Christopher Spinrath March 29, 2016

March 29, 2016

Christopher Spinrath (christopher.spinrath(a)rwth-aachen.de) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14183 -gerrit commit 1a4973c23ed94d6ef06df95d95752bf7b8b79bbc Author: Christopher Spinrath <christopher.spinrath(a)rwth-aachen.de> Date: Thu Mar 24 20:45:13 2016 +0100 ec/lenovo/h8: do not reset volume on s3 wakeup On s3 wakeup h8_enable is called which resets the (audio) volume. But the volume should be same as before the s3 state. In particular, userland programs (i.e. pulseaudio) may be out of sync, if the volume can be changed by hardware buttons also emitting acpi events. Hence, do not reset the volume on s3 wakeup. Tested on a Lenovo ThinkPad X220. Change-Id: I2af08dea1a3f14a40734d67d372e845cc18c5e09 Signed-off-by: Christopher Spinrath <christopher.spinrath(a)rwth-aachen.de> --- src/ec/lenovo/h8/h8.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/ec/lenovo/h8/h8.c b/src/ec/lenovo/h8/h8.c index 4f882c1..943bdd4 100644 --- a/src/ec/lenovo/h8/h8.c +++ b/src/ec/lenovo/h8/h8.c @@ -13,6 +13,7 @@ * GNU General Public License for more details. */ +#include <arch/acpi.h> #include <arch/io.h> #include <console/console.h> #include <device/device.h> @@ -258,7 +259,7 @@ static void h8_enable(struct device *dev) h8_trackpoint_enable(1); h8_usb_power_enable(1); - if (get_option(&val, "volume") == CB_SUCCESS) + if (get_option(&val, "volume") == CB_SUCCESS && !acpi_is_wakeup_s3()) ec_write(H8_VOLUME_CONTROL, val); if (get_option(&val, "bluetooth") != CB_SUCCESS)

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Patch set updated for coreboot: ipq806x/storm: Return NULL for cbmem_top if DRAM is not initialized
by Furquan Shaikh March 28, 2016

March 28, 2016

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14182 -gerrit commit 170df3445552b21110dae322b322493788f26bb3 Author: Furquan Shaikh <furquan(a)google.com> Date: Mon Mar 28 13:29:33 2016 -0700 ipq806x/storm: Return NULL for cbmem_top if DRAM is not initialized DRAM initialization on storm requires ipq blobs to be loaded from cbfs. vboot_locator first checks cbmem_find to see if cbmem is initialized and contains selected region info, else it falls back to vboot work buffer. Since cbmem_find calls into cbmem_top to identify the location of cbmem area, board/chipset is expected to return NULL until the backing store is ready, which in this case until DRAM is initialized in romstage, return NULL for cbmem_top. Change-Id: I1880ce61dcfdabaa527d7a6dcc3482dfe5d5fd17 Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- src/mainboard/google/storm/mmu.c | 2 ++ src/soc/qualcomm/ipq806x/cbmem.c | 16 ++++++++++++++++ src/soc/qualcomm/ipq806x/include/soc/soc_services.h | 3 +++ 3 files changed, 21 insertions(+) diff --git a/src/mainboard/google/storm/mmu.c b/src/mainboard/google/storm/mmu.c index 4d2e9a0..fcea8e2 100644 --- a/src/mainboard/google/storm/mmu.c +++ b/src/mainboard/google/storm/mmu.c @@ -34,6 +34,8 @@ void setup_dram_mappings(enum dram_state dram) mmu_config_range(DRAM_START, DRAM_SIZE, DCACHE_WRITEBACK); /* Map DMA memory */ mmu_config_range(DMA_START, DMA_SIZE, DCACHE_OFF); + /* Mark cbmem backing store as ready. */ + ipq_cbmem_backing_store_ready(); } else { mmu_disable_range(DRAM_START, DRAM_SIZE); /* Map DMA memory */ diff --git a/src/soc/qualcomm/ipq806x/cbmem.c b/src/soc/qualcomm/ipq806x/cbmem.c index 7aff231..05325cc 100644 --- a/src/soc/qualcomm/ipq806x/cbmem.c +++ b/src/soc/qualcomm/ipq806x/cbmem.c @@ -16,7 +16,23 @@ #include <cbmem.h> #include <soc/soc_services.h> +static int cbmem_backing_store_ready; + +void ipq_cbmem_backing_store_ready(void) +{ + cbmem_backing_store_ready = 1; +} + void *cbmem_top(void) { + /* + * In romstage, make sure that cbmem backing store is ready before + * returning pointer to cbmem top. Otherwise, it could lead to issues + * with components that utilize cbmem in romstage (e.g. vboot_locator + * for loading ipq blobs before DRAM is initialized). + */ + if (ENV_ROMSTAGE && (cbmem_backing_store_ready == 0)) + return NULL; + return _memlayout_cbmem_top; } diff --git a/src/soc/qualcomm/ipq806x/include/soc/soc_services.h b/src/soc/qualcomm/ipq806x/include/soc/soc_services.h index 7006b82..e7a6d68 100644 --- a/src/soc/qualcomm/ipq806x/include/soc/soc_services.h +++ b/src/soc/qualcomm/ipq806x/include/soc/soc_services.h @@ -32,4 +32,7 @@ int tz_init_wrapper(int, int, void *); /* Load RPM code into memory and trigger its execution. */ void start_rpm(void); +/* Mark cbmem backing store as ready. */ +void ipq_cbmem_backing_store_ready(void); + #endif

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