Patch merged into coreboot/master: nb/amd/mct_ddr3: Disable MCE framework during DRAM training

the following patch was just integrated into master:
commit c094d9961144871c472698c41ce634e58abb6a32
Author: Timothy Pearson 
Date:   Tue Mar 29 20:37:36 2016 -0500

nb/amd/mct_ddr3: Disable MCE framework during DRAM training

On Family 15h processors, with certain RDIMMs, MCEs are generated
    as a normal part of DCT startup / DRAM training.  Disable sync
    flood on parity or UC data error until ECC has been enabled.

Change-Id: Ife54751ff127ffd59baaad35d3fea14ea01ef505
    Signed-off-by: Timothy Pearson 
    Reviewed-on: https://review.coreboot.org/14186
    Tested-by: Raptor Engineering Automated Test Stand 
    Reviewed-by: Paul Menzel 
    Tested-by: build bot (Jenkins)
    Reviewed-by: Martin Roth

See https://review.coreboot.org/14186 for details.

-gerrit