coreboot-gerrit March 2016

coreboot-gerrit@coreboot.org

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1119 discussions

Patch merged into coreboot/master: google/oak: Move external buck initialization to coreboot
by gerrit＠coreboot.org 21 Mar '16

21 Mar '16

the following patch was just integrated into master: commit 316ded82f5f9b51333e96cd1d002e60a6c8ce8c7 Author: henryc.chen <henryc.chen(a)mediatek.com> Date: Fri Mar 11 14:55:30 2016 +0800 google/oak: Move external buck initialization to coreboot Remove the code which is passing parameters to ARMTF and move external buck initilizaton from ARMTF to coreboot. BRANCH=none BUG=none TEST=verified on Oak rev4/rev5 Change-Id: I4f4b30acbee9b42a202b326f2fe4517cb4b9d83c Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 37bec54b4d8a3bce38878e292e4821da3959026a Original-Change-Id: Ib81709812a064f6daf13c9b4d6525f1858c81393 Original-Signed-off-by: henryc.chen <henryc.chen(a)mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/332343 Original-Commit-Ready: Yidi Lin <yidi.lin(a)mediatek.com> Original-Tested-by: Yidi Lin <yidi.lin(a)mediatek.com> Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> Reviewed-on: https://review.coreboot.org/14123 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See https://review.coreboot.org/14123 for details. -gerrit

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Patch merged into coreboot/master: mediatek/mt8173: Add da9212 driver
by gerrit＠coreboot.org 21 Mar '16

21 Mar '16

the following patch was just integrated into master: commit 0bb292e384ba540f9b0c4901f75a9bf2db1413ec Author: henryc.chen <henryc.chen(a)mediatek.com> Date: Wed Mar 2 15:51:44 2016 +0800 mediatek/mt8173: Add da9212 driver Add secondary PMIC for external buck control on Oak rev0/1/2/5 BRANCH=none BUG=none TEST=verified on Oak rev4/rev5 Change-Id: Ia000b0c7d61e8396856656247f9627e33b21b19b Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 241508e7d781fac8ee085ee81962043dd654c52d Original-Change-Id: I6c75e2462363a5523bf1ebb03af7a36740293624 Original-Signed-off-by: henryc.chen <henryc.chen(a)mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/332342 Original-Commit-Ready: Yidi Lin <yidi.lin(a)mediatek.com> Original-Tested-by: Yidi Lin <yidi.lin(a)mediatek.com> Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> Reviewed-on: https://review.coreboot.org/14122 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See https://review.coreboot.org/14122 for details. -gerrit

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Patch merged into coreboot/master: mediatek/mt8173: Add mt6311 driver
by gerrit＠coreboot.org 21 Mar '16

21 Mar '16

the following patch was just integrated into master: commit 7c54d2a760c278412c0b2002ddcb555413f96231 Author: henryc.chen <henryc.chen(a)mediatek.com> Date: Wed Mar 2 15:49:52 2016 +0800 mediatek/mt8173: Add mt6311 driver Add secondary PMIC for external buck control on Oak rev3/4 BRANCH=none BUG=none TEST=verified on Oak rev4/rev5 Change-Id: I24c18a1cf71fc57deacedcbeb6a100b131c28077 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 7f7f8ceac795d8193194a6918a73c4b391009025 Original-Change-Id: I312d8281d2c09d8bc43f092edef3e405d51ee7d0 Original-Signed-off-by: henryc.chen <henryc.chen(a)mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/332341 Original-Commit-Ready: Yidi Lin <yidi.lin(a)mediatek.com> Original-Tested-by: Yidi Lin <yidi.lin(a)mediatek.com> Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> Reviewed-on: https://review.coreboot.org/14121 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See https://review.coreboot.org/14121 for details. -gerrit

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Patch merged into coreboot/master: device: Add i2c read/write register field API
by gerrit＠coreboot.org 21 Mar '16

21 Mar '16

the following patch was just integrated into master: commit d33ebd13741b7473e93a1a6780edbb1e2dca8258 Author: Yidi Lin <yidi.lin(a)mediatek.com> Date: Tue Mar 15 14:38:44 2016 +0800 device: Add i2c read/write register field API i2c_read_field() - read the value from the specific register field i2c_write_field() - write the value to the specific register field BRANCH=none BUG=none TEST=none Change-Id: I2098715b4583c1936c93b3ff45ec330910964304 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 0817fc76d07491b39c066f1393a6435f0831b50c Original-Change-Id: I92c187a89d10cfcecf3dfd9291e0bc015459c393 Original-Signed-off-by: Yidi Lin <yidi.lin(a)mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/332712 Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> Reviewed-on: https://review.coreboot.org/14105 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/14105 for details. -gerrit

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Patch set updated for coreboot: nb/amd/mct_ddr3: Set the NBP0 read latency from P0 trained values
by Timothy Pearson 21 Mar '16

21 Mar '16

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14150 -gerrit commit 61b22554bdf4ac83faf627bcf20a5a6c8a0a7211 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Mon Mar 21 13:22:37 2016 -0500 nb/amd/mct_ddr3: Set the NBP0 read latency from P0 trained values During maximum read latency training on Family 15h processors, the maximum read latency was incorrectly set from the NBP1 value instead of the correct NBP0 value. Modify maximimum read latency training to explicitly operate on the NBP0 value, and store the previously calculated NBP1 value for reference by other portions of the training algorithm. Change-Id: I5d4a6c2def83df3e23f1a4c598314c31a0172cd7 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 4 ++-- src/northbridge/amd/amdmct/mct_ddr3/mct_d.h | 4 ++-- src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c | 7 ++++--- src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c | 20 ++++++++++---------- src/northbridge/amd/amdmct/mct_ddr3/mcttmrl.c | 6 +++--- 5 files changed, 21 insertions(+), 20 deletions(-) diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c index 4615dd2..c530848 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c @@ -3798,7 +3798,7 @@ static void LoadDQSSigTmgRegs_D(struct MCTStatStruc *pMCTstat, reg = 0x78; val = Get_NB32_DCT(dev, Channel, reg); val &= ~(0x3ff<<22); - val |= ((u32) pDCTstat->CH_MaxRdLat[Channel] << 22); + val |= ((u32) pDCTstat->CH_MaxRdLat[Channel][0] << 22); val &= ~(1<<DqsRcvEnTrain); Set_NB32_DCT(dev, Channel, reg, val); /* program MaxRdLatency to correspond with current delay*/ } @@ -7391,7 +7391,7 @@ static void mct_ResetDataStruct_D(struct MCTStatStruc *pMCTstat, p = (u8 *) pDCTstat; start = 0; - stop = ((u32) &((struct DCTStatStruc *)0)->CH_MaxRdLat[2]); + stop = ((u32) &((struct DCTStatStruc *)0)->CH_MaxRdLat[2][2]); for (i = start; i < stop ; i++) { p[i] = 0; } diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h index 654acc0..fd35f9c 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering + * Copyright (C) 2015-2016 Raptor Engineering, LLC * Copyright (C) 2010 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify @@ -498,7 +498,7 @@ struct DCTStatStruc { /* A per Node structure*/ u16 CSUsrTestFail; /* Chip selects excluded by user */ /* DCTStatStruct_F - end */ - u16 CH_MaxRdLat[2]; /* Max Read Latency (ns) for DCT 0*/ + u16 CH_MaxRdLat[2][2]; /* Max Read Latency (nclks) [dct][pstate] */ /* Max Read Latency (ns) for DCT 1*/ u8 CH_D_DIR_B_DQS[2][4][2][9]; /* [A/B] [DIMM1-4] [R/W] [DQS] */ /* CHA DIMM0 Byte 0 - 7 and Check Write DQS Delay*/ diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c index 5d75fb0..a9097ea 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c @@ -877,7 +877,8 @@ static void Calc_SetMaxRdLatency_D_Fam15(struct MCTStatStruc *pMCTstat, mem_clk = Get_NB32_DCT(dev, dct, 0x94) & 0x1f; if (fam15h_freq_tab[mem_clk] == 0) { - pDCTstat->CH_MaxRdLat[dct] = 0x55; + pDCTstat->CH_MaxRdLat[dct][0] = 0x55; + pDCTstat->CH_MaxRdLat[dct][1] = 0x55; return; } @@ -947,10 +948,10 @@ static void Calc_SetMaxRdLatency_D_Fam15(struct MCTStatStruc *pMCTstat, } /* Save result for later use */ - pDCTstat->CH_MaxRdLat[dct] = n - 1; + pDCTstat->CH_MaxRdLat[dct][nb_pstate] = n - 1; #if DQS_TRAIN_DEBUG > 0 - printk(BIOS_DEBUG, "%s: CH_MaxRdLat[%d]: %03x\n", __func__, dct, pDCTstat->CH_MaxRdLat[dct]); + printk(BIOS_DEBUG, "%s: CH_MaxRdLat[%d][%d]: %03x\n", __func__, dct, nb_pstate, pDCTstat->CH_MaxRdLat[dct][nb_pstate]); #endif } diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c index 9a0d372..524bea0 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c @@ -998,7 +998,7 @@ static void dqsTrainRcvrEn_SW_Fam10(struct MCTStatStruc *pMCTstat, printk(BIOS_DEBUG, "TrainRcvrEn: CH_MaxRdLat:\n"); for(ChannelDTD = 0; ChannelDTD<2; ChannelDTD++) { printk(BIOS_DEBUG, "Channel:%x: %x\n", - ChannelDTD, pDCTstat->CH_MaxRdLat[ChannelDTD]); + ChannelDTD, pDCTstat->CH_MaxRdLat[ChannelDTD][0]); } } #endif @@ -1498,7 +1498,7 @@ static void dqsTrainRcvrEn_SW_Fam15(struct MCTStatStruc *pMCTstat, printk(BIOS_DEBUG, "TrainRcvrEn: CH_MaxRdLat:\n"); for(ChannelDTD = 0; ChannelDTD<2; ChannelDTD++) { printk(BIOS_DEBUG, "Channel:%x: %x\n", - ChannelDTD, pDCTstat->CH_MaxRdLat[ChannelDTD]); + ChannelDTD, pDCTstat->CH_MaxRdLat[ChannelDTD][0]); } } #endif @@ -1533,7 +1533,7 @@ static void dqsTrainRcvrEn_SW_Fam15(struct MCTStatStruc *pMCTstat, } static void write_max_read_latency_to_registers(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, uint8_t dct, uint16_t latency) + struct DCTStatStruc *pDCTstat, uint8_t dct, uint16_t *latency) { uint32_t dword; uint8_t nb_pstate; @@ -1541,7 +1541,7 @@ static void write_max_read_latency_to_registers(struct MCTStatStruc *pMCTstat, for (nb_pstate = 0; nb_pstate < 2; nb_pstate++) { dword = Get_NB32_DCT_NBPstate(pDCTstat->dev_dct, dct, nb_pstate, 0x210); dword &= ~(0x3ff << 22); - dword |= ((latency & 0x3ff) << 22); + dword |= ((latency[nb_pstate] & 0x3ff) << 22); Set_NB32_DCT_NBPstate(pDCTstat->dev_dct, dct, nb_pstate, 0x210, dword); } } @@ -1665,7 +1665,7 @@ static void dqsTrainMaxRdLatency_SW_Fam15(struct MCTStatStruc *pMCTstat, /* 2.10.5.8.5.1.4 * Incrementally test each MaxRdLatency candidate */ - for (; pDCTstat->CH_MaxRdLat[Channel] < 0x3ff; pDCTstat->CH_MaxRdLat[Channel]++) { + for (; pDCTstat->CH_MaxRdLat[Channel][0] < 0x3ff; pDCTstat->CH_MaxRdLat[Channel][0]++) { write_max_read_latency_to_registers(pMCTstat, pDCTstat, Channel, pDCTstat->CH_MaxRdLat[Channel]); read_dram_dqs_training_pattern_fam15(pMCTstat, pDCTstat, Channel, current_worst_case_total_delay_dimm << 1, 0xff, 0); dword = Get_NB32_DCT(dev, Channel, 0x268) & 0x3ffff; @@ -1683,8 +1683,8 @@ static void dqsTrainMaxRdLatency_SW_Fam15(struct MCTStatStruc *pMCTstat, dword = Get_NB32(pDCTstat->dev_nbctl, (0x160 + (nb_pstate * 4))); /* Retrieve NbDid, NbFid */ nb_clk = (200 * (((dword >> 1) & 0x1f) + 0x4)) / (((dword >> 7) & 0x1)?2:1); - pDCTstat->CH_MaxRdLat[Channel]++; - pDCTstat->CH_MaxRdLat[Channel] += ((((uint64_t)15 * 100000000000ULL) / ((uint64_t)fam15h_freq_tab[mem_clk] * 1000000ULL)) + pDCTstat->CH_MaxRdLat[Channel][0]++; + pDCTstat->CH_MaxRdLat[Channel][0] += ((((uint64_t)15 * 100000000000ULL) / ((uint64_t)fam15h_freq_tab[mem_clk] * 1000000ULL)) * ((uint64_t)nb_clk * 1000)) / 1000000000ULL; write_max_read_latency_to_registers(pMCTstat, pDCTstat, Channel, pDCTstat->CH_MaxRdLat[Channel]); @@ -1712,7 +1712,7 @@ static void dqsTrainMaxRdLatency_SW_Fam15(struct MCTStatStruc *pMCTstat, printk(BIOS_DEBUG, "TrainMaxRdLatency: CH_MaxRdLat:\n"); for(ChannelDTD = 0; ChannelDTD<2; ChannelDTD++) { printk(BIOS_DEBUG, "Channel:%x: %x\n", - ChannelDTD, pDCTstat->CH_MaxRdLat[ChannelDTD]); + ChannelDTD, pDCTstat->CH_MaxRdLat[ChannelDTD][0]); } } #endif @@ -1904,9 +1904,9 @@ static void mct_SetMaxLatency_D(struct DCTStatStruc *pDCTstat, u8 Channel, u16 D */ SubTotal += (cpu_val_n) / 2; - pDCTstat->CH_MaxRdLat[Channel] = SubTotal; + pDCTstat->CH_MaxRdLat[Channel][0] = SubTotal; if(pDCTstat->GangedMode) { - pDCTstat->CH_MaxRdLat[1] = SubTotal; + pDCTstat->CH_MaxRdLat[1][0] = SubTotal; } /* Program the F2x[1, 0]78[MaxRdLatency] register with diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mcttmrl.c b/src/northbridge/amd/amdmct/mct_ddr3/mcttmrl.c index 1b18efa..8cda2f8 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mcttmrl.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mcttmrl.c @@ -191,7 +191,7 @@ static void maxRdLatencyTrain_D(struct MCTStatStruc *pMCTstat, u8 ChannelDTD; printk(BIOS_DEBUG, "maxRdLatencyTrain: CH_MaxRdLat:\n"); for(ChannelDTD = 0; ChannelDTD<2; ChannelDTD++) { - printk(BIOS_DEBUG, "Channel: %02x: %02x\n", ChannelDTD, pDCTstat->CH_MaxRdLat[ChannelDTD]); + printk(BIOS_DEBUG, "Channel: %02x: %02x\n", ChannelDTD, pDCTstat->CH_MaxRdLat[ChannelDTD][0]); } } #endif @@ -208,9 +208,9 @@ static void mct_setMaxRdLatTrnVal_D(struct DCTStatStruc *pDCTstat, if (pDCTstat->GangedMode) { Channel = 0; /* for safe */ for (i=0; i<2; i++) - pDCTstat->CH_MaxRdLat[i] = MaxRdLatVal; + pDCTstat->CH_MaxRdLat[i][0] = MaxRdLatVal; } else { - pDCTstat->CH_MaxRdLat[Channel] = MaxRdLatVal; + pDCTstat->CH_MaxRdLat[Channel][0] = MaxRdLatVal; } dev = pDCTstat->dev_dct;

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Patch set updated for coreboot: gpio: Add support for binary_first base3 number system
by Julius Werner 21 Mar '16

21 Mar '16

Julius Werner (jwerner(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14116 -gerrit commit 790a3836203d35a9d425628b1e64aec1f68ff2d8 Author: Julius Werner <jwerner(a)chromium.org> Date: Wed Mar 16 17:11:55 2016 -0700 gpio: Add support for binary_first base3 number system This patch adds support for an alternative ternary number system in which group of GPIOs can be interpreted. In this system, the digit combinations that would form a binary number (i.e. that contain no 'Z' state) are used to represent the lower values in the way they're used in the normal binary system, and all the combinations that do contain a 'Z' are used to represent values above those. We can use this for boards that originally get strapped with binary board IDs but eventually require more revisions than that representation allows. We can switch their code to binary_first base3 and all old revisions with already produced boards will still get read as the correct numbers. Credit for the algorithm idea goes to Haran Talmon. BRANCH=None BUG=None TEST=Stubbed out the actual GPIO reading and simulated all combinations of 4 ternary digits for both number systems. Change-Id: Ib5127656455f97f890ce2999ba5ac5f58a20cf93 Signed-off-by: Julius Werner <jwerner(a)chromium.org> --- src/include/gpio.h | 36 +++++++++++++++++++++++++++++++++++- src/lib/gpio.c | 49 +++++++++++++++++++++++++++++++++++++++++++++++-- 2 files changed, 82 insertions(+), 3 deletions(-) diff --git a/src/include/gpio.h b/src/include/gpio.h index ea03a23..4627e44 100644 --- a/src/include/gpio.h +++ b/src/include/gpio.h @@ -29,6 +29,7 @@ void gpio_input_pulldown(gpio_t gpio); void gpio_input_pullup(gpio_t gpio); void gpio_input(gpio_t gpio); void gpio_output(gpio_t gpio, int value); +int _gpio_base3_value(gpio_t gpio[], int num_gpio, int binary_first); /* * Read the value presented by the set of GPIOs, when each pin is interpreted @@ -48,6 +49,39 @@ int gpio_base2_value(gpio_t gpio[], int num_gpio); * gpio[]: pin positions to read. gpio[0] is less significant than gpio[1]. * num_gpio: number of pins to read. */ -int gpio_base3_value(gpio_t gpio[], int num_gpio); +static inline int gpio_base3_value(gpio_t gpio[], int num_gpio) +{ + return _gpio_base3_value(gpio, num_gpio, 0); +} + +/* + * Read the value presented by the set of GPIOs, when each pin is interpreted + * as a base-3 digit (LOW = 0, HIGH = 1, Z/floating = 2) in a non-standard + * ternary number system where the first 2^n natural numbers are represented + * as they would be in a binary system (without any Z digits), and the following + * 3^n-2^n numbers use the remaining ternary representations in the normal + * ternary system order (skipping the values that were already used up). + * This is useful for boards which initially used a binary board ID and later + * decided to switch to tri-state after some revisions have already been built. + * Example: For num_gpio = 2 we get the following representation: + * + * Number X1 X0 + * 0 0 0 + * 1 0 1 + * 2 1 0 + * 3 1 1 // Start counting ternaries back at 0 after this + * 4 0 2 // Skipping 00 and 01 which are already used up + * 5 1 2 // Skipping 10 and 11 which are already used up + * 6 2 0 + * 7 2 1 + * 8 2 2 + * + * gpio[]: pin positions to read. gpio[0] is less significant than gpio[1]. + * num_gpio: number of pins to read. + */ +static inline int gpio_binary_first_base3_value(gpio_t gpio[], int num_gpio) +{ + return _gpio_base3_value(gpio, num_gpio, 1); +} #endif /* __SRC_INCLUDE_GPIO_H__ */ diff --git a/src/lib/gpio.c b/src/lib/gpio.c index 5147cfe..2e34595 100644 --- a/src/lib/gpio.c +++ b/src/lib/gpio.c @@ -35,7 +35,7 @@ int gpio_base2_value(gpio_t gpio[], int num_gpio) return result; } -int gpio_base3_value(gpio_t gpio[], int num_gpio) +int _gpio_base3_value(gpio_t gpio[], int num_gpio, int binary_first) { /* * GPIOs which are tied to stronger external pull up or pull down @@ -50,6 +50,8 @@ int gpio_base3_value(gpio_t gpio[], int num_gpio) int temp; int index; int result = 0; + int has_z = 0; + int binary_below = 0; char value[32]; assert(num_gpio <= 32); @@ -85,8 +87,51 @@ int gpio_base3_value(gpio_t gpio[], int num_gpio) temp |= ((value[index] ^ temp) << 1); printk(BIOS_DEBUG, "%c ", tristate_char[temp]); result = (result * 3) + temp; + + /* + * For binary_first we keep track of the normal ternary result + * and whether we found any pin that was a Z. We also determine + * the amount of numbers that can be represented with only + * binary digits (no Z) whose value in the normal ternary system + * is lower than the one we are parsing. Counting from the left, + * we add 2^i for any '1' digit to account for the binary + * numbers whose values would be below it if all following + * digits we parsed would be '0'. As soon as we find a '2' digit + * we can total the remaining binary numbers below as 2^(i+1) + * because we know that all binary representations counting only + * this and following digits must have values below our number + * (since 1xxx is always smaller than 2xxx). + * + * Example: 1 0 2 1 (counting from the left / most significant) + * '1' at 3^3: Add 2^3 = 8 to account for binaries 0000-0111 + * '0' at 3^2: Ignore (not all binaries 1000-1100 are below us) + * '2' at 3^1: Add 2^(1+1) = 4 to account for binaries 1000-1011 + * Stop adding for lower digits (3^0), all already accounted + * now. We know that there can be no binary numbers 1020-102X. + */ + if (binary_first && !has_z) { + switch(temp) { + case 0: /* Ignore '0' digits. */ + break; + case 1: /* Account for binaries 0 to 2^index - 1. */ + binary_below += 1 << index; + break; + case 2: /* Account for binaries 0 to 2^(index+1) - 1. */ + binary_below += 1 << (index + 1); + has_z = 1; + } + } + } + + if (binary_first) { + if (has_z) + result = result + (1 << num_gpio) - binary_below; + else /* binary_below is normal binary system value if !has_z. */ + result = binary_below; } - printk(BIOS_DEBUG, "= %d\n", result); + + printk(BIOS_DEBUG, "= %d (%s base3 number system)\n", result, + binary_first ? "binary_first" : "standard"); /* Disable pull up / pull down to conserve power */ for (index = 0; index < num_gpio; ++index)

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Patch merged into coreboot/master: nb/amd/amdmct/mct_ddr3: Ensure BlockRxDqsLock does not remain set
by gerrit＠coreboot.org 21 Mar '16

21 Mar '16

the following patch was just integrated into master: commit f7d4f73053f0c26bfe411a9f3ef86f98389538b5 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Sun Mar 20 14:21:53 2016 -0500 nb/amd/amdmct/mct_ddr3: Ensure BlockRxDqsLock does not remain set Under certain conditions (training abort) BlockRxDqsLock could remain set in violation of the BKDG. Ensure BlockRxDqsLock is reset to 0 after a lane training abort. Change-Id: I1a49a24d02b2b7cacae074794ec274a424a9e66b Reviewed-on: https://review.coreboot.org/14144 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply(a)raptorengineeringinc.com> Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/14144 for details. -gerrit

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Patch merged into coreboot/master: Documentation: x86 MTRR setup, TempRamExit and MTRR loading
by gerrit＠coreboot.org 21 Mar '16

21 Mar '16

the following patch was just integrated into master: commit a4d81809137b8b53903303b201c2d1bfbc615143 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Sun Jan 31 12:19:13 2016 -0800 Documentation: x86 MTRR setup, TempRamExit and MTRR loading Document how to test TempRamExit and verify the MTRR setup and loading. TEST=None Change-Id: I57a604fa139edac4b05453547d3caf185db491e0 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> Reviewed-on: https://review.coreboot.org/14113 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/14113 for details. -gerrit

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Patch set updated for coreboot: nb/amd/mct_ddr3: Set the NBP0 read latency from P0 trained values
by Timothy Pearson 21 Mar '16

21 Mar '16

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14150 -gerrit commit 0d941c18e306b0af3bdce513b66e10e5d01c91c5 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Mon Mar 21 13:22:37 2016 -0500 nb/amd/mct_ddr3: Set the NBP0 read latency from P0 trained values During maximum read latency training on Family 15h processors, the maximum read latency was incorrectly set from the NBP1 value instead of the correct NBP0 value. Modify maximimum read latency training to explicitly operate on the NBP0 value, and store the previously calculated NBP1 value for reference by other portions of the training algorithm. Change-Id: I5d4a6c2def83df3e23f1a4c598314c31a0172cd7 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 4 ++-- src/northbridge/amd/amdmct/mct_ddr3/mct_d.h | 4 ++-- src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c | 7 ++++--- src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c | 20 ++++++++++---------- src/northbridge/amd/amdmct/mct_ddr3/mcttmrl.c | 6 +++--- 5 files changed, 21 insertions(+), 20 deletions(-) diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c index 4615dd2..c530848 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c @@ -3798,7 +3798,7 @@ static void LoadDQSSigTmgRegs_D(struct MCTStatStruc *pMCTstat, reg = 0x78; val = Get_NB32_DCT(dev, Channel, reg); val &= ~(0x3ff<<22); - val |= ((u32) pDCTstat->CH_MaxRdLat[Channel] << 22); + val |= ((u32) pDCTstat->CH_MaxRdLat[Channel][0] << 22); val &= ~(1<<DqsRcvEnTrain); Set_NB32_DCT(dev, Channel, reg, val); /* program MaxRdLatency to correspond with current delay*/ } @@ -7391,7 +7391,7 @@ static void mct_ResetDataStruct_D(struct MCTStatStruc *pMCTstat, p = (u8 *) pDCTstat; start = 0; - stop = ((u32) &((struct DCTStatStruc *)0)->CH_MaxRdLat[2]); + stop = ((u32) &((struct DCTStatStruc *)0)->CH_MaxRdLat[2][2]); for (i = start; i < stop ; i++) { p[i] = 0; } diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h index 654acc0..fd35f9c 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering + * Copyright (C) 2015-2016 Raptor Engineering, LLC * Copyright (C) 2010 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify @@ -498,7 +498,7 @@ struct DCTStatStruc { /* A per Node structure*/ u16 CSUsrTestFail; /* Chip selects excluded by user */ /* DCTStatStruct_F - end */ - u16 CH_MaxRdLat[2]; /* Max Read Latency (ns) for DCT 0*/ + u16 CH_MaxRdLat[2][2]; /* Max Read Latency (nclks) [dct][pstate] */ /* Max Read Latency (ns) for DCT 1*/ u8 CH_D_DIR_B_DQS[2][4][2][9]; /* [A/B] [DIMM1-4] [R/W] [DQS] */ /* CHA DIMM0 Byte 0 - 7 and Check Write DQS Delay*/ diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c index 5d75fb0..3309c31 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c @@ -877,7 +877,8 @@ static void Calc_SetMaxRdLatency_D_Fam15(struct MCTStatStruc *pMCTstat, mem_clk = Get_NB32_DCT(dev, dct, 0x94) & 0x1f; if (fam15h_freq_tab[mem_clk] == 0) { - pDCTstat->CH_MaxRdLat[dct] = 0x55; + pDCTstat->CH_MaxRdLat[dct][0] = 0x55; + pDCTstat->CH_MaxRdLat[dct][1] = 0x55; return; } @@ -947,10 +948,10 @@ static void Calc_SetMaxRdLatency_D_Fam15(struct MCTStatStruc *pMCTstat, } /* Save result for later use */ - pDCTstat->CH_MaxRdLat[dct] = n - 1; + pDCTstat->CH_MaxRdLat[dct][nb_pstate] = n - 1; #if DQS_TRAIN_DEBUG > 0 - printk(BIOS_DEBUG, "%s: CH_MaxRdLat[%d]: %03x\n", __func__, dct, pDCTstat->CH_MaxRdLat[dct]); + printk(BIOS_DEBUG, "%s: CH_MaxRdLat[%d][%d]: %03x\n", __func__, dct, pDCTstat->CH_MaxRdLat[dct][nb_pstate]); #endif } diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c index 9a0d372..524bea0 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c @@ -998,7 +998,7 @@ static void dqsTrainRcvrEn_SW_Fam10(struct MCTStatStruc *pMCTstat, printk(BIOS_DEBUG, "TrainRcvrEn: CH_MaxRdLat:\n"); for(ChannelDTD = 0; ChannelDTD<2; ChannelDTD++) { printk(BIOS_DEBUG, "Channel:%x: %x\n", - ChannelDTD, pDCTstat->CH_MaxRdLat[ChannelDTD]); + ChannelDTD, pDCTstat->CH_MaxRdLat[ChannelDTD][0]); } } #endif @@ -1498,7 +1498,7 @@ static void dqsTrainRcvrEn_SW_Fam15(struct MCTStatStruc *pMCTstat, printk(BIOS_DEBUG, "TrainRcvrEn: CH_MaxRdLat:\n"); for(ChannelDTD = 0; ChannelDTD<2; ChannelDTD++) { printk(BIOS_DEBUG, "Channel:%x: %x\n", - ChannelDTD, pDCTstat->CH_MaxRdLat[ChannelDTD]); + ChannelDTD, pDCTstat->CH_MaxRdLat[ChannelDTD][0]); } } #endif @@ -1533,7 +1533,7 @@ static void dqsTrainRcvrEn_SW_Fam15(struct MCTStatStruc *pMCTstat, } static void write_max_read_latency_to_registers(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, uint8_t dct, uint16_t latency) + struct DCTStatStruc *pDCTstat, uint8_t dct, uint16_t *latency) { uint32_t dword; uint8_t nb_pstate; @@ -1541,7 +1541,7 @@ static void write_max_read_latency_to_registers(struct MCTStatStruc *pMCTstat, for (nb_pstate = 0; nb_pstate < 2; nb_pstate++) { dword = Get_NB32_DCT_NBPstate(pDCTstat->dev_dct, dct, nb_pstate, 0x210); dword &= ~(0x3ff << 22); - dword |= ((latency & 0x3ff) << 22); + dword |= ((latency[nb_pstate] & 0x3ff) << 22); Set_NB32_DCT_NBPstate(pDCTstat->dev_dct, dct, nb_pstate, 0x210, dword); } } @@ -1665,7 +1665,7 @@ static void dqsTrainMaxRdLatency_SW_Fam15(struct MCTStatStruc *pMCTstat, /* 2.10.5.8.5.1.4 * Incrementally test each MaxRdLatency candidate */ - for (; pDCTstat->CH_MaxRdLat[Channel] < 0x3ff; pDCTstat->CH_MaxRdLat[Channel]++) { + for (; pDCTstat->CH_MaxRdLat[Channel][0] < 0x3ff; pDCTstat->CH_MaxRdLat[Channel][0]++) { write_max_read_latency_to_registers(pMCTstat, pDCTstat, Channel, pDCTstat->CH_MaxRdLat[Channel]); read_dram_dqs_training_pattern_fam15(pMCTstat, pDCTstat, Channel, current_worst_case_total_delay_dimm << 1, 0xff, 0); dword = Get_NB32_DCT(dev, Channel, 0x268) & 0x3ffff; @@ -1683,8 +1683,8 @@ static void dqsTrainMaxRdLatency_SW_Fam15(struct MCTStatStruc *pMCTstat, dword = Get_NB32(pDCTstat->dev_nbctl, (0x160 + (nb_pstate * 4))); /* Retrieve NbDid, NbFid */ nb_clk = (200 * (((dword >> 1) & 0x1f) + 0x4)) / (((dword >> 7) & 0x1)?2:1); - pDCTstat->CH_MaxRdLat[Channel]++; - pDCTstat->CH_MaxRdLat[Channel] += ((((uint64_t)15 * 100000000000ULL) / ((uint64_t)fam15h_freq_tab[mem_clk] * 1000000ULL)) + pDCTstat->CH_MaxRdLat[Channel][0]++; + pDCTstat->CH_MaxRdLat[Channel][0] += ((((uint64_t)15 * 100000000000ULL) / ((uint64_t)fam15h_freq_tab[mem_clk] * 1000000ULL)) * ((uint64_t)nb_clk * 1000)) / 1000000000ULL; write_max_read_latency_to_registers(pMCTstat, pDCTstat, Channel, pDCTstat->CH_MaxRdLat[Channel]); @@ -1712,7 +1712,7 @@ static void dqsTrainMaxRdLatency_SW_Fam15(struct MCTStatStruc *pMCTstat, printk(BIOS_DEBUG, "TrainMaxRdLatency: CH_MaxRdLat:\n"); for(ChannelDTD = 0; ChannelDTD<2; ChannelDTD++) { printk(BIOS_DEBUG, "Channel:%x: %x\n", - ChannelDTD, pDCTstat->CH_MaxRdLat[ChannelDTD]); + ChannelDTD, pDCTstat->CH_MaxRdLat[ChannelDTD][0]); } } #endif @@ -1904,9 +1904,9 @@ static void mct_SetMaxLatency_D(struct DCTStatStruc *pDCTstat, u8 Channel, u16 D */ SubTotal += (cpu_val_n) / 2; - pDCTstat->CH_MaxRdLat[Channel] = SubTotal; + pDCTstat->CH_MaxRdLat[Channel][0] = SubTotal; if(pDCTstat->GangedMode) { - pDCTstat->CH_MaxRdLat[1] = SubTotal; + pDCTstat->CH_MaxRdLat[1][0] = SubTotal; } /* Program the F2x[1, 0]78[MaxRdLatency] register with diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mcttmrl.c b/src/northbridge/amd/amdmct/mct_ddr3/mcttmrl.c index 1b18efa..8cda2f8 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mcttmrl.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mcttmrl.c @@ -191,7 +191,7 @@ static void maxRdLatencyTrain_D(struct MCTStatStruc *pMCTstat, u8 ChannelDTD; printk(BIOS_DEBUG, "maxRdLatencyTrain: CH_MaxRdLat:\n"); for(ChannelDTD = 0; ChannelDTD<2; ChannelDTD++) { - printk(BIOS_DEBUG, "Channel: %02x: %02x\n", ChannelDTD, pDCTstat->CH_MaxRdLat[ChannelDTD]); + printk(BIOS_DEBUG, "Channel: %02x: %02x\n", ChannelDTD, pDCTstat->CH_MaxRdLat[ChannelDTD][0]); } } #endif @@ -208,9 +208,9 @@ static void mct_setMaxRdLatTrnVal_D(struct DCTStatStruc *pDCTstat, if (pDCTstat->GangedMode) { Channel = 0; /* for safe */ for (i=0; i<2; i++) - pDCTstat->CH_MaxRdLat[i] = MaxRdLatVal; + pDCTstat->CH_MaxRdLat[i][0] = MaxRdLatVal; } else { - pDCTstat->CH_MaxRdLat[Channel] = MaxRdLatVal; + pDCTstat->CH_MaxRdLat[Channel][0] = MaxRdLatVal; } dev = pDCTstat->dev_dct;

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Patch merged into coreboot/master: Documentation/Intel: Add more Galileo Gen2 links
by gerrit＠coreboot.org 21 Mar '16

21 Mar '16

the following patch was just integrated into master: commit b953d05e604917ad2acb935e06bcc0344f8a09a1 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Wed Mar 16 08:58:01 2016 -0700 Documentation/Intel: Add more Galileo Gen2 links Add datasheet links for the components supporting GPIO. This includes I2C I/O ports, I2C PWMs, bus buffers and multiplexers. TEST=None Change-Id: I0a1d222d6f9bdbd824b78edf2338cd797e83ebba Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> Reviewed-on: https://review.coreboot.org/14114 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/14114 for details. -gerrit

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