coreboot-gerrit March 2016

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: Documentation: x86 MTRR setup, TempRamExit and MTRR loading
by Martin Roth 21 Mar '16

21 Mar '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14113 -gerrit commit 8f6dcd985dfb12eee6d9771f5a72a10ff7fcd3c5 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Sun Jan 31 12:19:13 2016 -0800 Documentation: x86 MTRR setup, TempRamExit and MTRR loading Document how to test TempRamExit and verify the MTRR setup and loading. TEST=None Change-Id: I57a604fa139edac4b05453547d3caf185db491e0 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- Documentation/Intel/development.html | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/Documentation/Intel/development.html b/Documentation/Intel/development.html index a36acaa..a2ba278 100644 --- a/Documentation/Intel/development.html +++ b/Documentation/Intel/development.html @@ -97,6 +97,7 @@ <li>Disable the <a target="_blank" href="SoC/soc.html#DisableShadowRom">Shadow ROM</a> </li> + <li>Enable CONFIG_DISPLAY_MTRRS to verify the MTRR configuration</li> <li> Implement the .init routine for the <a target="_blank" href="SoC/soc.html#ChipOperations">chip operations</a> @@ -115,6 +116,7 @@ Implement the <a target="_blank" href="SoC/soc.html#MemoryMap">memory map</a> </li> + <li>coreboot should now attempt to load the payload</li> </ol> @@ -185,6 +187,20 @@ <td>coreboot displays the memory map correctly during the BS_WRITE_TABLES state</td> </tr> <tr> + <td>MTRRs</td> + <td> + Set values: src/drivers/intel/fsp1_1/stack.c/<a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/inte…">setup_stack_and_mtrrs</a><br> + Load values: src/drivers/intel/fsp1_1/<a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/inte…">after_raminit.S</a> + </td> + <td>Set: Post code 0x91 + (<a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/include/cons…">POST_FSP_TEMP_RAM_EXIT</a>) + is displayed by + <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/inte…">after_raminit.S</a><br> + Load: Post code 0x3C is displayed by + <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/inte…">after_raminit.S</a><br> + and CONFIG_DISPLAY_MTRRS=y displays the correct memory regions</td> + </tr> + <tr> <td>PCI Device Support</td> <td>Implement a PCI <a target="_blank" href="SoC/soc.html#DeviceDrivers">device driver</a></td> <td>The device is detected by coreboot and usable by the payload</td>

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Patch merged into coreboot/master: Documentation: x86 shadow ROM disable
by gerrit＠coreboot.org 21 Mar '16

21 Mar '16

the following patch was just integrated into master: commit e9a6d1a813f61b505f9463160c27992419cb9056 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Sun Jan 31 11:28:06 2016 -0800 Documentation: x86 shadow ROM disable Add documentation on disabling the SPI flash which is mapped (shadowed) into the x86 address space at 0x000e0000 - 0x000fffff. TEST=None Change-Id: I1d94d84c6cade97886a3274a7e7403f7b3275c5a Signed-off-by: Lee Leahy <Leroy.P.Leahy(a)intel.com> Reviewed-on: https://review.coreboot.org/14112 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/14112 for details. -gerrit

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Patch merged into coreboot/master: soc/intel/quark: Disable the ROM shadow
by gerrit＠coreboot.org 21 Mar '16

21 Mar '16

the following patch was just integrated into master: commit d75ed0bfd9238b210fdca136784cd699696421c7 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Fri Mar 4 16:49:40 2016 -0800 soc/intel/quark: Disable the ROM shadow Disable the ROM shadow and enable RAM for 0x000e0000 - 0x000fffff. Testing on Galileo: * Edit the src/mainboard/intel/galileo/Makefile.inc file: * Add "select ADD_FSP_PDAT_FILE" * Add "select ADD_FSP_RAW_BIN" * Add "select ADD_RMU_FILE" * Place the FSP.bin file in the location specified by CONFIG_FSP_FILE * Place the pdat.bin files in the location specified by CONFIG_FSP_PDAT_FILE * Place the rmu.bin file in the location specified by CONFIG_RMU_FILE * Build EDK2 CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc to generate UEFIPAYLOAD.fd * Testing successful display of 0x000ffff0 - 0x000fffff does not match the end of the SPI flash. Change-Id: I6e0a50417815320333eae0b69b96280c39db7eaa Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> Reviewed-on: https://review.coreboot.org/14110 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/14110 for details. -gerrit

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Patch merged into coreboot/master: mainboard/intel/galileo: Enable SPI controllers
by gerrit＠coreboot.org 21 Mar '16

21 Mar '16

the following patch was just integrated into master: commit 1f1f2c4d38dc5b58e0051f9d80086bc2a083a7cd Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Thu Mar 3 15:30:48 2016 -0800 mainboard/intel/galileo: Enable SPI controllers Enable the SPI controllers on the Quark SoC. Testing on Galileo: * Edit the src/mainboard/intel/galileo/Makefile.inc file: * Add "select ADD_FSP_PDAT_FILE" * Add "select ADD_FSP_RAW_BIN" * Add "select ADD_RMU_FILE" * Place the FSP.bin file in the location specified by CONFIG_FSP_FILE * Place the pdat.bin files in the location specified by CONFIG_FSP_PDAT_FILE * Place the rmu.bin file in the location specified by CONFIG_RMU_FILE * Build EDK2 CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc to generate UEFIPAYLOAD.fd * Load the SPI driver stack * Testing is successful when the time is able to be displayed on a set of seven-segment displays controlled by a Maxim MAX6950 SPI display controller. Change-Id: Ic9c4575730c5a9a27cf9a38a41e82d8462467f3f Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> Reviewed-on: https://review.coreboot.org/14109 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/14109 for details. -gerrit

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Patch merged into coreboot/master: device/dram/ddr3: fix debug output
by gerrit＠coreboot.org 21 Mar '16

21 Mar '16

the following patch was just integrated into master: commit 66a98ee9675d73dc4e5343782d42f80a09c2425e Author: Patrick Rudolph <siro(a)das-labor.org> Date: Sun Mar 13 13:02:16 2016 +0100 device/dram/ddr3: fix debug output Add missing punctuation and align output. No functionality is changed. Old logging output: Revision: 11 Type : b Key : 2 Banks : 8 Capacity: 4 Gb Supported voltages: 1.5V SDRAM width : 8 Bus extension : 0 bits Bus width : 64 Optional features : DLL-Off_mode RZQ/7 RZQ/6 Thermal features : ASR ext_temp_range Thermal sensor : no Standard SDRAM : yes DIMM Rank1 Address bits mirrored!!! DIMM Reference card B DIMM Manufacturer ID cd04 DIMM Part number F3-1866C9-8GSR XMP Profile 1 Max DIMMs per channel: 4 XMP Revision: 1.3 Requested voltage: 1500 mV New logging output: Revision : 11 Type : b Key : 2 Banks : 8 Capacity : 4 Gb Supported voltages : 1.5V SDRAM width : 8 Bus extension : 0 bits Bus width : 64 Optional features : DLL-Off_mode RZQ/7 RZQ/6 Thermal features : ASR ext_temp_range Thermal sensor : no Standard SDRAM : yes Rank1 Address bits : mirrored DIMM Reference card: B Manufacturer ID : cd04 Part number : F3-1866C9-8GSR XMP Profile : 1 Max DIMMs/channel : 4 XMP Revision : 1.3 Requested voltage : 1500 mV Change-Id: Iee4d7a7c0e1070706fb60d7316fad49813963b51 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> Reviewed-on: https://review.coreboot.org/14083 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/14083 for details. -gerrit

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Patch merged into coreboot/master: arch/x86: honor CONFIG_X86_TOP4G_BOOTMEDIA_MAP for verstage
by gerrit＠coreboot.org 21 Mar '16

21 Mar '16

the following patch was just integrated into master: commit 57dbbbb5960c3720aadc66c1d6dbdbe131943bb7 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Mar 18 13:12:41 2016 -0500 arch/x86: honor CONFIG_X86_TOP4G_BOOTMEDIA_MAP for verstage When CONFIG_X86_TOP4G_BOOTMEDIA_MAP was introduced verstage was not updated. Correct this oversight. Change-Id: I2775c08798906ba0ba55a361407d7d2b52313229 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://review.coreboot.org/14142 Reviewed-by: Andrey Petrov <andrey.petrov(a)intel.com> Tested-by: build bot (Jenkins) See https://review.coreboot.org/14142 for details. -gerrit

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Patch merged into coreboot/master: MAINTAINERS: Add maintainers for power8 architecture
by gerrit＠coreboot.org 21 Mar '16

21 Mar '16

the following patch was just integrated into master: commit 57fcae10310745067408b114f168ed709710d790 Author: Martin Roth <martinroth(a)google.com> Date: Thu Mar 17 12:00:25 2016 -0600 MAINTAINERS: Add maintainers for power8 architecture Change-Id: I0eedda5f31c2809db7871b81ceb3045b782f9df1 Signed-off-by: Martin Roth <martinroth(a)google.com> Reviewed-on: https://review.coreboot.org/14126 Tested-by: build bot (Jenkins) Reviewed-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> See https://review.coreboot.org/14126 for details. -gerrit

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Patch merged into coreboot/master: MAINTAINERS: Add maintainer to lint scripts, board status & payloads
by gerrit＠coreboot.org 21 Mar '16

21 Mar '16

the following patch was just integrated into master: commit 057ce5fa55dbbe25cefc38c661022e7b9788bc82 Author: Martin Roth <martinroth(a)google.com> Date: Thu Mar 17 12:03:00 2016 -0600 MAINTAINERS: Add maintainer to lint scripts, board status & payloads Change-Id: I3efd4116da1ffda2dbc768d1a447141d8ec76f81 Signed-off-by: Martin Roth <martinroth(a)google.com> Reviewed-on: https://review.coreboot.org/14128 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See https://review.coreboot.org/14128 for details. -gerrit

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Patch merged into coreboot/master: payloads: Add a target to print payload git urls and directories
by gerrit＠coreboot.org 21 Mar '16

21 Mar '16

the following patch was just integrated into master: commit ae269c0276d5a0938b76cdd1561f504a7cc2a858 Author: Martin Roth <martinroth(a)google.com> Date: Wed Mar 16 12:42:05 2016 -0600 payloads: Add a target to print payload git urls and directories Being able to fetch this list will allow the jenkins builder to securely fetch the external payloads so we can start testing payload builds. Change-Id: I777229216b2f11f0f427cd5f8cfa003da4171a77 Signed-off-by: Martin Roth <martinroth(a)google.com> Reviewed-on: https://review.coreboot.org/14132 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See https://review.coreboot.org/14132 for details. -gerrit

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New patch to review for coreboot: nb/amd/mct_ddr3: Remove spurious Addl_Index variable in dqsTrainMaxRdLatency_SW_Fam15()
by Timothy Pearson 21 Mar '16

21 Mar '16

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14148 -gerrit commit d81baf1817618e572eb7efd39383de1f338e27f3 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Mon Mar 21 02:14:50 2016 -0500 nb/amd/mct_ddr3: Remove spurious Addl_Index variable in dqsTrainMaxRdLatency_SW_Fam15() Change-Id: Ic3f636983cf6ba2796ee56e2a25b56513a4343c1 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c index da71816..9a0d372 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c @@ -1555,7 +1555,6 @@ static void dqsTrainMaxRdLatency_SW_Fam15(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat) { u8 Channel; - u8 Addl_Index = 0; u8 Receiver; u8 _DisableDramECC = 0, _Wrap32Dis = 0, _SSE2 = 0; u32 Errors; @@ -1629,10 +1628,9 @@ static void dqsTrainMaxRdLatency_SW_Fam15(struct MCTStatStruc *pMCTstat, * This is essentially looping over each DIMM. */ for (; Receiver < 8; Receiver += 2) { - Addl_Index = (Receiver >> 1) * 3 + 0x10; dimm = (Receiver >> 1); - print_debug_dqs("\t\tTrainMaxRdLatency52: index ", Addl_Index, 2); + print_debug_dqs("\t\tTrainMaxRdLatency52: Receiver ", Receiver, 2); if (!mct_RcvrRankEnabled_D(pMCTstat, pDCTstat, Channel, Receiver)) { continue;

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coreboot-gerrit March 2016