coreboot-gerrit March 2016

coreboot-gerrit@coreboot.org

1 participants
1119 discussions

Patch merged into coreboot/master: google/oak: Enable RAM_CODE_SUPPORT
by gerrit＠coreboot.org 18 Mar '16

18 Mar '16

the following patch was just integrated into master: commit 39e55209dce7d971c2e5b53706c5124e1ec01bb3 Author: Yidi Lin <yidi.lin(a)mediatek.com> Date: Mon Mar 14 10:06:46 2016 +0800 google/oak: Enable RAM_CODE_SUPPORT BRANCH=none BUG=chrome-os-partner:50820 TEST=check /proc/device-tree/firmware/coreboot/ram-code Change-Id: I5ecf45cada7f8999ad607487d5d9281c4fb659ed Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 79d2f0e183a2bde70817d673ae315709f46e3361 Original-Change-Id: I35e91b4e29f8e09acd74770715c96cf7320ac22c Original-Signed-off-by: Yidi Lin <yidi.lin(a)mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/332564 Original-Reviewed-by: Milton Chiang <milton.chiang(a)mediatek.com> Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> Reviewed-on: https://review.coreboot.org/14104 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See https://review.coreboot.org/14104 for details. -gerrit

1 0

Patch merged into coreboot/master: mediatek/mt8173: mt6391: set VSRMCA7 to HW control by SRCVOLTEN
by gerrit＠coreboot.org 18 Mar '16

18 Mar '16

the following patch was just integrated into master: commit aad2903c9ceefa9ffb86660c07a7b3eb1ead46b5 Author: henryc.chen <henryc.chen(a)mediatek.com> Date: Mon Mar 7 15:17:01 2016 +0800 mediatek/mt8173: mt6391: set VSRMCA7 to HW control by SRCVOLTEN When system enters suspend, SPM will pull SRCVOLTEN low to turn off some power rails. VSRMCA7 should follow this pin to turn on/off the power. BRANCH=none BUG=none TEST=verified on Oak rev5 Change-Id: I9d81f855a74fe02a59246ce0c6a7f0e162b9fd0a Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: d92fb1029b810028138eb91b064b63a58b82602f Original-Change-Id: I37ff0694cbd7b17d5a1ae172c463b4e6aae2b99c Original-Signed-off-by: henryc.chen <henryc.chen(a)mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/332345 Original-Commit-Ready: Yidi Lin <yidi.lin(a)mediatek.com> Original-Tested-by: Yidi Lin <yidi.lin(a)mediatek.com> Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> Reviewed-on: https://review.coreboot.org/14103 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See https://review.coreboot.org/14103 for details. -gerrit

1 0

Patch set updated for coreboot: soc/apollolake: Add skeleton ACPI entry
by Lijian Zhao 18 Mar '16

18 Mar '16

Lijian Zhao (lijian.zhao(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13348 -gerrit commit 3282b13e2321d05b3834bf95d0b0970d8614c72c Author: Lance Zhao <lijian.zhao(a)intel.com> Date: Mon Nov 9 17:06:34 2015 -0800 soc/apollolake: Add skeleton ACPI entry Change-Id: Ib127af5392ca2b349480f5b21fad2186b444d7e6 Signed-off-by: Lance Zhao <lijian.zhao(a)intel.com> --- src/mainboard/intel/apollolake_rvp/Kconfig | 1 + src/mainboard/intel/apollolake_rvp/acpi_tables.c | 17 ++++++++++++++ src/mainboard/intel/apollolake_rvp/dsdt.asl | 29 ++++++++++++++++++++++++ src/soc/intel/apollolake/Makefile.inc | 2 ++ src/soc/intel/apollolake/acpi.c | 22 ++++++++++++++++++ 5 files changed, 71 insertions(+) diff --git a/src/mainboard/intel/apollolake_rvp/Kconfig b/src/mainboard/intel/apollolake_rvp/Kconfig index 9920b46..5006695 100644 --- a/src/mainboard/intel/apollolake_rvp/Kconfig +++ b/src/mainboard/intel/apollolake_rvp/Kconfig @@ -4,6 +4,7 @@ config BOARD_SPECIFIC_OPTIONS def_bool y select SOC_INTEL_APOLLOLAKE select BOARD_ROMSIZE_KB_8192 + select HAVE_ACPI_TABLES config MAINBOARD_DIR string diff --git a/src/mainboard/intel/apollolake_rvp/acpi_tables.c b/src/mainboard/intel/apollolake_rvp/acpi_tables.c new file mode 100644 index 0000000..95de1f5 --- /dev/null +++ b/src/mainboard/intel/apollolake_rvp/acpi_tables.c @@ -0,0 +1,17 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corp. + * (Written by Lijian Zhao <lijian.zhao(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include <arch/acpi.h> + +void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt) +{ +} diff --git a/src/mainboard/intel/apollolake_rvp/dsdt.asl b/src/mainboard/intel/apollolake_rvp/dsdt.asl new file mode 100644 index 0000000..7b9fe29 --- /dev/null +++ b/src/mainboard/intel/apollolake_rvp/dsdt.asl @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corp. + * (Written by Lijian Zhao <lijian.zhao(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, /* DSDT revision: ACPI v2.0 */ + "COREv4", /* OEM id */ + "COREBOOT", /* OEM table id */ + 0x20110725 /* OEM revision */ +) +{ + Scope (\_SB) { + Device (PCI0) + { + Name (_HID, EISAID ("PNP0A08")) /* PCIe */ + } + } + +} diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index 4e05726..c425f2e 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -25,6 +25,8 @@ romstage-y += memmap.c romstage-y += mmap_boot.c smm-y += placeholders.c + +ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c ramstage-y += cpu.c ramstage-y += chip.c ramstage-y += placeholders.c diff --git a/src/soc/intel/apollolake/acpi.c b/src/soc/intel/apollolake/acpi.c new file mode 100644 index 0000000..d7249c2 --- /dev/null +++ b/src/soc/intel/apollolake/acpi.c @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corp. + * (Written by Lijian Zhao <lijian.zhao(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include <arch/acpi.h> + +unsigned long acpi_fill_mcfg(unsigned long current) +{ + return 0; +} +unsigned long acpi_fill_madt(unsigned long current) +{ + return 0; +}

1 0

New patch to review for coreboot: soc/intel/apollolake: utilize postcar phase/stage
by Aaron Durbin 18 Mar '16

18 Mar '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14141 -gerrit commit 0cb29560cbf00de217345d8b1c7b9036a48da515 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Mar 18 11:19:38 2016 -0500 soc/intel/apollolake: utilize postcar phase/stage The current Apollolake flow has its code executing out of cache-as-ram for the pre-DRAM stages. This is different from past platforms where they were just executing-in-place against the memory-mapped SPI flash boot media. The implication is that when cache-as-ram needs to be torn down one needs to be executing out of DRAM since the act of cache-as-ram going away means the code disappears out from under the processor. Therefore load and use the postcar infrastructure to bootstap this process for tearing down cache-as-ram and subsequently loading ramstage. Change-Id: I856f4b992dd2609b95375767bfa4fe64a267d89e Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/soc/intel/apollolake/Kconfig | 1 + src/soc/intel/apollolake/Makefile.inc | 5 +++ src/soc/intel/apollolake/bootblock/cache_as_ram.S | 7 ++-- src/soc/intel/apollolake/exit_car.S | 47 +++++++++++++++++++++++ src/soc/intel/apollolake/include/soc/cpu.h | 8 ++-- src/soc/intel/apollolake/include/soc/pci_devs.h | 2 +- src/soc/intel/apollolake/romstage.c | 7 +++- 7 files changed, 68 insertions(+), 9 deletions(-) diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index a11c5a2..efebe51 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -28,6 +28,7 @@ config CPU_SPECIFIC_OPTIONS select PCIEXP_COMMON_CLOCK select PCIEXP_CLK_PM select PCIEXP_L1_SUB_STATE + select POSTCAR_STAGE select REG_SCRIPT select RELOCATABLE_RAMSTAGE # Build fails if this is not selected select SOC_INTEL_COMMON diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index 4e05726..cac9100 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -35,6 +35,11 @@ ramstage-y += mmap_boot.c ramstage-y += uart.c ramstage-y += northbridge.c +postcar-y += exit_car.S +postcar-y += memmap.c +postcar-y += mmap_boot.c +postcar-$(CONFIG_SOC_UART_DEBUG) += uart_early.c + CPPFLAGS_common += -I$(src)/soc/intel/apollolake/include endif diff --git a/src/soc/intel/apollolake/bootblock/cache_as_ram.S b/src/soc/intel/apollolake/bootblock/cache_as_ram.S index c81fe0a..cc021dc 100644 --- a/src/soc/intel/apollolake/bootblock/cache_as_ram.S +++ b/src/soc/intel/apollolake/bootblock/cache_as_ram.S @@ -16,8 +16,7 @@ #include <cpu/x86/cache.h> #include <cpu/x86/cr.h> #include <cpu/x86/post_code.h> - -#define EVICT_CTL_MSR 0x2e0 +#include <soc/cpu.h> .global bootblock_pre_c_entry bootblock_pre_c_entry: @@ -96,7 +95,7 @@ clear_var_mtrr: mov %eax, %cr0 /* Disable cache eviction (setup stage) */ - mov $EVICT_CTL_MSR, %ecx + mov $MSR_EVICT_CTL, %ecx rdmsr or $0x1, %eax wrmsr @@ -112,7 +111,7 @@ clear_var_mtrr: post_code(0x27) /* Disable cache eviction (run stage) */ - mov $EVICT_CTL_MSR, %ecx + mov $MSR_EVICT_CTL, %ecx rdmsr or $0x2, %eax wrmsr diff --git a/src/soc/intel/apollolake/exit_car.S b/src/soc/intel/apollolake/exit_car.S new file mode 100644 index 0000000..339242b --- /dev/null +++ b/src/soc/intel/apollolake/exit_car.S @@ -0,0 +1,47 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <cpu/x86/mtrr.h> +#include <cpu/x86/cr.h> +#include <soc/cpu.h> + +.text +.global chipset_teardown_car +chipset_teardown_car: + /* + * Retrieve return address from stack as it will get trashed below if + * execution is utilizing the cache-as-ram stack. + */ + pop %ebx + + /* invalidate cache contents. */ + invd + /* Disable MTRRs. */ + mov $(MTRR_DEF_TYPE_MSR), %ecx + rdmsr + and $(~(MTRR_DEF_TYPE_EN | MTRR_DEF_TYPE_FIX_EN)), %eax + wrmsr + + /* Knock down bit 1 then bit 0 of NEM control not combining steps. */ + mov $(MSR_EVICT_CTL), %ecx + rdmsr + and $(~(1 << 1)), %eax + wrmsr + and $(~(1 << 0)), %eax + wrmsr + + /* Return to caller. */ + jmp *%ebx diff --git a/src/soc/intel/apollolake/include/soc/cpu.h b/src/soc/intel/apollolake/include/soc/cpu.h index 765be70..7c3228e 100644 --- a/src/soc/intel/apollolake/include/soc/cpu.h +++ b/src/soc/intel/apollolake/include/soc/cpu.h @@ -13,19 +13,21 @@ #ifndef _SOC_APOLLOLAKE_CPU_H_ #define _SOC_APOLLOLAKE_CPU_H_ +#ifndef __ASSEMBLER__ #include <cpu/x86/msr.h> #include <device/device.h> +void apollolake_init_cpus(struct device *dev); +#endif + #define CPUID_APOLLOLAKE_A0 0x506c8 #define CPUID_APOLLOLAKE_B0 0x506c9 #define MSR_PLATFORM_INFO 0xce #define MSR_POWER_MISC 0x120 #define MSR_CORE_THREAD_COUNT 0x35 +#define MSR_EVICT_CTL 0x2e0 #define BASE_CLOCK_MHZ 100 -void apollolake_init_cpus(struct device *dev); - - #endif /* _SOC_APOLLOLAKE_CPU_H_ */ diff --git a/src/soc/intel/apollolake/include/soc/pci_devs.h b/src/soc/intel/apollolake/include/soc/pci_devs.h index 3116389..2a65a22 100644 --- a/src/soc/intel/apollolake/include/soc/pci_devs.h +++ b/src/soc/intel/apollolake/include/soc/pci_devs.h @@ -7,7 +7,7 @@ #define _LPSS_PCI_DEVFN(slot, func) PCI_DEVFN(LPSS_DEV_SLOT_##slot, func) -#if ENV_RAMSTAGE +#if !defined(__SIMPLE_DEVICE__) #include <device/device.h> #include <device/pci_def.h> #define _NB_DEV(slot) dev_find_slot(0, _NB_DEVFN(slot)) diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c index 7c8924d..d24cdf8 100644 --- a/src/soc/intel/apollolake/romstage.c +++ b/src/soc/intel/apollolake/romstage.c @@ -11,6 +11,7 @@ * (at your option) any later version. */ +#include <arch/cpu.h> #include <arch/io.h> #include <arch/symbols.h> #include <cbfs.h> @@ -80,6 +81,7 @@ asmlinkage void car_stage_entry(void) void *hob_list_ptr; struct range_entry fsp_mem; struct range_entry reg_car; + struct postcar_frame pcf; printk(BIOS_DEBUG, "Starting romstage...\n"); @@ -109,7 +111,10 @@ asmlinkage void car_stage_entry(void) /* Now that CBMEM is up, save the list so ramstage can use it */ fsp_save_hob_list(hob_list_ptr); - run_ramstage(); + if (postcar_frame_init(&pcf, 1*KiB)) + die("Unable to initialize postcar frame.\n"); + + run_postcar_phase(&pcf); } static void fill_console_params(struct FSPM_UPD *mupd)

1 0

New patch to review for coreboot: arch/x86: introduce postcar stage/phase
by Aaron Durbin 18 Mar '16

18 Mar '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14140 -gerrit commit 216dd9df62f5d80d4ef30c26df94efe727b696e5 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Mar 18 12:21:23 2016 -0500 arch/x86: introduce postcar stage/phase Certain chipsets don't have a memory-mapped boot media so their code execution for stages prior to DRAM initialization is backed by SRAM or cache-as-ram. The postcar stage/phase handles the cache-as-ram situation where in order to tear down cache-as-ram one needs to be executing out of a backing store that isn't transient. By current definition, cache-as-ram is volatile and tearing it down leads to its contents disappearing. Therefore provide a shim layer, postcar, that's loaded into memory and executed which does 2 things: 1. Tears down cache-as-ram with a chipset helper function. 2. Loads and runs ramstage. Because those 2 things are executed out of ram there's no issue of the code's backing store while executing the code that tears down cache-as-ram. The current implementation makes no assumption regarding cacheability of the DRAM itself. If the chipset code wishes to cache DRAM for loading of the postcar stage/phase then it's also up to the chipset to handle any coherency issues pertaining to cache-as-ram destruction. Change-Id: Ia58efdadd0b48f20cfe7de2f49ab462306c3a19b Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- Makefile.inc | 2 +- src/arch/x86/Kconfig | 5 ++ src/arch/x86/Makefile.inc | 25 +++++++ src/arch/x86/exit_car.S | 106 ++++++++++++++++++++++++++ src/arch/x86/include/arch/cpu.h | 37 ++++++++++ src/arch/x86/memlayout.ld | 2 + src/arch/x86/postcar_loader.c | 115 +++++++++++++++++++++++++++++ src/commonlib/Makefile.inc | 4 + src/commonlib/include/commonlib/cbmem_id.h | 2 + src/console/Makefile.inc | 5 ++ src/cpu/x86/lapic/Makefile.inc | 1 + src/include/console/console.h | 2 +- src/include/memlayout.h | 12 +++ src/include/rules.h | 25 ++++++- src/lib/Makefile.inc | 27 ++++++- 15 files changed, 363 insertions(+), 7 deletions(-) diff --git a/Makefile.inc b/Makefile.inc index 87dc0f7..6be9d52 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -84,7 +84,7 @@ subdirs-y += site-local ####################################################################### # Add source classes and their build options -classes-y := ramstage romstage bootblock smm smmstub cpu_microcode libverstage verstage +classes-y := ramstage romstage bootblock postcar smm smmstub cpu_microcode libverstage verstage # Add dynamic classes for rmodules $(foreach supported_arch,$(ARCH_SUPPORTED), \ diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig index 4102b68..b174c2a 100644 --- a/src/arch/x86/Kconfig +++ b/src/arch/x86/Kconfig @@ -167,3 +167,8 @@ config ROMSTAGE_ADDR config VERSTAGE_ADDR hex default 0x2000000 + +# Use the post CAR infrastructure for tearing down cache-as-ram +# from a prgoram laoded in ram and subsequently loading ramstage. +config POSTCAR_STAGE + def_bool n diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 249cdd1..6980555 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -331,6 +331,7 @@ endif # CONFIG_ARCH_RAMSTAGE_X86_32 / CONFIG_ARCH_RAMSTAGE_X86_64 ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32)$(CONFIG_ARCH_ROMSTAGE_X86_64),y) +romstage-y += postcar_loader.c romstage-y += cbmem.c romstage-y += boot.c @@ -390,3 +391,27 @@ rmodules_x86_64-y += memmove.c endif endif # CONFIG_ARCH_RAMSTAGE_X86_32 / CONFIG_ARCH_RAMSTAGE_X86_64 + +$(eval $(call create_class_compiler,postcar,x86_32)) +postcar-generic-ccopts += -D__POSTCAR__ + +postcar-y += boot.c +postcar-y += cbfs_and_run.c +postcar-y += exit_car.S +postcar-y += memset.c +postcar-y += memcpy.c +postcar-y += memmove.c +postcar-y += memlayout.ld +postcar-$(CONFIG_X86_TOP4G_BOOTMEDIA_MAP) += mmap_boot.c + +$(objcbfs)/postcar.debug: $$(postcar-objs) + @printf " LINK $(subst $(obj)/,,$(@))\n" + $(LD_postcar) $(LDFLAGS_postcar) -o $@ -L$(obj) $(COMPILER_RT_FLAGS_postcar) --whole-archive --start-group $(filter-out %.ld,$^) --no-whole-archive $(COMPILER_RT_postcar) --end-group -T $(call src-to-obj,postcar,src/arch/x86/memlayout.ld) + +$(objcbfs)/postcar.elf: $(objcbfs)/postcar.debug.rmod + cp $< $@ + +cbfs-files-$(CONFIG_POSTCAR_STAGE) += $(CONFIG_CBFS_PREFIX)/postcar +$(CONFIG_CBFS_PREFIX)/postcar-file := $(objcbfs)/postcar.elf +$(CONFIG_CBFS_PREFIX)/postcar-type := stage +$(CONFIG_CBFS_PREFIX)/postcar-compression := none diff --git a/src/arch/x86/exit_car.S b/src/arch/x86/exit_car.S new file mode 100644 index 0000000..e7e2866 --- /dev/null +++ b/src/arch/x86/exit_car.S @@ -0,0 +1,106 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <cpu/x86/mtrr.h> +#include <cpu/x86/cr.h> + +.section ".module_parameters", "aw", @progbits +/* stack_top indicates the stack to pull MTRR information from. */ +stack_top: +.long 0 +.long 0 + +.text +.global _start +_start: + /* chipset_teardown_car() is expected to disable cache-as-ram. */ + call chipset_teardown_car + + /* Enable caching if not already enabled. */ + mov %cr0, %eax + and $(~(CR0_CD | CR0_NW)), %eax + mov %eax, %cr0 + + /* Ensure cache is clean. */ + invd + + /* Set up new stack. */ + mov stack_top, %esp + + /* + * Honor MTRR information pushed on the stack with the following + * layout: + * + * Offset: Value + * ... + * 0x14: MTRR mask 0 63:32 + * 0x10: MTRR mask 0 31:0 + * 0x0c: MTRR base 0 63:32 + * 0x08: MTRR base 0 31:0 + * 0x04: Number of variable MTRRs to set + * 0x00: Number of variable MTRRs to clear + */ + + /* Clear variable MTRRs. */ + pop %ebx /* Number to clear */ + test %ebx, %ebx + jz 2f + xor %eax, %eax + xor %edx, %edx + mov $(MTRR_PHYS_BASE(0)), %ecx +1: + wrmsr + inc %ecx + wrmsr + inc %ecx + dec %ebx + jnz 1b +2: + + /* Set Variable MTRRs based on stack contents. */ + pop %ebx /* Number to set. */ + test %ebx, %ebx + jz 2f + mov $(MTRR_PHYS_BASE(0)), %ecx +1: + /* Write MTRR base. */ + pop %eax + pop %edx + wrmsr + inc %ecx + /* Write MTRR mask. */ + pop %eax + pop %edx + wrmsr + inc %ecx + + dec %ebx + jnz 1b +2: + + /* Enable MTRR. */ + mov $(MTRR_DEF_TYPE_MSR), %ecx + rdmsr + /* Make default type uncacheable. */ + and $(~(MTRR_DEF_TYPE_MASK)), %eax + or $(MTRR_DEF_TYPE_EN), %eax + wrmsr + + /* Load and run ramstage. */ + call copy_and_run + /* Should never return. */ +1: + jmp 1b diff --git a/src/arch/x86/include/arch/cpu.h b/src/arch/x86/include/arch/cpu.h index f50901f..87663a7 100644 --- a/src/arch/x86/include/arch/cpu.h +++ b/src/arch/x86/include/arch/cpu.h @@ -15,6 +15,7 @@ #define ARCH_CPU_H #include <stdint.h> +#include <stddef.h> #include <rules.h> /* @@ -246,6 +247,42 @@ static inline void get_fms(struct cpuinfo_x86 *c, uint32_t tfms) * cache-as-ram. */ void asmlinkage car_stage_entry(void); + +/* + * Support setting up a stack frame consisting of MTRR information + * for use in bootstrapping the caching attributes after cache-as-ram + * is torn down. + */ + +struct postcar_frame { + uintptr_t stack; + uint32_t upper_mask; + int max_var_mttrs; + int num_var_mttrs; +}; + +/* + * Initialize postcar_frame object allocating stack size in cbmem + * with the provided size. Returns 0 on success, < 0 on error. + */ +int postcar_frame_init(struct postcar_frame *pcf, size_t stack_size); + +/* + * Add variable MTRR covering the provided range with MTRR type. + */ +void postcar_frame_add_mtrr(struct postcar_frame *pcf, + uintptr_t addr, size_t size, int type); + +/* + * Load and run a program that takes control of execution that + * tears down CAR and loads ramstage. The postcar_frame object + * indicates how to set up the frame. If caching is enabled at + * the time of the call it is up to the platform code to handle + * coherency with dirty lines in the cache using some mechansim + * such as platform_prog_run() becaus run_postcar_phase() + * utilizes prog_run() internally. + */ +void run_postcar_phase(struct postcar_frame *pcf); #endif #endif /* ARCH_CPU_H */ diff --git a/src/arch/x86/memlayout.ld b/src/arch/x86/memlayout.ld index 56611041..e6db0b8 100644 --- a/src/arch/x86/memlayout.ld +++ b/src/arch/x86/memlayout.ld @@ -51,6 +51,8 @@ SECTIONS /* Pull in the cache-as-ram rules. */ #include "car.ld" +#elif ENV_POSTCAR + POSTCAR(32M, 1M) #endif } diff --git a/src/arch/x86/postcar_loader.c b/src/arch/x86/postcar_loader.c new file mode 100644 index 0000000..580cc45 --- /dev/null +++ b/src/arch/x86/postcar_loader.c @@ -0,0 +1,115 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/cpu.h> +#include <cbmem.h> +#include <console/console.h> +#include <cpu/x86/msr.h> +#include <cpu/x86/mtrr.h> +#include <program_loading.h> +#include <rmodule.h> + +static inline void stack_push(struct postcar_frame *pcf, uint32_t val) +{ + uint32_t *ptr; + + pcf->stack -= sizeof(val); + ptr = (void *)pcf->stack; + *ptr = val; +} + +int postcar_frame_init(struct postcar_frame *pcf, size_t stack_size) +{ + void *stack; + msr_t msr; + + msr = rdmsr(MTRR_CAP_MSR); + + stack = cbmem_add(CBMEM_ID_ROMSTAGE_RAM_STACK, stack_size); + if (stack == NULL) { + printk(BIOS_ERR, "Couldn't add %zd byte stack in cbmem.\n", + stack_size); + return -1; + } + + pcf->stack = (uintptr_t)stack; + pcf->stack += stack_size; + + pcf->upper_mask = (1 << (cpu_phys_address_size() - 32)) - 1; + + pcf->max_var_mttrs = msr.lo & MTRR_CAP_VCNT; + + pcf->num_var_mttrs = 0; + + return 0; +} + +void postcar_frame_add_mtrr(struct postcar_frame *pcf, + uintptr_t addr, size_t size, int type) +{ + size_t align; + + if (pcf->num_var_mttrs >= pcf->max_var_mttrs) { + printk(BIOS_ERR, "No more variable MTRRs: %d\n", + pcf->max_var_mttrs); + return; + } + + /* Determine address alignment by lowest bit set in address. */ + align = addr & (addr ^ (addr - 1)); + + if (align < size) { + printk(BIOS_ERR, "Address (%lx) alignment (%zx) < size (%zx)\n", + addr, align, size); + size = align; + } + + /* Push MTRR mask then base -- upper 32-bits then lower 32-bits. */ + stack_push(pcf, pcf->upper_mask); + stack_push(pcf, ~(size - 1) | MTRR_PHYS_MASK_VALID); + stack_push(pcf, 0); + stack_push(pcf, addr | type); + pcf->num_var_mttrs++; +} + +void run_postcar_phase(struct postcar_frame *pcf) +{ + struct prog prog = + PROG_INIT(PROG_UNKNOWN, CONFIG_CBFS_PREFIX "/postcar"); + struct rmod_stage_load rsl = { + .cbmem_id = CBMEM_ID_AFTER_CAR, + .prog = &prog, + }; + + /* + * Place the number of used variable MTRRs on stack then max number + * of variable MTRRs supported in the system. + */ + stack_push(pcf, pcf->num_var_mttrs); + stack_push(pcf, pcf->max_var_mttrs); + + if (prog_locate(&prog)) + die("Failed to locate after CAR program.\n"); + if (rmodule_stage_load(&rsl)) + die("Failed to load after CAR program.\n"); + + /* Set the stack pointer within parameters of the program loaded. */ + if (rsl.params == NULL) + die("No parameters found in after CAR program.\n"); + + *(uintptr_t *)rsl.params = pcf->stack; + + prog_run(&prog); +} diff --git a/src/commonlib/Makefile.inc b/src/commonlib/Makefile.inc index 2752922..7c14f7c 100644 --- a/src/commonlib/Makefile.inc +++ b/src/commonlib/Makefile.inc @@ -2,12 +2,14 @@ bootblock-y += mem_pool.c verstage-y += mem_pool.c romstage-y += mem_pool.c ramstage-y += mem_pool.c +postcar-y += mem_pool.c bootblock-y += region.c verstage-y += region.c romstage-y += region.c ramstage-y += region.c smm-y += region.c +postcar-y += region.c ramstage-$(CONFIG_PLATFORM_USES_FSP1_1) += fsp1_1_relocate.c @@ -16,8 +18,10 @@ verstage-y += cbfs.c romstage-y += cbfs.c ramstage-y += cbfs.c smm-y += cbfs.c +postcar-y += cbfs.c bootblock-y += lz4_wrapper.c verstage-y += lz4_wrapper.c romstage-y += lz4_wrapper.c ramstage-y += lz4_wrapper.c +postcar-y += lz4_wrapper.c diff --git a/src/commonlib/include/commonlib/cbmem_id.h b/src/commonlib/include/commonlib/cbmem_id.h index 46c5d49..adeb291 100644 --- a/src/commonlib/include/commonlib/cbmem_id.h +++ b/src/commonlib/include/commonlib/cbmem_id.h @@ -20,6 +20,7 @@ #define CBMEM_ID_ACPI 0x41435049 #define CBMEM_ID_ACPI_GNVS 0x474e5653 #define CBMEM_ID_ACPI_GNVS_PTR 0x474e5650 +#define CBMEM_ID_AFTER_CAR 0xc4787a93 #define CBMEM_ID_AGESA_RUNTIME 0x41474553 #define CBMEM_ID_AMDMCT_MEMINFO 0x494D454E #define CBMEM_ID_CAR_GLOBALS 0xcac4e6a3 @@ -71,6 +72,7 @@ { CBMEM_ID_ACPI_GNVS, "ACPI GNVS " }, \ { CBMEM_ID_ACPI_GNVS_PTR, "GNVS PTR " }, \ { CBMEM_ID_AGESA_RUNTIME, "AGESA RSVD " }, \ + { CBMEM_ID_AFTER_CAR, "AFTER CAR" }, \ { CBMEM_ID_AMDMCT_MEMINFO, "AMDMEM INFO" }, \ { CBMEM_ID_CAR_GLOBALS, "CAR GLOBALS" }, \ { CBMEM_ID_CBTABLE, "COREBOOT " }, \ diff --git a/src/console/Makefile.inc b/src/console/Makefile.inc index 94b456c..0fee12a 100644 --- a/src/console/Makefile.inc +++ b/src/console/Makefile.inc @@ -18,6 +18,11 @@ romstage-y += init.c console.c romstage-y += post.c romstage-y += die.c +postcar-y += vtxprintf.c printk.c +postcar-y += init.c console.c +postcar-y += post.c +postcar-y += die.c + bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += vtxprintf.c printk.c bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += init.c console.c bootblock-y += die.c diff --git a/src/cpu/x86/lapic/Makefile.inc b/src/cpu/x86/lapic/Makefile.inc index c0a3572..9df2c5f 100644 --- a/src/cpu/x86/lapic/Makefile.inc +++ b/src/cpu/x86/lapic/Makefile.inc @@ -7,3 +7,4 @@ bootblock-y += boot_cpu.c verstage-y += boot_cpu.c romstage-y += boot_cpu.c ramstage-y += boot_cpu.c +postcar-y += boot_cpu.c diff --git a/src/include/console/console.h b/src/include/console/console.h index 7704899..ddb5c052 100644 --- a/src/include/console/console.h +++ b/src/include/console/console.h @@ -47,7 +47,7 @@ void __attribute__ ((noreturn)) die(const char *msg); #define __CONSOLE_ENABLE__ \ ((ENV_BOOTBLOCK && CONFIG_BOOTBLOCK_CONSOLE) || \ - ENV_VERSTAGE || ENV_ROMSTAGE || ENV_RAMSTAGE || \ + ENV_VERSTAGE || ENV_ROMSTAGE || ENV_RAMSTAGE || ENV_POSTCAR || \ (ENV_SMM && CONFIG_DEBUG_SMI)) #if __CONSOLE_ENABLE__ diff --git a/src/include/memlayout.h b/src/include/memlayout.h index 49aa1cc..43a1cac 100644 --- a/src/include/memlayout.h +++ b/src/include/memlayout.h @@ -160,6 +160,18 @@ #define OVERLAP_VERSTAGE_ROMSTAGE(addr, size) ROMSTAGE(addr, size) #endif +#if ENV_POSTCAR + #define POSTCAR(addr, sz) \ + SYMBOL(postcar, addr) \ + _epostcar = _postcar + sz; \ + _ = ASSERT(_eprogram - _program <= sz, \ + STR(Aftercar exceeded its allotted size! (sz))); \ + INCLUDE "postcar/lib/program.ld" +#else + #define POSTCAR(addr, sz) \ + REGION(postcar, addr, sz, 1) +#endif + #define WATCHDOG_TOMBSTONE(addr, size) \ REGION(watchdog_tombstone, addr, size, 4) \ _ = ASSERT(size == 4, "watchdog tombstones should be exactly 4 byte!"); diff --git a/src/include/rules.h b/src/include/rules.h index 6a05ae9..89fdd21 100644 --- a/src/include/rules.h +++ b/src/include/rules.h @@ -26,6 +26,7 @@ #define ENV_SMM 0 #define ENV_VERSTAGE 0 #define ENV_RMODULE 0 +#define ENV_POSTCAR 0 #define ENV_STRING "bootblock" #elif defined(__ROMSTAGE__) @@ -35,6 +36,7 @@ #define ENV_SMM 0 #define ENV_VERSTAGE 0 #define ENV_RMODULE 0 +#define ENV_POSTCAR 0 #define ENV_STRING "romstage" #elif defined(__SMM__) @@ -44,6 +46,7 @@ #define ENV_SMM 1 #define ENV_VERSTAGE 0 #define ENV_RMODULE 0 +#define ENV_POSTCAR 0 #define ENV_STRING "smm" #elif defined(__VERSTAGE__) @@ -53,6 +56,7 @@ #define ENV_SMM 0 #define ENV_VERSTAGE 1 #define ENV_RMODULE 0 +#define ENV_POSTCAR 0 #define ENV_STRING "verstage" #elif defined(__RAMSTAGE__) @@ -62,6 +66,7 @@ #define ENV_SMM 0 #define ENV_VERSTAGE 0 #define ENV_RMODULE 0 +#define ENV_POSTCAR 0 #define ENV_STRING "ramstage" #elif defined(__RMODULE__) @@ -71,8 +76,19 @@ #define ENV_SMM 0 #define ENV_VERSTAGE 0 #define ENV_RMODULE 1 +#define ENV_POSTCAR 0 #define ENV_STRING "rmodule" +#elif defined(__POSTCAR__) +#define ENV_BOOTBLOCK 0 +#define ENV_ROMSTAGE 0 +#define ENV_RAMSTAGE 0 +#define ENV_SMM 0 +#define ENV_VERSTAGE 0 +#define ENV_RMODULE 0 +#define ENV_POSTCAR 1 +#define ENV_STRING "postcar" + #else /* * Default case of nothing set for random blob generation using @@ -86,18 +102,21 @@ #define ENV_SMM 0 #define ENV_VERSTAGE 0 #define ENV_RMODULE 0 +#define ENV_POSTCAR 0 #define ENV_STRING "UNKNOWN" #endif -/* For romstage and ramstage always build with simple device model, ie. - * PCI, PNP and CPU functions operate without use of devicetree. +/* For pre-DRAM stages and post-CAR always build with simple device model, ie. + * PCI, PNP and CPU functions operate without use of devicetree. The reason + * post-CAR utilizes __SIMPLE_DEVICE__ is for simplicity. Currently there's + * no known requirement that devicetree would be needed during that stage. * * For ramstage individual source file may define __SIMPLE_DEVICE__ * before including any header files to force that particular source * be built with simple device model. */ -#if defined(__PRE_RAM__) || defined(__SMM__) +#if defined(__PRE_RAM__) || ENV_SMM || ENV_POSTCAR #define __SIMPLE_DEVICE__ #endif diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 646fefa..3352a30 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -131,13 +131,16 @@ ramstage-$(CONFIG_ACPI_NHLT) += nhlt.c romstage-y += cbmem_common.c romstage-y += imd_cbmem.c +romstage-y += imd.c ramstage-y += cbmem_common.c ramstage-y += imd_cbmem.c - -romstage-y += imd.c ramstage-y += imd.c +postcar-y += cbmem_common.c +postcar-y += imd_cbmem.c +postcar-y += imd.c + bootblock-y += hexdump.c ramstage-y += hexdump.c romstage-y += hexdump.c @@ -167,12 +170,14 @@ romstage-y += version.c ramstage-y += version.c smm-y += version.c verstage-y += version.c +postcar-y += version.c $(call src-to-obj,bootblock,$(dir)/version.c) : $(obj)/build.h $(call src-to-obj,romstage,$(dir)/version.c) : $(obj)/build.h $(call src-to-obj,ramstage,$(dir)/version.c) : $(obj)/build.h $(call src-to-obj,smm,$(dir)/version.c) : $(obj)/build.h $(call src-to-obj,verstage,$(dir)/version.c) : $(obj)/build.h +$(call src-to-obj,postcar,$(dir)/version.c) : $(obj)/build.h romstage-y += bootmode.c ramstage-y += bootmode.c @@ -183,9 +188,27 @@ romstage-y += halt.c ramstage-y += halt.c smm-y += halt.c +postcar-y += bootmode.c +postcar-y += boot_device.c +postcar-y += cbfs.c +postcar-$(CONFIG_COMMON_CBFS_SPI_WRAPPER) += cbfs_spi.c +postcar-y += delay.c +postcar-y += fmap.c +postcar-y += gcc.c +postcar-y += halt.c +postcar-y += libgcc.c +postcar-$(CONFIG_COMPRESS_RAMSTAGE) += lzma.c lzmadecode.c +postcar-y += memchr.c +postcar-y += memcmp.c +postcar-y += prog_loaders.c +postcar-y += prog_ops.c +postcar-y += rmodule.c +postcar-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c + # Use program.ld for all the platforms which use C fo the bootblock. bootblock-$(CONFIG_C_ENVIRONMENT_BOOTBLOCK) += program.ld +postcar-y += program.ld romstage-y += program.ld ramstage-y += program.ld verstage-y += program.ld

1 0

New patch to review for coreboot: lib/rmodule: export parameters in struct rmod_stage_load
by Aaron Durbin 18 Mar '16

18 Mar '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14139 -gerrit commit b23dd2f5b21c4bf5a4fa8aeb1bbbfad428f53d62 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Mar 17 23:13:34 2016 -0500 lib/rmodule: export parameters in struct rmod_stage_load In order for a caller to utilize an rmodule's parameters section after calling rmodule_stage_load() export the rmodule's parameter pointer in struct rmod_stage_load. Change-Id: I9cd51652cf8cdb3fae773256989851638aa1a60f Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/include/rmodule.h | 1 + src/lib/rmodule.c | 3 +++ 2 files changed, 4 insertions(+) diff --git a/src/include/rmodule.h b/src/include/rmodule.h index a2612d1..c0c062c 100644 --- a/src/include/rmodule.h +++ b/src/include/rmodule.h @@ -55,6 +55,7 @@ struct prog; struct rmod_stage_load { uint32_t cbmem_id; struct prog *prog; + void *params; }; /* Both of the following functions return 0 on success, -1 on error. */ diff --git a/src/lib/rmodule.c b/src/lib/rmodule.c index 585fb5f..9825e6a 100644 --- a/src/lib/rmodule.c +++ b/src/lib/rmodule.c @@ -296,5 +296,8 @@ int rmodule_stage_load(struct rmod_stage_load *rsl) rmodule_memory_size(&rmod_stage)); prog_set_entry(rsl->prog, rmodule_entry(&rmod_stage), NULL); + /* Allow caller to pick up parameters, if available. */ + rsl->params = rmodule_parameters(&rmod_stage); + return 0; }

1 0

Patch set updated for coreboot: util/intelmetool: Add intelmetool from Damien Zammit
by Philipp Deppenwiese 18 Mar '16

18 Mar '16

Philipp Deppenwiese (zaolin.daisuki(a)googlemail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14136 -gerrit commit cb5d03836efb103d22d78e7e615bcf1edc4b8f8f Author: Philipp Deppenwiese <zaolin(a)das-labor.org> Date: Fri Mar 18 00:52:54 2016 +0100 util/intelmetool: Add intelmetool from Damien Zammit The intelmetool shows information about the Intel Management Engine for different platforms. Original source code can be found under following link: https://github.com/zamaudio/intelmetool.git Change-Id: I0eb17833a21eb04cf9245a7312289a4102bec1a9 Signed-off-by: Philipp Deppenwiese <zaolin(a)das-labor.org> --- util/intelmetool/Makefile | 87 ++++++ util/intelmetool/intelmetool.c | 312 ++++++++++++++++++++ util/intelmetool/intelmetool.h | 238 +++++++++++++++ util/intelmetool/me.c | 638 +++++++++++++++++++++++++++++++++++++++++ util/intelmetool/me.h | 409 ++++++++++++++++++++++++++ util/intelmetool/me_status.c | 205 +++++++++++++ util/intelmetool/mmap.c | 56 ++++ util/intelmetool/mmap.h | 24 ++ 8 files changed, 1969 insertions(+) diff --git a/util/intelmetool/Makefile b/util/intelmetool/Makefile new file mode 100644 index 0000000..c5dfa86 --- /dev/null +++ b/util/intelmetool/Makefile @@ -0,0 +1,87 @@ +# intelmetool + +# Copyright (C) 2013-2015 Damien Zammit <damien(a)zamaudio.com> + +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or any later version. + +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. + +PROGRAM = intelmetool + +CC ?= gcc +INSTALL ?= /usr/bin/install +PREFIX ?= /usr/local +CFLAGS ?= -O0 -g -Wall -W -Wno-unused-parameter -Wno-unused-but-set-variable -Wno-sign-compare +LDFLAGS += -lpci -lz + +OBJS = intelmetool.o me.o me_status.o mmap.o + +OS_ARCH = $(shell uname) +ifeq ($(OS_ARCH), Darwin) +LDFLAGS += -framework DirectHW +endif +ifeq ($(OS_ARCH), FreeBSD) +CFLAGS += -I/usr/local/include +LDFLAGS += -L/usr/local/lib +LIBS = -lz +endif +ifeq ($(OS_ARCH), NetBSD) +CFLAGS += -I/usr/pkg/include +LDFLAGS += -L/usr/pkg/lib -Wl,-rpath-link,/usr/pkg/lib -lz -lpciutils -lpci -l$(shell uname -p) +endif + +all: pciutils dep $(PROGRAM) + +$(PROGRAM): $(OBJS) + $(CC) $(CFLAGS) -o $(PROGRAM) $(OBJS) $(LDFLAGS) + +clean: + rm -f $(PROGRAM) *.o *~ junit.xml + +distclean: clean + rm -f .dependencies + +dep: + @$(CC) $(CFLAGS) -MM *.c > .dependencies + +define LIBPCI_TEST +/* Avoid a failing test due to libpci header symbol shadowing breakage */ +#define index shadow_workaround_index +#ifdef __NetBSD__ +#include <pciutils/pci.h> +#else +#include <pci/pci.h> +#endif +struct pci_access *pacc; +int main(int argc, char **argv) +{ + (void) argc; + (void) argv; + pacc = pci_alloc(); + return 0; +} +endef +export LIBPCI_TEST + +pciutils: + @printf "\nChecking for pciutils and zlib... " + @echo "$$LIBPCI_TEST" > .test.c + @$(CC) $(CFLAGS) .test.c -o .test $(LDFLAGS) >/dev/null 2>&1 && \ + printf "found.\n" || ( printf "not found.\n\n"; \ + printf "Please install pciutils-devel and zlib-devel.\n"; \ + rm -f .test.c .test; exit 1) + @rm -rf .test.c .test .test.dSYM + +install: $(PROGRAM) + mkdir -p $(DESTDIR)$(PREFIX)/sbin + $(INSTALL) $(PROGRAM) $(DESTDIR)$(PREFIX)/sbin + +.PHONY: all clean distclean dep pciutils + +-include .dependencies diff --git a/util/intelmetool/intelmetool.c b/util/intelmetool/intelmetool.c new file mode 100644 index 0000000..b81d6ce --- /dev/null +++ b/util/intelmetool/intelmetool.c @@ -0,0 +1,312 @@ +/* intelmetool Dump interesting things about Management Engine even if hidden + * Copyright (C) 2014 Damien Zammit <damien(a)zamaudio.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdio.h> +#include <inttypes.h> +#include <pci/pci.h> +#include <sys/io.h> +#include <stdlib.h> +#include "me.h" +#include "mmap.h" +#include "intelmetool.h" + +extern int fd_mem; +#define FD2 0x3428 + +void dumpmem(uint8_t *phys, uint32_t size) +{ + uint32_t i; + printf("Dumping cloned ME memory:\n"); + for (i = 0; i < size; i++) { + printf("%02X",*((uint8_t *) (phys + i))); + } + printf("\n"); +} + +void zeroit(uint8_t *phys, uint32_t size) +{ + uint32_t i; + for (i = 0; i < size; i++) { + *((uint8_t *) (phys + i)) = 0x00; + } +} + +void dumpmemfile(uint8_t *phys, uint32_t size) +{ + FILE *fp = fopen("medump.bin", "w"); + uint32_t i; + for (i = 0; i < size; i++) { + fprintf(fp, "%c", *((uint8_t *) (phys + i))); + } + fclose(fp); +} + +int main(void) +{ + struct pci_access *pacc; + struct pci_dev *dev; + struct pci_dev *sb; + uint32_t stat, stat2; + char namebuf[1024], *name; + int size = 0x4000; + if (iopl(3)) { + perror("iopl"); + printf("You need to be root\n"); + exit(1); + } + + if ((fd_mem = open("/dev/mem", O_RDWR)) < 0) { + perror("Can not open /dev/mem"); + exit(1); + } + + volatile uint8_t *rcba; + uint32_t rcba_phys; + uint32_t fd2; + uint8_t me; + + pacc = pci_alloc(); + pacc->method = PCI_ACCESS_I386_TYPE1; + pci_init(pacc); + pci_scan_bus(pacc); + me = ME_FOUND_NOTHING; + for (dev=pacc->devices; dev; dev=dev->next) { + pci_fill_info(dev, PCI_FILL_IDENT | PCI_FILL_BASES | PCI_FILL_SIZES | PCI_FILL_CLASS); + name = pci_lookup_name(pacc, namebuf, sizeof(namebuf), + PCI_LOOKUP_DEVICE, dev->vendor_id, dev->device_id); + if (dev->vendor_id == 0x8086) { + if (PCI_DEV_NO_ME(dev->device_id)) { + me = ME_NOT_PRESENT; + break; + } + if (PCI_DEV_HAS_ME_DISABLE(dev->device_id)) { + me = ME_PRESENT_CAN_DISABLE; + break; + } + if (PCI_DEV_HAS_ME_DIFFICULT(dev->device_id)) { + me = ME_PRESENT_CANNOT_DISABLE; + break; + } + if (PCI_DEV_CAN_DISABLE_ME_IF_PRESENT(dev->device_id)) { + me = ME_CAN_DISABLE_IF_PRESENT; + break; + } + if (PCI_DEV_ME_NOT_SURE(dev->device_id)) { + me = ME_FOUND_SOMETHING_NOT_SURE; + break; + } + } + } + + switch (me) { + case ME_FOUND_NOTHING: + printf("Hardware unsupported by intelmetool, exiting\n"); + pci_cleanup(pacc); + exit(ME_FOUND_NOTHING); + break; + case ME_FOUND_SOMETHING_NOT_SURE: + printf("Found `%s`. Not sure whether you have ME hardware, exiting\n", name); + pci_cleanup(pacc); + exit(ME_FOUND_SOMETHING_NOT_SURE); + break; + case ME_NOT_PRESENT: + printf("ME is not present on your board because we found a `%s`, you are safe, exiting\n", name); + pci_cleanup(pacc); + exit(ME_NOT_PRESENT); + break; + case ME_CAN_DISABLE_IF_PRESENT: + printf("Not sure if ME hardware is present because you have a `%s`, but it is possible to disable it if you do, continuing...\n", name); + break; + case ME_PRESENT_CANNOT_DISABLE: + printf("Bad news, you have a `%s` so you have ME hardware on board and it is very difficult to remove, continuing...\n", name); + break; + case ME_PRESENT_CAN_DISABLE: + printf("Good news, you have a `%s` so ME is present but can be disabled, continuing...\n", name); + break; + default: + printf("Something horrible happened, exiting\n"); + pci_cleanup(pacc); + exit(1); + break; + } + + + pacc = pci_alloc(); + pacc->method = PCI_ACCESS_I386_TYPE1; + pci_init(pacc); + pci_scan_bus(pacc); + sb = pci_get_dev(pacc, 0, 0, 0x1f, 0); + if (!sb) { + printf("Uh oh, southbridge not on BDF(0:31:0), please report this error, exiting.\n"); + pci_cleanup(pacc); + exit(1); + } + pci_fill_info(sb, PCI_FILL_IDENT | PCI_FILL_BASES | PCI_FILL_SIZES | PCI_FILL_CLASS); + + /* Enable MEI */ + rcba_phys = pci_read_long(sb, 0xf0) & 0xfffffffe; + rcba = map_physical(rcba_phys, size); + printf("RCBA at 0x%08" PRIx32 "\n", (uint32_t)rcba_phys); + fd2 = *(uint32_t *)(rcba + FD2); + *(uint32_t *)(rcba + FD2) = fd2 & ~0x2; + if (fd2 & 0x2) { + printf("MEI was hidden on PCI, now unlocked\n"); + } else { + printf("MEI not hidden on PCI, checking if visible\n"); + } + + pci_cleanup(pacc); + + pacc = pci_alloc(); + pacc->method = PCI_ACCESS_I386_TYPE1; + pci_init(pacc); + pci_scan_bus(pacc); + me = 0; + for (dev=pacc->devices; dev; dev=dev->next) { + pci_fill_info(dev, PCI_FILL_IDENT | PCI_FILL_BASES | PCI_FILL_SIZES | PCI_FILL_CLASS); + name = pci_lookup_name(pacc, namebuf, sizeof(namebuf), + PCI_LOOKUP_DEVICE, dev->vendor_id, dev->device_id); + if (dev->vendor_id == 0x8086) { + switch (dev->device_id) { + case 0x1C3A: /* Cougar Point */ + case 0x1CBA: /* Panther Point */ + case 0x1D3A: /* C600/X79 Patsburg */ + case 0x1DBA: /* Panther Point */ + case 0x1E3A: /* Panther Point */ + case 0x2364: /* Cave Creek */ + case 0x28B4: /* Bearlake */ + case 0x28C4: /* Bearlake */ + case 0x28D4: /* Bearlake */ + case 0x28E4: /* Bearlake */ + case 0x28F4: /* Bearlake */ + case 0x2974: /* 82946GZ/GL */ + case 0x2984: /* 82G35 Express */ + case 0x2994: /* 82Q963/Q965 */ + case 0x29A4: /* 82P965/G965 */ + case 0x29B4: /* 82Q35 Express */ + case 0x29C4: /* 82G33/G31/P35/P31 Express */ + case 0x29D4: /* 82Q33 Express */ + case 0x29E4: /* 82X38/X48 Express */ + case 0x29F4: /* 3200/3210 Server */ + case 0x2A04: /* Mobile PM965/GM965 */ + case 0x2A14: /* Mobile GME965/GLE960 */ + case 0x2A44: /* Cantiga */ + case 0x2a50: /* Cantiga */ + case 0x2A54: /* Cantiga */ + case 0x2A64: /* Cantiga */ + case 0x2A74: /* Cantiga */ + case 0x2E04: /* Eaglelake */ + case 0x2E14: /* Eaglelake */ + case 0x2E24: /* Eaglelake */ + case 0x2E34: /* Eaglelake */ + case 0x3B64: /* Calpella */ + case 0x3B65: /* Calpella */ + case 0x8C3A: /* Lynx Point H */ + case 0x8CBA: /* Lynx Point H Refresh */ + case 0x8D3A: /* Lynx Point - Wellsburg */ + case 0x9C3A: /* Lynx Point LP */ + case 0x9CBA: /* Wildcat Point LP */ + case 0x9CBB: /* Wildcat Point LP 2 */ + me = 1; + break; + default: + me = 0; + break; + } + } + if (me) break; + } + if (me == 0) { + printf("MEI device not found, huh?\n"); + if (fd2 & 0x2) { + printf("Re-hiding MEI device..."); + fd2 = *(uint32_t *)(rcba + FD2); + *(uint32_t *)(rcba + FD2) = fd2 | 0x2; + printf("done\n"); + } + printf ("exiting\n"); + pci_cleanup(pacc); + munmap((void*)rcba, size); + return 0; + } + + printf("MEI found: [%x:%x] %s\n\n", dev->vendor_id, dev->device_id, name); + stat = pci_read_long(dev, 0x40); + printf("ME Status : 0x%x\n", stat); + stat2 = pci_read_long(dev, 0x48); + printf("ME Status 2 : 0x%x\n\n", stat2); + + intel_me_status(stat, stat2); + printf("\n"); + intel_me_extend_valid(dev); + printf("\n"); + + if ((stat & 0xf000) >> 12 == 0) { + printf("ME seems okay on this board\n"); + } else { + printf("ME has a broken implementation on your board with this BIOS\n"); + } + + intel_mei_setup(dev); + udelay(1000); + mei_reset(); + udelay(10000); + mkhi_get_fw_version(); + udelay(10000); + mei_reset(); + udelay(10000); + mkhi_get_fwcaps(); + udelay(10000); + + /* You need >4GB total ram, in kernel cmdline, use 'mem=1000m' + * then this code will clone to absolute memory address 0xe0000000 + * which can be read using a mmap tool at that offset. + * Real ME memory is located around top of memory minus 64MB. (I think) + * so we avoid cloning to this part. + */ +/* + uint32_t me_clone = 0x60000000; + volatile uint8_t *dump; + dump = map_physical_exact(me_clone, me_clone, 0x2000000); + zeroit(dump, 0x2000000); + printf("Send magic command for memory clone\n"); + + mei_reset(); + udelay(10000); + int err = mkhi_debug_me_memory(me_clone); + + if (!err) { + printf("Wait a second..."); + udelay(30000); + printf("done\n\nHere are the first bytes:\n"); + dumpmemfile(dump, 0x2000000); + printf("Try reading 0x%zx with other mmap tool...\n" + "Press enter to quit, you only get one chance to run this tool before reboot required for some reason\n", me_clone); + while (getc(stdin) != '\n') {}; + unmap_physical(dump, 0x2000000); + } +*/ + intel_mei_unmap(); + + pci_cleanup(pacc); + + if (fd2 & 0x2) { + printf("Re-hiding MEI device..."); + fd2 = *(uint32_t *)(rcba + FD2); + *(uint32_t *)(rcba + FD2) = fd2 | 0x2; + printf("done, "); + } + printf("exiting\n"); + munmap((void*)rcba, size); + return 0; +} diff --git a/util/intelmetool/intelmetool.h b/util/intelmetool/intelmetool.h new file mode 100644 index 0000000..a0088b9 --- /dev/null +++ b/util/intelmetool/intelmetool.h @@ -0,0 +1,238 @@ +/* + * intelmetool + * + * Copyright (C) 2008-2010 by coresystems GmbH + * Copyright (C) 2009 Carl-Daniel Hailfinger + * Copyright (C) 2015 Damien Zammit + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define ME_NOT_PRESENT 0 +#define ME_FOUND_NOTHING 1 +#define ME_FOUND_SOMETHING_NOT_SURE 2 +#define ME_CAN_DISABLE_IF_PRESENT 3 +#define ME_PRESENT_CAN_DISABLE 4 +#define ME_PRESENT_CANNOT_DISABLE 5 + +// If any of the following pci device IDs are found, +// the heading they fall under is the corresponding result. + +// Chipset does not have ME +#define PCI_DEVICE_ID_INTEL_82810 0x7120 +#define PCI_DEVICE_ID_INTEL_82810_DC 0x7122 +#define PCI_DEVICE_ID_INTEL_82810E_DC 0x7124 +#define PCI_DEVICE_ID_INTEL_82830M 0x3575 +#define PCI_DEVICE_ID_INTEL_82845 0x1a30 +#define PCI_DEVICE_ID_INTEL_82865 0x2570 +#define PCI_DEVICE_ID_INTEL_82915 0x2580 +#define PCI_DEVICE_ID_INTEL_82945P 0x2770 +#define PCI_DEVICE_ID_INTEL_82945GM 0x27a0 +#define PCI_DEVICE_ID_INTEL_82945GSE 0x27ac +#define PCI_DEVICE_ID_INTEL_82X58 0x3405 +#define PCI_DEVICE_ID_INTEL_ATOM_DXXX 0xa000 +#define PCI_DEVICE_ID_INTEL_I63XX 0x2670 +#define PCI_DEVICE_ID_INTEL_I5000X 0x25c0 +#define PCI_DEVICE_ID_INTEL_I5000Z 0x25d0 +#define PCI_DEVICE_ID_INTEL_I5000V 0x25d4 +#define PCI_DEVICE_ID_INTEL_I5000P 0x25d8 +#define PCI_DEVICE_ID_INTEL_82443LX 0x7180 +#define PCI_DEVICE_ID_INTEL_82443BX 0x7190 +#define PCI_DEVICE_ID_INTEL_82443BX_NO_AGP 0x7192 +#define PCI_DEVICE_ID_INTEL_82371XX 0x7110 +#define PCI_DEVICE_ID_INTEL_ICH 0x2410 +#define PCI_DEVICE_ID_INTEL_ICH0 0x2420 +#define PCI_DEVICE_ID_INTEL_ICH2 0x2440 +#define PCI_DEVICE_ID_INTEL_ICH4 0x24c0 +#define PCI_DEVICE_ID_INTEL_ICH4M 0x24cc +#define PCI_DEVICE_ID_INTEL_ICH5 0x24d0 +#define PCI_DEVICE_ID_INTEL_ICH6 0x2640 +#define PCI_DEVICE_ID_INTEL_ICH7DH 0x27b0 +#define PCI_DEVICE_ID_INTEL_ICH7 0x27b8 +#define PCI_DEVICE_ID_INTEL_ICH7M 0x27b9 +#define PCI_DEVICE_ID_INTEL_ICH7MDH 0x27bd +#define PCI_DEVICE_ID_INTEL_NM10 0x27bc + +#define PCI_DEV_NO_ME(x) ( \ + ( (x) == PCI_DEVICE_ID_INTEL_82810 ) || \ + ( (x) == PCI_DEVICE_ID_INTEL_82810_DC ) || \ + ( (x) == PCI_DEVICE_ID_INTEL_82810E_DC ) || \ + ( (x) == PCI_DEVICE_ID_INTEL_82830M ) || \ + ( (x) == PCI_DEVICE_ID_INTEL_82845 ) || \ + ( (x) == PCI_DEVICE_ID_INTEL_82865 ) || \ + ( (x) == PCI_DEVICE_ID_INTEL_82915 ) || \ + ( (x) == PCI_DEVICE_ID_INTEL_82945P ) || \ + ( (x) == PCI_DEVICE_ID_INTEL_82945GM ) || \ + ( (x) == PCI_DEVICE_ID_INTEL_82945GSE ) || \ + ( (x) == PCI_DEVICE_ID_INTEL_82X58 ) || \ + ( (x) == PCI_DEVICE_ID_INTEL_ATOM_DXXX ) || \ + ( (x) == PCI_DEVICE_ID_INTEL_I63XX ) || \ + ( (x) == PCI_DEVICE_ID_INTEL_I5000X ) || \ + ( (x) == PCI_DEVICE_ID_INTEL_I5000Z ) || \ + ( (x) == PCI_DEVICE_ID_INTEL_I5000V ) || \ + ( (x) == PCI_DEVICE_ID_INTEL_I5000P ) || \ + ( (x) == PCI_DEVICE_ID_INTEL_82443LX ) || \ + ( (x) == PCI_DEVICE_ID_INTEL_82443BX ) || \ + ( (x) == PCI_DEVICE_ID_INTEL_82443BX_NO_AGP) || \ + ( (x) == PCI_DEVICE_ID_INTEL_82371XX ) || \ + ( (x) == PCI_DEVICE_ID_INTEL_ICH ) || \ + ( (x) == PCI_DEVICE_ID_INTEL_ICH0 ) || \ + ( (x) == PCI_DEVICE_ID_INTEL_ICH2 ) || \ + ( (x) == PCI_DEVICE_ID_INTEL_ICH4 ) || \ + ( (x) == PCI_DEVICE_ID_INTEL_ICH4M ) || \ + ( (x) == PCI_DEVICE_ID_INTEL_ICH5 ) || \ + ( (x) == PCI_DEVICE_ID_INTEL_ICH6 ) || \ + ( (x) == PCI_DEVICE_ID_INTEL_ICH7DH ) || \ + ( (x) == PCI_DEVICE_ID_INTEL_ICH7 ) || \ + ( (x) == PCI_DEVICE_ID_INTEL_ICH7M ) || \ + ( (x) == PCI_DEVICE_ID_INTEL_ICH7MDH ) || \ + ( (x) == PCI_DEVICE_ID_INTEL_NM10 )) + +// Definitely has ME and can be disabled +#define PCI_DEVICE_ID_INTEL_ICH8ME 0x2811 +#define PCI_DEVICE_ID_INTEL_ICH9ME 0x2917 +#define PCI_DEVICE_ID_INTEL_ICH9M 0x2919 + +#define PCI_DEV_HAS_ME_DISABLE(x) ( \ + ( (x) == PCI_DEVICE_ID_INTEL_ICH8ME ) || \ + ( (x) == PCI_DEVICE_ID_INTEL_ICH9ME ) || \ + ( (x) == PCI_DEVICE_ID_INTEL_ICH9M )) + +// Definitely has ME and is very difficult to remove +#define PCI_DEVICE_ID_INTEL_ICH10R 0x3a16 +#define PCI_DEVICE_ID_INTEL_3400_DESKTOP 0x3b00 +#define PCI_DEVICE_ID_INTEL_3400_MOBILE 0x3b01 +#define PCI_DEVICE_ID_INTEL_P55 0x3b02 +#define PCI_DEVICE_ID_INTEL_PM55 0x3b03 +#define PCI_DEVICE_ID_INTEL_H55 0x3b06 +#define PCI_DEVICE_ID_INTEL_QM57 0x3b07 +#define PCI_DEVICE_ID_INTEL_H57 0x3b08 +#define PCI_DEVICE_ID_INTEL_HM55 0x3b09 +#define PCI_DEVICE_ID_INTEL_Q57 0x3b0a +#define PCI_DEVICE_ID_INTEL_HM57 0x3b0b +#define PCI_DEVICE_ID_INTEL_3400_MOBILE_SFF 0x3b0d +#define PCI_DEVICE_ID_INTEL_B55_A 0x3b0e +#define PCI_DEVICE_ID_INTEL_QS57 0x3b0f +#define PCI_DEVICE_ID_INTEL_3400 0x3b12 +#define PCI_DEVICE_ID_INTEL_3420 0x3b14 +#define PCI_DEVICE_ID_INTEL_3450 0x3b16 +#define PCI_DEVICE_ID_INTEL_B55_B 0x3b1e +#define PCI_DEVICE_ID_INTEL_Z68 0x1c44 +#define PCI_DEVICE_ID_INTEL_P67 0x1c46 +#define PCI_DEVICE_ID_INTEL_UM67 0x1c47 +#define PCI_DEVICE_ID_INTEL_HM65 0x1c49 +#define PCI_DEVICE_ID_INTEL_H67 0x1c4a +#define PCI_DEVICE_ID_INTEL_HM67 0x1c4b +#define PCI_DEVICE_ID_INTEL_Q65 0x1c4c +#define PCI_DEVICE_ID_INTEL_QS67 0x1c4d +#define PCI_DEVICE_ID_INTEL_Q67 0x1c4e +#define PCI_DEVICE_ID_INTEL_QM67 0x1c4f +#define PCI_DEVICE_ID_INTEL_B65 0x1c50 +#define PCI_DEVICE_ID_INTEL_C202 0x1c52 +#define PCI_DEVICE_ID_INTEL_C204 0x1c54 +#define PCI_DEVICE_ID_INTEL_C206 0x1c56 +#define PCI_DEVICE_ID_INTEL_H61 0x1c5c +#define PCI_DEVICE_ID_INTEL_Z77 0x1e44 +#define PCI_DEVICE_ID_INTEL_Z75 0x1e46 +#define PCI_DEVICE_ID_INTEL_Q77 0x1e47 +#define PCI_DEVICE_ID_INTEL_Q75 0x1e48 +#define PCI_DEVICE_ID_INTEL_B75 0x1e49 +#define PCI_DEVICE_ID_INTEL_H77 0x1e4a +#define PCI_DEVICE_ID_INTEL_C216 0x1e53 +#define PCI_DEVICE_ID_INTEL_QM77 0x1e55 +#define PCI_DEVICE_ID_INTEL_QS77 0x1e56 +#define PCI_DEVICE_ID_INTEL_HM77 0x1e57 +#define PCI_DEVICE_ID_INTEL_UM77 0x1e58 +#define PCI_DEVICE_ID_INTEL_HM76 0x1e59 +#define PCI_DEVICE_ID_INTEL_HM75 0x1e5d +#define PCI_DEVICE_ID_INTEL_HM70 0x1e5e +#define PCI_DEVICE_ID_INTEL_NM70 0x1e5f +#define PCI_DEVICE_ID_INTEL_DH89XXCC 0x2310 +#define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_FULL 0x9c41 +#define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_PREM 0x9c43 +#define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_BASE 0x9c45 + +#define PCI_DEV_HAS_ME_DIFFICULT(x) ( \ + ( (x) == PCI_DEVICE_ID_INTEL_ICH10R ) || \ + ( (x) == PCI_DEVICE_ID_INTEL_3400_DESKTOP ) || \ + ( (x) == PCI_DEVICE_ID_INTEL_3400_MOBILE ) || \ + ( (x) == PCI_DEVICE_ID_INTEL_P55 ) || \ + ( (x) == PCI_DEVICE_ID_INTEL_PM55 ) || \ + ( (x) == PCI_DEVICE_ID_INTEL_H55 ) || \ + ( (x) == PCI_DEVICE_ID_INTEL_QM57 ) || \ + ( (x) == PCI_DEVICE_ID_INTEL_H57 ) || \ + ( (x) == PCI_DEVICE_ID_INTEL_HM55 ) || \ + ( (x) == PCI_DEVICE_ID_INTEL_Q57 ) || \ + ( (x) == PCI_DEVICE_ID_INTEL_HM57 ) || \ + ( (x) == PCI_DEVICE_ID_INTEL_3400_MOBILE_SFF ) || \ + ( (x) == PCI_DEVICE_ID_INTEL_B55_A ) || \ + ( (x) == PCI_DEVICE_ID_INTEL_QS57 ) || \ + ( (x) == PCI_DEVICE_ID_INTEL_3400 ) || \ + ( (x) == PCI_DEVICE_ID_INTEL_3420 ) || \ + ( (x) == PCI_DEVICE_ID_INTEL_3450 ) || \ + ( (x) == PCI_DEVICE_ID_INTEL_B55_B ) || \ + ( (x) == PCI_DEVICE_ID_INTEL_Z68 ) || \ + ( (x) == PCI_DEVICE_ID_INTEL_P67 ) || \ + ( (x) == PCI_DEVICE_ID_INTEL_UM67 ) || \ + ( (x) == PCI_DEVICE_ID_INTEL_HM65 ) || \ + ( (x) == PCI_DEVICE_ID_INTEL_H67 ) || \ + ( (x) == PCI_DEVICE_ID_INTEL_HM67 ) || \ + ( (x) == PCI_DEVICE_ID_INTEL_Q65 ) || \ + ( (x) == PCI_DEVICE_ID_INTEL_QS67 ) || \ + ( (x) == PCI_DEVICE_ID_INTEL_Q67 ) || \ + ( (x) == PCI_DEVICE_ID_INTEL_QM67 ) || \ + ( (x) == PCI_DEVICE_ID_INTEL_B65 ) || \ + ( (x) == PCI_DEVICE_ID_INTEL_C202 ) || \ + ( (x) == PCI_DEVICE_ID_INTEL_C204 ) || \ + ( (x) == PCI_DEVICE_ID_INTEL_C206 ) || \ + ( (x) == PCI_DEVICE_ID_INTEL_H61 ) || \ + ( (x) == PCI_DEVICE_ID_INTEL_Z77 ) || \ + ( (x) == PCI_DEVICE_ID_INTEL_Z75 ) || \ + ( (x) == PCI_DEVICE_ID_INTEL_Q77 ) || \ + ( (x) == PCI_DEVICE_ID_INTEL_Q75 ) || \ + ( (x) == PCI_DEVICE_ID_INTEL_B75 ) || \ + ( (x) == PCI_DEVICE_ID_INTEL_H77 ) || \ + ( (x) == PCI_DEVICE_ID_INTEL_C216 ) || \ + ( (x) == PCI_DEVICE_ID_INTEL_QM77 ) || \ + ( (x) == PCI_DEVICE_ID_INTEL_QS77 ) || \ + ( (x) == PCI_DEVICE_ID_INTEL_HM77 ) || \ + ( (x) == PCI_DEVICE_ID_INTEL_UM77 ) || \ + ( (x) == PCI_DEVICE_ID_INTEL_HM76 ) || \ + ( (x) == PCI_DEVICE_ID_INTEL_HM75 ) || \ + ( (x) == PCI_DEVICE_ID_INTEL_HM70 ) || \ + ( (x) == PCI_DEVICE_ID_INTEL_NM70 ) || \ + ( (x) == PCI_DEVICE_ID_INTEL_DH89XXCC ) || \ + ( (x) == PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_FULL ) || \ + ( (x) == PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_PREM ) || \ + ( (x) == PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_BASE )) + +// Not sure if ME present, but should be able to disable it easily +#define PCI_DEVICE_ID_INTEL_ICH8 0x2810 +#define PCI_DEVICE_ID_INTEL_ICH8M 0x2815 +#define PCI_DEVICE_ID_INTEL_ICH9DH 0x2912 +#define PCI_DEVICE_ID_INTEL_ICH9DO 0x2914 +#define PCI_DEVICE_ID_INTEL_ICH9R 0x2916 +#define PCI_DEVICE_ID_INTEL_ICH9 0x2918 + +#define PCI_DEV_CAN_DISABLE_ME_IF_PRESENT(x) ( \ + ( (x) == PCI_DEVICE_ID_INTEL_ICH8 ) || \ + ( (x) == PCI_DEVICE_ID_INTEL_ICH8M ) || \ + ( (x) == PCI_DEVICE_ID_INTEL_ICH9DH ) || \ + ( (x) == PCI_DEVICE_ID_INTEL_ICH9DO ) || \ + ( (x) == PCI_DEVICE_ID_INTEL_ICH9R ) || \ + ( (x) == PCI_DEVICE_ID_INTEL_ICH9 )) + +// Not sure at all +#define PCI_DEVICE_ID_INTEL_SCH_POULSBO_LPC 0x8119 +#define PCI_DEVICE_ID_INTEL_SCH_POULSBO 0x8100 + +#define PCI_DEV_ME_NOT_SURE(x) ( \ + ( (x) == PCI_DEVICE_ID_INTEL_SCH_POULSBO_LPC ) || \ + ( (x) == PCI_DEVICE_ID_INTEL_SCH_POULSBO)) diff --git a/util/intelmetool/me.c b/util/intelmetool/me.c new file mode 100644 index 0000000..709abae --- /dev/null +++ b/util/intelmetool/me.c @@ -0,0 +1,638 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <pci/pci.h> +#include <stdio.h> +#include <string.h> +#include <stdlib.h> +#include <sys/io.h> +#include <assert.h> +#include "me.h" +#include "mmap.h" + +#define read32(addr, off) ( *((uint32_t *) (addr + off)) ) +#define write32(addr, off, val) ( *((uint32_t *) (addr + off)) = val) + +// FIXME: define this for old firmware only +//#define OLDARC 1 + +void udelay(uint32_t usecs) +{ + uint32_t i; + for(i = 0; i < usecs; i++) + inb(0x80); +} + +/* Path that the BIOS should take based on ME state */ +/* +static const char *me_bios_path_values[] = { + [ME_NORMAL_BIOS_PATH] = "Normal", + [ME_S3WAKE_BIOS_PATH] = "S3 Wake", + [ME_ERROR_BIOS_PATH] = "Error", + [ME_RECOVERY_BIOS_PATH] = "Recovery", + [ME_DISABLE_BIOS_PATH] = "Disable", + [ME_FIRMWARE_UPDATE_BIOS_PATH] = "Firmware Update", +}; +*/ + +/* MMIO base address for MEI interface */ +static uint32_t mei_base_address; +static uint8_t* mei_mmap; + +#if 1 +static void mei_dump(void *ptr, int dword, int offset, const char *type) +{ + struct mei_csr *csr; + + + switch (offset) { + case MEI_H_CSR: + case MEI_ME_CSR_HA: + csr = ptr; +/* if (!csr) { + printf("%-9s[%02x] : ", type, offset); + printf("ERROR: 0x%08x\n", dword); + break; + } + printf("%-9s[%02x] : ", type, offset); + printf("depth=%u read=%02u write=%02u ready=%u " + "reset=%u intgen=%u intstatus=%u intenable=%u\n", csr->buffer_depth, + csr->buffer_read_ptr, csr->buffer_write_ptr, + csr->ready, csr->reset, csr->interrupt_generate, + csr->interrupt_status, csr->interrupt_enable); +*/ break; + case MEI_ME_CB_RW: + case MEI_H_CB_WW: + printf("%-9s[%02x] : ", type, offset); + printf("CB: 0x%08x\n", dword); + break; + default: + printf("%-9s[%02x] : ", type, offset); + printf("0x%08x\n", offset); + break; + } +} +#else +# define mei_dump(ptr,dword,offset,type) do {} while (0) +#endif + +/* + * ME/MEI access helpers using memcpy to avoid aliasing. + */ + +static inline void mei_read_dword_ptr(void *ptr, uint32_t offset) +{ + uint32_t dword = read32(mei_mmap, offset); + memcpy(ptr, &dword, sizeof(dword)); + mei_dump(ptr, dword, offset, "READ"); +} + +static inline void mei_write_dword_ptr(void *ptr, uint32_t offset) +{ + uint32_t dword = 0; + memcpy(&dword, ptr, sizeof(dword)); + write32(mei_mmap, offset, dword); + mei_dump(ptr, dword, offset, "WRITE"); +} + +static inline void pci_read_dword_ptr(struct pci_dev *dev, void *ptr, uint32_t offset) +{ + uint32_t dword = pci_read_long(dev, offset); + memcpy(ptr, &dword, sizeof(dword)); + mei_dump(ptr, dword, offset, "PCI READ"); +} + +static inline void read_host_csr(struct mei_csr *csr) +{ + mei_read_dword_ptr(csr, MEI_H_CSR); +} + +static inline void write_host_csr(struct mei_csr *csr) +{ + mei_write_dword_ptr(csr, MEI_H_CSR); +} + +static inline void read_me_csr(struct mei_csr *csr) +{ + mei_read_dword_ptr(csr, MEI_ME_CSR_HA); +} + +static inline void write_cb(uint32_t dword) +{ + write32(mei_mmap, MEI_H_CB_WW, dword); + mei_dump(NULL, dword, MEI_H_CB_WW, "WRITE"); +} + +static inline uint32_t read_cb(void) +{ + uint32_t dword = read32(mei_mmap, MEI_ME_CB_RW); + mei_dump(NULL, dword, MEI_ME_CB_RW, "READ"); + return dword; +} + +/* Wait for ME ready bit to be asserted */ +static int mei_wait_for_me_ready(void) +{ + struct mei_csr me; + unsigned try = ME_RETRY; + + while (try--) { + read_me_csr(&me); + if (me.ready) + return 0; + udelay(ME_DELAY); + } + + printf("ME: failed to become ready\n"); + return -1; +} + +void mei_reset(void) +{ + struct mei_csr host; + + if (mei_wait_for_me_ready() < 0) + return; + + /* Reset host and ME circular buffers for next message */ + read_host_csr(&host); + host.reset = 1; + host.interrupt_generate = 1; + write_host_csr(&host); + + if (mei_wait_for_me_ready() < 0) + return; + + /* Re-init and indicate host is ready */ + read_host_csr(&host); + host.interrupt_generate = 1; + host.ready = 1; + host.reset = 0; + write_host_csr(&host); +} + +static int mei_send_msg(struct mei_header *mei, struct mkhi_header *mkhi, + void *req_data) +{ + struct mei_csr host; + unsigned ndata , n; + uint32_t *data; + + /* Number of dwords to write, ignoring MKHI */ + ndata = (mei->length) >> 2; + + /* Pad non-dword aligned request message length */ + if (mei->length & 3) + ndata++; + if (!ndata) { + printf("ME: request does not include MKHI\n"); + return -1; + } + ndata++; /* Add MEI header */ + + /* + * Make sure there is still room left in the circular buffer. + * Reset the buffer pointers if the requested message will not fit. + */ + read_host_csr(&host); + if ((host.buffer_depth - host.buffer_write_ptr) < ndata) { + printf("ME: circular buffer full, resetting...\n"); + mei_reset(); + read_host_csr(&host); + } + + /* + * This implementation does not handle splitting large messages + * across multiple transactions. Ensure the requested length + * will fit in the available circular buffer depth. + */ + if ((host.buffer_depth - host.buffer_write_ptr) < ndata) { + printf("ME: message (%u) too large for buffer (%u)\n", + ndata + 2, host.buffer_depth); + return -1; + } + + /* Write MEI header */ + mei_write_dword_ptr(mei, MEI_H_CB_WW); + ndata--; + + /* Write MKHI header */ + mei_write_dword_ptr(mkhi, MEI_H_CB_WW); + ndata--; + + /* Write message data */ + data = req_data; + for (n = 0; n < ndata; ++n) + write_cb(*data++); + + /* Generate interrupt to the ME */ + read_host_csr(&host); + host.interrupt_generate = 1; + write_host_csr(&host); + + /* Make sure ME is ready after sending request data */ + return mei_wait_for_me_ready(); +} + +static int mei_recv_msg(struct mei_header *mei, struct mkhi_header *mkhi, + void *rsp_data, uint32_t rsp_bytes) +{ + struct mei_header mei_rsp; + struct mkhi_header mkhi_rsp; + struct mei_csr me, host; + unsigned ndata, n; + unsigned expected; + uint32_t *data; + + /* Total number of dwords to read from circular buffer */ + expected = (rsp_bytes + sizeof(mei_rsp) + sizeof(mkhi_rsp)) >> 2; + if (rsp_bytes & 3) + expected++; + + //printf("expected u32 = %d\n", expected); + /* + * The interrupt status bit does not appear to indicate that the + * message has actually been received. Instead we wait until the + * expected number of dwords are present in the circular buffer. + */ + for (n = ME_RETRY; n; --n) { + read_me_csr(&me); + if ((me.buffer_write_ptr - me.buffer_read_ptr) >= expected) + //if (me.interrupt_generate && !me.interrupt_status) + //if (me.interrupt_status) + break; + udelay(ME_DELAY); + } + if (!n) { + printf("ME: timeout waiting for data: expected " + "%u, available %u\n", expected, + me.buffer_write_ptr - me.buffer_read_ptr); + return -1; + } + /* Read and verify MEI response header from the ME */ + mei_read_dword_ptr(&mei_rsp, MEI_ME_CB_RW); + if (!mei_rsp.is_complete) { + printf("ME: response is not complete\n"); + return -1; + } + + /* Handle non-dword responses and expect at least MKHI header */ + ndata = mei_rsp.length >> 2; + if (mei_rsp.length & 3) + ndata++; + if (ndata != (expected - 1)) { //XXX + printf("ME: response is missing data\n"); + //return -1; + } + + /* Read and verify MKHI response header from the ME */ + mei_read_dword_ptr(&mkhi_rsp, MEI_ME_CB_RW); + if (!mkhi_rsp.is_response || + mkhi->group_id != mkhi_rsp.group_id || + mkhi->command != mkhi_rsp.command) { + printf("ME: invalid response, group %u ?= %u, " + "command %u ?= %u, is_response %u\n", mkhi->group_id, + mkhi_rsp.group_id, mkhi->command, mkhi_rsp.command, + mkhi_rsp.is_response); + //return -1; + } + ndata--; /* MKHI header has been read */ + + /* Make sure caller passed a buffer with enough space */ + if (ndata != (rsp_bytes >> 2)) { + printf("ME: not enough room in response buffer: " + "%u != %u\n", ndata, rsp_bytes >> 2); + //return -1; + } + + /* Read response data from the circular buffer */ + data = rsp_data; + for (n = 0; n < ndata; ++n) + *data++ = read_cb(); + + /* Tell the ME that we have consumed the response */ + read_host_csr(&host); + host.interrupt_status = 1; + host.interrupt_generate = 1; + write_host_csr(&host); + + return mei_wait_for_me_ready(); +} + +static inline int mei_sendrecv(struct mei_header *mei, struct mkhi_header *mkhi, + void *req_data, void *rsp_data, uint32_t rsp_bytes) +{ + if (mei_send_msg(mei, mkhi, req_data) < 0) + return -1; + if (mei_recv_msg(mei, mkhi, rsp_data, rsp_bytes) < 0) + return -1; + return 0; +} + +/* Send END OF POST message to the ME */ +/* +static int mkhi_end_of_post(void) +{ + struct mkhi_header mkhi = { + .group_id = MKHI_GROUP_ID_GEN, + .command = MKHI_END_OF_POST, + }; + struct mei_header mei = { + .is_complete = 1, + .host_address = MEI_HOST_ADDRESS, + .client_address = MEI_ADDRESS_MKHI, + .length = sizeof(mkhi), + }; + + if (mei_sendrecv(&mei, &mkhi, NULL, NULL, 0) < 0) { + printf("ME: END OF POST message failed\n"); + return -1; + } + + printf("ME: END OF POST message successful\n"); + return 0; +} +*/ + +/* Get ME firmware version */ +int mkhi_get_fw_version(void) +{ + uint32_t data = 0; + struct me_fw_version version = {0}; + + struct mkhi_header mkhi = { + .group_id = MKHI_GROUP_ID_GEN, + .command = GEN_GET_FW_VERSION, + .is_response = 0, + }; + + struct mei_header mei = { + .is_complete = 1, + .host_address = MEI_HOST_ADDRESS, + .client_address = MEI_ADDRESS_MKHI, + .length = sizeof(mkhi), + }; + +#ifndef OLDARC + /* Send request and wait for response */ + if (mei_sendrecv(&mei, &mkhi, &data, &version, sizeof(version) ) < 0) { + printf("ME: GET FW VERSION message failed\n"); + return -1; + } + printf("ME: Firmware Version %u.%u.%u.%u (code) " + "%u.%u.%u.%u (recovery) " + "%u.%u.%u.%u (fitc)\n", + version.code_major, version.code_minor, + version.code_build_number, version.code_hot_fix, + version.recovery_major, version.recovery_minor, + version.recovery_build_number, version.recovery_hot_fix, + version.fitcmajor, version.fitcminor, + version.fitcbuildno, version.fitchotfix); +#else + /* Send request and wait for response */ + if (mei_sendrecv(&mei, &mkhi, &data, &version, 2*sizeof(uint32_t) ) < 0) { + printf("ME: GET FW VERSION message failed\n"); + return -1; + } + printf("ME: Firmware Version %u.%u (code)\n" + version.code_major, version.code_minor); +#endif + return 0; +} + +static inline void print_cap(const char *name, int state) +{ + printf("ME Capability: %-30s : %s\n", + name, state ? "ON" : "OFF"); +} + +/* Get ME Firmware Capabilities */ +int mkhi_get_fwcaps(void) +{ + struct { + uint32_t rule_id; + uint32_t rule_len; + + struct me_fwcaps cap; + } fwcaps; + + fwcaps.rule_id = 0; + fwcaps.rule_len = 0; + + struct mkhi_header mkhi = { + .group_id = MKHI_GROUP_ID_FWCAPS, + .command = MKHI_FWCAPS_GET_RULE, + .is_response = 0, + }; + struct mei_header mei = { + .is_complete = 1, + .host_address = MEI_HOST_ADDRESS, + .client_address = MEI_ADDRESS_MKHI, + .length = sizeof(mkhi) + sizeof(fwcaps.rule_id), + }; + + /* Send request and wait for response */ + if (mei_sendrecv(&mei, &mkhi, &fwcaps.rule_id, &fwcaps.cap, sizeof(fwcaps.cap)) < 0) { + printf("ME: GET FWCAPS message failed\n"); + return -1; + } + + print_cap("Full Network manageability ", fwcaps.cap.caps_sku.full_net); + print_cap("Regular Network manageability ", fwcaps.cap.caps_sku.std_net); + print_cap("Manageability ", fwcaps.cap.caps_sku.manageability); + print_cap("Small business technology ", fwcaps.cap.caps_sku.small_business); + print_cap("Level III manageability ", fwcaps.cap.caps_sku.l3manageability); + print_cap("IntelR Anti-Theft (AT) ", fwcaps.cap.caps_sku.intel_at); + print_cap("IntelR Capability Licensing Service (CLS) ", + fwcaps.cap.caps_sku.intel_cls); + print_cap("IntelR Power Sharing Technology (MPC) ", + fwcaps.cap.caps_sku.intel_mpc); + print_cap("ICC Over Clocking ", fwcaps.cap.caps_sku.icc_over_clocking); + print_cap("Protected Audio Video Path (PAVP) ", fwcaps.cap.caps_sku.pavp); + print_cap("IPV6 ", fwcaps.cap.caps_sku.ipv6); + print_cap("KVM Remote Control (KVM) ", fwcaps.cap.caps_sku.kvm); + print_cap("Outbreak Containment Heuristic (OCH) ", fwcaps.cap.caps_sku.och); + print_cap("Virtual LAN (VLAN) ", fwcaps.cap.caps_sku.vlan); + print_cap("TLS ", fwcaps.cap.caps_sku.tls); + print_cap("Wireless LAN (WLAN) ", fwcaps.cap.caps_sku.wlan); + + return 0; +} + +/* Tell ME to issue a global reset */ +uint32_t mkhi_global_reset(void) +{ + struct me_global_reset reset = { + .request_origin = GLOBAL_RESET_BIOS_POST, + .reset_type = CBM_RR_GLOBAL_RESET, + }; + struct mkhi_header mkhi = { + .group_id = MKHI_GROUP_ID_CBM, + .command = MKHI_GLOBAL_RESET, + }; + struct mei_header mei = { + .is_complete = 1, + .length = sizeof(mkhi) + sizeof(reset), + .host_address = MEI_HOST_ADDRESS, + .client_address = MEI_ADDRESS_MKHI, + }; + + printf("ME: Requesting global reset\n"); + + /* Send request and wait for response */ + if (mei_sendrecv(&mei, &mkhi, &reset, NULL, 0) < 0) { + /* No response means reset will happen shortly... */ + asm("hlt"); + } + + /* If the ME responded it rejected the reset request */ + printf("ME: Global Reset failed\n"); + return -1; +} + +/* Tell ME thermal reporting parameters */ +/* +void mkhi_thermal(void) +{ + struct me_thermal_reporting thermal = { + .polling_timeout = 2, + .smbus_ec_msglen = 1, + .smbus_ec_msgpec = 0, + .dimmnumber = 4, + }; + struct mkhi_header mkhi = { + .group_id = MKHI_GROUP_ID_CBM, + .command = MKHI_THERMAL_REPORTING, + }; + struct mei_header mei = { + .is_complete = 1, + .length = sizeof(mkhi) + sizeof(thermal), + .host_address = MEI_HOST_ADDRESS, + .client_address = MEI_ADDRESS_THERMAL, + }; + + printf("ME: Sending thermal reporting params\n"); + + mei_sendrecv(&mei, &mkhi, &thermal, NULL, 0); +} +*/ + +/* Enable debug of internal ME memory */ +int mkhi_debug_me_memory(void *physaddr) +{ + uint32_t data = 0; + + /* copy whole ME memory to a readable space */ + struct me_debug_mem memory = { + .debug_phys = (uintptr_t)physaddr, + .debug_size = 0x2000000, + .me_phys = 0x20000000, + .me_size = 0x2000000, + }; + struct mkhi_header mkhi = { + .group_id = MKHI_GROUP_ID_GEN, + .command = GEN_SET_DEBUG_MEM, + .is_response = 0, + }; + struct mei_header mei = { + .is_complete = 1, + .length = sizeof(mkhi) + sizeof(memory), + .host_address = MEI_HOST_ADDRESS, + .client_address = MEI_ADDRESS_MKHI, + }; + + printf("ME: Debug memory to 0x%zx ...", (size_t)physaddr); + if (mei_sendrecv(&mei, &mkhi, &memory, &data, 0) < 0) { + printf("failed\n"); + return -1; + } else { + printf("done\n"); + } + return 0; +} + +/* Prepare ME for MEI messages */ +uint32_t intel_mei_setup(struct pci_dev *dev) +{ + struct mei_csr host; + uint32_t reg32; + uint32_t pagerounded; + + mei_base_address = dev->base_addr[0] & ~0xf; + pagerounded = mei_base_address & ~0xfff; + mei_mmap = map_physical(pagerounded, 0x2000) + mei_base_address - pagerounded; + + /* Ensure Memory and Bus Master bits are set */ + reg32 = pci_read_long(dev, PCI_COMMAND); + reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; + pci_write_long(dev, PCI_COMMAND, reg32); + + /* Clean up status for next message */ + read_host_csr(&host); + host.interrupt_generate = 1; + host.ready = 1; + host.reset = 0; + write_host_csr(&host); + + return 0; +} + +void intel_mei_unmap(void) +{ + //munmap(mei_mmap, 0x2000); +} + +/* Read the Extend register hash of ME firmware */ +int intel_me_extend_valid(struct pci_dev *dev) +{ + struct me_heres status; + uint32_t extend[8] = {0}; + int i, count = 0; + + pci_read_dword_ptr(dev, &status, PCI_ME_HERES); + if (!status.extend_feature_present) { + printf("ME: Extend Feature not present\n"); + return -1; + } + + if (!status.extend_reg_valid) { + printf("ME: Extend Register not valid\n"); + return -1; + } + + switch (status.extend_reg_algorithm) { + case PCI_ME_EXT_SHA1: + count = 5; + printf("ME: Extend SHA-1: "); + break; + case PCI_ME_EXT_SHA256: + count = 8; + printf("ME: Extend SHA-256: "); + break; + default: + printf("ME: Extend Algorithm %d unknown\n", + status.extend_reg_algorithm); + return -1; + } + + for (i = 0; i < count; ++i) { + extend[i] = pci_read_long(dev, PCI_ME_HER(i)); + printf("%08x", extend[i]); + } + printf("\n"); + + return 0; +} diff --git a/util/intelmetool/me.h b/util/intelmetool/me.h new file mode 100644 index 0000000..2778266 --- /dev/null +++ b/util/intelmetool/me.h @@ -0,0 +1,409 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef ME_H +#define ME_H + +#include <inttypes.h> +#include <pci/pci.h> + +#define ME_RETRY 100000 /* 1 second */ +#define ME_DELAY 10 /* 10 us */ + +#pragma pack(1) + +/* + * Management Engine PCI registers + */ + +#define PCI_ME_HFS 0x40 +#define ME_HFS_CWS_RESET 0 +#define ME_HFS_CWS_INIT 1 +#define ME_HFS_CWS_REC 2 +#define ME_HFS_CWS_NORMAL 5 +#define ME_HFS_CWS_WAIT 6 +#define ME_HFS_CWS_TRANS 7 +#define ME_HFS_CWS_INVALID 8 +#define ME_HFS_STATE_PREBOOT 0 +#define ME_HFS_STATE_M0_UMA 1 +#define ME_HFS_STATE_M3 4 +#define ME_HFS_STATE_M0 5 +#define ME_HFS_STATE_BRINGUP 6 +#define ME_HFS_STATE_ERROR 7 +#define ME_HFS_ERROR_NONE 0 +#define ME_HFS_ERROR_UNCAT 1 +#define ME_HFS_ERROR_IMAGE 3 +#define ME_HFS_ERROR_DEBUG 4 +#define ME_HFS_MODE_NORMAL 0 +#define ME_HFS_MODE_DEBUG 2 +#define ME_HFS_MODE_DIS 3 +#define ME_HFS_MODE_OVER_JMPR 4 +#define ME_HFS_MODE_OVER_MEI 5 +#define ME_HFS_BIOS_DRAM_ACK 1 +#define ME_HFS_ACK_NO_DID 0 +#define ME_HFS_ACK_RESET 1 +#define ME_HFS_ACK_PWR_CYCLE 2 +#define ME_HFS_ACK_S3 3 +#define ME_HFS_ACK_S4 4 +#define ME_HFS_ACK_S5 5 +#define ME_HFS_ACK_GBL_RESET 6 +#define ME_HFS_ACK_CONTINUE 7 + +struct me_hfs { + uint32_t working_state: 4; + uint32_t mfg_mode: 1; + uint32_t fpt_bad: 1; + uint32_t operation_state: 3; + uint32_t fw_init_complete: 1; + uint32_t ft_bup_ld_flr: 1; + uint32_t update_in_progress: 1; + uint32_t error_code: 4; + uint32_t operation_mode: 4; + uint32_t reserved: 4; + uint32_t boot_options_present: 1; + uint32_t ack_data: 3; + uint32_t bios_msg_ack: 4; +} __attribute__ ((packed)); + +#define PCI_ME_UMA 0x44 + +struct me_uma { + uint32_t size: 6; + uint32_t reserved_1: 10; + uint32_t valid: 1; + uint32_t reserved_0: 14; + uint32_t set_to_one: 1; +} __attribute__ ((packed)); + +#define PCI_ME_H_GS 0x4c +#define ME_INIT_DONE 1 +#define ME_INIT_STATUS_SUCCESS 0 +#define ME_INIT_STATUS_NOMEM 1 +#define ME_INIT_STATUS_ERROR 2 + +struct me_did { + uint32_t uma_base: 16; + uint32_t reserved: 8; + uint32_t status: 4; + uint32_t init_done: 4; +} __attribute__ ((packed)); + +#define PCI_ME_GMES 0x48 +#define ME_GMES_PHASE_ROM 0 +#define ME_GMES_PHASE_BUP 1 +#define ME_GMES_PHASE_UKERNEL 2 +#define ME_GMES_PHASE_POLICY 3 +#define ME_GMES_PHASE_MODULE 4 +#define ME_GMES_PHASE_UNKNOWN 5 +#define ME_GMES_PHASE_HOST 6 + +struct me_gmes { + uint32_t bist_in_prog : 1; + uint32_t icc_prog_sts : 2; + uint32_t invoke_mebx : 1; + uint32_t cpu_replaced_sts : 1; + uint32_t mbp_rdy : 1; + uint32_t mfs_failure : 1; + uint32_t warm_rst_req_for_df : 1; + uint32_t cpu_replaced_valid : 1; + uint32_t reserved_1 : 2; + uint32_t fw_upd_ipu : 1; + uint32_t reserved_2 : 4; + uint32_t current_state: 8; + uint32_t current_pmevent: 4; + uint32_t progress_code: 4; +} __attribute__ ((packed)); + +#define PCI_ME_HERES 0xbc +#define PCI_ME_EXT_SHA1 0x00 +#define PCI_ME_EXT_SHA256 0x02 +#define PCI_ME_HER(x) (0xc0+(4*(x))) + +struct me_heres { + uint32_t extend_reg_algorithm: 4; + uint32_t reserved: 26; + uint32_t extend_feature_present: 1; + uint32_t extend_reg_valid: 1; +} __attribute__ ((packed)); + +struct me_thermal_reporting { + uint32_t polling_timeout: 8; + uint32_t smbus_ec_msglen: 8; + uint32_t smbus_ec_msgpec: 8; + uint32_t dimmnumber: 8; +} __attribute__ ((packed)); + +/* + * Management Engine MEI registers + */ + +#define MEI_H_CB_WW 0x00 +#define MEI_H_CSR 0x04 +#define MEI_ME_CB_RW 0x08 +#define MEI_ME_CSR_HA 0x0c + +struct mei_csr { + uint32_t interrupt_enable: 1; + uint32_t interrupt_status: 1; + uint32_t interrupt_generate: 1; + uint32_t ready: 1; + uint32_t reset: 1; + uint32_t reserved: 3; + uint32_t buffer_read_ptr: 8; + uint32_t buffer_write_ptr: 8; + uint32_t buffer_depth: 8; +} __attribute__ ((packed)); + +#define MEI_ADDRESS_HBM 0x00 +#define MEI_ADDRESS_CORE_WD 0x01 +#define MEI_ADDRESS_AMT 0x02 +#define MEI_ADDRESS_RESERVED 0x03 +#define MEI_ADDRESS_WDT 0x04 +#define MEI_ADDRESS_POLICY 0x05 +#define MEI_ADDRESS_PASSWORD 0x06 +#define MEI_ADDRESS_MKHI 0x07 +#define MEI_ADDRESS_ICC 0x08 +#define MEI_ADDRESS_THERMAL 0x09 +#define MEI_ADDRESS_SPI 0x0a + +#define MEI_HOST_ADDRESS 0 + +struct mei_header { + uint32_t client_address: 8; + uint32_t host_address: 8; + uint32_t length: 9; + uint32_t reserved: 6; + uint32_t is_complete: 1; +} __attribute__ ((packed)); + +#define MKHI_GROUP_ID_CBM 0x00 +#define MKHI_GROUP_ID_PM 0x01 +#define MKHI_GROUP_ID_PWD 0x02 +#define MKHI_GROUP_ID_FWCAPS 0x03 +#define MKHI_GROUP_ID_APP 0x04 +#define MKHI_GROUP_ID_SPI 0x05 +#define MKHI_GROUP_ID_MDES 0x08 +#define MKHI_GROUP_ID_MAX 0x09 +#define MKHI_GROUP_ID_GEN 0xff + +#define MKHI_FWCAPS_GET_RULE 0x02 +#define MKHI_FWCAPS_SET_RULE 0x03 +#define MKHI_GLOBAL_RESET 0x0b + +#define GEN_GET_MKHI_VERSION 0x01 +#define GEN_GET_FW_VERSION 0x02 +#define GEN_UNCONFIG_NO_PWD 0x0d +#define GEN_SET_DEBUG_MEM 0x11 + +#define FWCAPS_ME_FWU_RULE 0x2e +#define FWCAPS_OVERRIDE 0x14 + +#define MKHI_THERMAL_REPORTING 0x00 +#define MKHI_GET_FW_VERSION 0x02 +#define MKHI_MDES_ENABLE 0x09 +#define MKHI_END_OF_POST 0x0c +#define MKHI_FEATURE_OVERRIDE 0x14 + +#define HBM_HOST_START_REQ_CMD 0x01 +#define HBM_HOST_STOP_REQ_CMD 0x02 +#define HBM_ME_STOP_REQ_CMD 0x03 +#define HBM_HOST_ENUM_REQ_CMD 0x04 +#define HBM_HOST_CLIENT_PROPERTIES_REQ_CMD 0x05 +#define HBM_CLIENT_CONNECT_REQ_CMD 0x06 +#define HBM_CLIENT_DISCONNECT_REQ_CMD 0x07 + +struct mkhi_header { + uint32_t group_id: 8; + uint32_t command: 7; + uint32_t is_response: 1; + uint32_t reserved: 8; + uint32_t result: 8; +} __attribute__ ((packed)); + +struct me_fw_version { + uint16_t code_minor; + uint16_t code_major; + uint16_t code_build_number; + uint16_t code_hot_fix; + uint16_t recovery_minor; + uint16_t recovery_major; + uint16_t recovery_build_number; + uint16_t recovery_hot_fix; + uint16_t fitcminor; + uint16_t fitcmajor; + uint16_t fitcbuildno; + uint16_t fitchotfix; +} __attribute__ ((packed)); + + +#define HECI_EOP_STATUS_SUCCESS 0x0 +#define HECI_EOP_PERFORM_GLOBAL_RESET 0x1 + +#define CBM_RR_GLOBAL_RESET 0x01 + +#define GLOBAL_RESET_BIOS_MRC 0x01 +#define GLOBAL_RESET_BIOS_POST 0x02 +#define GLOBAL_RESET_MEBX 0x03 + +struct me_global_reset { + uint8_t request_origin; + uint8_t reset_type; +} __attribute__ ((packed)); + +typedef enum { + ME_NORMAL_BIOS_PATH, + ME_S3WAKE_BIOS_PATH, + ME_ERROR_BIOS_PATH, + ME_RECOVERY_BIOS_PATH, + ME_DISABLE_BIOS_PATH, + ME_FIRMWARE_UPDATE_BIOS_PATH, +} me_bios_path; + +typedef struct { + uint32_t major_version : 16; + uint32_t minor_version : 16; + uint32_t hotfix_version : 16; + uint32_t build_version : 16; +} __attribute__ ((packed)) mbp_fw_version_name; + +typedef struct { + uint8_t num_icc_profiles; + uint8_t icc_profile_soft_strap; + uint8_t icc_profile_index; + uint8_t reserved; + uint32_t register_lock_mask[3]; +} __attribute__ ((packed)) mbp_icc_profile; + +typedef struct { + uint32_t full_net : 1; + uint32_t std_net : 1; + uint32_t manageability : 1; + uint32_t small_business : 1; + uint32_t l3manageability : 1; + uint32_t intel_at : 1; + uint32_t intel_cls : 1; + uint32_t reserved : 3; + uint32_t intel_mpc : 1; + uint32_t icc_over_clocking : 1; + uint32_t pavp : 1; + uint32_t reserved_1 : 4; + uint32_t ipv6 : 1; + uint32_t kvm : 1; + uint32_t och : 1; + uint32_t vlan : 1; + uint32_t tls : 1; + uint32_t reserved_4 : 1; + uint32_t wlan : 1; + uint32_t reserved_5 : 8; +} __attribute__ ((packed)) mefwcaps_sku; + +typedef struct { + uint16_t lock_state : 1; + uint16_t authenticate_module : 1; + uint16_t s3authentication : 1; + uint16_t flash_wear_out : 1; + uint16_t flash_variable_security : 1; + uint16_t wwan3gpresent : 1; + uint16_t wwan3goob : 1; + uint16_t reserved : 9; +} __attribute__ ((packed)) tdt_state_flag; + +typedef struct { + uint8_t state; + uint8_t last_theft_trigger; + tdt_state_flag flags; +} __attribute__ ((packed)) tdt_state_info; + +typedef struct { + uint32_t platform_target_usage_type : 4; + uint32_t platform_target_market_type : 2; + uint32_t super_sku : 1; + uint32_t reserved : 1; + uint32_t intel_me_fw_image_type : 4; + uint32_t platform_brand : 4; + uint32_t reserved_1 : 16; +} __attribute__ ((packed)) platform_type_rule_data; + +typedef struct { + mefwcaps_sku fw_capabilities; + uint8_t available; +} mbp_fw_caps; + +typedef struct { + uint16_t device_id; + uint16_t fuse_test_flags; + uint32_t umchid[4]; +} __attribute__ ((packed)) mbp_rom_bist_data; + +typedef struct { + uint32_t key[8]; +} mbp_platform_key; + +typedef struct { + platform_type_rule_data rule_data; + uint8_t available; +} mbp_plat_type; + +typedef struct { + mbp_fw_version_name fw_version_name; + mbp_fw_caps fw_caps_sku; + mbp_rom_bist_data rom_bist_data; + mbp_platform_key platform_key; + mbp_plat_type fw_plat_type; + mbp_icc_profile icc_profile; + tdt_state_info at_state; + uint32_t mfsintegrity; +} me_bios_payload; + +typedef struct { + uint32_t mbp_size : 8; + uint32_t num_entries : 8; + uint32_t rsvd : 16; +} __attribute__ ((packed)) mbp_header; + +typedef struct { + uint32_t app_id : 8; + uint32_t item_id : 8; + uint32_t length : 8; + uint32_t rsvd : 8; +} __attribute__ ((packed)) mbp_item_header; + +struct me_fwcaps { + uint32_t id; + uint8_t length; + mefwcaps_sku caps_sku; + uint8_t reserved[3]; +} __attribute__ ((packed)); + +struct me_debug_mem { + uint32_t debug_phys; + uint32_t debug_size; + uint32_t me_phys; + uint32_t me_size; +} __attribute__ ((packed)); + +void intel_me_status(uint32_t hfs, uint32_t gmes); +void mkhi_thermal(void); +uint32_t intel_mei_setup(struct pci_dev *dev); +void intel_mei_unmap(void); +int mkhi_get_fwcaps(void); +int mkhi_get_fw_version(void); +int mkhi_debug_me_memory(void *addr); +void mei_reset(void); +void udelay(uint32_t usecs); +int intel_me_extend_valid(struct pci_dev *dev); + +#endif diff --git a/util/intelmetool/me_status.c b/util/intelmetool/me_status.c new file mode 100644 index 0000000..1de51f4 --- /dev/null +++ b/util/intelmetool/me_status.c @@ -0,0 +1,205 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdio.h> +#include "me.h" + +#define ARRAY_SIZE(a) (sizeof(a) / sizeof(a[0])) + +/* HFS1[3:0] Current Working State Values */ +static const char *me_cws_values[] = { + [ME_HFS_CWS_RESET] = "Reset", + [ME_HFS_CWS_INIT] = "Initializing", + [ME_HFS_CWS_REC] = "Recovery", + [ME_HFS_CWS_NORMAL] = "Normal", + [ME_HFS_CWS_WAIT] = "Platform Disable Wait", + [ME_HFS_CWS_TRANS] = "OP State Transition", + [ME_HFS_CWS_INVALID] = "Invalid CPU Plugged In" +}; + +/* HFS1[8:6] Current Operation State Values */ +static const char *me_opstate_values[] = { + [ME_HFS_STATE_PREBOOT] = "Preboot", + [ME_HFS_STATE_M0_UMA] = "M0 with UMA", + [ME_HFS_STATE_M3] = "M3 without UMA", + [ME_HFS_STATE_M0] = "M0 without UMA", + [ME_HFS_STATE_BRINGUP] = "Bring up", + [ME_HFS_STATE_ERROR] = "M0 without UMA but with error" +}; + +/* HFS[19:16] Current Operation Mode Values */ +static const char *me_opmode_values[] = { + [ME_HFS_MODE_NORMAL] = "Normal", + [ME_HFS_MODE_DEBUG] = "Debug", + [ME_HFS_MODE_DIS] = "Soft Temporary Disable", + [ME_HFS_MODE_OVER_JMPR] = "Security Override via Jumper", + [ME_HFS_MODE_OVER_MEI] = "Security Override via MEI Message" +}; + +/* HFS[15:12] Error Code Values */ +static const char *me_error_values[] = { + [ME_HFS_ERROR_NONE] = "No Error", + [ME_HFS_ERROR_UNCAT] = "Uncategorized Failure", + [ME_HFS_ERROR_IMAGE] = "Image Failure", + [ME_HFS_ERROR_DEBUG] = "Debug Failure" +}; + +/* GMES[31:28] ME Progress Code */ +static const char *me_progress_values[] = { + [ME_GMES_PHASE_ROM] = "ROM Phase", + [ME_GMES_PHASE_BUP] = "BUP Phase", + [ME_GMES_PHASE_UKERNEL] = "uKernel Phase", + [ME_GMES_PHASE_POLICY] = "Policy Module", + [ME_GMES_PHASE_MODULE] = "Module Loading", + [ME_GMES_PHASE_UNKNOWN] = "Unknown", + [ME_GMES_PHASE_HOST] = "Host Communication" +}; + +/* GMES[27:24] Power Management Event */ +static const char *me_pmevent_values[] = { + [0x00] = "Clean Moff->Mx wake", + [0x01] = "Moff->Mx wake after an error", + [0x02] = "Clean global reset", + [0x03] = "Global reset after an error", + [0x04] = "Clean Intel ME reset", + [0x05] = "Intel ME reset due to exception", + [0x06] = "Pseudo-global reset", + [0x07] = "S0/M0->Sx/M3", + [0x08] = "Sx/M3->S0/M0", + [0x09] = "Non-power cycle reset", + [0x0a] = "Power cycle reset through M3", + [0x0b] = "Power cycle reset through Moff", + [0x0c] = "Sx/Mx->Sx/Moff" +}; + +/* Progress Code 0 states */ +static const char *me_progress_rom_values[] = { + [0x00] = "BEGIN", + [0x06] = "DISABLE" +}; + +/* Progress Code 1 states */ +static const char *me_progress_bup_values[] = { + [0x00] = "Initialization starts", + [0x01] = "Disable the host wake event", + [0x04] = "Flow determination start process", + [0x08] = "Error reading/matching the VSCC table in the descriptor", + [0x0a] = "Check to see if straps say ME DISABLED", + [0x0b] = "Timeout waiting for PWROK", + [0x0d] = "Possibly handle BUP manufacturing override strap", + [0x11] = "Bringup in M3", + [0x12] = "Bringup in M0", + [0x13] = "Flow detection error", + [0x15] = "M3 clock switching error", + [0x18] = "M3 kernel load", + [0x1c] = "T34 missing - cannot program ICC", + [0x1f] = "Waiting for DID BIOS message", + [0x20] = "Waiting for DID BIOS message failure", + [0x21] = "DID reported an error", + [0x22] = "Enabling UMA", + [0x23] = "Enabling UMA error", + [0x24] = "Sending DID Ack to BIOS", + [0x25] = "Sending DID Ack to BIOS error", + [0x26] = "Switching clocks in M0", + [0x27] = "Switching clocks in M0 error", + [0x28] = "ME in temp disable", + [0x32] = "M0 kernel load", +}; + +/* Progress Code 3 states */ +static const char *me_progress_policy_values[] = { + [0x00] = "Entery into Policy Module", + [0x03] = "Received S3 entry", + [0x04] = "Received S4 entry", + [0x05] = "Received S5 entry", + [0x06] = "Received UPD entry", + [0x07] = "Received PCR entry", + [0x08] = "Received NPCR entry", + [0x09] = "Received host wake", + [0x0a] = "Received AC<>DC switch", + [0x0b] = "Received DRAM Init Done", + [0x0c] = "VSCC Data not found for flash device", + [0x0d] = "VSCC Table is not valid", + [0x0e] = "Flash Partition Boundary is outside address space", + [0x0f] = "ME cannot access the chipset descriptor region", + [0x10] = "Required VSCC values for flash parts do not match", +}; + +void intel_me_status(uint32_t hfs, uint32_t gmes) +{ + /* Check Current States */ + printf("ME: FW Partition Table : %s\n", + ((hfs & 0x20) >> 5) ? "BAD" : "OK"); + printf("ME: Bringup Loader Failure : %s\n", + ((hfs & 0x400) >> 10) ? "YES" : "NO"); + printf("ME: Firmware Init Complete : %s\n", + ((hfs & 0x200) >> 9) ? "YES" : "NO"); + printf("ME: Manufacturing Mode : %s\n", + ((hfs & 0x10) >> 4) ? "YES" : "NO"); + printf("ME: Boot Options Present : %s\n", + ((hfs & 0x1000000) >> 24) ? "YES" : "NO"); + printf("ME: Update In Progress : %s\n", + ((hfs & 0x800) >> 11) ? "YES" : "NO"); + printf("ME: Current Working State : %s\n", + me_cws_values[hfs & 0xf]); + printf("ME: Current Operation State : %s\n", + me_opstate_values[(hfs & 0x1c0) >> 6]); + printf("ME: Current Operation Mode : %s\n", + me_opmode_values[(hfs & 0xf0000) >> 16]); + printf("ME: Error Code : %s\n", + me_error_values[(hfs & 0xf000) >> 12]); + printf("ME: Progress Phase : %s\n", + me_progress_values[(gmes & 0xf0000000) >> 28]); + printf("ME: Power Management Event : %s\n", + me_pmevent_values[(gmes & 0xf000000) >> 24]); + + printf("ME: Progress Phase State : "); + switch ((gmes & 0xf0000000) >> 28) { + case ME_GMES_PHASE_ROM: /* ROM Phase */ + printf("%s", + me_progress_rom_values[(gmes & 0xff0000) >> 16]); + break; + + case ME_GMES_PHASE_BUP: /* Bringup Phase */ + if ((gmes & 0xff0000) >> 16 < ARRAY_SIZE(me_progress_bup_values) + && me_progress_bup_values[(gmes & 0xff0000) >> 16]) + printf("%s", + me_progress_bup_values[(gmes & 0xff0000) >> 16]); + else + printf("0x%02x", (gmes & 0xff0000) >> 16); + break; + + case ME_GMES_PHASE_POLICY: /* Policy Module Phase */ + if ((gmes & 0xff0000) >> 16 < ARRAY_SIZE(me_progress_policy_values) + && me_progress_policy_values[(gmes & 0xff0000) >> 16]) + printf("%s", + me_progress_policy_values[(gmes & 0xff0000) >> 16]); + else + printf("0x%02x", (gmes & 0xff0000) >> 16); + break; + + case ME_GMES_PHASE_HOST: /* Host Communication Phase */ + if (!((gmes & 0xff0000) >> 16)) + printf("Host communication established"); + else + printf("0x%02x", (gmes & 0xff0000) >> 16); + break; + + default: + printf("Unknown 0x%02x", (gmes & 0xff0000) >> 16); + } + printf("\n"); +} diff --git a/util/intelmetool/mmap.c b/util/intelmetool/mmap.c new file mode 100644 index 0000000..474edfe --- /dev/null +++ b/util/intelmetool/mmap.c @@ -0,0 +1,56 @@ +/* intelmetool + * + * Copyright (C) 2013-2015 Damien Zammit <damien(a)zamaudio.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "mmap.h" +#include <errno.h> + +int fd_mem; + +void *map_physical_exact(uint64_t phys_addr, uint64_t mapto, size_t len) { + void *virt_addr; + int err; + + virt_addr = mmap((void*)mapto, len, PROT_WRITE | PROT_READ, + MAP_SHARED | MAP_FIXED, fd_mem, (off_t) phys_addr); + + if (virt_addr == MAP_FAILED) { + err = errno; + printf("Error mapping physical memory 0x%016" PRIx64 "[0x%zx] ERRNO=%d\n", + phys_addr, len, err); + return NULL; + } + + return virt_addr; +} + +void *map_physical(uint64_t phys_addr, size_t len) { + void *virt_addr; + int err; + + virt_addr = mmap(NULL, len, PROT_WRITE | PROT_READ, MAP_SHARED, fd_mem, (off_t) phys_addr); + + if (virt_addr == MAP_FAILED) { + err = errno; + printf("Error mapping physical memory 0x%016" PRIx64 "[0x%zx] ERRNO=%d\n", + phys_addr, len, err); + return NULL; + } + + return virt_addr; +} + +void unmap_physical(void *virt_addr, size_t len) { + munmap(virt_addr, len); +} diff --git a/util/intelmetool/mmap.h b/util/intelmetool/mmap.h new file mode 100644 index 0000000..84c4218 --- /dev/null +++ b/util/intelmetool/mmap.h @@ -0,0 +1,24 @@ +/* intelmetool + * + * Copyright (C) 2013-2015 Damien Zammit <damien(a)zamaudio.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <inttypes.h> +#include <stdlib.h> +#include <fcntl.h> +#include <sys/mman.h> +#include <stdio.h> + +extern int fd_mem; +void *map_physical(uint64_t phys_addr, size_t len); +void unmap_physical(void *virt_addr, size_t len);

1 0

Patch set updated for coreboot: src/arch/x86/acpi.c: Use correct host address width in DMAR ACPI table
by Jacob Laska 18 Mar '16

18 Mar '16

Jacob Laska (jlaska91(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14102 -gerrit commit 79ef17971a8a441b8d0bed8421e15df3b36c4b95 Author: Jacob Laska <jlaska(a)xes-inc.com> Date: Tue Mar 15 21:53:27 2016 -0500 src/arch/x86/acpi.c: Use correct host address width in DMAR ACPI table The previous implementation assumed the CPU physical address size to be 40 which is not true of all platforms. Use an existing function to obtain the correct CPU physical address to report in the DMAR ACPI table. Change-Id: Ia79e9dadecc3f5f6a86ce3789b213222bef482b3 Signed-off-by: Jacob Laska <jlaska91(a)gmail.com> --- src/arch/x86/acpi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/arch/x86/acpi.c b/src/arch/x86/acpi.c index a21bae2..5640ad0 100644 --- a/src/arch/x86/acpi.c +++ b/src/arch/x86/acpi.c @@ -411,7 +411,7 @@ void acpi_create_dmar(acpi_dmar_t *dmar, enum dmar_flags flags, header->length = sizeof(acpi_dmar_t); header->revision = 1; - dmar->host_address_width = 40 - 1; /* FIXME: == MTRR size? */ + dmar->host_address_width = cpu_phys_address_size() - 1; dmar->flags = flags; current = acpi_fill_dmar(current);

1 0

Patch set updated for coreboot: soc/intel: Add Broadwell-DE SoC support
by York Yang 18 Mar '16

18 Mar '16

York Yang (york.yang(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14014 -gerrit commit 85120e73d1c067309db1bb426cad1fcdeef91e5f Author: York Yang <york.yang(a)intel.com> Date: Wed Mar 9 10:54:26 2016 -0800 soc/intel: Add Broadwell-DE SoC support Initial files to support Broadwell-DE SoC. This is FSP 1.0 based project and is based on Broadwell-DE Gold release. Change has been verified on Intel Camelback Mountain CRB. Change-Id: I20ce8ee8dd1113a7a20a96910292697421f1ca57 Signed-off-by: York Yang <york.yang(a)intel.com> --- src/soc/intel/fsp_broadwell_de/Kconfig | 86 +++ src/soc/intel/fsp_broadwell_de/Makefile.inc | 35 ++ src/soc/intel/fsp_broadwell_de/acpi.c | 454 +++++++++++++++ src/soc/intel/fsp_broadwell_de/acpi/irq_helper.h | 45 ++ src/soc/intel/fsp_broadwell_de/acpi/irqlinks.asl | 464 +++++++++++++++ src/soc/intel/fsp_broadwell_de/acpi/irqroute.asl | 39 ++ src/soc/intel/fsp_broadwell_de/acpi/lpc.asl | 94 +++ src/soc/intel/fsp_broadwell_de/acpi/pcie1.asl | 465 +++++++++++++++ .../intel/fsp_broadwell_de/acpi/southcluster.asl | 424 ++++++++++++++ .../intel/fsp_broadwell_de/bootblock/bootblock.c | 23 + src/soc/intel/fsp_broadwell_de/chip.c | 106 ++++ src/soc/intel/fsp_broadwell_de/chip.h | 29 + src/soc/intel/fsp_broadwell_de/cpu.c | 110 ++++ src/soc/intel/fsp_broadwell_de/fsp/Kconfig | 93 +++ src/soc/intel/fsp_broadwell_de/fsp/Makefile.inc | 18 + .../intel/fsp_broadwell_de/fsp/chipset_fsp_util.c | 131 +++++ .../intel/fsp_broadwell_de/fsp/chipset_fsp_util.h | 35 ++ src/soc/intel/fsp_broadwell_de/include/soc/acpi.h | 27 + .../fsp_broadwell_de/include/soc/broadwell_de.h | 20 + src/soc/intel/fsp_broadwell_de/include/soc/gpio.h | 24 + src/soc/intel/fsp_broadwell_de/include/soc/iomap.h | 66 +++ src/soc/intel/fsp_broadwell_de/include/soc/irq.h | 88 +++ src/soc/intel/fsp_broadwell_de/include/soc/lpc.h | 86 +++ src/soc/intel/fsp_broadwell_de/include/soc/msr.h | 28 + .../intel/fsp_broadwell_de/include/soc/pattrs.h | 52 ++ .../intel/fsp_broadwell_de/include/soc/pci_devs.h | 112 ++++ .../intel/fsp_broadwell_de/include/soc/ramstage.h | 30 + src/soc/intel/fsp_broadwell_de/include/soc/reset.h | 24 + .../intel/fsp_broadwell_de/include/soc/romstage.h | 35 ++ src/soc/intel/fsp_broadwell_de/memmap.c | 23 + src/soc/intel/fsp_broadwell_de/northcluster.c | 156 +++++ src/soc/intel/fsp_broadwell_de/ramstage.c | 86 +++ src/soc/intel/fsp_broadwell_de/reset.c | 29 + .../intel/fsp_broadwell_de/romstage/Makefile.inc | 3 + src/soc/intel/fsp_broadwell_de/romstage/romstage.c | 131 +++++ src/soc/intel/fsp_broadwell_de/southcluster.c | 267 +++++++++ src/soc/intel/fsp_broadwell_de/spi.c | 633 +++++++++++++++++++++ src/soc/intel/fsp_broadwell_de/uart.c | 112 ++++ 38 files changed, 4683 insertions(+) diff --git a/src/soc/intel/fsp_broadwell_de/Kconfig b/src/soc/intel/fsp_broadwell_de/Kconfig new file mode 100644 index 0000000..f186468 --- /dev/null +++ b/src/soc/intel/fsp_broadwell_de/Kconfig @@ -0,0 +1,86 @@ +config SOC_INTEL_FSP_BROADWELL_DE + bool + help + Broadwell-DE support using the Intel FSP. + +if SOC_INTEL_FSP_BROADWELL_DE + +config CPU_SPECIFIC_OPTIONS + def_bool y + select ARCH_BOOTBLOCK_X86_32 + select ARCH_VERSTAGE_X86_32 + select ARCH_ROMSTAGE_X86_32 + select ARCH_RAMSTAGE_X86_32 + select HAVE_HARD_RESET + select MMCONF_SUPPORT + select MMCONF_SUPPORT_DEFAULT + select RELOCATABLE_MODULES + select PARALLEL_MP + select SMP + select IOAPIC + select SPI_FLASH + select UDELAY_TSC + select SUPPORT_CPU_UCODE_IN_CBFS + # Microcode header files are delivered in FSP package + select USES_MICROCODE_HEADER_FILES if HAVE_FSP_BIN + +config CBFS_SIZE + hex + default 0x200000 + +config RAMTOP + hex + default 0x400000 + +config HEAP_SIZE + hex + default 0x100000 + +config BOOTBLOCK_CPU_INIT + string + default "soc/intel/fsp_broadwell_de/bootblock/bootblock.c" + +config MMCONF_BASE_ADDRESS + hex + default 0x80000000 + +config MAX_CPUS + int + default 16 + +config CPU_ADDR_BITS + int + default 36 + +config VGA_BIOS + bool + default n + +config DRIVERS_UART_8250IO + bool "Serial port on SuperIO (Broadwell-DE's UART ports will be disabled)" + default n + help + Select to choose SuperIO's serial port for console output. + CANNOT select if intend to use SoC integrated serial ports. + +config INTEGRATED_UART + bool "Integrated UART ports" + depends on !DRIVERS_UART_8250IO + default y + select HAVE_UART_SPECIAL + select CONSOLE_SERIAL + help + Use Broadwell-DE Integrated UART ports @3F8h and 2F8h. + +config CONSOLE_CBMEM + bool "Send console output to a CBMEM buffer" + default n + +config CPU_MICROCODE_HEADER_FILES + string + default "../intel/cpu/broadwell_de/microcode/M1050663_07000001.h ../intel/cpu/broadwell_de/microcode/M1050662_0000000A.h ../intel/cpu/broadwell_de/microcode/MFF50661_F1000008.h" + +## Broadwell-DE Specific FSP Kconfig +source src/soc/intel/fsp_broadwell_de/fsp/Kconfig + +endif # SOC_INTEL_FSP_BROADWELL_DE diff --git a/src/soc/intel/fsp_broadwell_de/Makefile.inc b/src/soc/intel/fsp_broadwell_de/Makefile.inc new file mode 100644 index 0000000..a0d5203 --- /dev/null +++ b/src/soc/intel/fsp_broadwell_de/Makefile.inc @@ -0,0 +1,35 @@ +ifeq ($(CONFIG_SOC_INTEL_FSP_BROADWELL_DE),y) + +subdirs-y += romstage +subdirs-y += ../../../cpu/intel/microcode +subdirs-y += ../../../cpu/intel/turbo +subdirs-y += ../../../cpu/x86/lapic +subdirs-y += ../../../cpu/x86/mtrr +subdirs-y += ../../../cpu/x86/tsc +subdirs-y += ../../../cpu/x86/cache +subdirs-y += ../../../lib/fsp +subdirs-y += fsp + +ramstage-y += spi.c +ramstage-y += cpu.c +ramstage-y += chip.c +ramstage-y += northcluster.c +ramstage-y += ramstage.c +romstage-y += memmap.c +ramstage-y += memmap.c +ramstage-y += southcluster.c +romstage-y += reset.c +ramstage-y += reset.c +ramstage-y += acpi.c + +ifeq ($(CONFIG_INTEGRATED_UART),y) +romstage-y += uart.c +ramstage-y += uart.c +smm-$(CONFIG_DEBUG_SMI) += uart.c +endif + +CPPFLAGS_common += -I$(src)/soc/intel/fsp_broadwell_de/include +CPPFLAGS_common += -I$(src)/soc/intel/fsp_broadwell_de/fsp +CPPFLAGS_common += -I$(src)/soc/intel/fsp_broadwell_de/ + +endif # ifeq ($(CONFIG_SOC_INTEL_FSP_BROADWELL_DE),y) diff --git a/src/soc/intel/fsp_broadwell_de/acpi.c b/src/soc/intel/fsp_broadwell_de/acpi.c new file mode 100644 index 0000000..3040ea3 --- /dev/null +++ b/src/soc/intel/fsp_broadwell_de/acpi.c @@ -0,0 +1,454 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015-2016 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <string.h> +#include <types.h> +#include <arch/acpigen.h> +#include <arch/cpu.h> +#include <arch/io.h> +#include <arch/smp/mpspec.h> +#include <console/console.h> +#include <cpu/x86/msr.h> +#include <cpu/intel/speedstep.h> +#include <cpu/intel/turbo.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <soc/acpi.h> +#include <soc/iomap.h> +#include <soc/irq.h> +#include <soc/lpc.h> +#include <soc/msr.h> +#include <soc/pattrs.h> +#include <soc/pci_devs.h> +#include <chip.h> + +uint16_t get_pmbase(void) +{ + return ACPI_BASE_ADDRESS; +} + +#define MWAIT_RES(state, sub_state) \ + { \ + .addrl = (((state) << 4) | (sub_state)), \ + .space_id = ACPI_ADDRESS_SPACE_FIXED, \ + .bit_width = ACPI_FFIXEDHW_VENDOR_INTEL, \ + .bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT, \ + .access_size = ACPI_FFIXEDHW_FLAG_HW_COORD, \ + } + +/* C-state map */ +static acpi_cstate_t cstate_map[] = { + { + /* C1 */ + .ctype = 1, /* ACPI C1 */ + .latency = 1, + .power = 1000, + .resource = MWAIT_RES(0, 0), + }, + { + /* C3 */ + .ctype = 2, /* ACPI C2 */ + .latency = 15, + .power = 500, + .resource = MWAIT_RES(1, 0), + }, + { + /* C6 */ + .ctype = 3, /* ACPI C3 */ + .latency = 41, + .power = 350, + .resource = MWAIT_RES(2, 0), + } +}; + +static int acpi_sci_irq(void) +{ + return 9; +} + +void acpi_create_intel_hpet(acpi_hpet_t *hpet) +{ + acpi_header_t *header = &(hpet->header); + acpi_addr_t *addr = &(hpet->addr); + + memset((void *) hpet, 0, sizeof(acpi_hpet_t)); + + /* fill out header fields */ + memcpy(header->signature, "HPET", 4); + memcpy(header->oem_id, OEM_ID, 6); + memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); + memcpy(header->asl_compiler_id, ASLC, 4); + + header->length = sizeof(acpi_hpet_t); + header->revision = 1; + + /* fill out HPET address */ + addr->space_id = 0; /* Memory */ + addr->bit_width = 64; + addr->bit_offset = 0; + addr->addrl = (unsigned long long)HPET_BASE_ADDRESS & 0xffffffff; + addr->addrh = (unsigned long long)HPET_BASE_ADDRESS >> 32; + + hpet->id = 0x8086a201; /* Intel */ + hpet->number = 0x00; + hpet->min_tick = 0x0080; + + header->checksum = acpi_checksum((void *) hpet, sizeof(acpi_hpet_t)); +} + +unsigned long acpi_fill_mcfg(unsigned long current) +{ + current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *)current, + MCFG_BASE_ADDRESS, 0, 0, 255); + return current; +} + +/** + * Fill in the fadt with generic values that can be overridden later. + */ + +void acpi_fill_in_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt) +{ + acpi_header_t *header = &(fadt->header); + u16 pmbase = get_pmbase(); + + memset((void *) fadt, 0, sizeof(acpi_fadt_t)); + + /* + * Reference section 5.2.9 Fixed ACPI Description Table (FADT) + * in the ACPI 3.0b specification. + */ + + /* FADT Header Structure */ + memcpy(header->signature, "FACP", 4); + header->length = sizeof(acpi_fadt_t); + header->revision = ACPI_FADT_REV_ACPI_3_0; + memcpy(header->oem_id, OEM_ID, 6); + memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); + memcpy(header->asl_compiler_id, ASLC, 4); + header->asl_compiler_revision = 1; + + /* ACPI Pointers */ + fadt->firmware_ctrl = (unsigned long) facs; + fadt->dsdt = (unsigned long) dsdt; + + fadt->model = 0; /* reserved, should be 0 ACPI 3.0 */ + fadt->preferred_pm_profile = 0; + fadt->sci_int = acpi_sci_irq(); + + /* System Management */ + fadt->smi_cmd = 0x00; /* disable SMM */ + fadt->acpi_enable = 0x00; /* unused if SMI_CMD = 0 */ + fadt->acpi_disable = 0x00; /* unused if SMI_CMD = 0 */ + + /* Enable ACPI */ + outl(inl(pmbase + 4) | 0x01, pmbase + 4); + + /* Power Control */ + fadt->s4bios_req = 0x00; + fadt->pstate_cnt = 0x00; + + /* Control Registers - Base Address */ + fadt->pm1a_evt_blk = pmbase + PM1_STS; + fadt->pm1b_evt_blk = 0x00; /* Not Used */ + fadt->pm1a_cnt_blk = pmbase + PM1_CNT; + fadt->pm1b_cnt_blk = 0x00; /* Not Used */ + fadt->pm2_cnt_blk = pmbase + PM2A_CNT_BLK; + fadt->pm_tmr_blk = pmbase + PM1_TMR; + fadt->gpe0_blk = pmbase + GPE0_STS; + fadt->gpe1_blk = 0x00; /* Not Used */ + + /* Control Registers - Length */ + fadt->pm1_evt_len = 4; /* 32 bits */ + fadt->pm1_cnt_len = 2; /* 32 bit register, 16 bits used */ + fadt->pm2_cnt_len = 1; /* 8 bits */ + fadt->pm_tmr_len = 4; /* 32 bits */ + fadt->gpe0_blk_len = 8; /* 64 bits */ + fadt->gpe1_blk_len = 0; + fadt->gpe1_base = 0; + fadt->cst_cnt = 0; + fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED; + fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED; + fadt->flush_size = 0; /* set to 0 if WBINVD is 1 in flags */ + fadt->flush_stride = 0; /* set to 0 if WBINVD is 1 in flags */ + fadt->duty_offset = 1; + fadt->duty_width = 0; + + /* RTC Registers */ + fadt->day_alrm = 0x0D; + fadt->mon_alrm = 0x00; + fadt->century = 0x00; + fadt->iapc_boot_arch = 0; + + fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED | + ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON | + ACPI_FADT_RESET_REGISTER | ACPI_FADT_SLEEP_TYPE | + ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_PLATFORM_CLOCK; + + /* Reset Register */ + fadt->reset_reg.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->reset_reg.bit_width = 8; + fadt->reset_reg.bit_offset = 0; + fadt->reset_reg.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; + fadt->reset_reg.addrl = 0xCF9; + fadt->reset_reg.addrh = 0x00; + fadt->reset_value = 6; + + /* Reserved Bits */ + fadt->res3 = 0x00; /* reserved, MUST be 0 ACPI 3.0 */ + fadt->res4 = 0x00; /* reserved, MUST be 0 ACPI 3.0 */ + fadt->res5 = 0x00; /* reserved, MUST be 0 ACPI 3.0 */ + + /* Extended ACPI Pointers */ + fadt->x_firmware_ctl_l = (unsigned long)facs; + fadt->x_firmware_ctl_h = 0x00; + fadt->x_dsdt_l = (unsigned long)dsdt; + fadt->x_dsdt_h = 0x00; + + /* PM1 Status & PM1 Enable */ + fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->x_pm1a_evt_blk.bit_width = fadt->pm1_evt_len * 8; + fadt->x_pm1a_evt_blk.bit_offset = 0; + fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; + fadt->x_pm1a_evt_blk.addrl = fadt->pm1a_evt_blk; + fadt->x_pm1a_evt_blk.addrh = 0x00; + + fadt->x_pm1b_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->x_pm1b_evt_blk.bit_width = 0; + fadt->x_pm1b_evt_blk.bit_offset = 0; + fadt->x_pm1b_evt_blk.access_size = 0; + fadt->x_pm1b_evt_blk.addrl = fadt->pm1b_evt_blk; + fadt->x_pm1b_evt_blk.addrh = 0x00; + + /* PM1 Control Registers */ + fadt->x_pm1a_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->x_pm1a_cnt_blk.bit_width = 16; + fadt->x_pm1a_cnt_blk.bit_offset = 0; + fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; + fadt->x_pm1a_cnt_blk.addrl = fadt->pm1a_cnt_blk; + fadt->x_pm1a_cnt_blk.addrh = 0x00; + + fadt->x_pm1b_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->x_pm1b_cnt_blk.bit_width = 0; + fadt->x_pm1b_cnt_blk.bit_offset = 0; + fadt->x_pm1b_cnt_blk.access_size = 0; + fadt->x_pm1b_cnt_blk.addrl = fadt->pm1b_cnt_blk; + fadt->x_pm1b_cnt_blk.addrh = 0x00; + + /* PM2 Control Registers */ + fadt->x_pm2_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->x_pm2_cnt_blk.bit_width = 8; + fadt->x_pm2_cnt_blk.bit_offset = 0; + fadt->x_pm2_cnt_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; + fadt->x_pm2_cnt_blk.addrl = fadt->pm2_cnt_blk; + fadt->x_pm2_cnt_blk.addrh = 0x00; + + /* PM1 Timer Register */ + fadt->x_pm_tmr_blk.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->x_pm_tmr_blk.bit_width = 32; + fadt->x_pm_tmr_blk.bit_offset = 0; + fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; + fadt->x_pm_tmr_blk.addrl = fadt->pm_tmr_blk; + fadt->x_pm_tmr_blk.addrh = 0x00; + + /* General-Purpose Event Registers */ + fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->x_gpe0_blk.bit_width = 64; /* EventStatus + EventEnable */ + fadt->x_gpe0_blk.bit_offset = 0; + fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; + fadt->x_gpe0_blk.addrl = fadt->gpe0_blk; + fadt->x_gpe0_blk.addrh = 0x00; + + fadt->x_gpe1_blk.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->x_gpe1_blk.bit_width = 0; + fadt->x_gpe1_blk.bit_offset = 0; + fadt->x_gpe1_blk.access_size = 0; + fadt->x_gpe1_blk.addrl = fadt->gpe1_blk; + fadt->x_gpe1_blk.addrh = 0x00; + + header->checksum = acpi_checksum((void *) fadt, sizeof(acpi_fadt_t)); +} + +static int calculate_power(int tdp, int p1_ratio, int ratio) +{ + u32 m; + u32 power; + + /* + * M = ((1.1 - ((p1_ratio - ratio) * 0.00625)) / 1.1) ^ 2 + * + * Power = (ratio / p1_ratio) * m * tdp + */ + + m = (110000 - ((p1_ratio - ratio) * 625)) / 11; + m = (m * m) / 1000; + + power = ((ratio * 100000 / p1_ratio) / 100); + power *= (m / 100) * (tdp / 1000); + power /= 1000; + + return (int)power; +} + +static void generate_P_state_entries(int core, int cores_per_package) +{ + int ratio_min, ratio_max, ratio_step; + int coord_type, power_max, power_unit, num_entries; + int ratio, power, clock, clock_max; + int turbo; + u32 control_status; + msr_t msr; + + /* Hardware coordination of P-states */ + coord_type = HW_ALL; + + /* Check for Turbo Mode */ + turbo = get_turbo_state() == TURBO_ENABLED; + + /* CPU attributes */ + msr = rdmsr(MSR_PLATFORM_INFO); + ratio_min = (msr.hi >> 8) & 0xff; // LFM + ratio_max = (msr.lo >> 8) & 0xff; // HFM + clock_max = (ratio_max * 100); + + /* Calculate CPU TDP in mW */ + msr = rdmsr(MSR_PKG_POWER_SKU_UNIT); + power_unit = 1 << (msr.lo & 0xf); + msr = rdmsr(MSR_PKG_POWER_LIMIT); + power_max = ((msr.lo & 0x7fff) / power_unit) * 1000; + + /* Write _PCT indicating use of FFixedHW */ + acpigen_write_empty_PCT(); + + /* Write _PPC starting from first supported P-state */ + acpigen_write_PPC(0); + + /* Write PSD indicating configured coordination type */ + acpigen_write_PSD_package(core, 1, coord_type); + + /* Add P-state entries in _PSS table */ + acpigen_write_name("_PSS"); + + /* Determine ratio points */ + /* Note: There should be at most 16 performance states. If Turbo Mode + is enabled, the Max Turbo Ratio will occupy one of these states. */ + ratio_step = 1; + num_entries = (ratio_max - ratio_min) / ratio_step; + while (num_entries > (15-turbo)) { + ratio_step <<= 1; + num_entries >>= 1; + } + + if (turbo) { + /* _PSS package count (with turbo) */ + acpigen_write_package(num_entries + 2); + + /* Get Max Turbo Ratio */ + msr = rdmsr(MSR_TURBO_RATIO_LIMIT); + ratio = msr.lo & 0xff; + + acpigen_write_PSS_package( + ratio * 100, /* MHz */ + power_max, /* mW */ + 10, /* lat1 */ + 10, /* lat2 */ + ratio << 8, /* control */ + ratio << 8); /* status */ + } else { + /* _PSS package count (without turbo) */ + acpigen_write_package(num_entries + 1); + } + + /* Generate the _PSS entries */ + for (ratio = ratio_min + (num_entries * ratio_step); + ratio >= ratio_min; ratio -= ratio_step) { + + /* Calculate power at this ratio */ + power = calculate_power(power_max, ratio_max, ratio); + clock = ratio * 100; + control_status = ratio << 8; + + acpigen_write_PSS_package( + clock, /* MHz */ + power, /* mW */ + 10, /* lat1 */ + 10, /* lat2 */ + control_status, /* control */ + control_status); /* status */ + } + + /* Fix package length */ + acpigen_pop_len(); +} + +void generate_cpu_entries(device_t device) +{ + int core; + int pcontrol_blk = get_pmbase(), plen = 6; + const struct pattrs *pattrs = pattrs_get(); + + for (core = 0; core < pattrs->num_cpus; core++) { + if (core > 0) { + pcontrol_blk = 0; + plen = 0; + } + + /* Generate processor \_PR.CP0x */ + acpigen_write_processor(core, pcontrol_blk, plen); + + /* Generate P-state tables */ + generate_P_state_entries(core, pattrs->num_cpus); + + /* Generate C-state tables */ + acpigen_write_CST_package(cstate_map, ARRAY_SIZE(cstate_map)); + + acpigen_pop_len(); + } +} + +unsigned long acpi_madt_irq_overrides(unsigned long current) +{ + int sci_irq = acpi_sci_irq(); + acpi_madt_irqoverride_t *irqovr; + uint16_t sci_flags = MP_IRQ_TRIGGER_LEVEL; + + /* INT_SRC_OVR */ + irqovr = (void *)current; + current += acpi_create_madt_irqoverride(irqovr, 0, 0, 2, 0); + + if (sci_irq >= 20) + sci_flags |= MP_IRQ_POLARITY_LOW; + else + sci_flags |= MP_IRQ_POLARITY_HIGH; + + irqovr = (void *)current; + current += acpi_create_madt_irqoverride(irqovr, 0, sci_irq, sci_irq, + sci_flags); + + irqovr = (void *)current; + current += acpi_create_madt_irqoverride(irqovr, 0, 3, 3, + (MP_IRQ_TRIGGER_LEVEL + | MP_IRQ_POLARITY_LOW)); + + irqovr = (void *)current; + current += acpi_create_madt_irqoverride(irqovr, 0, 4, 4, + (MP_IRQ_TRIGGER_LEVEL + | MP_IRQ_POLARITY_LOW)); + + return current; +} diff --git a/src/soc/intel/fsp_broadwell_de/acpi/irq_helper.h b/src/soc/intel/fsp_broadwell_de/acpi/irq_helper.h new file mode 100644 index 0000000..8799a9b --- /dev/null +++ b/src/soc/intel/fsp_broadwell_de/acpi/irq_helper.h @@ -0,0 +1,45 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#undef PCI_DEV_PIRQ_ROUTES +#undef ACPI_DEV_IRQ +#undef PCI_DEV_PIRQ_ROUTE +#undef PIRQ_PIC_ROUTES +#undef PIRQ_PIC +#undef IRQROUTE_H + +#if defined(PIC_MODE) + +#define ACPI_DEV_IRQ(dev_, pin_, pin_name_) \ + { Package() { ## dev_ ## ffff, pin_, \_SB.PCI0.LPCB.LNK ## pin_name_, 0 } } + +#else /* defined(PIC_MODE) */ + +#define ACPI_DEV_IRQ(dev_, pin_, pin_name_) \ + { Package() { ## dev_ ## ffff, pin_, 0, PIRQ ## pin_name_ ## _APIC_IRQ } } + +#endif + +#define PCI_DEV_PIRQ_ROUTE(dev_, a_, b_, c_, d_) \ + { ACPI_DEV_IRQ(dev_, 0, a_), \ + ACPI_DEV_IRQ(dev_, 1, b_), \ + ACPI_DEV_IRQ(dev_, 2, c_), \ + ACPI_DEV_IRQ(dev_, 3, d_) } + +/* Empty PIRQ_PIC definition. */ +#define PIRQ_PIC(pirq_, pic_irq_) + +/* Include the mainboard irq route definition */ +#include "irqroute.h" diff --git a/src/soc/intel/fsp_broadwell_de/acpi/irqlinks.asl b/src/soc/intel/fsp_broadwell_de/acpi/irqlinks.asl new file mode 100644 index 0000000..7d02eb0 --- /dev/null +++ b/src/soc/intel/fsp_broadwell_de/acpi/irqlinks.asl @@ -0,0 +1,464 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +OperationRegion (PRR0, PCI_Config, 0x00, 0x100) +Field (PRR0, AnyAcc, NoLock, Preserve) { + Offset(0x60), + PIRA, 8, + PIRB, 8, + PIRC, 8, + PIRD, 8, + Offset(0x68), + PIRE, 8, + PIRF, 8, + PIRG, 8, + PIRH, 8 +} + +Device (LNKA) { // PCI IRQ link A + Name (_HID,EISAID("PNP0C0F")) + //Name(_UID, 1) + Method (_STA,0,NotSerialized) { + If(And(PIRA, 0x80)) { + Return (0x9) + } Else { + Return (0xB) + } // Don't display + } + + Method (_DIS,0,NotSerialized) { + Or (PIRA, 0x80, PIRA) + } + + Method (_CRS,0,Serialized) { + Name (BUF0, ResourceTemplate() {IRQ(Level,ActiveLow,Shared){0}}) + // + // Define references to buffer elements + // + CreateWordField (BUF0, 0x01, IRQW) // IRQ low + // + // Write current settings into IRQ descriptor + // + If (And(PIRA, 0x80)) { + Store (Zero, Local0) + } Else { + Store (One,Local0) + } + // + // Shift 1 by value in register 70, Save in buffer + // + ShiftLeft (Local0,And (PIRA,0x0F),IRQW) // Save in buffer + Return (BUF0) // Return Buf0 + } // End of _CRS method + + Name (_PRS, ResourceTemplate() + {IRQ(Level,ActiveLow,Shared){3,4,5,6,7,9,10,11,12,14,15}}) + + Method (_SRS,1,NotSerialized) { + CreateWordField (ARG0, 0x01, IRQW) // IRQ low + + FindSetRightBit(IRQW,Local0) // Set IRQ + If (LNotEqual (IRQW,Zero)){ + And (Local0, 0x7F,Local0) + Decrement (Local0) + } Else { + Or (Local0, 0x80,Local0) + } + Store (Local0, PIRA) + } // End of _SRS Method +} + +Device(LNKB) { // PCI IRQ link B + Name (_HID,EISAID("PNP0C0F")) + //Name(_UID, 2) + Method (_STA,0,NotSerialized) { + If (And (PIRB, 0x80)) { + Return (0x9) + } Else { + Return (0xB) + } // Don't display + } + + Method (_DIS,0,NotSerialized) { + Or (PIRB, 0x80,PIRB) + } + + Method (_CRS,0,Serialized) { + Name(BUF0, ResourceTemplate() + {IRQ(Level,ActiveLow,Shared){0}}) + // + // Define references to buffer elements + // + CreateWordField (BUF0, 0x01, IRQW) // IRQ low + // + // Write current settings into IRQ descriptor + // + If (And (PIRB, 0x80)) { + Store (Zero, Local0) + } Else { + Store (One,Local0) + } + // + // Shift 1 by value in register 70, Save in buffer + // + ShiftLeft (Local0,And (PIRB,0x0F),IRQW) // Save in buffer + Return (BUF0) // Return Buf0 + } // End of _CRS method + + Name (_PRS, + ResourceTemplate() + {IRQ(Level,ActiveLow,Shared){3,4,5,6,7,9,10,11,12,14,15}}) + + Method (_SRS,1,NotSerialized) { + CreateWordField (ARG0, 0x01, IRQW) // IRQ low + + FindSetRightBit(IRQW,Local0) // Set IRQ + If (LNotEqual(IRQW,Zero)) { + And (Local0, 0x7F, Local0) + Decrement (Local0) + } Else { + Or (Local0, 0x80, Local0) + } + Store (Local0, PIRB) + } // End of _SRS Method +} + +Device(LNKC) { // PCI IRQ link C + Name(_HID, EISAID("PNP0C0F")) + //Name(_UID, 3) + + Method (_STA,0,NotSerialized) { + If (And (PIRC, 0x80)) { + Return (0x9) + } Else { + Return (0xB) + } // Don't display + } + + Method (_DIS, 0, NotSerialized) { + Or (PIRC, 0x80, PIRC) + } + + Method (_CRS, 0, Serialized) { + Name (BUF0, ResourceTemplate() + {IRQ(Level,ActiveLow,Shared){0}}) + // + // Define references to buffer elements + // + CreateWordField (BUF0, 0x01, IRQW) // IRQ low + // + // Write current settings into IRQ descriptor + // + If (And (PIRC, 0x80)) { + Store (Zero, Local0) + } Else { + Store (One,Local0) + } + // + // Shift 1 by value in register 70, Save in buffer + // + ShiftLeft (Local0,And (PIRC,0x0F),IRQW) + Return (BUF0) + } // End of _CRS method + + Name (_PRS, ResourceTemplate() + {IRQ(Level,ActiveLow,Shared){3,4,5,6,7,9,10,11,12,14,15}}) + + Method (_SRS,1,NotSerialized) { + CreateWordField (ARG0, 0x01, IRQW) // IRQ low + FindSetRightBit(IRQW,Local0) // Set IRQ + If (LNotEqual (IRQW,Zero)) { + And (Local0, 0x7F, Local0) + Decrement (Local0) + } Else { + Or (Local0, 0x80,Local0) + } + Store (Local0, PIRC) + } // End of _SRS Method +} + +Device (LNKD) { // PCI IRQ link D + Name (_HID,EISAID ("PNP0C0F")) + + //Name(_UID, 4) + + Method (_STA, 0, NotSerialized) { + If (And (PIRD, 0x80)) { + Return (0x9) + } Else { + Return (0xB) + } // Don't display + } + + Method (_DIS, 0, NotSerialized) { + Or(PIRD, 0x80,PIRD) + } + + Method (_CRS,0,Serialized) { + Name (BUF0, ResourceTemplate() + {IRQ(Level,ActiveLow,Shared){0}}) + // + // Define references to buffer elements + // + CreateWordField (BUF0, 0x01, IRQW) // IRQ low + // + // Write current settings into IRQ descriptor + // + If (And (PIRD, 0x80)) { + Store (Zero, Local0) + } Else { + Store (One,Local0) + } + // + // Shift 1 by value in register 70, Save in buffer + // + ShiftLeft (Local0, And (PIRD,0x0F), IRQW) + Return (BUF0) // Return Buf0 + } // End of _CRS method + + Name (_PRS, ResourceTemplate() + {IRQ(Level,ActiveLow,Shared){3,4,5,6,7,9,10,11,12,14,15}}) + + Method (_SRS,1,NotSerialized) { + CreateWordField (ARG0, 0x01, IRQW) // IRQ low + FindSetRightBit (IRQW, Local0)// Set IRQ + If (LNotEqual (IRQW, Zero)) { + And (Local0, 0x7F, Local0) + Decrement (Local0) + } Else { + Or (Local0, 0x80, Local0) + } + Store(Local0, PIRD) + } // End of _SRS Method +} + +Device(LNKE) { // PCI IRQ link E + Name(_HID,EISAID("PNP0C0F")) + + //Name(_UID, 5) + + Method (_STA,0,NotSerialized) { + If (And (PIRE, 0x80)) { + Return(0x9) + } Else { + Return(0xB) + } // Don't display + } + + Method (_DIS,0,NotSerialized) { + Or (PIRE, 0x80, PIRE) + } + + Method (_CRS, 0, Serialized) { + Name (BUF0, ResourceTemplate() + {IRQ(Level,ActiveLow,Shared){0}}) + // + // Define references to buffer elements + // + CreateWordField (BUF0, 0x01, IRQW) // IRQ low + // + // Write current settings into IRQ descriptor + // + If (And (PIRE, 0x80)) { + Store (Zero, Local0) + } Else { + Store (One, Local0) + } + // + // Shift 1 by value in register 70, Save in buffer + // + ShiftLeft (Local0, And (PIRE,0x0F), IRQW) + Return (BUF0) // Return Buf0 + } // End of _CRS method + + Name(_PRS, ResourceTemplate() + {IRQ(Level,ActiveLow,Shared){3,4,5,6,7,9,10,11,12,14,15}}) + + Method (_SRS,1,NotSerialized) { + CreateWordField (ARG0, 0x01, IRQW) // IRQ low + FindSetRightBit (IRQW, Local0) // Set IRQ + If (LNotEqual (IRQW, Zero)) { + And (Local0, 0x7F, Local0) + Decrement (Local0) + } Else { + Or (Local0, 0x80, Local0) + } + Store (Local0, PIRE) + } // End of _SRS Method +} + +Device(LNKF) { // PCI IRQ link F + Name (_HID,EISAID("PNP0C0F")) + + //Name(_UID, 6) + + Method (_STA,0,NotSerialized) { + If (And (PIRF, 0x80)) { + Return (0x9) + } Else { + Return (0xB) + } // Don't display + } + + Method (_DIS,0,NotSerialized) { + Or (PIRB, 0x80, PIRF) + } + + Method (_CRS,0,Serialized) { + Name(BUF0, ResourceTemplate() + {IRQ(Level,ActiveLow,Shared){0}}) + // + // Define references to buffer elements + // + CreateWordField (BUF0, 0x01, IRQW) // IRQ low + // + // Write current settings into IRQ descriptor + // + If (And (PIRF, 0x80)) { + Store (Zero, Local0) + } Else { + Store (One, Local0) + } + // + // Shift 1 by value in register 70, Save in buffer + // + ShiftLeft (Local0, And (PIRF, 0x0F),IRQW) + Return (BUF0) + } // End of _CRS method + + Name(_PRS, ResourceTemplate() + {IRQ(Level,ActiveLow,Shared){3,4,5,6,7,9,10,11,12,14,15}}) + + Method (_SRS,1,NotSerialized) { + CreateWordField (ARG0, 0x01, IRQW) // IRQ low + FindSetRightBit (IRQW,Local0) // Set IRQ + If (LNotEqual (IRQW,Zero)) { + And (Local0, 0x7F,Local0) + Decrement (Local0) + } Else { + Or (Local0, 0x80, Local0) + } + Store (Local0, PIRF) + } // End of _SRS Method +} + +Device(LNKG) { // PCI IRQ link G + Name(_HID,EISAID("PNP0C0F")) + //Name(_UID, 7) + Method(_STA,0,NotSerialized) { + If (And (PIRG, 0x80)) { + Return (0x9) + } Else { + Return (0xB) + } // Don't display + } + + Method (_DIS, 0, NotSerialized) { + Or(PIRG, 0x80,PIRG) + } + + Method (_CRS,0,Serialized){ + Name(BUF0,ResourceTemplate() + {IRQ(Level,ActiveLow,Shared){0}}) + // + // Define references to buffer elements + // + CreateWordField (BUF0, 0x01, IRQW) // IRQ low + // + // Write current settings into IRQ descriptor + // + If (And(PIRG, 0x80)) { + Store(Zero, Local0) + } Else { + Store(One,Local0) + } + // + // Shift 1 by value in register 70, Save in buffer + // + ShiftLeft (Local0,And(PIRG,0x0F),IRQW) + Return (BUF0) + } // End of _CRS method + + Name (_PRS, ResourceTemplate() + {IRQ(Level,ActiveLow,Shared){3,4,5,6,7,9,10,11,12,14,15}}) + + Method (_SRS,1,NotSerialized) { + CreateWordField (ARG0, 0x01, IRQW) // IRQ low + FindSetRightBit(IRQW,Local0) // Set IRQ + If (LNotEqual (IRQW,Zero)) { + And (Local0, 0x7F,Local0) + Decrement (Local0) + } Else { + Or (Local0, 0x80,Local0) + } + Store (Local0, PIRG) + } // End of _SRS Method +} + +Device(LNKH) { // PCI IRQ link H + Name (_HID,EISAID("PNP0C0F")) + + //Name(_UID, 8) + + Method (_STA,0,NotSerialized) { + If (And(PIRH, 0x80)) { + Return(0x9) + } Else { + Return(0xB) + } // Don't display + } + + Method (_DIS,0,NotSerialized) { + Or(PIRH, 0x80,PIRH) + } + + Method (_CRS,0,Serialized) { + Name(BUF0, ResourceTemplate() + {IRQ(Level,ActiveLow,Shared){0}}) + // + // Define references to buffer elements + // + CreateWordField (BUF0, 0x01, IRQW) // IRQ low + // + // Write current settings into IRQ descriptor + // + If (And (PIRH, 0x80)) { + Store (Zero, Local0) + } Else { + Store (One,Local0) + } + // + // Shift 1 by value in register 70, Save in buffer + // + ShiftLeft (Local0,And(PIRH,0x0F),IRQW) + Return (BUF0) + } // End of _CRS method + + Name(_PRS, ResourceTemplate() + {IRQ(Level,ActiveLow,Shared){3,4,5,6,7,9,10,11,12,14,15}}) + + Method (_SRS,1,NotSerialized) { + CreateWordField (ARG0, 0x01, IRQW) // IRQ low + FindSetRightBit (IRQW,Local0)// Set IRQ + If (LNotEqual (IRQW,Zero)) { + And (Local0, 0x7F,Local0) + Decrement (Local0) + } Else { + Or (Local0, 0x80,Local0) + } + Store (Local0, PIRH) + } +} diff --git a/src/soc/intel/fsp_broadwell_de/acpi/irqroute.asl b/src/soc/intel/fsp_broadwell_de/acpi/irqroute.asl new file mode 100644 index 0000000..a4ce5ea --- /dev/null +++ b/src/soc/intel/fsp_broadwell_de/acpi/irqroute.asl @@ -0,0 +1,39 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* PCI Interrupt Routing */ +Method(_PRT) +{ + /* + * PICM comes from _PIC, which returns the following: + * 0 – PIC mode + * 1 – APIC mode + * 2 – SAPIC mode + */ + If (PICM) { + Return (Package() { + #undef PIC_MODE + #include "irq_helper.h" + PCI_DEV_PIRQ_ROUTES + }) + } Else { + Return (Package() { + #define PIC_MODE + #include "irq_helper.h" + PCI_DEV_PIRQ_ROUTES + }) + } +} diff --git a/src/soc/intel/fsp_broadwell_de/acpi/lpc.asl b/src/soc/intel/fsp_broadwell_de/acpi/lpc.asl new file mode 100644 index 0000000..92ead9f --- /dev/null +++ b/src/soc/intel/fsp_broadwell_de/acpi/lpc.asl @@ -0,0 +1,94 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* Intel LPC Bus Device - 0:1f.0 */ + +Device (LPC0) +{ + Name(_ADR, 0x001f0000) + + #include "irqlinks.asl" + + Device (FWH) // Firmware Hub + { + Name (_HID, EISAID("INT0800")) + Name (_CRS, ResourceTemplate() + { + Memory32Fixed(ReadOnly, 0xff000000, 0x01000000) + }) + } + + Device (HPET) + { + Name (_HID, EISAID("PNP0103")) + Name (_CID, 0x010CD041) + + Method (_STA, 0) // Device Status + { + Return (0xf) // Enable and show device + } + + Name(_CRS, ResourceTemplate() + { + Memory32Fixed(ReadOnly, 0xfed00000, 0x400) + }) + } + + Device(LDRC) // LPC device: Resource consumption + { + Name (_HID, EISAID("PNP0C02")) + Name (_UID, 2) + + Name (RBUF, ResourceTemplate() + { + IO (Decode16, 0x61, 0x61, 0x1, 0x01) // NMI Status + IO (Decode16, 0x63, 0x63, 0x1, 0x01) // CPU Reserved + IO (Decode16, 0x65, 0x65, 0x1, 0x01) // CPU Reserved + IO (Decode16, 0x67, 0x67, 0x1, 0x01) // CPU Reserved + IO (Decode16, 0x80, 0x80, 0x1, 0x01) // Port 80 Post + IO (Decode16, 0x92, 0x92, 0x1, 0x01) // CPU Reserved + IO (Decode16, 0xb2, 0xb2, 0x1, 0x02) // SWSMI + }) + + Method (_CRS, 0, NotSerialized) + { + Return (RBUF) + } + } + + Device (RTC) // Real Time Clock + { + Name (_HID, EISAID("PNP0B00")) + Name (_CRS, ResourceTemplate() + { + IO (Decode16, 0x70, 0x70, 1, 8) +// Disable as Windows doesn't like it, and systems don't seem to use it. +// IRQNoFlags() { 8 } + }) + } + + Device (TIMR) // Intel 8254 timer + { + Name(_HID, EISAID("PNP0100")) + Name(_CRS, ResourceTemplate() + { + IO (Decode16, 0x40, 0x40, 0x01, 0x04) + IO (Decode16, 0x50, 0x50, 0x10, 0x04) + IRQNoFlags() {0} + }) + } +} diff --git a/src/soc/intel/fsp_broadwell_de/acpi/pcie1.asl b/src/soc/intel/fsp_broadwell_de/acpi/pcie1.asl new file mode 100644 index 0000000..950a362 --- /dev/null +++ b/src/soc/intel/fsp_broadwell_de/acpi/pcie1.asl @@ -0,0 +1,465 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015-2016 Intel Corp. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Name (PR01, Package() { + // [SL01]: PCI Express Slot 1 on 1A on PCI0 + Package() { 0x0000FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, + Package() { 0x0000FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, + Package() { 0x0000FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, + Package() { 0x0000FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, +}) + +Name (AR01, Package() { + // [SL01]: PCI Express Slot 1 on 1A on PCI0 + Package() { 0x0000FFFF, 0, 0, 16 }, + Package() { 0x0000FFFF, 1, 0, 17 }, + Package() { 0x0000FFFF, 2, 0, 18 }, + Package() { 0x0000FFFF, 3, 0, 19 }, +}) + +Name (AH01, Package() { + // [SL01]: PCI Express Slot 1 on 1A on PCI0 + Package() { 0x0000FFFF, 0, 0, 26 }, + Package() { 0x0000FFFF, 1, 0, 28 }, + Package() { 0x0000FFFF, 2, 0, 29 }, + Package() { 0x0000FFFF, 3, 0, 30 }, +}) + +Name (PR02, Package() { + // [SL02]: PCI Express Slot 2 on 1B on PCI0 + Package() { 0x0000FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, + Package() { 0x0000FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, + Package() { 0x0000FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, + Package() { 0x0000FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, +}) + +Name (AR02, Package() { + // [SL02]: PCI Express Slot 2 on 1B on PCI0 + Package() { 0x0000FFFF, 0, 0, 16 }, + Package() { 0x0000FFFF, 1, 0, 17 }, + Package() { 0x0000FFFF, 2, 0, 18 }, + Package() { 0x0000FFFF, 3, 0, 19 }, +}) + +Name (AH02, Package() { + // [SL02]: PCI Express Slot 2 on 1B on PCI0 + Package() { 0x0000FFFF, 0, 0, 27 }, + Package() { 0x0000FFFF, 1, 0, 30 }, + Package() { 0x0000FFFF, 2, 0, 28 }, + Package() { 0x0000FFFF, 3, 0, 29 }, +}) + +Name (PR03, Package() { + // [CB0I]: CB3DMA on IOSF + Package() { 0x0000FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, + // [CB0J]: CB3DMA on IOSF + Package() { 0x0000FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, + // [CB0K]: CB3DMA on IOSF + Package() { 0x0000FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, + // [CB0L]: CB3DMA on IOSF + Package() { 0x0000FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, +}) + +Name (AR03, Package() { + // [CB0I]: CB3DMA on IOSF + Package() { 0x0000FFFF, 0, 0, 16 }, + // [CB0J]: CB3DMA on IOSF + Package() { 0x0000FFFF, 1, 0, 17 }, + // [CB0K]: CB3DMA on IOSF + Package() { 0x0000FFFF, 2, 0, 18 }, + // [CB0L]: CB3DMA on IOSF + Package() { 0x0000FFFF, 3, 0, 19 }, +}) + +Name (AH03, Package() { + // [CB0I]: CB3DMA on IOSF + Package() { 0x0000FFFF, 0, 0, 32 }, + // [CB0J]: CB3DMA on IOSF + Package() { 0x0000FFFF, 1, 0, 36 }, + // [CB0K]: CB3DMA on IOSF + Package() { 0x0000FFFF, 2, 0, 37 }, + // [CB0L]: CB3DMA on IOSF + Package() { 0x0000FFFF, 3, 0, 38 }, +}) + +Name (PR04, Package() { + // [SL04]: PCI Express Slot 4 on 2B on PCI0 + Package() { 0x0000FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, + Package() { 0x0000FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, + Package() { 0x0000FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, + Package() { 0x0000FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, +}) + +Name (AR04, Package() { + // [SL04]: PCI Express Slot 4 on 2B on PCI0 + Package() { 0x0000FFFF, 0, 0, 16 }, + Package() { 0x0000FFFF, 1, 0, 17 }, + Package() { 0x0000FFFF, 2, 0, 18 }, + Package() { 0x0000FFFF, 3, 0, 19 }, +}) + +Name (AH04, Package() { + // [SL04]: PCI Express Slot 4 on 2B on PCI0 + Package() { 0x0000FFFF, 0, 0, 33 }, + Package() { 0x0000FFFF, 1, 0, 37 }, + Package() { 0x0000FFFF, 2, 0, 38 }, + Package() { 0x0000FFFF, 3, 0, 36 }, +}) + +Name (PR05, Package() { + // [SL05]: PCI Express Slot 5 on 2C on PCI0 + Package() { 0x0000FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, + Package() { 0x0000FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, + Package() { 0x0000FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, + Package() { 0x0000FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, +}) + +Name (AR05, Package() { + // [SL05]: PCI Express Slot 5 on 2C on PCI0 + Package() { 0x0000FFFF, 0, 0, 16 }, + Package() { 0x0000FFFF, 1, 0, 17 }, + Package() { 0x0000FFFF, 2, 0, 18 }, + Package() { 0x0000FFFF, 3, 0, 19 }, +}) + +Name (AH05, Package() { + // [SL05]: PCI Express Slot 5 on 2C on PCI0 + Package() { 0x0000FFFF, 0, 0, 34 }, + Package() { 0x0000FFFF, 1, 0, 37 }, + Package() { 0x0000FFFF, 2, 0, 36 }, + Package() { 0x0000FFFF, 3, 0, 38 }, +}) + +Name (PR06, Package() { + // [SL06]: PCI Express Slot 6 on 2D on PCI0 + Package() { 0x0000FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, + Package() { 0x0000FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, + Package() { 0x0000FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, + Package() { 0x0000FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, +}) + +Name (AR06, Package() { + // [SL06]: PCI Express Slot 6 on 2D on PCI0 + Package() { 0x0000FFFF, 0, 0, 16 }, + Package() { 0x0000FFFF, 1, 0, 17 }, + Package() { 0x0000FFFF, 2, 0, 18 }, + Package() { 0x0000FFFF, 3, 0, 19 }, +}) + +Name (AH06, Package() { + // [SL06]: PCI Express Slot 6 on 2D on PCI0 + Package() { 0x0000FFFF, 0, 0, 35 }, + Package() { 0x0000FFFF, 1, 0, 36 }, + Package() { 0x0000FFFF, 2, 0, 38 }, + Package() { 0x0000FFFF, 3, 0, 37 }, +}) + +Name (PR07, Package() { + // [SL07]: PCI Express Slot 7 on 3A on PCI0 + Package() { 0x0000FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, + Package() { 0x0000FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, + Package() { 0x0000FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, + Package() { 0x0000FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, +}) + +Name (AR07, Package() { + // [SL07]: PCI Express Slot 7 on 3A on PCI0 + Package() { 0x0000FFFF, 0, 0, 16 }, + Package() { 0x0000FFFF, 1, 0, 17 }, + Package() { 0x0000FFFF, 2, 0, 18 }, + Package() { 0x0000FFFF, 3, 0, 19 }, +}) + +Name (AH07, Package() { + // [SL07]: PCI Express Slot 7 on 3A on PCI0 + Package() { 0x0000FFFF, 0, 0, 40 }, + Package() { 0x0000FFFF, 1, 0, 44 }, + Package() { 0x0000FFFF, 2, 0, 45 }, + Package() { 0x0000FFFF, 3, 0, 46 }, +}) + +Name (PR08, Package() { + // [SL08]: PCI Express Slot 8 on 3B on PCI0 + Package() { 0x0000FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, + Package() { 0x0000FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, + Package() { 0x0000FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, + Package() { 0x0000FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, +}) + +Name (AR08, Package() { + // [SL08]: PCI Express Slot 8 on 3B on PCI0 + Package() { 0x0000FFFF, 0, 0, 16 }, + Package() { 0x0000FFFF, 1, 0, 17 }, + Package() { 0x0000FFFF, 2, 0, 18 }, + Package() { 0x0000FFFF, 3, 0, 19 }, +}) + +Name (AH08, Package() { + // [SL08]: PCI Express Slot 8 on 3B on PCI0 + Package() { 0x0000FFFF, 0, 0, 41 }, + Package() { 0x0000FFFF, 1, 0, 45 }, + Package() { 0x0000FFFF, 2, 0, 46 }, + Package() { 0x0000FFFF, 3, 0, 44 }, +}) + +Name (PR09, Package() { + // [SL09]: PCI Express Slot 9 on 3C on PCI0 + Package() { 0x0000FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, + Package() { 0x0000FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, + Package() { 0x0000FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, + Package() { 0x0000FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, +}) + +Name (AR09, Package() { + // [SL09]: PCI Express Slot 9 on 3C on PCI0 + Package() { 0x0000FFFF, 0, 0, 16 }, + Package() { 0x0000FFFF, 1, 0, 17 }, + Package() { 0x0000FFFF, 2, 0, 18 }, + Package() { 0x0000FFFF, 3, 0, 19 }, +}) + +Name (AH09, Package() { + // [SL09]: PCI Express Slot 9 on 3C on PCI0 + Package() { 0x0000FFFF, 0, 0, 42 }, + Package() { 0x0000FFFF, 1, 0, 45 }, + Package() { 0x0000FFFF, 2, 0, 44 }, + Package() { 0x0000FFFF, 3, 0, 46 }, +}) + +Name (PR0A, Package() { + // [SL0A]: PCI Express Slot 10 on 3D on PCI0 + Package() { 0x0000FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, + Package() { 0x0000FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, + Package() { 0x0000FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, + Package() { 0x0000FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, +}) + +Name (AR0A, Package() { + // [SL0A]: PCI Express Slot 10 on 3D on PCI0 + Package() { 0x0000FFFF, 0, 0, 16 }, + Package() { 0x0000FFFF, 1, 0, 17 }, + Package() { 0x0000FFFF, 2, 0, 18 }, + Package() { 0x0000FFFF, 3, 0, 19 }, +}) + +Name (AH0A, Package() { + // [SL0A]: PCI Express Slot 10 on 3D on PCI0 + Package() { 0x0000FFFF, 0, 0, 43 }, + Package() { 0x0000FFFF, 1, 0, 44 }, + Package() { 0x0000FFFF, 2, 0, 46 }, + Package() { 0x0000FFFF, 3, 0, 45 }, +}) + + + // PCI Express Port 1A on PCI0 +Device (BR1A) { + Name (_ADR, 0x00010000) + Method (_PRW, 0) { + Return (Package (0x02) {0x09, 0x04}) + } + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR01) + } + If (LEqual(APC1, One)) { + Return (AH01) + } + Return (AR01) + } + +} + +// PCI Express Port 1B on PCI0 +Device (BR1B) { + Name (_ADR, 0x00010001) + Method (_PRW, 0) { + Return (Package (0x02) {0x09, 0x04}) + } + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR02) + } + If (LEqual(APC1, One)) { + Return (AH02) + } + Return (AR02) + } + +} + +// PCI Express Port 2A on PCI0 +Device (BR2A) { + Name (_ADR, 0x00020000) + Method (_PRW, 0) { + Return (Package (0x02) {0x09, 0x04}) + } + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR03) + } + If (LEqual(APC1, One)) { + Return (AH03) + } + Return (AR03) + } + + + // CB3DMA on IOSF + Device (CB0I) { + Name (_ADR, 0x00000000) + } + + // CB3DMA on IOSF + Device (CB0J) { + Name (_ADR, 0x00000001) + } + + // CB3DMA on IOSF + Device (CB0K) { + Name (_ADR, 0x00000002) + } + + // CB3DMA on IOSF + Device (CB0L) { + Name (_ADR, 0x00000003) + } +} + +// PCI Express Port 2B on PCI0 +Device (BR2B) { + Name (_ADR, 0x00020001) + Method (_PRW, 0) { + Return (Package (0x02) {0x09, 0x04}) + } + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR04) + } + If (LEqual(APC1, One)) { + Return (AH04) + } + Return (AR04) + } + +} + +// PCI Express Port 2C on PCI0 +Device (BR2C) { + Name (_ADR, 0x00020002) + Method (_PRW, 0) { + Return (Package (0x02) {0x09, 0x04}) + } + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR05) + } + If (LEqual(APC1, One)) { + Return (AH05) + } + Return (AR05) + } + +} + +// PCI Express Port 2D on PCI0 +Device (BR2D) { + Name (_ADR, 0x00020003) + Method (_PRW, 0) { + Return (Package (0x02) {0x09, 0x04}) + } + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR06) + } + If (LEqual(APC1, One)) { + Return (AH06) + } + Return (AR06) + } + +} + +// PCI Express Port 3A on PCI0 +Device (BR3A) { + Name (_ADR, 0x00030000) + Method (_PRW, 0) { + Return (Package (0x02) {0x09, 0x04}) + } + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR07) + } + If (LEqual(APC1, One)) { + Return (AH07) + } + Return (AR07) + } + +} + +// PCI Express Port 3B on PCI0 +Device (BR3B) { + Name (_ADR, 0x00030001) + Method (_PRW, 0) { + Return (Package (0x02) {0x09, 0x04}) + } + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR08) + } + If (LEqual(APC1, One)) { + Return (AH08) + } + Return (AR08) + } + +} + +// PCI Express Port 3C on PCI0 +Device (BR3C) { + Name (_ADR, 0x00030002) + Method (_PRW, 0) { + Return (Package (0x02) {0x09, 0x04}) + } + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR09) + } + If (LEqual(APC1, One)) { + Return (AH09) + } + Return (AR09) + } + +} + +// PCI Express Port 3D on PCI0 +Device (BR3D) { + Name (_ADR, 0x00030003) + Method (_PRW, 0) { + Return (Package (0x02) {0x09, 0x04}) + } + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR0A) + } + If (LEqual(APC1, One)) { + Return (AH0A) + } + Return (AR0A) + } + +} diff --git a/src/soc/intel/fsp_broadwell_de/acpi/southcluster.asl b/src/soc/intel/fsp_broadwell_de/acpi/southcluster.asl new file mode 100644 index 0000000..a82a402 --- /dev/null +++ b/src/soc/intel/fsp_broadwell_de/acpi/southcluster.asl @@ -0,0 +1,424 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015-2016 Intel Corp. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <soc/iomap.h> +#include <soc/irq.h> + +Name(_HID,EISAID("PNP0A08")) // PCIe +Name(_CID,EISAID("PNP0A03")) // PCI + +Name(_ADR, 0) +Name(_BBN, 0) + +Name (MCRS, ResourceTemplate() { + // Bus Numbers + WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, + 0x0000, 0x0000, 0x00fe, 0x0000, 0xff,,, PB00) + + // IO Region 0 + DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, 0x0000, 0x0cf7, 0x0000, 0x0cf8,,, PI00) + + // PCI Config Space + Io (Decode16, 0x0cf8, 0x0cf8, 0x0001, 0x0008) + + // IO Region 1 + DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, 0x0d00, 0xefff, 0x0000, 0xE300,,, PI01) + + // VGA memory (0xa0000-0xbffff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000a0000, 0x000bffff, 0x00000000, + 0x00020000,,, ASEG) + + // OPROM reserved (0xc0000-0xc3fff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000c0000, 0x000c3fff, 0x00000000, + 0x00004000,,, OPR0) + + // OPROM reserved (0xc4000-0xc7fff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000c4000, 0x000c7fff, 0x00000000, + 0x00004000,,, OPR1) + + // OPROM reserved (0xc8000-0xcbfff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000c8000, 0x000cbfff, 0x00000000, + 0x00004000,,, OPR2) + + // OPROM reserved (0xcc000-0xcffff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000cc000, 0x000cffff, 0x00000000, + 0x00004000,,, OPR3) + + // OPROM reserved (0xd0000-0xd3fff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000d0000, 0x000d3fff, 0x00000000, + 0x00004000,,, OPR4) + + // OPROM reserved (0xd4000-0xd7fff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000d4000, 0x000d7fff, 0x00000000, + 0x00004000,,, OPR5) + + // OPROM reserved (0xd8000-0xdbfff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000d8000, 0x000dbfff, 0x00000000, + 0x00004000,,, OPR6) + + // OPROM reserved (0xdc000-0xdffff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000dc000, 0x000dffff, 0x00000000, + 0x00004000,,, OPR7) + + // BIOS Extension (0xe0000-0xe3fff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000e0000, 0x000e3fff, 0x00000000, + 0x00004000,,, ESG0) + + // BIOS Extension (0xe4000-0xe7fff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000e4000, 0x000e7fff, 0x00000000, + 0x00004000,,, ESG1) + + // BIOS Extension (0xe8000-0xebfff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000e8000, 0x000ebfff, 0x00000000, + 0x00004000,,, ESG2) + + // BIOS Extension (0xec000-0xeffff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000ec000, 0x000effff, 0x00000000, + 0x00004000,,, ESG3) + + // System BIOS (0xf0000-0xfffff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000f0000, 0x000fffff, 0x00000000, + 0x00010000,,, FSEG) + + // PCI Memory Region (Top of memory-0xfeafffff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x90000000, 0xFEAFFFFF, 0x00000000, + 0x6EB00000,,, PMEM) + + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0xfec00000, 0xfecfffff, 0x00000000, + 0x00100000,,, APIC) + + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0xfed00000, 0xfedfffff, 0x00000000, + 0x00100000,,, PCHR) + + QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite, + 0x0000000000000000, // Granularity + 0x0000380000000000, // Range Minimum + 0x0000383FFFFFFFFF, // Range Maximum + 0x0000000000000000, // Translation Offset + 0x0000004000000000, // Length + ,,, AddressRangeMemory, TypeStatic) +}) + +Method (_CRS, 0, Serialized) { + Return (MCRS) +} + +/* Device Resource Consumption */ +Device (PDRC) { + Name (_HID, EISAID("PNP0C02")) + Name (_UID, 1) + + Name (PDRS, ResourceTemplate() { + Memory32Fixed(ReadWrite, ABORT_BASE_ADDRESS, ABORT_BASE_SIZE) + Memory32Fixed(ReadWrite, PSEG_BASE_ADDRESS, PSEG_BASE_SIZE) + Memory32Fixed(ReadWrite, IOXAPIC1_BASE_ADDRESS, IOXAPIC1_BASE_SIZE) + Memory32Fixed(ReadWrite, IOXAPIC2_BASE_ADDRESS, IOXAPIC2_BASE_SIZE) + Memory32Fixed(ReadWrite, PCH_BASE_ADDRESS, PCH_BASE_SIZE) + Memory32Fixed(ReadWrite, LXAPIC_BASE_ADDRESS, LXAPIC_BASE_SIZE) + Memory32Fixed(ReadWrite, FIRMWARE_BASE_ADDRESS, FIRMWARE_BASE_SIZE) + }) + + // Current Resource Settings + Method (_CRS, 0, Serialized) + { + Return(PDRS) + } +} + +Method (_OSC, 4) { + /* Check for proper GUID */ + If (LEqual (Arg0, ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) + { + /* Let OS control everything */ + Return (Arg3) + } + Else + { + /* Unrecognized UUID */ + CreateDWordField (Arg3, 0, CDW1) + Or (CDW1, 4, CDW1) + Return (Arg3) + } +} + +Name (PR00, Package() { + // [DMI0]: Legacy PCI Express Port 0 on PCI0 + Package() { 0x0000FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, + // [BR1A]: PCI Express Port 1A on PCI0 + // [BR1B]: PCI Express Port 1B on PCI0 + Package() { 0x0001FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, + // [BR2A]: PCI Express Port 2A on PCI0 + // [BR2B]: PCI Express Port 2B on PCI0 + // [BR2C]: PCI Express Port 2C on PCI0 + // [BR2D]: PCI Express Port 2D on PCI0 + Package() { 0x0002FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, + // [BR3A]: PCI Express Port 3A on PCI0 + // [BR3B]: PCI Express Port 3B on PCI0 + // [BR3C]: PCI Express Port 3C on PCI0 + // [BR3D]: PCI Express Port 3D on PCI0 + Package() { 0x0003FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, + // [CB0A]: CB3DMA on PCI0 + // [CB0E]: CB3DMA on PCI0 + Package() { 0x0004FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, + // [CB0B]: CB3DMA on PCI0 + // [CB0F]: CB3DMA on PCI0 + Package() { 0x0004FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, + // [CB0C]: CB3DMA on PCI0 + // [CB0G]: CB3DMA on PCI0 + Package() { 0x0004FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, + // [CB0D]: CB3DMA on PCI0 + // [CB0H]: CB3DMA on PCI0 + Package() { 0x0004FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, + // [IIM0]: IIOMISC on PCI0 + Package() { 0x0005FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, + Package() { 0x0005FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, + Package() { 0x0005FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, + Package() { 0x0005FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, + // [IID0]: IIODFX0 on PCI0 + Package() { 0x0006FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, + Package() { 0x0006FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, + Package() { 0x0006FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, + Package() { 0x0006FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, + // [XHCI]: xHCI controller 1 on PCH + Package() { 0x0014FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, + // [HECI]: ME HECI on PCH + // [IDER]: ME IDE redirect on PCH + Package() { 0x0016FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, + // [HEC2]: ME HECI2 on PCH + // [MEKT]: MEKT on PCH + Package() { 0x0016FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, + // [GBEM]: GbE Controller VPRO + Package() { 0x0019FFFF, 0, \_SB.PCI0.LPC0.LNKE, 0 }, + // [EHC2]: EHCI controller #2 on PCH + Package() { 0x001AFFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, + // [ALZA]: High definition Audio Controller + Package() { 0x001BFFFF, 0, \_SB.PCI0.LPC0.LNKG, 0 }, + // [RP01]: Pci Express Port 1 on PCH + // [RP05]: Pci Express Port 5 on PCH + Package() { 0x001CFFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, + // [RP02]: Pci Express Port 2 on PCH + // [RP06]: Pci Express Port 6 on PCH + Package() { 0x001CFFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, + // [RP03]: Pci Express Port 3 on PCH + // [RP07]: Pci Express Port 7 on PCH + Package() { 0x001CFFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, + // [RP04]: Pci Express Port 4 on PCH + // [RP08]: Pci Express Port 8 on ICH + Package() { 0x001CFFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, + // [EHC1]: EHCI controller #1 on PCH + Package() { 0x001DFFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, + // [SAT1]: SATA controller 1 on PCH + // [SAT2]: SATA Host controller 2 on PCH + Package() { 0x001FFFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, + // [SMBS]: SMBus controller on PCH + // [TERM]: Thermal Subsystem on ICH + Package() { 0x001FFFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, +}) + +Name (AR00, Package() { + // [DMI0]: Legacy PCI Express Port 0 on PCI0 + Package() { 0x0000FFFF, 0, 0, 16 }, + // [BR1A]: PCI Express Port 1A on PCI0 + // [BR1B]: PCI Express Port 1B on PCI0 + Package() { 0x0001FFFF, 0, 0, 16 }, + // [BR2A]: PCI Express Port 2A on PCI0 + // [BR2B]: PCI Express Port 2B on PCI0 + // [BR2C]: PCI Express Port 2C on PCI0 + // [BR2D]: PCI Express Port 2D on PCI0 + Package() { 0x0002FFFF, 0, 0, 16 }, + // [BR3A]: PCI Express Port 3A on PCI0 + // [BR3B]: PCI Express Port 3B on PCI0 + // [BR3C]: PCI Express Port 3C on PCI0 + // [BR3D]: PCI Express Port 3D on PCI0 + Package() { 0x0003FFFF, 0, 0, 16 }, + // [CB0A]: CB3DMA on PCI0 + // [CB0E]: CB3DMA on PCI0 + Package() { 0x0004FFFF, 0, 0, 16 }, + // [CB0B]: CB3DMA on PCI0 + // [CB0F]: CB3DMA on PCI0 + Package() { 0x0004FFFF, 1, 0, 17 }, + // [CB0C]: CB3DMA on PCI0 + // [CB0G]: CB3DMA on PCI0 + Package() { 0x0004FFFF, 2, 0, 18 }, + // [CB0D]: CB3DMA on PCI0 + // [CB0H]: CB3DMA on PCI0 + Package() { 0x0004FFFF, 3, 0, 19 }, + // [IIM0]: IIOMISC on PCI0 + Package() { 0x0005FFFF, 0, 0, 16 }, + Package() { 0x0005FFFF, 1, 0, 17 }, + Package() { 0x0005FFFF, 2, 0, 18 }, + Package() { 0x0005FFFF, 3, 0, 19 }, + // [IID0]: IIODFX0 on PCI0 + Package() { 0x0006FFFF, 0, 0, 16 }, + Package() { 0x0006FFFF, 1, 0, 17 }, + Package() { 0x0006FFFF, 2, 0, 18 }, + Package() { 0x0006FFFF, 3, 0, 19 }, + // [XHCI]: xHCI controller 1 on PCH + Package() { 0x0014FFFF, 3, 0, 19 }, + // [HECI]: ME HECI on PCH + // [IDER]: ME IDE redirect on PCH + Package() { 0x0016FFFF, 0, 0, 16 }, + // [HEC2]: ME HECI2 on PCH + // [MEKT]: MEKT on PCH + Package() { 0x0016FFFF, 1, 0, 17 }, + // [GBEM]: GbE Controller VPRO + Package() { 0x0019FFFF, 0, 0, 20 }, + // [EHC2]: EHCI controller #2 on PCH + Package() { 0x001AFFFF, 2, 0, 18 }, + // [ALZA]: High definition Audio Controller + Package() { 0x001BFFFF, 0, 0, 22 }, + // [RP01]: Pci Express Port 1 on PCH + // [RP05]: Pci Express Port 5 on PCH + Package() { 0x001CFFFF, 0, 0, 16 }, + // [RP02]: Pci Express Port 2 on PCH + // [RP06]: Pci Express Port 6 on PCH + Package() { 0x001CFFFF, 1, 0, 17 }, + // [RP03]: Pci Express Port 3 on PCH + // [RP07]: Pci Express Port 7 on PCH + Package() { 0x001CFFFF, 2, 0, 18 }, + // [RP04]: Pci Express Port 4 on PCH + // [RP08]: Pci Express Port 8 on ICH + Package() { 0x001CFFFF, 3, 0, 19 }, + // [EHC1]: EHCI controller #1 on PCH + Package() { 0x001DFFFF, 2, 0, 18 }, + // [SAT1]: SATA controller 1 on PCH + // [SAT2]: SATA Host controller 2 on PCH + Package() { 0x001FFFFF, 0, 0, 16 }, + // [SMBS]: SMBus controller on PCH + // [TERM]: Thermal Subsystem on ICH + Package() { 0x001FFFFF, 2, 0, 18 }, +}) + +Name (AH00, Package() { + // [DMI0]: Legacy PCI Express Port 0 on PCI0 + Package() { 0x0000FFFF, 0, 0, 47 }, + // [BR1A]: PCI Express Port 1A on PCI0 + // [BR1B]: PCI Express Port 1B on PCI0 + Package() { 0x0001FFFF, 0, 0, 47 }, + // [BR2A]: PCI Express Port 2A on PCI0 + // [BR2B]: PCI Express Port 2B on PCI0 + // [BR2C]: PCI Express Port 2C on PCI0 + // [BR2D]: PCI Express Port 2D on PCI0 + Package() { 0x0002FFFF, 0, 0, 47 }, + // [BR3A]: PCI Express Port 3A on PCI0 + // [BR3B]: PCI Express Port 3B on PCI0 + // [BR3C]: PCI Express Port 3C on PCI0 + // [BR3D]: PCI Express Port 3D on PCI0 + Package() { 0x0003FFFF, 0, 0, 47 }, + // [CB0A]: CB3DMA on PCI0 + // [CB0E]: CB3DMA on PCI0 + Package() { 0x0004FFFF, 0, 0, 31 }, + // [CB0B]: CB3DMA on PCI0 + // [CB0F]: CB3DMA on PCI0 + Package() { 0x0004FFFF, 1, 0, 39 }, + // [CB0C]: CB3DMA on PCI0 + // [CB0G]: CB3DMA on PCI0 + Package() { 0x0004FFFF, 2, 0, 31 }, + // [CB0D]: CB3DMA on PCI0 + // [CB0H]: CB3DMA on PCI0 + Package() { 0x0004FFFF, 3, 0, 39 }, + // [IIM0]: IIOMISC on PCI0 + Package() { 0x0005FFFF, 0, 0, 16 }, + Package() { 0x0005FFFF, 1, 0, 17 }, + Package() { 0x0005FFFF, 2, 0, 18 }, + Package() { 0x0005FFFF, 3, 0, 19 }, + // [IID0]: IIODFX0 on PCI0 + Package() { 0x0006FFFF, 0, 0, 16 }, + Package() { 0x0006FFFF, 1, 0, 17 }, + Package() { 0x0006FFFF, 2, 0, 18 }, + Package() { 0x0006FFFF, 3, 0, 19 }, + // [XHCI]: xHCI controller 1 on PCH + Package() { 0x0014FFFF, 3, 0, 19 }, + // [HECI]: ME HECI on PCH + // [IDER]: ME IDE redirect on PCH + Package() { 0x0016FFFF, 0, 0, 16 }, + // [HEC2]: ME HECI2 on PCH + // [MEKT]: MEKT on PCH + Package() { 0x0016FFFF, 1, 0, 17 }, + // [GBEM]: GbE Controller VPRO + Package() { 0x0019FFFF, 0, 0, 20 }, + // [EHC2]: EHCI controller #2 on PCH + Package() { 0x001AFFFF, 2, 0, 18 }, + // [ALZA]: High definition Audio Controller + Package() { 0x001BFFFF, 0, 0, 22 }, + // [RP01]: Pci Express Port 1 on PCH + // [RP05]: Pci Express Port 5 on PCH + Package() { 0x001CFFFF, 0, 0, 16 }, + // [RP02]: Pci Express Port 2 on PCH + // [RP06]: Pci Express Port 6 on PCH + Package() { 0x001CFFFF, 1, 0, 17 }, + // [RP03]: Pci Express Port 3 on PCH + // [RP07]: Pci Express Port 7 on PCH + Package() { 0x001CFFFF, 2, 0, 18 }, + // [RP04]: Pci Express Port 4 on PCH + // [RP08]: Pci Express Port 8 on ICH + Package() { 0x001CFFFF, 3, 0, 19 }, + // [EHC1]: EHCI controller #1 on PCH + Package() { 0x001DFFFF, 2, 0, 18 }, + // [SAT1]: SATA controller 1 on PCH + // [SAT2]: SATA Host controller 2 on PCH + Package() { 0x001FFFFF, 0, 0, 16 }, + // [SMBS]: SMBus controller on PCH + // [TERM]: Thermal Subsystem on ICH + Package() { 0x001FFFFF, 2, 0, 18 }, +}) + +// Socket 0 Root bridge +Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR00) + } + Return (AH00) // If you disable the IOxAPIC in IIO, you should return AR00 +} + +#include "lpc.asl" \ No newline at end of file diff --git a/src/soc/intel/fsp_broadwell_de/bootblock/bootblock.c b/src/soc/intel/fsp_broadwell_de/bootblock/bootblock.c new file mode 100644 index 0000000..c026c83 --- /dev/null +++ b/src/soc/intel/fsp_broadwell_de/bootblock/bootblock.c @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google, Inc. + * Copyright (C) 2015-2016 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied wacbmem_entryanty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <cpu/intel/microcode/microcode.c> + +static void bootblock_cpu_init(void) +{ + /* Load microcode before any caching. */ + intel_update_microcode_from_cbfs(); +} diff --git a/src/soc/intel/fsp_broadwell_de/chip.c b/src/soc/intel/fsp_broadwell_de/chip.c new file mode 100644 index 0000000..78649fc --- /dev/null +++ b/src/soc/intel/fsp_broadwell_de/chip.c @@ -0,0 +1,106 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015-2016 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <lib.h> +#include <string.h> +#include <bootstate.h> +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <drivers/intel/fsp1_0/fsp_util.h> +#include <soc/pci_devs.h> +#include <soc/ramstage.h> +#include <chip.h> + +static void pci_domain_set_resources(device_t dev) +{ + assign_resources(dev->link_list); +} + +static struct device_operations pci_domain_ops = { + .read_resources = pci_domain_read_resources, + .set_resources = pci_domain_set_resources, + .enable_resources = NULL, + .init = NULL, + .scan_bus = pci_domain_scan_bus, + .ops_pci_bus = pci_bus_default_ops, +}; + +static struct device_operations cpu_bus_ops = { + .read_resources = DEVICE_NOOP, + .set_resources = DEVICE_NOOP, + .enable_resources = DEVICE_NOOP, + .init = broadwell_de_init_cpus, + .scan_bus = NULL, +}; + +static void enable_dev(device_t dev) +{ + printk(BIOS_DEBUG, "enable_dev(%s, %d)\n", + dev_name(dev), dev->path.type); + + /* Set the operations if it is a special bus type */ + if (dev->path.type == DEVICE_PATH_DOMAIN) { + dev->ops = &pci_domain_ops; + } else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) { + dev->ops = &cpu_bus_ops; + } else if (dev->path.type == DEVICE_PATH_PCI) { + /* Handle south cluster enablement. */ + if (PCI_SLOT(dev->path.pci.devfn) > 0 && + (dev->ops == NULL || dev->ops->enable == NULL)) { + southcluster_enable_dev(dev); + } + } +} + +static void fsp_notify(void *arg) +{ + FspNotify (*(uint32_t *)arg); +} + +static uint32_t gFspNotifyAfterPciEnumeration = EnumInitPhaseAfterPciEnumeration; +static uint32_t gFspNotifyReadtToBoot = EnumInitPhaseReadyToBoot; +static BOOT_STATE_CALLBACK(bscb_fspnotify1, fsp_notify, &gFspNotifyAfterPciEnumeration); +static BOOT_STATE_CALLBACK(bscb_fspnotify2, fsp_notify, &gFspNotifyReadtToBoot); + +/* Called at BS_DEV_INIT_CHIPS time -- very early. Just after BS_PRE_DEVICE. */ +static void soc_init(void *chip_info) +{ + boot_state_sched_on_exit(&bscb_fspnotify1, BS_DEV_RESOURCES); + boot_state_sched_on_exit(&bscb_fspnotify2, BS_PAYLOAD_LOAD); + broadwell_de_init_pre_device(); +} + +struct chip_operations soc_intel_fsp_broadwell_de_ops = { + CHIP_NAME("Intel(R) Xeon(R) Processor D-1500 Product Family") + .enable_dev = enable_dev, + .init = soc_init, +}; + +static void pci_set_subsystem(device_t dev, unsigned vendor, unsigned device) +{ + if (!vendor || !device) { + pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, + pci_read_config32(dev, PCI_VENDOR_ID)); + } else { + pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, + ((device & 0xffff) << 16) | (vendor & 0xffff)); + } +} + +struct pci_operations soc_pci_ops = { + .set_subsystem = &pci_set_subsystem, +}; diff --git a/src/soc/intel/fsp_broadwell_de/chip.h b/src/soc/intel/fsp_broadwell_de/chip.h new file mode 100644 index 0000000..ed01c89 --- /dev/null +++ b/src/soc/intel/fsp_broadwell_de/chip.h @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015-2016 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_CHIP_H_ +#define _SOC_CHIP_H_ + +#include <arch/acpi.h> + +/* The devicetree parser expects chip.h to reside directly in the path + * specified by the devicetree. */ + +struct soc_intel_fsp_broadwell_de_config { +}; + +extern struct chip_operations soc_intel_fsp_broadwell_de_ops; +#endif /* _SOC_CHIP_H_ */ diff --git a/src/soc/intel/fsp_broadwell_de/cpu.c b/src/soc/intel/fsp_broadwell_de/cpu.c new file mode 100644 index 0000000..173e978 --- /dev/null +++ b/src/soc/intel/fsp_broadwell_de/cpu.c @@ -0,0 +1,110 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015-2016 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdlib.h> +#include <console/console.h> +#include <cpu/cpu.h> +#include <cpu/intel/microcode.h> +#include <cpu/x86/cache.h> +#include <cpu/x86/lapic.h> +#include <cpu/x86/mp.h> +#include <cpu/x86/msr.h> +#include <cpu/x86/mtrr.h> +#include <soc/msr.h> +#include <soc/pattrs.h> +#include <soc/ramstage.h> + +static void configure_mca(void); + +static struct mp_flight_record mp_steps[] = { + MP_FR_BLOCK_APS(mp_initialize_cpu, NULL, mp_initialize_cpu, NULL), +}; + +static int adjust_apic_id(int index, int apic_id) +{ + return index; +} + +static void configure_mca(void) +{ + msr_t msr; + const unsigned int mcg_cap_msr = 0x179; + int i; + int num_banks; + + msr = rdmsr(mcg_cap_msr); + num_banks = msr.lo & 0xff; + + /* TODO(adurbin): This should only be done on a cold boot. Also, some + * of these banks are core vs package scope. For now every CPU clears + * every bank. */ + msr.lo = msr.hi = 0; + for (i = 0; i < num_banks; i++) { + wrmsr(MSR_IA32_MC0_STATUS + (i * 4) + 1, msr); + wrmsr(MSR_IA32_MC0_STATUS + (i * 4) + 2, msr); + wrmsr(MSR_IA32_MC0_STATUS + (i * 4) + 3, msr); + } + + msr.lo = msr.hi = 0xffffffff; + for (i = 0; i < num_banks; i++) + wrmsr(MSR_IA32_MC0_STATUS + (i * 4), msr); +} + +void broadwell_de_init_cpus(device_t dev) +{ + struct bus *cpu_bus = dev->link_list; + const struct pattrs *pattrs = pattrs_get(); + struct mp_params mp_params; + + x86_mtrr_check(); + + /* Enable the local cpu apics */ + setup_lapic(); + + mp_params.num_cpus = pattrs->num_cpus, + mp_params.parallel_microcode_load = 1, + mp_params.adjust_apic_id = adjust_apic_id; + mp_params.flight_plan = &mp_steps[0]; + mp_params.num_records = ARRAY_SIZE(mp_steps); + mp_params.microcode_pointer = pattrs->microcode_patch; + + if (mp_init(cpu_bus, &mp_params)) { + printk(BIOS_ERR, "MP initialization failure.\n"); + } +} + +static void broadwell_de_core_init(device_t cpu) +{ + printk(BIOS_DEBUG, "Init Broadwell-DE core.\n"); + configure_mca(); +} + +static struct device_operations cpu_dev_ops = { + .init = broadwell_de_core_init, +}; + +static struct cpu_device_id cpu_table[] = { + { X86_VENDOR_INTEL, 0x50661 }, + { X86_VENDOR_INTEL, 0x50662 }, + { X86_VENDOR_INTEL, 0x50663 }, + { X86_VENDOR_INTEL, 0x50664 }, + { 0, 0 }, +}; + +static const struct cpu_driver driver __cpu_driver = { + .ops = &cpu_dev_ops, + .id_table = cpu_table, +}; diff --git a/src/soc/intel/fsp_broadwell_de/fsp/Kconfig b/src/soc/intel/fsp_broadwell_de/fsp/Kconfig new file mode 100644 index 0000000..2e1ebeb --- /dev/null +++ b/src/soc/intel/fsp_broadwell_de/fsp/Kconfig @@ -0,0 +1,93 @@ +config BROADWELL_DE_FSP_SPECIFIC_OPTIONS + def_bool y + select PLATFORM_USES_FSP1_0 + select USE_GENERIC_FSP_CAR_INC + select FSP_USES_UPD + +config FSP_FILE + string + default "../intel/fsp/broadwell_de/BROADWELLDE_FSP.bin" + help + The path and filename of the Intel FSP binary for this platform. + +config FSP_LOC + hex + default 0xffeb0000 + help + The location in CBFS that the FSP is located. This must match the + value that is set in the FSP binary. If the FSP needs to be moved, + rebase the FSP with Intel's BCT (tool). + + The Broadwell-DE FSP is built with a preferred base address of + 0xffeb0000. + +config FSP_MEMORY_DOWN + bool "Enable Memory Down" + default n + help + Load SPD data from ROM instead of trying to read from SMBus. + + If the platform has DIMM sockets, say N. If memory is down, say Y and + supply the appropriate SPD data for each Channel/DIMM. + +config FSP_MEMORY_DOWN_CH0DIMM0_SPD_PRESENT + bool "Channel 0, DIMM 0 Present" + default n + depends on FSP_MEMORY_DOWN + help + Select Y if Channel 0, DIMM 0 is present. + +config FSP_MEMORY_DOWN_CH0DIMM0_SPD_FILE + string "Channel 0, DIMM 0 SPD File" + default "spd_ch0_dimm0.bin" + depends on FSP_MEMORY_DOWN_CH0DIMM0_SPD_PRESENT + help + Path to the file which contains the SPD data for Channel 0, DIMM 0. + +config FSP_MEMORY_DOWN_CH0DIMM1_SPD_PRESENT + bool "Channel 0, DIMM 1 Present" + default n + depends on FSP_MEMORY_DOWN + help + Select Y if Channel 0, DIMM 1 is present. + +config FSP_MEMORY_DOWN_CH0DIMM1_SPD_FILE + string "Channel 0, DIMM 1 SPD File" + default "spd_ch0_dimm1.bin" + depends on FSP_MEMORY_DOWN_CH0DIMM1_SPD_PRESENT + help + Path to the file which contains the SPD data for Channel 0, DIMM 1. + +config FSP_MEMORY_DOWN_CH1DIMM0_SPD_PRESENT + bool "Channel 1, DIMM 0 Present" + default n + depends on FSP_MEMORY_DOWN + help + Select Y if Channel 1, DIMM 0 is present. + +config FSP_MEMORY_DOWN_CH1DIMM0_SPD_FILE + string "Channel 1, DIMM 0 SPD File" + default "spd_ch1_dimm0.bin" + depends on FSP_MEMORY_DOWN_CH1DIMM0_SPD_PRESENT + help + Path to the file which contains the SPD data for Channel 1, DIMM 0. + +config FSP_MEMORY_DOWN_CH1DIMM1_SPD_PRESENT + bool "Channel 1, DIMM 1 Present" + default n + depends on FSP_MEMORY_DOWN + help + Select Y if Channel 1, DIMM 1 is present. + +config FSP_MEMORY_DOWN_CH1DIMM1_SPD_FILE + string "Channel 1, DIMM 1 SPD File" + default "spd_ch1_dimm1.bin" + depends on FSP_MEMORY_DOWN_CH1DIMM1_SPD_PRESENT + help + Path to the file which contains the SPD data for Channel 1, DIMM 1. + +config FSP_HYPERTHREADING + bool "Enable Hyper-Threading" + default y + help + Enable Intel(r) Hyper-Threading Technology for the Broadwell-DE SoC. diff --git a/src/soc/intel/fsp_broadwell_de/fsp/Makefile.inc b/src/soc/intel/fsp_broadwell_de/fsp/Makefile.inc new file mode 100644 index 0000000..8a83794 --- /dev/null +++ b/src/soc/intel/fsp_broadwell_de/fsp/Makefile.inc @@ -0,0 +1,18 @@ +romstage-y += chipset_fsp_util.c + + +cbfs-files-$(CONFIG_FSP_MEMORY_DOWN_CH0DIMM0_SPD_PRESENT) += spd_ch0_dimm0.bin +spd_ch0_dimm0.bin-file := $(call strip_quotes,$(CONFIG_FSP_MEMORY_DOWN_CH0DIMM0_SPD_FILE)) +spd_ch0_dimm0.bin-type := raw + +cbfs-files-$(CONFIG_FSP_MEMORY_DOWN_CH0DIMM1_SPD_PRESENT) += spd_ch0_dimm1.bin +spd_ch0_dimm1.bin-file := $(call strip_quotes,$(CONFIG_FSP_MEMORY_DOWN_CH0DIMM1_SPD_FILE)) +spd_ch0_dimm1.bin-type := raw + +cbfs-files-$(CONFIG_FSP_MEMORY_DOWN_CH1DIMM0_SPD_PRESENT) += spd_ch1_dimm0.bin +spd_ch1_dimm0.bin-file := $(call strip_quotes,$(CONFIG_FSP_MEMORY_DOWN_CH1DIMM0_SPD_FILE)) +spd_ch1_dimm0.bin-type := raw + +cbfs-files-$(CONFIG_FSP_MEMORY_DOWN_CH1DIMM1_SPD_PRESENT) += spd_ch1_dimm1.bin +spd_ch1_dimm1.bin-file := $(call strip_quotes,$(CONFIG_FSP_MEMORY_DOWN_CH1DIMM1_SPD_FILE)) +spd_ch1_dimm1.bin-type := raw diff --git a/src/soc/intel/fsp_broadwell_de/fsp/chipset_fsp_util.c b/src/soc/intel/fsp_broadwell_de/fsp/chipset_fsp_util.c new file mode 100644 index 0000000..de82c6e --- /dev/null +++ b/src/soc/intel/fsp_broadwell_de/fsp/chipset_fsp_util.c @@ -0,0 +1,131 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. + * Copyright (C) 2015-2016 Intel Corporation. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <types.h> +#include <string.h> +#include <console/console.h> +#include <bootstate.h> +#include <cbfs.h> +#include <cbmem.h> +#include <device/device.h> +#include <device/pci_def.h> +#include <drivers/intel/fsp1_0/fsp_util.h> +#include <soc/pci_devs.h> +#include <soc/reset.h> +#include <soc/romstage.h> +#include <chip.h> +#include <fsp.h> + +/* Copy the default UPD region and settings to a buffer for modification */ +static void GetUpdDefaultFromFsp (FSP_INFO_HEADER *FspInfo, UPD_DATA_REGION *UpdData) +{ + VPD_DATA_REGION *VpdDataRgnPtr; + UPD_DATA_REGION *UpdDataRgnPtr; + VpdDataRgnPtr = (VPD_DATA_REGION *)(UINT32)(FspInfo->CfgRegionOffset + FspInfo->ImageBase); + UpdDataRgnPtr = (UPD_DATA_REGION *)(UINT32)(VpdDataRgnPtr->PcdUpdRegionOffset + FspInfo->ImageBase); + memcpy((void *)UpdData, (void *)UpdDataRgnPtr, sizeof(UPD_DATA_REGION)); +} + +typedef struct soc_intel_fsp_broadwell_de_config config_t; + +/** + * Update the UPD data based on values from devicetree.cb + * + * @param UpdData Pointer to the UPD Data structure + */ +static void ConfigureDefaultUpdData(UPD_DATA_REGION *UpdData) +{ + /* + * Serial Port + */ +#if CONFIG_INTEGRATED_UART + UpdData->SerialPortConfigure = 1; +#endif + + /* + * Memory Down + */ +#if CONFIG_FSP_MEMORY_DOWN + UpdData->MemDownEnable = 1; + +#if CONFIG_FSP_MEMORY_DOWN_CH0DIMM0_SPD_PRESENT + UpdData->MemDownCh0Dimm0SpdPtr + = (UINT32)cbfs_boot_map_with_leak("spd_ch0_dimm0.bin", CBFS_TYPE_RAW, NULL); +#endif +#if CONFIG_FSP_MEMORY_DOWN_CH0DIMM1_SPD_PRESENT + UpdData->MemDownCh0Dimm1SpdPtr + = (UINT32)cbfs_boot_map_with_leak("spd_ch0_dimm1.bin", CBFS_TYPE_RAW, NULL); +#endif +#if CONFIG_FSP_MEMORY_DOWN_CH1DIMM0_SPD_PRESENT + UpdData->MemDownCh1Dimm0SpdPtr + = (UINT32)cbfs_boot_map_with_leak("spd_ch1_dimm0.bin", CBFS_TYPE_RAW, NULL); +#endif +#if CONFIG_FSP_MEMORY_DOWN_CH1DIMM1_SPD_PRESENT + UpdData->MemDownCh1Dimm1SpdPtr + = (UINT32)cbfs_boot_map_with_leak("spd_ch1_dimm1.bin", CBFS_TYPE_RAW, NULL); +#endif +#else + UpdData->MemDownEnable = 0; +#endif /* CONFIG_FSP_MEMORY_DOWN */ + + /* + * Fast Boot + */ +#if IS_ENABLED(CONFIG_ENABLE_MRC_CACHE) + UpdData->MemFastBoot = 1; +#else + UpdData->MemFastBoot = 0; +#endif + + /* + * Hyper-Threading + */ +#if IS_ENABLED(CONFIG_FSP_HYPERTHREADING) + UpdData->HyperThreading = 1; +#else + UpdData->HyperThreading = 0; +#endif +} + +/* Set up the Broadwell-DE specific structures for the call into the FSP */ +void chipset_fsp_early_init(FSP_INIT_PARAMS *pFspInitParams, FSP_INFO_HEADER *fsp_ptr) +{ + FSP_INIT_RT_BUFFER *pFspRtBuffer = pFspInitParams->RtBufferPtr; + + /* Initialize the UPD Data */ + GetUpdDefaultFromFsp (fsp_ptr, pFspRtBuffer->Common.UpdDataRgnPtr); + ConfigureDefaultUpdData(pFspRtBuffer->Common.UpdDataRgnPtr); + pFspInitParams->NvsBufferPtr = NULL; + +#if IS_ENABLED(CONFIG_ENABLE_MRC_CACHE) + /* Find the fastboot cache that was saved in the ROM */ + pFspInitParams->NvsBufferPtr = find_and_set_fastboot_cache(); +#endif + + return; +} + +/* The FSP returns here after the fsp_early_init call */ +void ChipsetFspReturnPoint(EFI_STATUS Status, VOID *HobListPtr) +{ + *(void **)CBMEM_FSP_HOB_PTR = HobListPtr; + + if (Status == 0xFFFFFFFF) { + warm_reset(); + } + + romstage_main_continue(Status, HobListPtr); +} diff --git a/src/soc/intel/fsp_broadwell_de/fsp/chipset_fsp_util.h b/src/soc/intel/fsp_broadwell_de/fsp/chipset_fsp_util.h new file mode 100644 index 0000000..057d7fd --- /dev/null +++ b/src/soc/intel/fsp_broadwell_de/fsp/chipset_fsp_util.h @@ -0,0 +1,35 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. + * Copyright (C) 2015-2016 Intel Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef CHIPSET_FSP_UTIL_H +#define CHIPSET_FSP_UTIL_H + +#include <fsp.h> + +#define FSP_INFO_HEADER_GUID \ + { \ + 0x912740BE, 0x2284, 0x4734, {0xB9, 0x71, 0x84, 0xB0, 0x27, 0x35, 0x3F, 0x0C} \ + } + +/* + * The FSP Image ID is different for each platform's FSP and + * can be used to verify that the right FSP binary is loaded. + * For the Broadwell-DE FSP, the Image Id is "BDX-DE". + */ +#define FSP_IMAGE_ID_DWORD0 ((unsigned int)(FSP_IMAGE_ID)) +#define FSP_IMAGE_ID_DWORD1 ((unsigned int)(FSP_IMAGE_ID >> 32)) + +#endif /* CHIPSET_FSP_UTIL_H */ diff --git a/src/soc/intel/fsp_broadwell_de/include/soc/acpi.h b/src/soc/intel/fsp_broadwell_de/include/soc/acpi.h new file mode 100644 index 0000000..f717d15 --- /dev/null +++ b/src/soc/intel/fsp_broadwell_de/include/soc/acpi.h @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google, Inc. + * Copyright (C) 2015-2016 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_ACPI_H_ +#define _SOC_ACPI_H_ + +#include <arch/acpi.h> + +void acpi_create_intel_hpet(acpi_hpet_t *hpet); +void acpi_fill_in_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt); +unsigned long acpi_madt_irq_overrides(unsigned long current); +uint16_t get_pmbase(void); + +#endif /* _SOC_ACPI_H_ */ diff --git a/src/soc/intel/fsp_broadwell_de/include/soc/broadwell_de.h b/src/soc/intel/fsp_broadwell_de/include/soc/broadwell_de.h new file mode 100644 index 0000000..6828d03 --- /dev/null +++ b/src/soc/intel/fsp_broadwell_de/include/soc/broadwell_de.h @@ -0,0 +1,20 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google, Inc. + * Copyright (C) 2015-2016 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_BROADWELL_DE_H_ +#define _SOC_BROADWELL_DE_H_ + +#endif /* _SOC_BROADWELL_DE_H_ */ diff --git a/src/soc/intel/fsp_broadwell_de/include/soc/gpio.h b/src/soc/intel/fsp_broadwell_de/include/soc/gpio.h new file mode 100644 index 0000000..bb12673 --- /dev/null +++ b/src/soc/intel/fsp_broadwell_de/include/soc/gpio.h @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015-2016 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_GPIO_H_ +#define _SOC_GPIO_H_ + +#include <stdint.h> +#include <arch/io.h> +#include <soc/iomap.h> + +#endif /* _SOC_GPIO_H_ */ diff --git a/src/soc/intel/fsp_broadwell_de/include/soc/iomap.h b/src/soc/intel/fsp_broadwell_de/include/soc/iomap.h new file mode 100644 index 0000000..ca84299 --- /dev/null +++ b/src/soc/intel/fsp_broadwell_de/include/soc/iomap.h @@ -0,0 +1,66 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015-2016 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_IOMAP_H_ +#define _SOC_IOMAP_H_ + +/* + * Memory Mapped IO bases. + */ + +/* PCI Configuration Space */ +#define MCFG_BASE_ADDRESS CONFIG_MMCONF_BASE_ADDRESS +#define MCFG_BASE_SIZE 0x10000000 + +/* Transactions in this range will abort */ +#define ABORT_BASE_ADDRESS 0xfeb00000 +#define ABORT_BASE_SIZE 0x00010000 + +/* PSEG */ +#define PSEG_BASE_ADDRESS 0xfeb80000 +#define PSEG_BASE_SIZE 0x00080000 + +/* IOxAPIC */ +#define IOXAPIC1_BASE_ADDRESS 0xfec00000 +#define IOXAPIC1_BASE_SIZE 0x00100000 +#define IOXAPIC2_BASE_ADDRESS 0xfec01000 +#define IOXAPIC2_BASE_SIZE 0x00100000 + +/* PCH (HPET/LT/TPM/Others) */ +#define PCH_BASE_ADDRESS 0xfed00000 +#define PCH_BASE_SIZE 0x00100000 + +/* Local XAPIC */ +#define LXAPIC_BASE_ADDRESS 0xfee00000 +#define LXAPIC_BASE_SIZE 0x00100000 + +/* High Performance Event Timer */ +#define HPET_BASE_ADDRESS 0xfed00000 +#define HPET_BASE_SIZE 0x400 + +/* Firmware */ +#define FIRMWARE_BASE_ADDRESS 0xff000000 +#define FIRMWARE_BASE_SIZE 0x01000000 + +/* + * IO Port bases. + */ + +/* ACPI Base Address */ +#define ACPI_BASE_ADDRESS 0x400 +#define ACPI_BASE_SIZE 0x80 + +#endif /* _SOC_IOMAP_H_ */ diff --git a/src/soc/intel/fsp_broadwell_de/include/soc/irq.h b/src/soc/intel/fsp_broadwell_de/include/soc/irq.h new file mode 100644 index 0000000..ea04326 --- /dev/null +++ b/src/soc/intel/fsp_broadwell_de/include/soc/irq.h @@ -0,0 +1,88 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015-2016 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_IRQ_H_ +#define _SOC_IRQ_H_ + +#define PIRQA_APIC_IRQ 16 +#define PIRQB_APIC_IRQ 17 +#define PIRQC_APIC_IRQ 18 +#define PIRQD_APIC_IRQ 19 +#define PIRQE_APIC_IRQ 20 +#define PIRQF_APIC_IRQ 21 +#define PIRQG_APIC_IRQ 22 +#define PIRQH_APIC_IRQ 23 + +/* PIC IRQ settings. */ +#define PIRQ_PIC_IRQ3 0x3 +#define PIRQ_PIC_IRQ4 0x4 +#define PIRQ_PIC_IRQ5 0x5 +#define PIRQ_PIC_IRQ6 0x6 +#define PIRQ_PIC_IRQ7 0x7 +#define PIRQ_PIC_IRQ9 0x9 +#define PIRQ_PIC_IRQ10 0xa +#define PIRQ_PIC_IRQ11 0xb +#define PIRQ_PIC_IRQ12 0xc +#define PIRQ_PIC_IRQ14 0xe +#define PIRQ_PIC_IRQ15 0xf +#define PIRQ_PIC_IRQDISABLE 0x80 +#define PIRQ_PIC_UNKNOWN_UNUSED 0xff + +/* Overloaded term, but these values determine the per device route. */ +#define PIRQA 0 +#define PIRQB 1 +#define PIRQC 2 +#define PIRQD 3 +#define PIRQE 4 +#define PIRQF 5 +#define PIRQG 6 +#define PIRQH 7 + +/* In each mainboard directory there should exist a header file irqroute.h that + * defines the PCI_DEV_PIRQ_ROUTES and PIRQ_PIC_ROUTES macros which + * consist of PCI_DEV_PIRQ_ROUTE and PIRQ_PIC entries. */ + +#if !defined(__ASSEMBLER__) && !defined(__ACPI__) +#include <stdint.h> + +#define NUM_OF_PCI_DEVS 32 +#define NUM_PIRQS 8 + +struct broadwell_de_irq_route { + /* Per device configuration. */ + uint16_t pcidev[NUM_OF_PCI_DEVS]; + /* Route path for each internal PIRQx in PIC mode. */ + uint8_t pic[NUM_PIRQS]; +}; + +extern const struct broadwell_de_irq_route global_broadwell_de_irq_route; + +#define DEFINE_IRQ_ROUTES \ + const struct broadwell_de_irq_route global_broadwell_de_irq_route = { \ + .pcidev = { PCI_DEV_PIRQ_ROUTES, }, \ + .pic = { PIRQ_PIC_ROUTES, }, \ + } + +#define PCI_DEV_PIRQ_ROUTE(dev_, a_, b_, c_, d_) \ + [dev_] = ((PIRQ ## d_) << 12) | ((PIRQ ## c_) << 8) | \ + ((PIRQ ## b_) << 4) | ((PIRQ ## a_) << 0) + +#define PIRQ_PIC(pirq_, pic_irq_) \ + [PIRQ ## pirq_] = PIRQ_PIC_IRQ ## pic_irq_ + +#endif /* !defined(__ASSEMBLER__) && !defined(__ACPI__) */ + +#endif /* _SOC_IRQ_H_ */ diff --git a/src/soc/intel/fsp_broadwell_de/include/soc/lpc.h b/src/soc/intel/fsp_broadwell_de/include/soc/lpc.h new file mode 100644 index 0000000..2c02ebd --- /dev/null +++ b/src/soc/intel/fsp_broadwell_de/include/soc/lpc.h @@ -0,0 +1,86 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015-2016 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_LPC_H_ +#define _SOC_LPC_H_ + +/* LPC Interface Bridge PCI Configuration Registers */ +#define REVID 0x08 +#define PIRQ_RCR1 0x60 +#define PIRQ_RCR2 0x68 +#define GEN_PMCON_1 0xA0 +#define GEN_PMCON_2 0xA2 +#define GEN_PMCON_3 0xA4 +#define RTC_PWR_STS (1 << 2) + +/* Default IO range claimed by the LPC device. The upper bound is exclusive. */ +#define LPC_DEFAULT_IO_RANGE_LOWER 0 +#define LPC_DEFAULT_IO_RANGE_UPPER 0x1000 + +/* IO Mapped registers behind ACPI_BASE_ADDRESS */ +#define PM1_STS 0x00 +#define WAK_STS (1 << 15) +#define PCIEXPWAK_STS (1 << 14) +#define USB_STS (1 << 13) +#define PRBTNOR_STS (1 << 11) +#define RTC_STS (1 << 10) +#define PWRBTN_STS (1 << 8) +#define GBL_STS (1 << 5) +#define TMROF_STS (1 << 0) +#define PM1_EN 0x02 +#define PCIEXPWAK_DIS (1 << 14) +#define RTC_EN (1 << 10) +#define PWRBTN_EN (1 << 8) +#define GBL_EN (1 << 5) +#define TMROF_EN (1 << 0) +#define PM1_CNT 0x04 +#define SLP_EN (1 << 13) +#define SLP_TYP_SHIFT 10 +#define SLP_TYP (7 << SLP_TYP_SHIFT) +#define SLP_TYP_S0 0 +#define SLP_TYP_S1 1 +#define SLP_TYP_S3 5 +#define SLP_TYP_S4 6 +#define SLP_TYP_S5 7 +#define GBL_RLS (1 << 2) +#define BM_RLD (1 << 1) +#define SCI_EN (1 << 0) +#define PM1_TMR 0x08 +#define GPE0_STS 0x20 +#define PCI_EXP_STS (1 << 9) +#define RI_STS (1 << 8) +#define SMB_WAK_STS (1 << 7) +#define TCOSCI_STS (1 << 6) +#define SWGPE_STS (1 << 2) +#define HOT_PLUG_STS (1 << 1) +#define GPE0_EN 0x28 +#define SMI_EN 0x30 +#define SMI_STS 0x34 +#define ALT_GPIO_SMI 0x38 +#define UPRWC 0x3c +#define UPRWC_WR_EN (1 << 1) // USB Per-Port Registers Write Enable +#define GPE_CTRL 0x40 +#define PM2A_CNT_BLK 0x50 +#define TCO_RLD 0x60 +#define TCO_STS 0x64 +#define SECOND_TO_STS (1 << 17) +#define TCO_TIMEOUT (1 << 3) +#define TCO1_CNT 0x68 +#define TCO_LOCK (1 << 12) +#define TCO_TMR_HALT (1 << 11) +#define TCO_TMR 0x70 + +#endif /* _SOC_LPC_H_ */ \ No newline at end of file diff --git a/src/soc/intel/fsp_broadwell_de/include/soc/msr.h b/src/soc/intel/fsp_broadwell_de/include/soc/msr.h new file mode 100644 index 0000000..c409ec8 --- /dev/null +++ b/src/soc/intel/fsp_broadwell_de/include/soc/msr.h @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google, Inc. + * Copyright (C) 2015-2016 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied wacbmem_entryanty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_MSR_H_ +#define _SOC_MSR_H_ + +#define MSR_IA32_PLATFORM_ID 0x17 +#define MSR_CORE_THREAD_COUNT 0x35 +#define MSR_PLATFORM_INFO 0xce +#define MSR_TURBO_RATIO_LIMIT 0x1ad +#define MSR_IA32_MC0_STATUS 0x400 +#define MSR_PKG_POWER_SKU_UNIT 0x606 +#define MSR_PKG_POWER_LIMIT 0x610 + +#endif /* _SOC_MSR_H_ */ diff --git a/src/soc/intel/fsp_broadwell_de/include/soc/pattrs.h b/src/soc/intel/fsp_broadwell_de/include/soc/pattrs.h new file mode 100644 index 0000000..232a4f4 --- /dev/null +++ b/src/soc/intel/fsp_broadwell_de/include/soc/pattrs.h @@ -0,0 +1,52 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015-2016 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_PATTRS_H_ +#define _SOC_PATTRS_H_ + +#include <stdint.h> +#include <cpu/x86/msr.h> + +/* + * The pattrs structure is a common place to stash pertinent information + * about the processor or platform. Instead of going to the source (msrs, cpuid) + * every time an attribute is needed use the pattrs structure. + */ +struct pattrs { + msr_t platform_id; + msr_t platform_info; + uint32_t cpuid; + int revid; + int stepping; + const void *microcode_patch; + int address_bits; + int num_cpus; +}; + +/* + * This is just to hide the abstraction w/o relying on how the underlying + * storage is allocated. + */ +#define PATTRS_GLOB_NAME __global_pattrs +#define DEFINE_PATTRS struct pattrs PATTRS_GLOB_NAME +extern DEFINE_PATTRS; + +static inline const struct pattrs *pattrs_get(void) +{ + return &PATTRS_GLOB_NAME; +} + +#endif /* _SOC_PATTRS_H_ */ diff --git a/src/soc/intel/fsp_broadwell_de/include/soc/pci_devs.h b/src/soc/intel/fsp_broadwell_de/include/soc/pci_devs.h new file mode 100644 index 0000000..15e0b92 --- /dev/null +++ b/src/soc/intel/fsp_broadwell_de/include/soc/pci_devs.h @@ -0,0 +1,112 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015-2016 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_PCI_DEVS_H_ +#define _SOC_PCI_DEVS_H_ + +#define BUS0 0 + +#define DEV_FUNC(x, y) ((x<<3) | y) + +#define SOC_DEV 0 +#define SOC_FUNC 0 +#define SOC_DEVID 0x2F00 +#define SOC_DEVID_ES2 0x6F00 +#define SOC_DEV_FUNC DEV_FUNC(SOC_DEV, SOC_FUNC) + +#define LPC_DEV 31 +#define LPC_FUNC 0 +#define LPC_DEVID 0x8C42 +#define LPC_DEVID_ES2 0x8C54 +#define LPC_DEV_FUNC DEV_FUNC(LPC_DEV, LPC_FUNC) + +#define SATA_DEV 31 +#define SATA_FUNC 2 +#define AHCI_DEVID 0x8C02 +#define SATA_DEV_FUNC DEV_FUNC(SATA_DEV, SATA_FUNC) + +#define SATA2_DEV 31 +#define SATA2_FUNC 5 +#define SATA2_DEV_FUNC DEV_FUNC(SATA2_DEV, SATA2_FUNC) + +#define EHCI1_DEV 29 +#define EHCI1_FUNC 0 +#define EHCI1_DEVID 0x8C26 +#define EHCI1_DEV_FUNC DEV_FUNC(EHCI_DEV1, EHCI_FUNC1) + +#define EHCI2_DEV 26 +#define EHCI2_FUNC 0 +#define EHCI2_DEVID 0x8C2D +#define EHCI2_DEV_FUNC DEV_FUNC(EHCI_DEV2, EHCI_FUNC2) + +#define XHCI_DEV 20 +#define XHCI_FUNC 0 +#define XHCI_DEVID 0x8C31 +#define XHCI_FUS_REG 0xE0 +#define XHCI_FUNC_DISABLE (1 << 0) +#define XHCI_USB2PR_REG 0xD0 +#define XHCI_DEV_FUNC DEV_FUNC(XHCI_DEV, XHCI_FUNC) + +#define GBE_DEV 25 +#define GBE_FUNC 0 +#define GBE_DEVID 0x8C33 +#define GBE_DEV_FUNC DEV_FUNC(GBE_DEV, GBE_FUNC) + +#define ME_DEV 22 +#define ME_FUNC 0 +#define ME_DEVID 0x8C3A +#define ME_DEV_FUNC DEV_FUNC(ME_DEV, ME_FUNC) + +#define HDA_DEV 27 +#define HDA_FUNC 0 +#define HDA_DEVID 0x8C20 +#define HDA_DEV_FUNC DEV_FUNC(HDA_DEV, HDA_FUNC) + +#define PCIE_DEV 28 +#define PCIE_PORT1_DEV PCIE_DEV +#define PCIE_PORT1_FUNC 0 +#define PCIE_PORT1_DEVID 0x8C10 +#define PCIE_PORT2_DEV PCIE_DEV +#define PCIE_PORT2_FUNC 1 +#define PCIE_PORT2_DEVID 0x8C12 +#define PCIE_PORT3_DEV PCIE_DEV +#define PCIE_PORT3_FUNC 2 +#define PCIE_PORT3_DEVID 0x8C14 +#define PCIE_PORT4_DEV PCIE_DEV +#define PCIE_PORT4_FUNC 3 +#define PCIE_PORT4_DEVID 0x8C16 +#define PCIE_PORT5_DEV PCIE_DEV +#define PCIE_PORT5_FUNC 4 +#define PCIE_PORT5_DEVID 0x8C18 +#define PCIE_PORT6_DEV PCIE_DEV +#define PCIE_PORT6_FUNC 5 +#define PCIE_PORT6_DEVID 0x8C1A +#define PCIE_PORT7_DEV PCIE_DEV +#define PCIE_PORT7_FUNC 6 +#define PCIE_PORT7_DEVID 0x8C1C +#define PCIE_PORT8_DEV PCIE_DEV +#define PCIE_PORT8_FUNC 7 +#define PCIE_PORT8_DEVID 0x8C1E +#define PCIE_PORT1_DEV_FUNC DEV_FUNC(PCIE_DEV, PCIE_PORT1_FUNC) +#define PCIE_PORT2_DEV_FUNC DEV_FUNC(PCIE_DEV, PCIE_PORT2_FUNC) +#define PCIE_PORT3_DEV_FUNC DEV_FUNC(PCIE_DEV, PCIE_PORT3_FUNC) +#define PCIE_PORT4_DEV_FUNC DEV_FUNC(PCIE_DEV, PCIE_PORT4_FUNC) +#define PCIE_PORT5_DEV_FUNC DEV_FUNC(PCIE_DEV, PCIE_PORT5_FUNC) +#define PCIE_PORT6_DEV_FUNC DEV_FUNC(PCIE_DEV, PCIE_PORT6_FUNC) +#define PCIE_PORT7_DEV_FUNC DEV_FUNC(PCIE_DEV, PCIE_PORT7_FUNC) +#define PCIE_PORT8_DEV_FUNC DEV_FUNC(PCIE_DEV, PCIE_PORT8_FUNC) + +#endif /* _SOC_PCI_DEVS_H_ */ diff --git a/src/soc/intel/fsp_broadwell_de/include/soc/ramstage.h b/src/soc/intel/fsp_broadwell_de/include/soc/ramstage.h new file mode 100644 index 0000000..c01c9ac --- /dev/null +++ b/src/soc/intel/fsp_broadwell_de/include/soc/ramstage.h @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015-2016 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_RAMSTAGE_H_ +#define _SOC_RAMSTAGE_H_ + +#include <device/device.h> + +/* The broadwell_de_init_pre_device() function is called prior to device + * initialization, but it's after console and cbmem has been reinitialized. */ +void broadwell_de_init_pre_device(void); +void broadwell_de_init_cpus(device_t dev); +void southcluster_enable_dev(device_t dev); + +extern struct pci_operations soc_pci_ops; + +#endif /* _SOC_RAMSTAGE_H_ */ diff --git a/src/soc/intel/fsp_broadwell_de/include/soc/reset.h b/src/soc/intel/fsp_broadwell_de/include/soc/reset.h new file mode 100644 index 0000000..fa0ceac --- /dev/null +++ b/src/soc/intel/fsp_broadwell_de/include/soc/reset.h @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015-2016 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_RESET_H_ +#define _SOC_RESET_H_ + +#include <reset.h> + +void warm_reset(void); + +#endif /* _SOC_RESET_H_ */ diff --git a/src/soc/intel/fsp_broadwell_de/include/soc/romstage.h b/src/soc/intel/fsp_broadwell_de/include/soc/romstage.h new file mode 100644 index 0000000..94a5a56 --- /dev/null +++ b/src/soc/intel/fsp_broadwell_de/include/soc/romstage.h @@ -0,0 +1,35 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015-2016 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_ROMSTAGE_H_ +#define _SOC_ROMSTAGE_H_ + +#if !defined(__PRE_RAM__) +#error "Don't include romstage.h from a ramstage compilation unit!" +#endif + +#include <stdint.h> +#include <arch/cpu.h> +#include <fsp.h> + +void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr); + +#define NUM_ROMSTAGE_TS 4 + +void early_mainboard_romstage_entry(void); +void late_mainboard_romstage_entry(void); + +#endif /* _SOC_ROMSTAGE_H_ */ diff --git a/src/soc/intel/fsp_broadwell_de/memmap.c b/src/soc/intel/fsp_broadwell_de/memmap.c new file mode 100644 index 0000000..7510094 --- /dev/null +++ b/src/soc/intel/fsp_broadwell_de/memmap.c @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google, Inc. + * Copyright (C) 2015-2016 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <cbmem.h> +#include <drivers/intel/fsp1_0/fsp_util.h> + +void *cbmem_top(void) +{ + return find_fsp_reserved_mem(*(void **)CBMEM_FSP_HOB_PTR); +} diff --git a/src/soc/intel/fsp_broadwell_de/northcluster.c b/src/soc/intel/fsp_broadwell_de/northcluster.c new file mode 100644 index 0000000..307137b --- /dev/null +++ b/src/soc/intel/fsp_broadwell_de/northcluster.c @@ -0,0 +1,156 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015-2016 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/acpi.h> +#include <console/console.h> +#include <cpu/x86/lapic.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <drivers/intel/fsp1_0/fsp_util.h> +#include <soc/iomap.h> +#include <soc/pci_devs.h> +#include <soc/ramstage.h> + +static const int legacy_hole_base_k = 0xa0000 / 1024; +static const int legacy_hole_size_k = 384; + +static int add_fixed_resources(struct device *dev, int index) +{ + struct resource *resource; + u32 pcie_config_base, pcie_config_size; + pcie_config_base = MCFG_BASE_ADDRESS; + pcie_config_size = MCFG_BASE_SIZE; + + printk(BIOS_DEBUG, "Adding PCIe config bar base=0x%08x " + "size=0x%x\n", pcie_config_base, pcie_config_size); + resource = new_resource(dev, index++); + resource->base = (resource_t) pcie_config_base; + resource->size = (resource_t) pcie_config_size; + resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | + IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; + + resource = new_resource(dev, index++); /* Local APIC */ + resource->base = LAPIC_DEFAULT_BASE; + resource->size = 0x00001000; + resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | + IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; + + mmio_resource(dev, index++, legacy_hole_base_k, legacy_hole_size_k); + + return index; +} + +static void mc_add_dram_resources(device_t dev) +{ + u32 fsp_mem_base, fsp_mem_len; + u32 tseg_base, tseg_length; + u32 rsv_base, rsv_length; + u32 tolm; + int index = 0; + uint64_t highmem_size = 0; + + fsp_mem_base = GetFspReservedMemory(FspHobListPtr, &fsp_mem_len); + highmem_size = GetUsableHighMemTop(FspHobListPtr) - 0x100000000L; + tseg_base = GetTsegReservedMemory(FspHobListPtr, &tseg_length); + tolm = GetPhysicalLowMemTop(FspHobListPtr); + + printk(BIOS_DEBUG, "\n\n"); + printk(BIOS_DEBUG, "fsp_mem_base: 0x%.8x\n", fsp_mem_base); + printk(BIOS_DEBUG, "fsp_mem_len: 0x%.8x\n", fsp_mem_len); + printk(BIOS_DEBUG, "tseg_base: 0x%.8x\n", tseg_base); + printk(BIOS_DEBUG, "tseg_len: 0x%.8x\n", tseg_length); + printk(BIOS_DEBUG, "highmem_size: 0x%.8x %.8x\n", + (u32)(highmem_size>>32), + (u32)(highmem_size&0xffffffff)); + printk(BIOS_DEBUG, "tolm: 0x%.8x\n", tolm); + printk(BIOS_DEBUG, "Top of system low memory: 0x%08x\n", tolm); + printk(BIOS_DEBUG, "FSP memory location: 0x%x\n (size: %dM)\n", + fsp_mem_base, fsp_mem_len >> 20); + printk(BIOS_DEBUG, "tseg: 0x%08x (size: 0x%.8x)\n", + tseg_base, tseg_length); + + /* Report the memory regions. */ + ram_resource(dev, index++, 0, legacy_hole_base_k); + ram_resource(dev, index++, legacy_hole_base_k + legacy_hole_size_k, + ((fsp_mem_base >> 10) - (legacy_hole_base_k + legacy_hole_size_k))); + + /* Mark SMM & FSP regions reserved */ + mmio_resource(dev, index++, tseg_base >> 10, tseg_length >> 10); + mmio_resource(dev, index++, fsp_mem_base >> 10, fsp_mem_len >> 10); + + /* Reserve MMIO space */ + rsv_base = fsp_mem_base + fsp_mem_len; + rsv_length = tseg_base - rsv_base; + if (rsv_length) { + mmio_resource(dev, index++, rsv_base >> 10, rsv_length >> 10); + printk(BIOS_DEBUG, "Reserved MMIO : 0x%08x length 0x%08x\n", + rsv_base, rsv_length); + } + + rsv_base = tseg_base + tseg_length; + rsv_length = tolm - rsv_base; + if (rsv_length) { + mmio_resource(dev, index++, rsv_base >> 10, rsv_length >> 10); + printk(BIOS_DEBUG, "Reserved MMIO : 0x%08x length 0x%08x\n", + rsv_base, rsv_length); + } + + if (highmem_size) { + ram_resource(dev, index++, 0x100000000 >> 10, highmem_size >> 10); + } + printk(BIOS_INFO, "Available memory above 4GB: %lluM\n", + highmem_size >> 20); + + index = add_fixed_resources(dev, index); +} + +static void nc_read_resources(device_t dev) +{ + /* Call the normal read_resources */ + pci_dev_read_resources(dev); + + /* Calculate and add DRAM resources. */ + mc_add_dram_resources(dev); +} + +static void nc_enable(device_t dev) +{ + print_fsp_info(); +} + +static struct device_operations nc_ops = { + .read_resources = nc_read_resources, + .acpi_fill_ssdt_generator = generate_cpu_entries, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = NULL, + .enable = &nc_enable, + .scan_bus = 0, + .ops_pci = &soc_pci_ops, +}; + +static const struct pci_driver nc_driver __pci_driver = { + .ops = &nc_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = SOC_DEVID, +}; + +static const struct pci_driver nc_driver_es2 __pci_driver = { + .ops = &nc_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = SOC_DEVID_ES2, +}; \ No newline at end of file diff --git a/src/soc/intel/fsp_broadwell_de/ramstage.c b/src/soc/intel/fsp_broadwell_de/ramstage.c new file mode 100644 index 0000000..7b2f141 --- /dev/null +++ b/src/soc/intel/fsp_broadwell_de/ramstage.c @@ -0,0 +1,86 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015-2016 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdlib.h> +#include <arch/cpu.h> +#include <arch/acpi.h> +#include <console/console.h> +#include <cpu/intel/microcode.h> +#include <cpu/x86/cr.h> +#include <cpu/x86/msr.h> +#include <device/device.h> +#include <device/pci_def.h> +#include <device/pci_ops.h> +#include <romstage_handoff.h> +#include <soc/lpc.h> +#include <soc/msr.h> +#include <soc/pattrs.h> +#include <soc/pci_devs.h> +#include <soc/ramstage.h> + +/* Global PATTRS */ +DEFINE_PATTRS; + +#define SHOW_PATTRS 1 + +static void detect_num_cpus(struct pattrs *attrs) +{ + msr_t core_thread_count = rdmsr(MSR_CORE_THREAD_COUNT); + attrs->num_cpus = core_thread_count.lo & 0xffff; +} + +static inline void fill_in_msr(msr_t *msr, int idx) +{ + *msr = rdmsr(idx); + if (SHOW_PATTRS) { + printk(BIOS_DEBUG, "msr(%x) = %08x%08x\n", + idx, msr->hi, msr->lo); + } +} + +static const char *stepping_str[] = { + "U0", "V1", "V2", "Y0" +}; + +static void fill_in_pattrs(void) +{ + device_t dev; + struct pattrs *attrs = (struct pattrs *)pattrs_get(); + + attrs->cpuid = cpuid_eax(1); + attrs->stepping = (attrs->cpuid & 0x0F) - 1; + dev = dev_find_slot(0, PCI_DEVFN(LPC_DEV, LPC_FUNC)); + attrs->revid = pci_read_config8(dev, REVID); + attrs->microcode_patch = intel_microcode_find(); + attrs->address_bits = cpuid_eax(0x80000008) & 0xff; + detect_num_cpus(attrs); + + if (SHOW_PATTRS) { + printk(BIOS_DEBUG, "CPUID: %08x\n", attrs->cpuid); + printk(BIOS_DEBUG, "Cores: %d\n", attrs->num_cpus); + printk(BIOS_DEBUG, "Stepping: %s\n", (attrs->stepping >= ARRAY_SIZE(stepping_str)) + ? "??" : stepping_str[attrs->stepping]); + printk(BIOS_DEBUG, "Revision ID: %02x\n", attrs->revid); + } + + fill_in_msr(&attrs->platform_id, MSR_IA32_PLATFORM_ID); + fill_in_msr(&attrs->platform_info, MSR_PLATFORM_INFO); +} + +void broadwell_de_init_pre_device(void) +{ + fill_in_pattrs(); +} diff --git a/src/soc/intel/fsp_broadwell_de/reset.c b/src/soc/intel/fsp_broadwell_de/reset.c new file mode 100644 index 0000000..7e1c582 --- /dev/null +++ b/src/soc/intel/fsp_broadwell_de/reset.c @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015-2016 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <soc/reset.h> + +void warm_reset(void) +{ + outb(0x00, 0xcf9); + outb(0x06, 0xcf9); +} + +void hard_reset(void) +{ + warm_reset(); +} diff --git a/src/soc/intel/fsp_broadwell_de/romstage/Makefile.inc b/src/soc/intel/fsp_broadwell_de/romstage/Makefile.inc new file mode 100644 index 0000000..436f038 --- /dev/null +++ b/src/soc/intel/fsp_broadwell_de/romstage/Makefile.inc @@ -0,0 +1,3 @@ +romstage-y += romstage.c + +$(obj)/soc/intel/fsp_broadwell_de/romstage/romstage.romstage.o : $(obj)/build.h \ No newline at end of file diff --git a/src/soc/intel/fsp_broadwell_de/romstage/romstage.c b/src/soc/intel/fsp_broadwell_de/romstage/romstage.c new file mode 100644 index 0000000..6d29df9 --- /dev/null +++ b/src/soc/intel/fsp_broadwell_de/romstage/romstage.c @@ -0,0 +1,131 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015-2016 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stddef.h> +#include <arch/cpu.h> +#include <lib.h> +#include <arch/io.h> +#include <arch/cbfs.h> +#include <arch/stages.h> +#include <console/console.h> +#include <cpu/x86/mtrr.h> +#include <romstage_handoff.h> +#include <timestamp.h> +#include <version.h> +#include <device/pci_def.h> +#include <drivers/intel/fsp1_0/fsp_util.h> +#include <pc80/mc146818rtc.h> +#include <soc/gpio.h> +#include <soc/iomap.h> +#include <soc/lpc.h> +#include <soc/pci_devs.h> +#include <soc/romstage.h> +#include <build.h> + +static void init_rtc(void) +{ + u16 gen_pmcon3 = pci_read_config16(PCI_DEV(0, LPC_DEV, LPC_FUNC), GEN_PMCON_3); + + if (gen_pmcon3 & RTC_PWR_STS) { + printk(BIOS_DEBUG, "RTC Failure detected. Resetting Date to %s\n", + coreboot_dmi_date); + } + cmos_init(gen_pmcon3 & RTC_PWR_STS); +} + +/* Entry from cache-as-ram.inc. */ +void *asmlinkage main(FSP_INFO_HEADER *fsp_info_header) +{ + post_code(0x40); + console_init(); + + init_rtc(); + + /* Call into mainboard. */ + early_mainboard_romstage_entry(); + + /* + * Call early init to initialize memory and chipset. This function returns + * to the romstage_main_continue function with a pointer to the HOB + * structure. + */ + post_code(0x48); + printk(BIOS_DEBUG, "Starting the Intel FSP (early_init)\n"); + fsp_early_init(fsp_info_header); + die("Uh Oh! fsp_early_init should not return here.\n"); +} + +/******************************************************************************* + * The FSP early_init function returns to this function. + * Memory is setup and the stack is set by the FSP. + */ +void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr) +{ + int cbmem_was_initted; + void *cbmem_hob_ptr; + +#if IS_ENABLED(CONFIG_COLLECT_TIMESTAMPS) + tsc_t after_initram_time = rdtsc(); + tsc_t base_time; + base_time.hi = 0; + base_time.lo = 0; +#endif + post_code(0x4a); + printk(BIOS_DEBUG, "%s status: %x hob_list_ptr: %x\n", + __func__, (u32) status, (u32) hob_list_ptr); + +#if IS_ENABLED(CONFIG_USBDEBUG_IN_ROMSTAGE) + /* FSP reconfigures USB, so reinit it to have debug */ + usbdebug_init(); +#endif /* IS_ENABLED(CONFIG_USBDEBUG_IN_ROMSTAGE) */ + + printk(BIOS_DEBUG, "FSP Status: 0x%0x\n", (u32)status); + +#if IS_ENABLED(CONFIG_COLLECT_TIMESTAMPS) + after_initram_time = rdtsc(); +#endif + post_code(0x4b); + + late_mainboard_romstage_entry(); + post_code(0x4c); + + quick_ram_check(); + post_code(0x4d); + + cbmem_was_initted = !cbmem_recovery(0); + + /* Save the HOB pointer in CBMEM to be used in ramstage*/ + cbmem_hob_ptr = cbmem_add (CBMEM_ID_HOB_POINTER, sizeof(*hob_list_ptr)); + if (cbmem_hob_ptr == NULL) { + printk(BIOS_DEBUG, "Failed to save HOB pointer in CBMEM.\n"); + return; + } + *(u32 *)cbmem_hob_ptr = (u32)hob_list_ptr; + post_code(0x4e); + +#if IS_ENABLED(CONFIG_COLLECT_TIMESTAMPS) + timestamp_init(base_time); + timestamp_reinit(); + timestamp_add(TS_AFTER_INITRAM, after_initram_time); + timestamp_add_now(TS_END_ROMSTAGE); +#endif + + post_code(0x4f); + + /* Load the ramstage. */ + copy_and_run(); + while (1); +} diff --git a/src/soc/intel/fsp_broadwell_de/southcluster.c b/src/soc/intel/fsp_broadwell_de/southcluster.c new file mode 100644 index 0000000..7024814 --- /dev/null +++ b/src/soc/intel/fsp_broadwell_de/southcluster.c @@ -0,0 +1,267 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015-2016 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdint.h> +#include <arch/io.h> +#include <arch/ioapic.h> +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <device/pci_def.h> +#include <pc80/mc146818rtc.h> +#include <pc80/i8254.h> +#include <pc80/i8259.h> +#include <pc80/isa-dma.h> +#include <romstage_handoff.h> +#include <soc/iomap.h> +#include <soc/irq.h> +#include <soc/lpc.h> +#include <soc/pci_devs.h> +#include <soc/ramstage.h> +#include <chip.h> + +typedef struct soc_intel_fsp_broadwell_de_config config_t; + +static inline void +add_mmio_resource(device_t dev, int i, unsigned long addr, unsigned long size) +{ + mmio_resource(dev, i, addr >> 10, size >> 10); +} + +static void sc_add_mmio_resources(device_t dev) +{ + add_mmio_resource(dev, 0xfeb0, + ABORT_BASE_ADDRESS, + ABORT_BASE_SIZE); + add_mmio_resource(dev, 0xfeb8, + PSEG_BASE_ADDRESS, + PSEG_BASE_SIZE); + add_mmio_resource(dev, 0xfec0, + IOXAPIC1_BASE_ADDRESS, + IOXAPIC1_BASE_SIZE); + add_mmio_resource(dev, 0xfec1, + IOXAPIC2_BASE_ADDRESS, + IOXAPIC2_BASE_SIZE); + add_mmio_resource(dev, 0xfed0, + PCH_BASE_ADDRESS, + PCH_BASE_SIZE); + add_mmio_resource(dev, 0xfee0, + LXAPIC_BASE_ADDRESS, + LXAPIC_BASE_SIZE); + add_mmio_resource(dev, 0xff00, + FIRMWARE_BASE_ADDRESS, + FIRMWARE_BASE_SIZE); +} + +/* + * Write PCI config space IRQ assignments. PCI devices have the INT_LINE + * (0x3C) and INT_PIN (0x3D) registers which report interrupt routing + * information to operating systems and drivers. The INT_PIN register is + * generally read only and reports which interrupt pin A - D it uses. The + * INT_LINE register is configurable and reports which IRQ (generally the + * PIC IRQs 1 - 15) it will use. This needs to take interrupt pin swizzling + * on devices that are downstream on a PCI bridge into account. + * + * This function will loop through all enabled PCI devices and program the + * INT_LINE register with the correct PIC IRQ number for the INT_PIN that it + * uses. It then configures each interrupt in the pic to be level triggered. + */ +static void write_pci_config_irqs(void) +{ + device_t irq_dev; + device_t targ_dev; + uint8_t int_line = 0; + uint8_t original_int_pin = 0; + uint8_t new_int_pin = 0; + uint16_t current_bdf = 0; + uint16_t parent_bdf = 0; + uint8_t pirq = 0; + uint8_t device_num = 0; + const struct broadwell_de_irq_route *ir = &global_broadwell_de_irq_route; + + if (ir == NULL) { + printk(BIOS_WARNING, "Warning: Can't write PCI IRQ assignments because" + " 'global_broadwell_de_irq_route' structure does not exist\n"); + return; + } + + /* + * Loop through all enabled devices and program their + * INT_LINE, INT_PIN registers from values taken from + * the Interrupt Route registers in the ILB + */ + printk(BIOS_DEBUG, "PCI_CFG IRQ: Write PCI config space IRQ assignments\n"); + for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) { + + if ((irq_dev->path.type != DEVICE_PATH_PCI) || + (!irq_dev->enabled)) + continue; + + current_bdf = irq_dev->path.pci.devfn | + irq_dev->bus->secondary << 8; + + /* + * Step 1: Get the INT_PIN and device structure to look for + * in the pirq_data table defined in the mainboard directory. + */ + targ_dev = NULL; + new_int_pin = get_pci_irq_pins(irq_dev, &targ_dev); + if (targ_dev == NULL || new_int_pin < 1) + continue; + + /* Get the original INT_PIN for record keeping */ + original_int_pin = pci_read_config8(irq_dev, PCI_INTERRUPT_PIN); + + parent_bdf = targ_dev->path.pci.devfn + | targ_dev->bus->secondary << 8; + device_num = PCI_SLOT(parent_bdf); + + if (ir->pcidev[device_num] == 0) { + printk(BIOS_WARNING, + "Warning: PCI Device %d does not have an IRQ entry, skipping it\n", + device_num); + continue; + } + + /* Find the PIRQ that is attached to the INT_PIN this device uses */ + pirq = (ir->pcidev[device_num] >> ((new_int_pin - 1) * 4)) & 0xF; + + /* Get the INT_LINE this device/function will use */ + int_line = ir->pic[pirq]; + + if (int_line != PIRQ_PIC_IRQDISABLE) { + /* Set this IRQ to level triggered since it is used by a PCI device */ + i8259_configure_irq_trigger(int_line, IRQ_LEVEL_TRIGGERED); + /* Set the Interrupt Line register in PCI config space */ + pci_write_config8(irq_dev, PCI_INTERRUPT_LINE, int_line); + } else { + /* Set the Interrupt line register as "unknown or unused" */ + pci_write_config8(irq_dev, PCI_INTERRUPT_LINE, + PIRQ_PIC_UNKNOWN_UNUSED); + } + + printk(BIOS_SPEW, "\tINT_PIN\t\t: %d (%s)\n", + original_int_pin, pin_to_str(original_int_pin)); + if (parent_bdf != current_bdf) + printk(BIOS_SPEW, "\tSwizzled to\t: %d (%s)\n", + new_int_pin, pin_to_str(new_int_pin)); + printk(BIOS_SPEW, "\tPIRQ\t\t: %c\n" + "\tINT_LINE\t: 0x%X (IRQ %d)\n", + 'A' + pirq, int_line, int_line); + } + printk(BIOS_DEBUG, "PCI_CFG IRQ: Finished writing PCI config space IRQ assignments\n"); +} + +static void sc_pirq_init(device_t dev) +{ + int i; + const uint8_t *pirq = global_broadwell_de_irq_route.pic; + printk(BIOS_DEBUG, "Programming PIRQ[A-H] Routing Control Register\n"); + + for (i = 0; i < 8; i++) { + pci_write_config8(dev, (i < 4) ? (PIRQ_RCR1+i) : (PIRQ_RCR2+i-4), pirq[i]); + printk(BIOS_DEBUG, " PIRQ[%c]: %.2x\n" + , 'A'+i + , pci_read_config8(dev, (i < 4) ? (PIRQ_RCR1+i) : (PIRQ_RCR2+i-4)) + ); + } +} + +static void sc_add_io_resources(device_t dev) +{ + struct resource *res; + u8 io_index = 0; + + /* + * Add the default claimed IO range for the LPC device + * and mark it as subtractive decode. + */ + res = new_resource(dev, IOINDEX_SUBTRACTIVE(io_index++, 0)); + res->base = LPC_DEFAULT_IO_RANGE_LOWER; + res->size = LPC_DEFAULT_IO_RANGE_UPPER - LPC_DEFAULT_IO_RANGE_LOWER; + res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | + IORESOURCE_ASSIGNED | IORESOURCE_FIXED; +} + +static void sc_read_resources(device_t dev) +{ + pci_dev_read_resources(dev); + sc_add_mmio_resources(dev); + sc_add_io_resources(dev); +} + +static void sc_init(struct device *dev) +{ + printk(BIOS_DEBUG, "soc: southcluster_init\n"); + + /* Set the value for PCI command register. */ + pci_write_config16(dev, PCI_COMMAND, + PCI_COMMAND_IO | PCI_COMMAND_MEMORY | + PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL); + + /* Program Serial IRQ register. */ + pci_write_config16(dev, 0x64, 0xd0); + + sc_pirq_init(dev); + write_pci_config_irqs(); + isa_dma_init(); + setup_i8259(); + setup_i8254(); +} + +/* + * Common code for the south cluster devices. + */ +void southcluster_enable_dev(device_t dev) +{ + uint32_t reg32; + + if (!dev->enabled) { + int slot = PCI_SLOT(dev->path.pci.devfn); + int func = PCI_FUNC(dev->path.pci.devfn); + printk(BIOS_DEBUG, "%s: Disabling device: %02x.%01x\n", + dev_path(dev), slot, func); + + /* Ensure memory, io, and bus master are all disabled */ + reg32 = pci_read_config32(dev, PCI_COMMAND); + reg32 &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO); + pci_write_config32(dev, PCI_COMMAND, reg32); + } +} + +static struct device_operations device_ops = { + .read_resources = sc_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = NULL, + .init = sc_init, + .enable = southcluster_enable_dev, + .scan_bus = scan_lpc_bus, + .ops_pci = &soc_pci_ops, +}; + +static const struct pci_driver southcluster __pci_driver = { + .ops = &device_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = LPC_DEVID, +}; + +static const struct pci_driver southcluster_es2 __pci_driver = { + .ops = &device_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = LPC_DEVID_ES2, +}; diff --git a/src/soc/intel/fsp_broadwell_de/spi.c b/src/soc/intel/fsp_broadwell_de/spi.c new file mode 100644 index 0000000..f98ab97 --- /dev/null +++ b/src/soc/intel/fsp_broadwell_de/spi.c @@ -0,0 +1,633 @@ +/* + * Copyright (c) 2013 Google Inc. + * Copyright (C) 2015-2016 Intel Corp. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but without any warranty; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* This file is derived from the flashrom project. */ +#include <stdint.h> +#include <stdlib.h> +#include <string.h> +#include <delay.h> +#include <arch/io.h> +#include <console/console.h> +#include <device/pci_ids.h> +#include <spi_flash.h> +#include <spi-generic.h> + +#ifdef __SMM__ +#define pci_read_config_byte(dev, reg, targ)\ + *(targ) = pci_read_config8(dev, reg) +#define pci_read_config_word(dev, reg, targ)\ + *(targ) = pci_read_config16(dev, reg) +#define pci_read_config_dword(dev, reg, targ)\ + *(targ) = pci_read_config32(dev, reg) +#define pci_write_config_byte(dev, reg, val)\ + pci_write_config8(dev, reg, val) +#define pci_write_config_word(dev, reg, val)\ + pci_write_config16(dev, reg, val) +#define pci_write_config_dword(dev, reg, val)\ + pci_write_config32(dev, reg, val) +#else /* !__SMM__ */ +#include <device/device.h> +#include <device/pci.h> +#define pci_read_config_byte(dev, reg, targ)\ + *(targ) = pci_read_config8(dev, reg) +#define pci_read_config_word(dev, reg, targ)\ + *(targ) = pci_read_config16(dev, reg) +#define pci_read_config_dword(dev, reg, targ)\ + *(targ) = pci_read_config32(dev, reg) +#define pci_write_config_byte(dev, reg, val)\ + pci_write_config8(dev, reg, val) +#define pci_write_config_word(dev, reg, val)\ + pci_write_config16(dev, reg, val) +#define pci_write_config_dword(dev, reg, val)\ + pci_write_config32(dev, reg, val) +#endif /* !__SMM__ */ + +typedef struct spi_slave ich_spi_slave; + +static int ichspi_lock = 0; + +typedef struct ich9_spi_regs { + uint32_t bfpr; + uint16_t hsfs; + uint16_t hsfc; + uint32_t faddr; + uint32_t _reserved0; + uint32_t fdata[16]; + uint32_t frap; + uint32_t freg[5]; + uint32_t _reserved1[3]; + uint32_t pr[5]; + uint32_t _reserved2[2]; + uint8_t ssfs; + uint8_t ssfc[3]; + uint16_t preop; + uint16_t optype; + uint8_t opmenu[8]; + uint32_t bbar; + uint8_t _reserved3[12]; + uint32_t fdoc; + uint32_t fdod; + uint8_t _reserved4[8]; + uint32_t afc; + uint32_t lvscc; + uint32_t uvscc; + uint8_t _reserved5[4]; + uint32_t fpb; + uint8_t _reserved6[28]; + uint32_t srdl; + uint32_t srdc; + uint32_t srd; +} __attribute__((packed)) ich9_spi_regs; + +typedef struct ich_spi_controller { + int locked; + + uint8_t *opmenu; + int menubytes; + uint16_t *preop; + uint16_t *optype; + uint32_t *addr; + uint8_t *data; + unsigned databytes; + uint8_t *status; + uint16_t *control; + uint32_t *bbar; +} ich_spi_controller; + +static ich_spi_controller cntlr; + +enum { + SPIS_SCIP = 0x0001, + SPIS_GRANT = 0x0002, + SPIS_CDS = 0x0004, + SPIS_FCERR = 0x0008, + SSFS_AEL = 0x0010, + SPIS_LOCK = 0x8000, + SPIS_RESERVED_MASK = 0x7ff0, + SSFS_RESERVED_MASK = 0x7fe2 +}; + +enum { + SPIC_SCGO = 0x000002, + SPIC_ACS = 0x000004, + SPIC_SPOP = 0x000008, + SPIC_DBC = 0x003f00, + SPIC_DS = 0x004000, + SPIC_SME = 0x008000, + SSFC_SCF_MASK = 0x070000, + SSFC_RESERVED = 0xf80000 +}; + +enum { + HSFS_FDONE = 0x0001, + HSFS_FCERR = 0x0002, + HSFS_AEL = 0x0004, + HSFS_BERASE_MASK = 0x0018, + HSFS_BERASE_SHIFT = 3, + HSFS_SCIP = 0x0020, + HSFS_FDOPSS = 0x2000, + HSFS_FDV = 0x4000, + HSFS_FLOCKDN = 0x8000 +}; + +enum { + HSFC_FGO = 0x0001, + HSFC_FCYCLE_MASK = 0x0006, + HSFC_FCYCLE_SHIFT = 1, + HSFC_FDBC_MASK = 0x3f00, + HSFC_FDBC_SHIFT = 8, + HSFC_FSMIE = 0x8000 +}; + +enum { + SPI_OPCODE_TYPE_READ_NO_ADDRESS = 0, + SPI_OPCODE_TYPE_WRITE_NO_ADDRESS = 1, + SPI_OPCODE_TYPE_READ_WITH_ADDRESS = 2, + SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS = 3 +}; + +#if IS_ENABLED(CONFIG_DEBUG_SPI_FLASH) + +static u8 readb_(const void *addr) +{ + u8 v = read8(addr); + printk(BIOS_DEBUG, "read %2.2x from %4.4x\n", + v, ((unsigned) addr & 0xffff) - 0xf020); + return v; +} + +static u16 readw_(const void *addr) +{ + u16 v = read16(addr); + printk(BIOS_DEBUG, "read %4.4x from %4.4x\n", + v, ((unsigned) addr & 0xffff) - 0xf020); + return v; +} + +static u32 readl_(const void *addr) +{ + u32 v = read32(addr); + printk(BIOS_DEBUG, "read %8.8x from %4.4x\n", + v, ((unsigned) addr & 0xffff) - 0xf020); + return v; +} + +static void writeb_(u8 b, const void *addr) +{ + write8(addr, b); + printk(BIOS_DEBUG, "wrote %2.2x to %4.4x\n", + b, ((unsigned) addr & 0xffff) - 0xf020); +} + +static void writew_(u16 b, const void *addr) +{ + write16(addr, b); + printk(BIOS_DEBUG, "wrote %4.4x to %4.4x\n", + b, ((unsigned) addr & 0xffff) - 0xf020); +} + +static void writel_(u32 b, const void *addr) +{ + write32(addr, b); + printk(BIOS_DEBUG, "wrote %8.8x to %4.4x\n", + b, ((unsigned) addr & 0xffff) - 0xf020); +} + +#else /* CONFIG_DEBUG_SPI_FLASH ^^^ enabled vvv NOT enabled */ + +#define readb_(a) read8(a) +#define readw_(a) read16(a) +#define readl_(a) read32(a) +#define writeb_(val, addr) write8(addr, val) +#define writew_(val, addr) write16(addr, val) +#define writel_(val, addr) write32(addr, val) + +#endif /* CONFIG_DEBUG_SPI_FLASH ^^^ NOT enabled */ + +static void write_reg(const void *value, void *dest, uint32_t size) +{ + const uint8_t *bvalue = value; + uint8_t *bdest = dest; + + while (size >= 4) { + writel_(*(const uint32_t *)bvalue, bdest); + bdest += 4; bvalue += 4; size -= 4; + } + while (size) { + writeb_(*bvalue, bdest); + bdest++; bvalue++; size--; + } +} + +static void read_reg(const void *src, void *value, uint32_t size) +{ + const uint8_t *bsrc = src; + uint8_t *bvalue = value; + + while (size >= 4) { + *(uint32_t *)bvalue = readl_(bsrc); + bsrc += 4; bvalue += 4; size -= 4; + } + while (size) { + *bvalue = readb_(bsrc); + bsrc++; bvalue++; size--; + } +} + +static void ich_set_bbar(uint32_t minaddr) +{ + const uint32_t bbar_mask = 0x00ffff00; + uint32_t ichspi_bbar; + + minaddr &= bbar_mask; + ichspi_bbar = readl_(cntlr.bbar) & ~bbar_mask; + ichspi_bbar |= minaddr; + writel_(ichspi_bbar, cntlr.bbar); +} + +struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs) +{ + ich_spi_slave *slave = malloc(sizeof(*slave)); + + if (!slave) { + printk(BIOS_DEBUG, "ICH SPI: Bad allocation\n"); + return NULL; + } + + memset(slave, 0, sizeof(*slave)); + + slave->bus = bus; + slave->cs = cs; + return slave; +} + +void spi_init(void) +{ + uint8_t *rcrb; /* Root Complex Register Block */ + uint32_t rcba; /* Root Complex Base Address */ + uint8_t bios_cntl; + device_t dev; + ich9_spi_regs *ich9_spi; + +#ifdef __SMM__ + dev = PCI_DEV(0, 31, 0); +#else + dev = dev_find_slot(0, PCI_DEVFN(31, 0)); +#endif + + pci_read_config_dword(dev, 0xf0, &rcba); + /* Bits 31-14 are the base address, 13-1 are reserved, 0 is enable. */ + rcrb = (uint8_t *)(rcba & 0xffffc000); + ich9_spi = (ich9_spi_regs *)(rcrb + 0x3800); + ichspi_lock = readw_(&ich9_spi->hsfs) & HSFS_FLOCKDN; + cntlr.opmenu = ich9_spi->opmenu; + cntlr.menubytes = sizeof(ich9_spi->opmenu); + cntlr.optype = &ich9_spi->optype; + cntlr.addr = &ich9_spi->faddr; + cntlr.data = (uint8_t *)ich9_spi->fdata; + cntlr.databytes = sizeof(ich9_spi->fdata); + cntlr.status = &ich9_spi->ssfs; + cntlr.control = (uint16_t *)ich9_spi->ssfc; + cntlr.bbar = &ich9_spi->bbar; + cntlr.preop = &ich9_spi->preop; + ich_set_bbar(0); + + /* Disable the BIOS write protect so write commands are allowed. */ + pci_read_config_byte(dev, 0xdc, &bios_cntl); + bios_cntl &= ~(1 << 5); + pci_write_config_byte(dev, 0xdc, bios_cntl | 0x1); +} + +int spi_claim_bus(struct spi_slave *slave) +{ + /* Handled by ICH automatically. */ + return 0; +} + +void spi_release_bus(struct spi_slave *slave) +{ + /* Handled by ICH automatically. */ +} + +typedef struct spi_transaction { + const uint8_t *out; + uint32_t bytesout; + uint8_t *in; + uint32_t bytesin; + uint8_t type; + uint8_t opcode; + uint32_t offset; +} spi_transaction; + +static inline void spi_use_out(spi_transaction *trans, unsigned bytes) +{ + trans->out += bytes; + trans->bytesout -= bytes; +} + +static inline void spi_use_in(spi_transaction *trans, unsigned bytes) +{ + trans->in += bytes; + trans->bytesin -= bytes; +} + +static void spi_setup_type(spi_transaction *trans) +{ + trans->type = 0xFF; + + /* Try to guess spi type from read/write sizes. */ + if (trans->bytesin == 0) { + if (trans->bytesout > 4) + /* + * If bytesin = 0 and bytesout > 4, we presume this is + * a write data operation, which is accompanied by an + * address. + */ + trans->type = SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS; + else + trans->type = SPI_OPCODE_TYPE_WRITE_NO_ADDRESS; + return; + } + + if (trans->bytesout == 1) { /* and bytesin is > 0 */ + trans->type = SPI_OPCODE_TYPE_READ_NO_ADDRESS; + return; + } + + if (trans->bytesout == 4) { /* and bytesin is > 0 */ + trans->type = SPI_OPCODE_TYPE_READ_WITH_ADDRESS; + } + + /* Fast read command is called with 5 bytes instead of 4 */ + if (trans->out[0] == SPI_OPCODE_FAST_READ && trans->bytesout == 5) { + trans->type = SPI_OPCODE_TYPE_READ_WITH_ADDRESS; + --trans->bytesout; + } +} + +static int spi_setup_opcode(spi_transaction *trans) +{ + uint16_t optypes; + uint8_t opmenu[cntlr.menubytes]; + + trans->opcode = trans->out[0]; + spi_use_out(trans, 1); + if (!ichspi_lock) { + /* The lock is off, so just use index 0. */ + writeb_(trans->opcode, cntlr.opmenu); + optypes = readw_(cntlr.optype); + optypes = (optypes & 0xfffc) | (trans->type & 0x3); + writew_(optypes, cntlr.optype); + return 0; + } else { + /* The lock is on. See if what we need is on the menu. */ + uint8_t optype; + uint16_t opcode_index; + + /* Write Enable is handled as atomic prefix */ + if (trans->opcode == SPI_OPCODE_WREN) + return 0; + + read_reg(cntlr.opmenu, opmenu, sizeof(opmenu)); + for (opcode_index = 0; opcode_index < cntlr.menubytes; + opcode_index++) { + if (opmenu[opcode_index] == trans->opcode) + break; + } + + if (opcode_index == cntlr.menubytes) { + printk(BIOS_DEBUG, "ICH SPI: Opcode %x not found\n", + trans->opcode); + return -1; + } + + optypes = readw_(cntlr.optype); + optype = (optypes >> (opcode_index * 2)) & 0x3; + if (trans->type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS && + optype == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS && + trans->bytesout >= 3) { + /* We guessed wrong earlier. Fix it up. */ + trans->type = optype; + } + if (optype != trans->type) { + printk(BIOS_DEBUG, "ICH SPI: Transaction doesn't fit type %d\n", + optype); + return -1; + } + return opcode_index; + } +} + +static int spi_setup_offset(spi_transaction *trans) +{ + /* Separate the SPI address and data. */ + switch (trans->type) { + case SPI_OPCODE_TYPE_READ_NO_ADDRESS: + case SPI_OPCODE_TYPE_WRITE_NO_ADDRESS: + return 0; + case SPI_OPCODE_TYPE_READ_WITH_ADDRESS: + case SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS: + trans->offset = ((uint32_t)trans->out[0] << 16) | + ((uint32_t)trans->out[1] << 8) | + ((uint32_t)trans->out[2] << 0); + spi_use_out(trans, 3); + return 1; + default: + printk(BIOS_DEBUG, "Unrecognized SPI transaction type %#x\n", trans->type); + return -1; + } +} + +/* + * Wait for up to 60ms til status register bit(s) turn 1 (in case wait_til_set + * below is True) or 0. In case the wait was for the bit(s) to set - write + * those bits back, which would cause resetting them. + * + * Return the last read status value on success or -1 on failure. + */ +static int ich_status_poll(u16 bitmask, int wait_til_set) +{ + int timeout = 40000; /* This will result in 400 ms */ + u16 status = 0; + + while (timeout--) { + status = readw_(cntlr.status); + if (wait_til_set ^ ((status & bitmask) == 0)) { + if (wait_til_set) + writew_((status & bitmask), cntlr.status); + return status; + } + udelay(10); + } + + printk(BIOS_DEBUG, "ICH SPI: SCIP timeout, read %x, expected %x\n", + status, bitmask); + return -1; +} + +unsigned int spi_crop_chunk(unsigned int cmd_len, unsigned int buf_len) +{ + return min(cntlr.databytes, buf_len); +} + +int spi_xfer(struct spi_slave *slave, const void *dout, + unsigned int bytesout, void *din, unsigned int bytesin) +{ + uint16_t control; + int16_t opcode_index; + int with_address; + int status; + + spi_transaction trans = { + dout, bytesout, + din, bytesin, + 0xff, 0xff, 0 + }; + + /* There has to always at least be an opcode. */ + if (!bytesout || !dout) { + printk(BIOS_DEBUG, "ICH SPI: No opcode for transfer\n"); + return -1; + } + /* Make sure if we read something we have a place to put it. */ + if (bytesin != 0 && !din) { + printk(BIOS_DEBUG, "ICH SPI: Read but no target buffer\n"); + return -1; + } + + if (ich_status_poll(SPIS_SCIP, 0) == -1) + return -1; + + writew_(SPIS_CDS | SPIS_FCERR, cntlr.status); + + spi_setup_type(&trans); + opcode_index = spi_setup_opcode(&trans); + if (opcode_index < 0) + return -1; + with_address = spi_setup_offset(&trans); + if (with_address < 0) + return -1; + + if (!ichspi_lock && trans.opcode == SPI_OPCODE_WREN) { + /* + * Treat Write Enable as Atomic Pre-Op if possible + * in order to prevent the Management Engine from + * issuing a transaction between WREN and DATA. + */ + writew_(trans.opcode, cntlr.preop); + return 0; + } + + /* Preset control fields */ + control = SPIC_SCGO | ((opcode_index & 0x07) << 4); + + /* Issue atomic preop cycle if needed */ + if (readw_(cntlr.preop)) + control |= SPIC_ACS; + + if (!trans.bytesout && !trans.bytesin) { + /* SPI addresses are 24 bit only */ + if (with_address) + writel_(trans.offset & 0x00FFFFFF, cntlr.addr); + + /* + * This is a 'no data' command (like Write Enable), its + * bitesout size was 1, decremented to zero while executing + * spi_setup_opcode() above. Tell the chip to send the + * command. + */ + writew_(control, cntlr.control); + + /* wait for the result */ + status = ich_status_poll(SPIS_CDS | SPIS_FCERR, 1); + if (status == -1) + return -1; + + if (status & SPIS_FCERR) { + printk(BIOS_DEBUG, "ICH SPI: Command transaction error\n"); + return -1; + } + + goto spi_xfer_exit; + } + + /* + * Check if this is a write command attempting to transfer more bytes + * than the controller can handle. Iterations for writes are not + * supported here because each SPI write command needs to be preceded + * and followed by other SPI commands, and this sequence is controlled + * by the SPI chip driver. + */ + if (trans.bytesout > cntlr.databytes) { + printk(BIOS_DEBUG, "ICH SPI: Too much to write. Does your SPI chip driver use" + " spi_crop_chunk()?\n"); + return -1; + } + + /* + * Read or write up to databytes bytes at a time until everything has + * been sent. + */ + while (trans.bytesout || trans.bytesin) { + uint32_t data_length; + + /* SPI addresses are 24 bit only */ + writel_(trans.offset & 0x00FFFFFF, cntlr.addr); + + if (trans.bytesout) + data_length = min(trans.bytesout, cntlr.databytes); + else + data_length = min(trans.bytesin, cntlr.databytes); + + /* Program data into FDATA0 to N */ + if (trans.bytesout) { + write_reg(trans.out, cntlr.data, data_length); + spi_use_out(&trans, data_length); + if (with_address) + trans.offset += data_length; + } + + /* Add proper control fields' values */ + control &= ~((cntlr.databytes - 1) << 8); + control |= SPIC_DS; + control |= (data_length - 1) << 8; + + /* write it */ + writew_(control, cntlr.control); + + /* Wait for Cycle Done Status or Flash Cycle Error. */ + status = ich_status_poll(SPIS_CDS | SPIS_FCERR, 1); + if (status == -1) + return -1; + + if (status & SPIS_FCERR) { + printk(BIOS_DEBUG, "ICH SPI: Data transaction error\n"); + return -1; + } + + if (trans.bytesin) { + read_reg(cntlr.data, trans.in, data_length); + spi_use_in(&trans, data_length); + if (with_address) + trans.offset += data_length; + } + } + +spi_xfer_exit: + /* Clear atomic preop now that xfer is done */ + writew_(0, cntlr.preop); + + return 0; +} diff --git a/src/soc/intel/fsp_broadwell_de/uart.c b/src/soc/intel/fsp_broadwell_de/uart.c new file mode 100644 index 0000000..d22dd0d --- /dev/null +++ b/src/soc/intel/fsp_broadwell_de/uart.c @@ -0,0 +1,112 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2003 Eric Biederman + * Copyright (C) 2006-2010 coresystems GmbH + * Copyright (C) 2015-2016 Intel Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <rules.h> +#include <stdlib.h> +#include <arch/io.h> +#include <console/uart.h> +#include <trace.h> +#include <drivers/uart/uart8250reg.h> + +#ifndef __ROMCC__ +#include <boot/coreboot_tables.h> +#endif + +/* Expected character delay at 1200bps is 9ms for a working UART + * and no flow-control. Assume UART as stuck if shift register + * or FIFO takes more than 50ms per character to appear empty. + * + * Estimated that inb() from UART takes 1 microsecond. + */ +#define SINGLE_CHAR_TIMEOUT (50 * 1000) +#define FIFO_TIMEOUT (16 * SINGLE_CHAR_TIMEOUT) + +static int uart8250_can_tx_byte(unsigned base_port) +{ + return inb(base_port + UART8250_LSR) & UART8250_LSR_THRE; +} + +static void uart8250_tx_byte(unsigned base_port, unsigned char data) +{ + unsigned long int i = SINGLE_CHAR_TIMEOUT; + while (i-- && !uart8250_can_tx_byte(base_port)); + outb(data, base_port + UART8250_TBR); +} + +static void uart8250_tx_flush(unsigned base_port) +{ + unsigned long int i = FIFO_TIMEOUT; + while (i-- && !(inb(base_port + UART8250_LSR) & UART8250_LSR_TEMT)); +} + +static int uart8250_can_rx_byte(unsigned base_port) +{ + return inb(base_port + UART8250_LSR) & UART8250_LSR_DR; +} + +static unsigned char uart8250_rx_byte(unsigned base_port) +{ + unsigned long int i = SINGLE_CHAR_TIMEOUT; + while (i-- && !uart8250_can_rx_byte(base_port)); + + if (i) + return inb(base_port + UART8250_RBR); + else + return 0x0; +} + +static const unsigned bases[] = { 0x3f8, 0x2f8 }; + +uintptr_t uart_platform_base(int idx) +{ + if (idx < ARRAY_SIZE(bases)) + return bases[idx]; + return 0; +} + +void uart_init(int idx) +{ + // No needed to configure as setting has been done in BDX-DE FSP +} + +void uart_tx_byte(int idx, unsigned char data) +{ + uart8250_tx_byte(uart_platform_base(idx), data); +} + +unsigned char uart_rx_byte(int idx) +{ + return uart8250_rx_byte(uart_platform_base(idx)); +} + +void uart_tx_flush(int idx) +{ + uart8250_tx_flush(uart_platform_base(idx)); +} + +#if ENV_RAMSTAGE +void uart_fill_lb(void *data) +{ + struct lb_serial serial; + serial.type = LB_SERIAL_TYPE_IO_MAPPED; + serial.baseaddr = uart_platform_base(CONFIG_UART_FOR_CONSOLE); + serial.baud = default_baudrate(); + lb_add_serial(&serial, data); + + lb_add_console(LB_TAG_CONSOLE_SERIAL8250, data); +} +#endif

1 0

Patch set updated for coreboot: mainboard/pcengines/apu2: WIP - Add PC Engines APU2 mainboard
by Philipp Deppenwiese 18 Mar '16

18 Mar '16

Philipp Deppenwiese (zaolin.daisuki(a)googlemail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14138 -gerrit commit 43dfeb839bdc2fb0087a383f41814515f62a4cfb Author: Philipp Deppenwiese <zaolin(a)das-labor.org> Date: Fri Mar 18 13:34:27 2016 +0100 mainboard/pcengines/apu2: WIP - Add PC Engines APU2 mainboard Currently WIP and not working ! Change-Id: Id23e448e27f4bba47b7e9e7fa7679e2690c6e4bc Signed-off-by: Philipp Deppenwiese <zaolin(a)das-labor.org> --- src/device/dram/Makefile.inc | 1 + src/mainboard/pcengines/apu1/Kconfig | 5 - src/mainboard/pcengines/apu2/BiosCallOuts.c | 163 +++++++ src/mainboard/pcengines/apu2/Kconfig | 128 ++++++ src/mainboard/pcengines/apu2/Kconfig.name | 2 + src/mainboard/pcengines/apu2/Makefile.inc | 45 ++ src/mainboard/pcengines/apu2/OptionsIds.h | 68 +++ src/mainboard/pcengines/apu2/PlatformGnbPcie.c | 122 ++++++ .../pcengines/apu2/PlatformGnbPcieComplex.h | 27 ++ src/mainboard/pcengines/apu2/acpi/gpe.asl | 80 ++++ src/mainboard/pcengines/apu2/acpi/ide.asl | 1 + src/mainboard/pcengines/apu2/acpi/mainboard.asl | 37 ++ src/mainboard/pcengines/apu2/acpi/pci_int.asl | 471 +++++++++++++++++++++ src/mainboard/pcengines/apu2/acpi/routing.asl | 213 ++++++++++ src/mainboard/pcengines/apu2/acpi/sata.asl | 1 + src/mainboard/pcengines/apu2/acpi/si.asl | 23 + src/mainboard/pcengines/apu2/acpi/sleep.asl | 93 ++++ src/mainboard/pcengines/apu2/acpi/superio.asl | 28 ++ src/mainboard/pcengines/apu2/acpi/thermal.asl | 1 + src/mainboard/pcengines/apu2/acpi/usb_oc.asl | 36 ++ src/mainboard/pcengines/apu2/acpi_tables.c | 276 ++++++++++++ src/mainboard/pcengines/apu2/apu2.h | 42 ++ src/mainboard/pcengines/apu2/board_info.txt | 6 + src/mainboard/pcengines/apu2/cmos.default | 13 + src/mainboard/pcengines/apu2/cmos.layout | 126 ++++++ src/mainboard/pcengines/apu2/devicetree.cb | 92 ++++ src/mainboard/pcengines/apu2/dsdt.asl | 90 ++++ src/mainboard/pcengines/apu2/irq_tables.c | 104 +++++ src/mainboard/pcengines/apu2/mainboard.c | 163 +++++++ src/mainboard/pcengines/apu2/mptable.c | 198 +++++++++ src/mainboard/pcengines/apu2/romstage.c | 236 +++++++++++ .../pcengines/apu2/spd/HYNIX-2G-1333.spd.hex | 263 ++++++++++++ .../pcengines/apu2/spd/HYNIX-4G-1333-ECC.spd.hex | 257 +++++++++++ .../pcengines/apu2/spd/HYNIX-4G-1333-NOECC.spd.hex | 258 +++++++++++ src/southbridge/amd/pi/hudson/Makefile.inc | 2 + src/southbridge/amd/pi/hudson/early_setup.c | 16 +- src/southbridge/amd/pi/hudson/fchgpio.c | 137 ++++++ src/southbridge/amd/pi/hudson/fchgpio.h | 44 ++ 38 files changed, 3862 insertions(+), 6 deletions(-) diff --git a/src/device/dram/Makefile.inc b/src/device/dram/Makefile.inc index 05f440b..9571ac3 100644 --- a/src/device/dram/Makefile.inc +++ b/src/device/dram/Makefile.inc @@ -1 +1,2 @@ romstage-$(CONFIG_SPD_CACHE) += spd_cache.c ddr3.c +ramstage-$(CONFIG_SPD_CACHE) += spd_cache.c ddr3.c diff --git a/src/mainboard/pcengines/apu1/Kconfig b/src/mainboard/pcengines/apu1/Kconfig index 2328776..60e92e2 100644 --- a/src/mainboard/pcengines/apu1/Kconfig +++ b/src/mainboard/pcengines/apu1/Kconfig @@ -63,11 +63,6 @@ config VGA_BIOS bool default n -#config VGA_BIOS_FILE -# string "VGA BIOS path and filename" -# depends on VGA_BIOS -# default "rom/video/OntarioGenericVbios.bin" - config VGA_BIOS_ID string default "1002,9802" diff --git a/src/mainboard/pcengines/apu2/BiosCallOuts.c b/src/mainboard/pcengines/apu2/BiosCallOuts.c new file mode 100644 index 0000000..5dda286 --- /dev/null +++ b/src/mainboard/pcengines/apu2/BiosCallOuts.c @@ -0,0 +1,163 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "AGESA.h" +#include "amdlib.h" +#include <northbridge/amd/pi/BiosCallOuts.h> +#include "Ids.h" +//#include "OptionsIds.h" +#include "heapManager.h" +#include "FchPlatform.h" +#include "cbfs.h" +#if IS_ENABLED(CONFIG_HUDSON_IMC_FWM) +#include "imc.h" +#endif +#include "hudson.h" +#include <stdlib.h> +#include <fchgpio.h> +#include "apu2.h" +#include <spd_cache.h> // for the apu2_ReadSpd_from_cbfs function + +static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr); +AGESA_STATUS apu2_ReadSpd_from_cbfs(UINT32 Func, UINT32 Data, VOID *ConfigPtr); + +const BIOS_CALLOUT_STRUCT BiosCallouts[] = +{ + {AGESA_ALLOCATE_BUFFER, agesa_AllocateBuffer }, + {AGESA_DEALLOCATE_BUFFER, agesa_DeallocateBuffer }, + {AGESA_LOCATE_BUFFER, agesa_LocateBuffer }, + {AGESA_READ_SPD, apu2_ReadSpd_from_cbfs }, + {AGESA_DO_RESET, agesa_Reset }, + {AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported }, + {AGESA_RUNFUNC_ONAP, agesa_RunFuncOnAp }, + {AGESA_GET_IDS_INIT_DATA, agesa_EmptyIdsInitData }, + {AGESA_HOOKBEFORE_DQS_TRAINING, agesa_NoopSuccess }, + {AGESA_HOOKBEFORE_EXIT_SELF_REF, agesa_NoopSuccess }, + {AGESA_FCH_OEM_CALLOUT, Fch_Oem_config } +}; +const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts); + +//{AGESA_GNB_GFX_GET_VBIOS_IMAGE, agesa_NoopUnsupported } + + +/* + * Hardware Monitor Fan Control + * Hardware limitation: + * HWM will fail to read the input temperature via I2C if other + * software switches the I2C address. AMD recommends using IMC + * to control fans, instead of HWM. + */ +static void oem_fan_control(FCH_DATA_BLOCK *FchParams) +{ + FchParams->Imc.ImcEnable = FALSE; + FchParams->Hwm.HwMonitorEnable = FALSE; + FchParams->Hwm.HwmFchtsiAutoPoll = FALSE; /* 1 enable, 0 disable TSI Auto Polling */ +} + +/** + * Fch Oem setting callback + * + * Configure platform specific Hudson device, + * such Azalia, SATA, IMC etc. + */ +static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr) +{ + AMD_CONFIG_PARAMS *StdHeader = (AMD_CONFIG_PARAMS *)ConfigPtr; + if (StdHeader->Func == AMD_INIT_RESET) { + FCH_RESET_DATA_BLOCK *FchParams = (FCH_RESET_DATA_BLOCK *) FchData; + printk(BIOS_DEBUG, "\n%s in INIT RESET\n", __func__ ); + //FchParams_reset->EcChannel0 = TRUE; /* logical devicd 3 */ + FchParams->LegacyFree = CONFIG_HUDSON_LEGACY_FREE; + FchParams->FchReset.SataEnable = hudson_sata_enable(); + FchParams->FchReset.IdeEnable = hudson_ide_enable(); + FchParams->FchReset.Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE); + FchParams->FchReset.Xhci1Enable = FALSE; + + + } else if (StdHeader->Func == AMD_INIT_ENV) { + FCH_DATA_BLOCK *FchParams = (FCH_DATA_BLOCK *)FchData; + printk(BIOS_DEBUG, "Fch OEM config in INIT ENV "); + + /* Azalia Controller OEM Codec Table Pointer */ + /* Azalia Controller Front Panel OEM Table Pointer */ + + // No audio support in this system + FchParams->Azalia.AzaliaEnable = AzDisable; + + /* Fan Control */ + oem_fan_control(FchParams); + + /* XHCI configuration */ + FchParams->Usb.Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE); + FchParams->Usb.Xhci1Enable = FALSE; + + /* EHCI configuration */ + FchParams->Usb.Ehci3Enable = !IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE); + FchParams->Usb.Ehci1Enable = FALSE; // Disable EHCI 0 (port 0 to 3) + FchParams->Usb.Ehci2Enable = TRUE; // Enable EHCI 1 ( port 4 to 7) port 4 and 5 to EHCI header port 6 and 7 to PCIe slot. + + /* sata configuration */ + FchParams->Sata.SataDevSlpPort0 = 0; // Disable DEVSLP0 and 1 to make sure GPIO55 and 59 are not used by DEVSLP + FchParams->Sata.SataDevSlpPort1 = 0; + + FchParams->Sata.SataClass = CONFIG_HUDSON_SATA_MODE; + switch ((SATA_CLASS)CONFIG_HUDSON_SATA_MODE) { + case SataRaid: + case SataAhci: + case SataAhci7804: + case SataLegacyIde: + FchParams->Sata.SataIdeMode = FALSE; + break; + case SataIde2Ahci: + case SataIde2Ahci7804: + default: /* SataNativeIde */ + FchParams->Sata.SataIdeMode = TRUE; + break; + } + } + printk(BIOS_DEBUG, "Done\n"); + + return AGESA_SUCCESS; +} + + +AGESA_STATUS apu2_ReadSpd_from_cbfs(UINT32 Func, UINT32 Data, VOID *ConfigPtr) +{ + AGESA_STATUS Status = AGESA_UNSUPPORTED; +#ifdef __PRE_RAM__ + AGESA_READ_SPD_PARAMS *info = ConfigPtr; + int index = 0; + + if (info->MemChannelId > 0) + return AGESA_UNSUPPORTED; + if (info->SocketId != 0) + return AGESA_UNSUPPORTED; + if (info->DimmId != 0) + return AGESA_UNSUPPORTED; + + /* One SPD file contains all 4 options, determine which index to read here, then call into the standard routines*/ + + if ( ReadFchGpio(APU2_SPD_STRAP0_GPIO) ) index |= BIT0; + if ( ReadFchGpio(APU2_SPD_STRAP1_GPIO) ) index |= BIT1; + + printk(BIOS_INFO, "Reading SPD index %d\n", index); + + if (read_spd_from_cbfs((u8*)info->Buffer, index) < 0) + die("No SPD data\n"); + + Status = AGESA_SUCCESS; +#endif + return Status; +} diff --git a/src/mainboard/pcengines/apu2/Kconfig b/src/mainboard/pcengines/apu2/Kconfig new file mode 100644 index 0000000..2dce547 --- /dev/null +++ b/src/mainboard/pcengines/apu2/Kconfig @@ -0,0 +1,128 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2012 Advanced Micro Devices, Inc. +# Copyright (C) 2016 Eltan B.V. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# + +if BOARD_PCENGINES_APU2 + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select CPU_AMD_PI_00730F01 + select NORTHBRIDGE_AMD_PI_00730F01 + select SOUTHBRIDGE_AMD_PI_AVALON + select SUPERIO_NUVOTON_NCT5104D + select HAVE_PIRQ_TABLE + select HAVE_MP_TABLE + select HAVE_ACPI_TABLES + select BOARD_ROMSIZE_KB_8192 + select SPD_CACHE + select HUDSON_DISABLE_IMC + select HAVE_OPTION_TABLE + select USE_OPTION_TABLE + select HAVE_CMOS_DEFAULT + +config MAINBOARD_DIR + string + default pcengines/apu2 + +config MAINBOARD_PART_NUMBER + string + default "PCEngines apu2" + +config SVI2_SLOW_SPEED + bool "SVI2 slow speed" + default n + help + Used when there are problems switching the VRM speed. By default + speed is 20 Mhz + +config SVI_WAIT_COMP_DIS + bool "Disable SVI2 controller waits for command completion" + default y + help + SVI2 controller will not wait for command completion from VRM + +config HW_MEM_HOLE_SIZEK + hex + default 0x200000 + +config MAX_CPUS + int + default 4 + +config HW_MEM_HOLE_SIZE_AUTO_INC + bool + default n + +config IRQ_SLOT_COUNT + int + default 11 + +config RAMTOP + hex + default 0x1000000 + +config HEAP_SIZE + hex + default 0xc0000 + +config ACPI_SSDTX_NUM + int + default 0 + +config RAMBASE + hex + default 0x200000 + +config HUDSON_LEGACY_FREE + bool + default y + +config HUDSON_XHCI_ENABLE + bool + default y + +config DRIVERS_PS2_KEYBOARD + bool + default n + +config AGESA_HEAP_MEMTEST + bool + default y + +config VGA_ROM_RUN + bool + default n + +config DUMP_GPIO_CONFIGURATION + bool "Dump FCH GPIO configuration in board finalize" + default n + +config DUMP_CLOCK_CONFIGURATION + bool "Dump FCH MISC configuration in board finalize" + default n + +config DUMP_LINK_CONFIGURATION + bool "Dump PCIe LINK configuration in board finalize" + default n + +config SUPERIO_NUVOTON_NCT5104D_UARTC_ENABLE + bool "enable uartc" + default n + +config SUPERIO_NUVOTON_NCT5104D_UARTD_ENABLE + bool "enable uartd" + default n + +endif # BOARD_PCENGINES_APU2 diff --git a/src/mainboard/pcengines/apu2/Kconfig.name b/src/mainboard/pcengines/apu2/Kconfig.name new file mode 100644 index 0000000..ab19ee4 --- /dev/null +++ b/src/mainboard/pcengines/apu2/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_PCENGINES_APU2 + bool "APU2" diff --git a/src/mainboard/pcengines/apu2/Makefile.inc b/src/mainboard/pcengines/apu2/Makefile.inc new file mode 100644 index 0000000..002770b --- /dev/null +++ b/src/mainboard/pcengines/apu2/Makefile.inc @@ -0,0 +1,45 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2012 Advanced Micro Devices, Inc. +# Copyright (C) 2016 Eltan B.V. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# + +#romstage-y += agesawrapper.c +romstage-y += BiosCallOuts.c +romstage-y += PlatformGnbPcie.c + +#ramstage-y += agesawrapper.c +ramstage-y += BiosCallOuts.c +ramstage-y += PlatformGnbPcie.c + +# WIV20141001 START ADD SPD FROM FILE +## DIMM SPD for on-board memory +SPD_BIN = $(obj)/spd.bin + +# Order of names in SPD_SOURCES is important! +SPD_SOURCES = HYNIX-2G-1333 HYNIX-4G-1333-ECC +SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) + +# Include spd rom data +$(SPD_BIN): $(SPD_DEPS) src/mainboard/$(MAINBOARDDIR)/Makefile.inc + echo " create SPD $@" + for f in $(SPD_DEPS); \ + do for c in $$(cat $$f | grep -v ^#); \ + do printf $$(printf '\%o' 0x$$c); \ + done; \ + done > $@ + +cbfs-files-y += spd.bin +spd.bin-file := $(SPD_BIN) +spd.bin-type := 0xab +# WIV20141001 END ADD SPD FROM FILE diff --git a/src/mainboard/pcengines/apu2/OptionsIds.h b/src/mainboard/pcengines/apu2/OptionsIds.h new file mode 100644 index 0000000..d1d3dab --- /dev/null +++ b/src/mainboard/pcengines/apu2/OptionsIds.h @@ -0,0 +1,68 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/** + * @file + * + * IDS Option File + * + * This file is used to switch on/off IDS features. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: Core + * @e \$Revision: 12067 $ @e \$Date: 2009-04-11 04:34:13 +0800 (Sat, 11 Apr 2009) $ + */ +#ifndef _OPTION_IDS_H_ +#define _OPTION_IDS_H_ + +/** + * + * This file generates the defaults tables for the Integrated Debug Support + * Module. The documented build options are imported from a user controlled + * file for processing. The build options for the Integrated Debug Support + * Module are listed below: + * + * IDSOPT_IDS_ENABLED + * IDSOPT_ERROR_TRAP_ENABLED + * IDSOPT_CONTROL_ENABLED + * IDSOPT_TRACING_ENABLED + * IDSOPT_PERF_ANALYSIS + * IDSOPT_ASSERT_ENABLED + * IDS_DEBUG_PORT + * IDSOPT_CAR_CORRUPTION_CHECK_ENABLED + * + **/ + +//#define IDSOPT_IDS_ENABLED TRUE +//#define IDSOPT_CONTROL_ENABLED TRUE + +//#define IDSOPT_TRACING_ENABLED TRUE +//#define IDS_DEBUG_PRINT_MASK (GNB_TRACE_DEFAULT | CPU_TRACE_ALL | MEM_FLOW | MEM_STATUS | TOPO_TRACE_ALL | FCH_TRACE_ALL | MAIN_FLOW | IDS_TRACE_DEFAULT | TEST_POINT) +//#define IDS_DEBUG_PRINT_MASK (FCH_TRACE_ALL) // We just want to see the FCH stuff now +//#define IDSOPT_TRACING_CONSOLE_SERIALPORT TRUE +//#define IDSOPT_TRACING_CONSOLE_REDIRECT_IO TRUE + +//#define IDSOPT_PERF_ANALYSIS TRUE +//#define IDSOPT_ASSERT_ENABLED TRUE +//#undef IDSOPT_DEBUG_ENABLED +//#define IDSOPT_DEBUG_ENABLED FALSE +//#undef IDSOPT_HOST_SIMNOW +//#define IDSOPT_HOST_SIMNOW FALSE +//#undef IDSOPT_HOST_HDT +//#define IDSOPT_HOST_HDT FALSE +//#define IDS_DEBUG_PORT 0x80 + +#endif diff --git a/src/mainboard/pcengines/apu2/PlatformGnbPcie.c b/src/mainboard/pcengines/apu2/PlatformGnbPcie.c new file mode 100644 index 0000000..284f1c6 --- /dev/null +++ b/src/mainboard/pcengines/apu2/PlatformGnbPcie.c @@ -0,0 +1,122 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <northbridge/amd/pi/agesawrapper.h> + +#define FILECODE PROC_GNB_PCIE_FAMILY_0X15_F15PCIECOMPLEXCONFIG_FILECODE + +const PCIe_PORT_DESCRIPTOR PortList [] = { + { + 0, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array + PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 3, 3), + PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 5, + HotplugDisabled, + PcieGenMaxSupported, + PcieGenMaxSupported, + AspmDisabled, 0x01, 0) + }, + /* Initialize Port descriptor (PCIe port, Lanes 1, PCI Device Number 2, ...) */ + { + 0, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array + PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 2, 2), + PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 4, + HotplugDisabled, + PcieGenMaxSupported, + PcieGenMaxSupported, + AspmDisabled, 0x02, 0) + }, + /* Initialize Port descriptor (PCIe port, Lanes 2, PCI Device Number 2, ...) */ + { + 0, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array + PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 1, 1), + PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 3, + HotplugDisabled, + PcieGenMaxSupported, + PcieGenMaxSupported, + AspmDisabled, 0x03, 0) + }, + /* Initialize Port descriptor (PCIe port, Lanes 3, PCI Device Number 2, ...) */ + { + 0, + PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 0), + PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 2, + HotplugDisabled, + PcieGenMaxSupported, + PcieGenMaxSupported, + AspmDisabled, 0x04, 0) + }, + /* Initialize Port descriptor (PCIe port, Lanes 4-7, PCI Device Number 4, ...) */ + { + DESCRIPTOR_TERMINATE_LIST, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array + PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 7), + PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 1, + HotplugDisabled, + PcieGenMaxSupported, + PcieGenMaxSupported, + AspmDisabled, 0x05, 0) + } +}; + +const PCIe_DDI_DESCRIPTOR DdiList [] = { + /* DP0 to HDMI0/DP */ + { + 0, + PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 8, 11), + PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux1, Hdp1) + }, + /* DP1 to FCH */ + { + 0, + PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 12, 15), + PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux2, Hdp2) + }, + /* DP2 to HDMI1/DP */ + { + DESCRIPTOR_TERMINATE_LIST, + PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 16, 19), + PCIE_DDI_DATA_INITIALIZER (ConnectorTypeCrt, Aux3, Hdp3) + }, +}; + +const PCIe_COMPLEX_DESCRIPTOR PcieComplex = { + .Flags = DESCRIPTOR_TERMINATE_LIST, + .SocketId = 0, + .PciePortList = PortList, + .DdiLinkList = DdiList +}; + +/*---------------------------------------------------------------------------------------*/ +/** + * OemCustomizeInitEarly + * + * Description: + * This stub function will call the host environment through the binary block + * interface (call-out port) to provide a user hook opportunity + * + * Parameters: + * @param[in] **PeiServices + * @param[in] *InitEarly + * + * @retval VOID + * + **/ +/*---------------------------------------------------------------------------------------*/ +VOID +OemCustomizeInitEarly ( + IN OUT AMD_EARLY_PARAMS *InitEarly + ) +{ + InitEarly->GnbConfig.PcieComplexList = &PcieComplex; +} diff --git a/src/mainboard/pcengines/apu2/PlatformGnbPcieComplex.h b/src/mainboard/pcengines/apu2/PlatformGnbPcieComplex.h new file mode 100644 index 0000000..8f49a6d --- /dev/null +++ b/src/mainboard/pcengines/apu2/PlatformGnbPcieComplex.h @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _PLATFORM_GNB_PCIE_COMPLEX_H +#define _PLATFORM_GNB_PCIE_COMPLEX_H + +#include <Porting.h> +#include <AGESA.h> + +VOID +OemCustomizeInitEarly ( + IN OUT AMD_EARLY_PARAMS *InitEarly + ); + +#endif //_PLATFORM_GNB_PCIE_COMPLEX_H diff --git a/src/mainboard/pcengines/apu2/acpi/gpe.asl b/src/mainboard/pcengines/apu2/acpi/gpe.asl new file mode 100644 index 0000000..31b9d0c --- /dev/null +++ b/src/mainboard/pcengines/apu2/acpi/gpe.asl @@ -0,0 +1,80 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Scope(\_GPE) { /* Start Scope GPE */ + + /* General event 3 */ + Method(_L03) { + /* DBGO("\\_GPE\\_L00\n") */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } + + /* Legacy PM event */ + Method(_L08) { + /* DBGO("\\_GPE\\_L08\n") */ + } + + /* Temp warning (TWarn) event */ + Method(_L09) { + /* DBGO("\\_GPE\\_L09\n") */ + /* Notify (\_TZ.TZ00, 0x80) */ + } + + /* USB controller PME# */ + Method(_L0B) { + /* DBGO("\\_GPE\\_L0B\n") */ + Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */ +#if !CONFIG_SOUTHBRIDGE_AMD_AGESA_AVALON && !CONFIG_SOUTHBRIDGE_AMD_PI_AVALON + Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */ +#endif //!CONFIG_SOUTHBRIDGE_AMD_AGESA_AVALON AND !CONFIG_SOUTHBRIDGE_AMD_PI_AVALON + Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */ +#if !CONFIG_SOUTHBRIDGE_AMD_AGESA_AVALON && !CONFIG_SOUTHBRIDGE_AMD_PI_AVALON + Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */ +#endif //!CONFIG_SOUTHBRIDGE_AMD_AGESA_AVALON AND !CONFIG_SOUTHBRIDGE_AMD_PI_AVALON + Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */ +#if !CONFIG_SOUTHBRIDGE_AMD_AGESA_AVALON && !CONFIG_SOUTHBRIDGE_AMD_PI_AVALON + Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */ +#endif //!CONFIG_SOUTHBRIDGE_AMD_AGESA_AVALON && !CONFIG_SOUTHBRIDGE_AMD_PI_AVALON + Notify(\_SB.PCI0.XHC0, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } + + /* ExtEvent0 SCI event */ + Method(_L10) { + /* DBGO("\\_GPE\\_L10\n") */ + } + + /* ExtEvent1 SCI event */ + Method(_L11) { + /* DBGO("\\_GPE\\_L11\n") */ + } + + /* GPIO0 or GEvent8 event */ + Method(_L18) { + /* DBGO("\\_GPE\\_L18\n") */ + Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } + +// /* Azalia SCI event */ +// Method(_L1B) { +// /* DBGO("\\_GPE\\_L1B\n") */ +// Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */ +// Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ +// } +} /* End Scope GPE */ diff --git a/src/mainboard/pcengines/apu2/acpi/ide.asl b/src/mainboard/pcengines/apu2/acpi/ide.asl new file mode 100644 index 0000000..95d1db4 --- /dev/null +++ b/src/mainboard/pcengines/apu2/acpi/ide.asl @@ -0,0 +1 @@ +/* No IDE functionality */ diff --git a/src/mainboard/pcengines/apu2/acpi/mainboard.asl b/src/mainboard/pcengines/apu2/acpi/mainboard.asl new file mode 100644 index 0000000..0141481 --- /dev/null +++ b/src/mainboard/pcengines/apu2/acpi/mainboard.asl @@ -0,0 +1,37 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* Memory related values */ +Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */ +Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */ +Name(PBLN, 0x0) /* Length of BIOS area */ + +Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */ +Name(PCLN, Multiply(0x100000, CONFIG_MMCONF_BUS_NUMBER)) /* Length of PCIe config space, 1MB each bus */ +Name(HPBA, 0xFED00000) /* Base address of HPET table */ + +Name(SSFG, 0x0D) /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */ + +/* Some global data */ +Name(OSVR, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */ +Name(OSV, Ones) /* Assume nothing */ +Name(PMOD, One) /* Assume APIC */ + +/* AcpiGpe0Blk */ +OperationRegion(GP0B, SystemMemory, 0xfed80814, 0x04) + Field(GP0B, ByteAcc, NoLock, Preserve) { + , 11, + USBS, 1, +} diff --git a/src/mainboard/pcengines/apu2/acpi/pci_int.asl b/src/mainboard/pcengines/apu2/acpi/pci_int.asl new file mode 100644 index 0000000..1dcb255 --- /dev/null +++ b/src/mainboard/pcengines/apu2/acpi/pci_int.asl @@ -0,0 +1,471 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + /* PCIe Configuration Space for CONFIG_MMCONF_BUS_NUMBER busses */ + OperationRegion(PCFG, SystemMemory, PCBA, PCLN) /* Each bus consumes 1MB */ + Field(PCFG, ByteAcc, NoLock, Preserve) { + /* Byte offsets are computed using the following technique: + * ((bus number + 1) * ((device number * 8) * 4096)) + register offset + * The 8 comes from 8 functions per device, and 4096 bytes per function config space + */ + Offset(0x00088024), /* Byte offset to SATA register 24h - Bus 0, Device 17, Function 0 */ + STB5, 32, + Offset(0x00098042), /* Byte offset to OHCI0 register 42h - Bus 0, Device 19, Function 0 */ + PT0D, 1, + PT1D, 1, + PT2D, 1, + PT3D, 1, + PT4D, 1, + PT5D, 1, + PT6D, 1, + PT7D, 1, + PT8D, 1, + PT9D, 1, + Offset(0x000A0004), /* Byte offset to SMBUS register 4h - Bus 0, Device 20, Function 0 */ + SBIE, 1, + SBME, 1, + Offset(0x000A0008), /* Byte offset to SMBUS register 8h - Bus 0, Device 20, Function 0 */ + SBRI, 8, + Offset(0x000A0014), /* Byte offset to SMBUS register 14h - Bus 0, Device 20, Function 0 */ + SBB1, 32, + Offset(0x000A0078), /* Byte offset to SMBUS register 78h - Bus 0, Device 20, Function 0 */ + ,14, + P92E, 1, /* Port92 decode enable */ + } + + OperationRegion(SB5, SystemMemory, STB5, 0x1000) + Field(SB5, AnyAcc, NoLock, Preserve){ + /* Port 0 */ + Offset(0x120), /* Port 0 Task file status */ + P0ER, 1, + , 2, + P0DQ, 1, + , 3, + P0BY, 1, + Offset(0x128), /* Port 0 Serial ATA status */ + P0DD, 4, + , 4, + P0IS, 4, + Offset(0x12C), /* Port 0 Serial ATA control */ + P0DI, 4, + Offset(0x130), /* Port 0 Serial ATA error */ + , 16, + P0PR, 1, + + /* Port 1 */ + offset(0x1A0), /* Port 1 Task file status */ + P1ER, 1, + , 2, + P1DQ, 1, + , 3, + P1BY, 1, + Offset(0x1A8), /* Port 1 Serial ATA status */ + P1DD, 4, + , 4, + P1IS, 4, + Offset(0x1AC), /* Port 1 Serial ATA control */ + P1DI, 4, + Offset(0x1B0), /* Port 1 Serial ATA error */ + , 16, + P1PR, 1, + + /* Port 2 */ + Offset(0x220), /* Port 2 Task file status */ + P2ER, 1, + , 2, + P2DQ, 1, + , 3, + P2BY, 1, + Offset(0x228), /* Port 2 Serial ATA status */ + P2DD, 4, + , 4, + P2IS, 4, + Offset(0x22C), /* Port 2 Serial ATA control */ + P2DI, 4, + Offset(0x230), /* Port 2 Serial ATA error */ + , 16, + P2PR, 1, + + /* Port 3 */ + Offset(0x2A0), /* Port 3 Task file status */ + P3ER, 1, + , 2, + P3DQ, 1, + , 3, + P3BY, 1, + Offset(0x2A8), /* Port 3 Serial ATA status */ + P3DD, 4, + , 4, + P3IS, 4, + Offset(0x2AC), /* Port 3 Serial ATA control */ + P3DI, 4, + Offset(0x2B0), /* Port 3 Serial ATA error */ + , 16, + P3PR, 1, + } + + Method(_PIC, 0x01, NotSerialized) + { + If (Arg0) + { + \_SB.CIRQ() + } + Store(Arg0, PMOD) + } + + Method(CIRQ, 0x00, NotSerialized){ + } + + Name(IRQB, ResourceTemplate(){ + IRQ(Level,ActiveLow,Shared){15} + }) + + Name(IRQP, ResourceTemplate(){ + /* IRQ(Level,ActiveLow,Exclusive){3, 4, 5, 7, 10, 11, 12, 15} */ + IRQ(Level,ActiveLow,Exclusive){3, 5, 7, 10, 11, 12, 15} + }) + + Name(PITF, ResourceTemplate(){ + IRQ(Level,ActiveLow,Exclusive){9} + }) + + Device(INTA) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 1) + + Method(_STA, 0) { + if (PIRA) { + Return(0x0B) /* sata is invisible */ + } else { + Return(0x09) /* sata is disabled */ + } + } /* End Method(_SB.INTA._STA) */ + + Method(_DIS ,0) { + /* DBGO("\\_SB\\LNKA\\_DIS\n") */ + } /* End Method(_SB.INTA._DIS) */ + + Method(_PRS ,0) { + /* DBGO("\\_SB\\LNKA\\_PRS\n") */ + Return(IRQP) + } /* Method(_SB.INTA._PRS) */ + + Method(_CRS ,0) { + /* DBGO("\\_SB\\LNKA\\_CRS\n") */ + CreateWordField(IRQB, 0x1, IRQN) + ShiftLeft(1, PIRA, IRQN) + Return(IRQB) + } /* Method(_SB.INTA._CRS) */ + + Method(_SRS, 1) { + /* DBGO("\\_SB\\LNKA\\_SRS\n") */ + CreateWordField(ARG0, 1, IRQM) + + /* Use lowest available IRQ */ + FindSetRightBit(IRQM, Local0) + if (Local0) { + Decrement(Local0) + } + Store(Local0, PIRA) + } /* End Method(_SB.INTA._SRS) */ + } /* End Device(INTA) */ + + Device(INTB) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 2) + + Method(_STA, 0) { + if (PIRB) { + Return(0x0B) /* sata is invisible */ + } else { + Return(0x09) /* sata is disabled */ + } + } /* End Method(_SB.INTB._STA) */ + + Method(_DIS ,0) { + /* DBGO("\\_SB\\LNKB\\_DIS\n") */ + } /* End Method(_SB.INTB._DIS) */ + + Method(_PRS ,0) { + /* DBGO("\\_SB\\LNKB\\_PRS\n") */ + Return(IRQP) + } /* Method(_SB.INTB._PRS) */ + + Method(_CRS ,0) { + /* DBGO("\\_SB\\LNKB\\_CRS\n") */ + CreateWordField(IRQB, 0x1, IRQN) + ShiftLeft(1, PIRB, IRQN) + Return(IRQB) + } /* Method(_SB.INTB._CRS) */ + + Method(_SRS, 1) { + /* DBGO("\\_SB\\LNKB\\_CRS\n") */ + CreateWordField(ARG0, 1, IRQM) + + /* Use lowest available IRQ */ + FindSetRightBit(IRQM, Local0) + if (Local0) { + Decrement(Local0) + } + Store(Local0, PIRB) + } /* End Method(_SB.INTB._SRS) */ + } /* End Device(INTB) */ + + Device(INTC) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 3) + + Method(_STA, 0) { + if (PIRC) { + Return(0x0B) /* sata is invisible */ + } else { + Return(0x09) /* sata is disabled */ + } + } /* End Method(_SB.INTC._STA) */ + + Method(_DIS ,0) { + /* DBGO("\\_SB\\LNKC\\_DIS\n") */ + } /* End Method(_SB.INTC._DIS) */ + + Method(_PRS ,0) { + /* DBGO("\\_SB\\LNKC\\_PRS\n") */ + Return(IRQP) + } /* Method(_SB.INTC._PRS) */ + + Method(_CRS ,0) { + /* DBGO("\\_SB\\LNKC\\_CRS\n") */ + CreateWordField(IRQB, 0x1, IRQN) + ShiftLeft(1, PIRC, IRQN) + Return(IRQB) + } /* Method(_SB.INTC._CRS) */ + + Method(_SRS, 1) { + /* DBGO("\\_SB\\LNKC\\_CRS\n") */ + CreateWordField(ARG0, 1, IRQM) + + /* Use lowest available IRQ */ + FindSetRightBit(IRQM, Local0) + if (Local0) { + Decrement(Local0) + } + Store(Local0, PIRC) + } /* End Method(_SB.INTC._SRS) */ + } /* End Device(INTC) */ + + Device(INTD) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 4) + + Method(_STA, 0) { + if (PIRD) { + Return(0x0B) /* sata is invisible */ + } else { + Return(0x09) /* sata is disabled */ + } + } /* End Method(_SB.INTD._STA) */ + + Method(_DIS ,0) { + /* DBGO("\\_SB\\LNKD\\_DIS\n") */ + } /* End Method(_SB.INTD._DIS) */ + + Method(_PRS ,0) { + /* DBGO("\\_SB\\LNKD\\_PRS\n") */ + Return(IRQP) + } /* Method(_SB.INTD._PRS) */ + + Method(_CRS ,0) { + /* DBGO("\\_SB\\LNKD\\_CRS\n") */ + CreateWordField(IRQB, 0x1, IRQN) + ShiftLeft(1, PIRD, IRQN) + Return(IRQB) + } /* Method(_SB.INTD._CRS) */ + + Method(_SRS, 1) { + /* DBGO("\\_SB\\LNKD\\_CRS\n") */ + CreateWordField(ARG0, 1, IRQM) + + /* Use lowest available IRQ */ + FindSetRightBit(IRQM, Local0) + if (Local0) { + Decrement(Local0) + } + Store(Local0, PIRD) + } /* End Method(_SB.INTD._SRS) */ + } /* End Device(INTD) */ + + Device(INTE) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 5) + + Method(_STA, 0) { + if (PIRE) { + Return(0x0B) /* sata is invisible */ + } else { + Return(0x09) /* sata is disabled */ + } + } /* End Method(_SB.INTE._STA) */ + + Method(_DIS ,0) { + /* DBGO("\\_SB\\LNKE\\_DIS\n") */ + } /* End Method(_SB.INTE._DIS) */ + + Method(_PRS ,0) { + /* DBGO("\\_SB\\LNKE\\_PRS\n") */ + Return(IRQP) + } /* Method(_SB.INTE._PRS) */ + + Method(_CRS ,0) { + /* DBGO("\\_SB\\LNKE\\_CRS\n") */ + CreateWordField(IRQB, 0x1, IRQN) + ShiftLeft(1, PIRE, IRQN) + Return(IRQB) + } /* Method(_SB.INTE._CRS) */ + + Method(_SRS, 1) { + /* DBGO("\\_SB\\LNKE\\_CRS\n") */ + CreateWordField(ARG0, 1, IRQM) + + /* Use lowest available IRQ */ + FindSetRightBit(IRQM, Local0) + if (Local0) { + Decrement(Local0) + } + Store(Local0, PIRE) + } /* End Method(_SB.INTE._SRS) */ + } /* End Device(INTE) */ + + Device(INTF) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 6) + + Method(_STA, 0) { + if (PIRF) { + Return(0x0B) /* sata is invisible */ + } else { + Return(0x09) /* sata is disabled */ + } + } /* End Method(_SB.INTF._STA) */ + + Method(_DIS ,0) { + /* DBGO("\\_SB\\LNKF\\_DIS\n") */ + } /* End Method(_SB.INTF._DIS) */ + + Method(_PRS ,0) { + /* DBGO("\\_SB\\LNKF\\_PRS\n") */ + Return(IRQP) +// Return(PITF) + } /* Method(_SB.INTF._PRS) */ + + Method(_CRS ,0) { + /* DBGO("\\_SB\\LNKF\\_CRS\n") */ + CreateWordField(IRQB, 0x1, IRQN) + ShiftLeft(1, PIRF, IRQN) + Return(IRQB) + } /* Method(_SB.INTF._CRS) */ + + Method(_SRS, 1) { + /* DBGO("\\_SB\\LNKF\\_CRS\n") */ + CreateWordField(ARG0, 1, IRQM) + + /* Use lowest available IRQ */ + FindSetRightBit(IRQM, Local0) + if (Local0) { + Decrement(Local0) + } + Store(Local0, PIRF) + } /* End Method(_SB.INTF._SRS) */ + } /* End Device(INTF) */ + +// Device(INTG) { +// Name(_HID, EISAID("PNP0C0F")) +// Name(_UID, 7) +// +// Method(_STA, 0) { +// if (PIRG) { +// Return(0x0B) /* sata is invisible */ +// } else { +// Return(0x09) /* sata is disabled */ +// } +// } /* End Method(_SB.INTG._STA) */ +// +// Method(_DIS ,0) { +// /* DBGO("\\_SB\\LNKG\\_DIS\n") */ +// } /* End Method(_SB.INTG._DIS) */ +// +// Method(_PRS ,0) { +// /* DBGO("\\_SB\\LNKG\\_PRS\n") */ +// Return(IRQP) +// } /* Method(_SB.INTG._CRS) */ +// +// Method(_CRS ,0) { +// /* DBGO("\\_SB\\LNKG\\_CRS\n") */ +// CreateWordField(IRQB, 0x1, IRQN) +// ShiftLeft(1, PIRG, IRQN) +// Return(IRQB) +// } /* Method(_SB.INTG._CRS) */ +// +// Method(_SRS, 1) { +// /* DBGO("\\_SB\\LNKG\\_CRS\n") */ +// CreateWordField(ARG0, 1, IRQM) +// +// /* Use lowest available IRQ */ +// FindSetRightBit(IRQM, Local0) +// if (Local0) { +// Decrement(Local0) +// } +// Store(Local0, PIRG) +// } /* End Method(_SB.INTG._SRS) */ +// } /* End Device(INTG) */ +// +// Device(INTH) { +// Name(_HID, EISAID("PNP0C0F")) +// Name(_UID, 8) +// +// Method(_STA, 0) { +// if (PIRH) { +// Return(0x0B) /* sata is invisible */ +// } else { +// Return(0x09) /* sata is disabled */ +// } +// } /* End Method(_SB.INTH._STA) */ +// +// Method(_DIS ,0) { +// /* DBGO("\\_SB\\LNKH\\_DIS\n") */ +// } /* End Method(_SB.INTH._DIS) */ +// +// Method(_PRS ,0) { +// /* DBGO("\\_SB\\LNKH\\_PRS\n") */ +// Return(IRQP) +// } /* Method(_SB.INTH._CRS) */ +// +// Method(_CRS ,0) { +// /* DBGO("\\_SB\\LNKH\\_CRS\n") */ +// CreateWordField(IRQB, 0x1, IRQN) +// ShiftLeft(1, PIRH, IRQN) +// Return(IRQB) +// } /* Method(_SB.INTH._CRS) */ +// +// Method(_SRS, 1) { +// /* DBGO("\\_SB\\LNKH\\_CRS\n") */ +// CreateWordField(ARG0, 1, IRQM) +// +// /* Use lowest available IRQ */ +// FindSetRightBit(IRQM, Local0) +// if (Local0) { +// Decrement(Local0) +// } +// Store(Local0, PIRH) +// } /* End Method(_SB.INTH._SRS) */ +// } /* End Device(INTH) */ diff --git a/src/mainboard/pcengines/apu2/acpi/routing.asl b/src/mainboard/pcengines/apu2/acpi/routing.asl new file mode 100644 index 0000000..37c01d0 --- /dev/null +++ b/src/mainboard/pcengines/apu2/acpi/routing.asl @@ -0,0 +1,213 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Advanced Micro Devices, Inc. + * Copyright (C) 2013 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* +DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001 + ) + { + #include "routing.asl" + } +*/ + +/* Routing is in System Bus scope */ +Name(PR0, Package(){ + /* NB devices */ + /* Bus 0, Dev 0 - F16 Host Controller */ + + /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */ + /* Bus 0, Dev 1, Func 1 - HDMI Audio Controller */ + Package(){0x0001FFFF, 0, INTB, 0 }, + Package(){0x0001FFFF, 1, INTC, 0 }, + + + /* Bus 0, Dev 2 Func 0,1,2,3,4,5 - PCIe Bridges */ + Package(){0x0002FFFF, 0, INTC, 0 }, + Package(){0x0002FFFF, 1, INTD, 0 }, + Package(){0x0002FFFF, 2, INTA, 0 }, + Package(){0x0002FFFF, 3, INTB, 0 }, + + /* FCH devices */ + /* Bus 0, Dev 20 - F0:SMBus/ACPI,F2:HDAudio;F3:LPC;F7:SD */ + Package(){0x0014FFFF, 0, INTA, 0 }, + Package(){0x0014FFFF, 1, INTB, 0 }, + Package(){0x0014FFFF, 2, INTC, 0 }, + Package(){0x0014FFFF, 3, INTD, 0 }, + +#if CONFIG_SOUTHBRIDGE_AMD_AGESA_AVALON || CONFIG_SOUTHBRIDGE_AMD_PI_AVALON + + /* Bus 0, Dev 18, 19, 22 Func 0 - USB: EHCI */ + Package(){0x0012FFFF, 0, INTC, 0 }, + Package(){0x0013FFFF, 0, INTC, 0 }, + Package(){0x0016FFFF, 0, INTC, 0 }, + +#else // CONFIG_SOUTHBRIDGE_AMD_AGESA_AVALON OR CONFIG_SOUTHBRIDGE_AMD_PI_AVALON + + /* Bus 0, Dev 18, 19, 22 Func 0 - USB: OHCI */ + /* Bus 0, Dev 18, 19, 22 Func 1 - USB: EHCI */ + Package(){0x0012FFFF, 0, INTC, 0 }, + Package(){0x0012FFFF, 1, INTB, 0 }, + + Package(){0x0013FFFF, 0, INTC, 0 }, + Package(){0x0013FFFF, 1, INTB, 0 }, + + Package(){0x0016FFFF, 0, INTC, 0 }, + Package(){0x0016FFFF, 1, INTB, 0 }, +#endif //CONFIG_SOUTHBRIDGE_AMD_AGESA_AVALON OR CONFIG_SOUTHBRIDGE_AMD_PI_AVALON + + /* Bus 0, Dev 10 - USB: XHCI func 0, 1 */ + Package(){0x0010FFFF, 0, INTC, 0 }, + Package(){0x0010FFFF, 1, INTB, 0 }, + + /* Bus 0, Dev 17 - SATA controller */ + Package(){0x0011FFFF, 0, INTD, 0 }, + +}) + +Name(APR0, Package(){ + /* NB devices in APIC mode */ + /* Bus 0, Dev 0 - F15 Host Controller */ + + /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */ + Package(){0x0001FFFF, 0, 0, 44 }, + Package(){0x0001FFFF, 1, 0, 45 }, + + /* Bus 0, Dev 2 - PCIe Bridges */ + Package(){0x0002FFFF, 0, 0, 24 }, + Package(){0x0002FFFF, 1, 0, 25 }, + Package(){0x0002FFFF, 2, 0, 26 }, + Package(){0x0002FFFF, 3, 0, 27 }, + + + /* SB devices in APIC mode */ + /* Bus 0, Dev 20 - F0:SMBus/ACPI,F2:HDAudio;F3:LPC;F7:SD */ + Package(){0x0014FFFF, 0, 0, 16 }, + Package(){0x0014FFFF, 1, 0, 17 }, + Package(){0x0014FFFF, 2, 0, 18 }, + Package(){0x0014FFFF, 3, 0, 19 }, +#if CONFIG_SOUTHBRIDGE_AMD_AGESA_AVALON || CONFIG_SOUTHBRIDGE_AMD_PI_AVALON + + /* Bus 0, Dev 18, 19, 22 Func 0 - USB: EHCI */ + + Package(){0x0012FFFF, 0, 0, 18 }, + Package(){0x0013FFFF, 0, 0, 18 }, + Package(){0x0016FFFF, 0, 0, 18 }, + +#else //CONFIG_SOUTHBRIDGE_AMD_AGESA_AVALON OR CONFIG_SOUTHBRIDGE_AMD_PI_AVALON + + /* Bus 0, Dev 18, 19, 22 Func 0 - USB: OHCI */ + /* Bus 0, Dev 18, 19, 22 Func 1 - USB: EHCI */ + Package(){0x0012FFFF, 0, 0, 18 }, + Package(){0x0012FFFF, 1, 0, 17 }, + + Package(){0x0013FFFF, 0, 0, 18 }, + Package(){0x0013FFFF, 1, 0, 17 }, + + Package(){0x0016FFFF, 0, 0, 18 }, + Package(){0x0016FFFF, 1, 0, 17 }, +#endif //CONFIG_SOUTHBRIDGE_AMD_AGESA_AVALON OR CONFIG_SOUTHBRIDGE_AMD_PI_AVALON + + /* Bus 0, Dev 10 - USB: XHCI func 0, 1 */ + Package(){0x0010FFFF, 0, 0, 0x12}, + Package(){0x0010FFFF, 1, 0, 0x11}, + + /* Bus 0, Dev 17 - SATA controller */ + Package(){0x0011FFFF, 0, 0, 19 }, + +}) + +Name(PS2, Package(){ + Package(){0x0000FFFF, 0, INTC, 0 }, + Package(){0x0000FFFF, 1, INTD, 0 }, + Package(){0x0000FFFF, 2, INTA, 0 }, + Package(){0x0000FFFF, 3, INTB, 0 }, +}) +Name(APS2, Package(){ + Package(){0x0000FFFF, 0, 0, 18 }, + Package(){0x0000FFFF, 1, 0, 19 }, + Package(){0x0000FFFF, 2, 0, 16 }, + Package(){0x0000FFFF, 3, 0, 17 }, +}) + +/* GFX */ +Name(PS4, Package(){ + Package(){0x0000FFFF, 0, INTA, 0 }, + Package(){0x0000FFFF, 1, INTB, 0 }, + Package(){0x0000FFFF, 2, INTC, 0 }, + Package(){0x0000FFFF, 3, INTD, 0 }, +}) +Name(APS4, Package(){ + /* PCIe slot - Hooked to PCIe slot 4 */ + Package(){0x0000FFFF, 0, 0, 24 }, + Package(){0x0000FFFF, 1, 0, 25 }, + Package(){0x0000FFFF, 2, 0, 26 }, + Package(){0x0000FFFF, 3, 0, 27 }, +}) + +/* GPP 0 */ +Name(PS5, Package(){ + Package(){0x0000FFFF, 0, INTB, 0 }, + Package(){0x0000FFFF, 1, INTC, 0 }, + Package(){0x0000FFFF, 2, INTD, 0 }, + Package(){0x0000FFFF, 3, INTA, 0 }, +}) +Name(APS5, Package(){ + Package(){0x0000FFFF, 0, 0, 28 }, + Package(){0x0000FFFF, 1, 0, 29 }, + Package(){0x0000FFFF, 2, 0, 30 }, + Package(){0x0000FFFF, 3, 0, 31 }, +}) + +/* GPP 1 */ +Name(PS6, Package(){ + Package(){0x0000FFFF, 0, INTC, 0 }, + Package(){0x0000FFFF, 1, INTD, 0 }, + Package(){0x0000FFFF, 2, INTA, 0 }, + Package(){0x0000FFFF, 3, INTB, 0 }, +}) +Name(APS6, Package(){ + Package(){0x0000FFFF, 0, 0, 32 }, + Package(){0x0000FFFF, 1, 0, 33 }, + Package(){0x0000FFFF, 2, 0, 34 }, + Package(){0x0000FFFF, 3, 0, 35 }, +}) + +/* GPP 2 */ +Name(PS7, Package(){ + Package(){0x0000FFFF, 0, INTD, 0 }, + Package(){0x0000FFFF, 1, INTA, 0 }, + Package(){0x0000FFFF, 2, INTB, 0 }, + Package(){0x0000FFFF, 3, INTC, 0 }, +}) +Name(APS7, Package(){ + Package(){0x0000FFFF, 0, 0, 36 }, + Package(){0x0000FFFF, 1, 0, 37 }, + Package(){0x0000FFFF, 2, 0, 38 }, + Package(){0x0000FFFF, 3, 0, 39 }, +}) + +/* GPP 3 */ +Name(PS8, Package(){ + Package(){0x0000FFFF, 0, INTA, 0 }, + Package(){0x0000FFFF, 1, INTB, 0 }, + Package(){0x0000FFFF, 2, INTC, 0 }, + Package(){0x0000FFFF, 3, INTD, 0 }, +}) +Name(APS8, Package(){ + Package(){0x0000FFFF, 0, 0, 40 }, + Package(){0x0000FFFF, 1, 0, 41 }, + Package(){0x0000FFFF, 2, 0, 42 }, + Package(){0x0000FFFF, 3, 0, 43 }, +}) diff --git a/src/mainboard/pcengines/apu2/acpi/sata.asl b/src/mainboard/pcengines/apu2/acpi/sata.asl new file mode 100644 index 0000000..f675323 --- /dev/null +++ b/src/mainboard/pcengines/apu2/acpi/sata.asl @@ -0,0 +1 @@ +/* No SATA functionality */ diff --git a/src/mainboard/pcengines/apu2/acpi/si.asl b/src/mainboard/pcengines/apu2/acpi/si.asl new file mode 100644 index 0000000..2923471 --- /dev/null +++ b/src/mainboard/pcengines/apu2/acpi/si.asl @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Scope(\_SI) { + Method(_SST, 1) { + /* DBGO("\\_SI\\_SST\n") */ + /* DBGO(" New Indicator state: ") */ + /* DBGO(Arg0) */ + /* DBGO("\n") */ + } +} /* End Scope SI */ diff --git a/src/mainboard/pcengines/apu2/acpi/sleep.asl b/src/mainboard/pcengines/apu2/acpi/sleep.asl new file mode 100644 index 0000000..4460aed --- /dev/null +++ b/src/mainboard/pcengines/apu2/acpi/sleep.asl @@ -0,0 +1,93 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* Wake status package */ +Name(WKST,Package(){Zero, Zero}) + +/* +* \_PTS - Prepare to Sleep method +* +* Entry: +* Arg0=The value of the sleeping state S1=1, S2=2, etc +* +*s Exit: +* -none- +* +* The _PTS control method is executed at the beginning of the sleep process +* for S1-S5. The sleeping value is passed to the _PTS control method. This +* control method may be executed a relatively long time before entering the +* sleep state and the OS may abort the operation without notification to +* the ACPI driver. This method cannot modify the configuration or power +* state of any device in the system. +*/ + +External(\_SB.APTS, MethodObj) +External(\_SB.AWAK, MethodObj) + +Method(_PTS, 1) { + /* DBGO("\\_PTS\n") */ + /* DBGO("From S0 to S") */ + /* DBGO(Arg0) */ + /* DBGO("\n") */ + + /* Clear wake status structure. */ + Store(0, Index(WKST,0)) + Store(0, Index(WKST,1)) + Store(7, UPWS) + \_SB.APTS(Arg0) +} /* End Method(\_PTS) */ + +/* +* \_BFS OEM Back From Sleep method +* +* Entry: +* Arg0=The value of the sleeping state S1=1, S2=2 +* +* Exit: +* -none- +*/ +Method(\_BFS, 1) { + /* DBGO("\\_BFS\n") */ + /* DBGO("From S") */ + /* DBGO(Arg0) */ + /* DBGO(" to S0\n") */ +} + +/* +* \_WAK System Wake method +* +* Entry: +* Arg0=The value of the sleeping state S1=1, S2=2 +* +* Exit: +* Return package of 2 DWords +* Dword 1 - Status +* 0x00000000 wake succeeded +* 0x00000001 Wake was signaled but failed due to lack of power +* 0x00000002 Wake was signaled but failed due to thermal condition +* Dword 2 - Power Supply state +* if non-zero the effective S-state the power supply entered +*/ +Method(\_WAK, 1) { + /* DBGO("\\_WAK\n") */ + /* DBGO("From S") */ + /* DBGO(Arg0) */ + /* DBGO(" to S0\n") */ + Store(1,USBS) + + \_SB.AWAK(Arg0) + + Return(WKST) +} /* End Method(\_WAK) */ diff --git a/src/mainboard/pcengines/apu2/acpi/superio.asl b/src/mainboard/pcengines/apu2/acpi/superio.asl new file mode 100644 index 0000000..be62853 --- /dev/null +++ b/src/mainboard/pcengines/apu2/acpi/superio.asl @@ -0,0 +1,28 @@ +/* We don't have a real SIO but lets define the serial port here, this is where it belongs */ + + Device (COM1) { + Name (_HID, EISAID ("PNP0501")) + Name (_UID, 1) + Name (_ADR, 0) + + Method (_STA, 0, NotSerialized) { + Return (0x0F) + } + + Name (_CRS, ResourceTemplate () + { + IO (Decode16, 0x03F8, 0x3F8, 0x08, 0x08) + IRQNoFlags () {4} +// IRQNoFlags () {} + }) + + Name (_PRS, ResourceTemplate () + { + StartDependentFn (0, 0) { + IO (Decode16, 0x03F8, 0x3F8, 0x08, 0x08) +// IRQNoFlags () {4} + IRQNoFlags () {} + } + EndDependentFn () + }) + } diff --git a/src/mainboard/pcengines/apu2/acpi/thermal.asl b/src/mainboard/pcengines/apu2/acpi/thermal.asl new file mode 100644 index 0000000..edb1daf --- /dev/null +++ b/src/mainboard/pcengines/apu2/acpi/thermal.asl @@ -0,0 +1 @@ +/* No thermal zone functionality */ diff --git a/src/mainboard/pcengines/apu2/acpi/usb_oc.asl b/src/mainboard/pcengines/apu2/acpi/usb_oc.asl new file mode 100644 index 0000000..1643fe7 --- /dev/null +++ b/src/mainboard/pcengines/apu2/acpi/usb_oc.asl @@ -0,0 +1,36 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * Copyright (C) 2013 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* simple name description */ +/* +DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001 + ) + { + #include "usb.asl" + } +*/ + +/* USB overcurrent mapping pins. */ +Name(UOM0, 0) +Name(UOM1, 2) +Name(UOM2, 0) +Name(UOM3, 7) +Name(UOM4, 2) +Name(UOM5, 2) +Name(UOM6, 6) +Name(UOM7, 2) +Name(UOM8, 6) +Name(UOM9, 6) diff --git a/src/mainboard/pcengines/apu2/acpi_tables.c b/src/mainboard/pcengines/apu2/acpi_tables.c new file mode 100644 index 0000000..84a33f8 --- /dev/null +++ b/src/mainboard/pcengines/apu2/acpi_tables.c @@ -0,0 +1,276 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <northbridge/amd/pi/agesawrapper.h> + +#include <console/console.h> +#include <string.h> +#include <arch/acpi.h> +#include <arch/acpigen.h> +#include <arch/ioapic.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <cpu/x86/msr.h> +#include <cpu/amd/mtrr.h> +#include <cpu/amd/amdfam16.h> + +unsigned long acpi_fill_madt(unsigned long current) +{ + /* create all subtables for processors */ + current = acpi_create_madt_lapics(current); + + /* Write SB800 IOAPIC, only one */ + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, CONFIG_MAX_CPUS, + IO_APIC_ADDR, 0); + + /* TODO: Remove the hardcode */ + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, CONFIG_MAX_CPUS+1, + 0xFEC20000, 24); + + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 0, 2, 0); + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 9, 9, 0xF); + /* 0: mean bus 0--->ISA */ + /* 0: PIC 0 */ + /* 2: APIC 2 */ + /* 5 mean: 0101 --> Edge-triggered, Active high */ + + /* create all subtables for processors */ + current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, 0xff, 5, 1); + /* 1: LINT1 connect to NMI */ + + return current; +} + +#if FALSE +unsigned long acpi_fill_hest(acpi_hest_t *hest) +{ + void *addr, *current; + + /* Skip the HEST header. */ + current = (void *)(hest + 1); + + addr = agesawrapper_getlateinitptr(PICK_WHEA_MCE); + if (addr != NULL) + current += acpi_create_hest_error_source(hest, current, 0, (void *)((u32)addr + 2), *(UINT16 *)addr - 2); + + addr = agesawrapper_getlateinitptr(PICK_WHEA_CMC); + if (addr != NULL) + current += acpi_create_hest_error_source(hest, current, 1, (void *)((u32)addr + 2), *(UINT16 *)addr - 2); + + return (unsigned long)current; +} + +unsigned long acpi_fill_slit(unsigned long current) +{ + /* Not implemented */ + return current; +} + +unsigned long acpi_fill_srat(unsigned long current) +{ + /* No NUMA, no SRAT */ + return current; +} + +unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id) +{ + int lens; + msr_t msr; + char pscope[] = "\\_SB.PCI0"; + + lens = acpigen_write_scope(pscope); + msr = rdmsr(TOP_MEM); + lens += acpigen_write_name_dword("TOM1", msr.lo); + msr = rdmsr(TOP_MEM2); + /* + * Since XP only implements parts of ACPI 2.0, we can't use a qword + * here. + * See http://www.acpi.info/presentations/S01USMOBS169_OS%2520new.ppt + * slide 22ff. + * Shift value right by 20 bit to make it fit into 32bit, + * giving us 1MB granularity and a limit of almost 4Exabyte of memory. + */ + lens += acpigen_write_name_dword("TOM2", (msr.hi << 12) | msr.lo >> 20); + acpigen_patch_len(lens - 1); + return (unsigned long) (acpigen_get_current()); +} + +unsigned long write_acpi_tables(unsigned long start) +{ + unsigned long current; + acpi_rsdp_t *rsdp; + acpi_rsdt_t *rsdt; + acpi_hpet_t *hpet; + acpi_madt_t *madt; + acpi_srat_t *srat; + acpi_slit_t *slit; + acpi_fadt_t *fadt; + acpi_facs_t *facs; + acpi_header_t *dsdt; + acpi_header_t *ssdt; + acpi_header_t *alib; + acpi_header_t *ivrs; + acpi_hest_t *hest; + + /* Align ACPI tables to 16 bytes */ + start = ALIGN(start, 16); + current = start; + + printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start); + + /* We need at least an RSDP and an RSDT Table */ + rsdp = (acpi_rsdp_t *) current; + current += sizeof(acpi_rsdp_t); + rsdt = (acpi_rsdt_t *) current; + current += sizeof(acpi_rsdt_t); + + /* clear all table memory */ + memset((void *)start, 0, current - start); + + acpi_write_rsdp(rsdp, rsdt, NULL); + acpi_write_rsdt(rsdt); + + /* DSDT */ + current = ALIGN(current, 8); + printk(BIOS_DEBUG, "ACPI: * DSDT at %lx\n", current); + dsdt = (acpi_header_t *)current; /* it will used by fadt */ + memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); + current += dsdt->length; + memcpy(dsdt, &AmlCode, dsdt->length); + printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n",dsdt,dsdt->length); + + /* FACS */ /* it needs 64 byte alignment */ + current = ALIGN(current, 64); + printk(BIOS_DEBUG, "ACPI: * FACS at %lx\n", current); + facs = (acpi_facs_t *) current; /* it will be used by fadt */ + current += sizeof(acpi_facs_t); + acpi_create_facs(facs); + + /* FADT */ + current = ALIGN(current, 8); + printk(BIOS_DEBUG, "ACPI: * FADT at %lx\n", current); + fadt = (acpi_fadt_t *) current; + current += sizeof(acpi_fadt_t); + + acpi_create_fadt(fadt, facs, dsdt); + acpi_add_table(rsdp, fadt); + + /* + * We explicitly add these tables later on: + */ + current = ALIGN(current, 8); + printk(BIOS_DEBUG, "ACPI: * HPET at %lx\n", current); + hpet = (acpi_hpet_t *) current; + current += sizeof(acpi_hpet_t); + acpi_create_hpet(hpet); + acpi_add_table(rsdp, hpet); + + /* If we want to use HPET Timers Linux wants an MADT */ + current = ALIGN(current, 8); + printk(BIOS_DEBUG, "ACPI: * MADT at %lx\n",current); + madt = (acpi_madt_t *) current; + acpi_create_madt(madt); + current += madt->header.length; + acpi_add_table(rsdp, madt); + + /* HEST */ + current = ALIGN(current, 8); + hest = (acpi_hest_t *)current; + acpi_write_hest((void *)current); + acpi_add_table(rsdp, (void *)current); + current += ((acpi_header_t *)current)->length; + + current = ALIGN(current, 8); + printk(BIOS_DEBUG, "ACPI: * IVRS at %lx\n", current); + ivrs = agesawrapper_getlateinitptr(PICK_IVRS); + if (ivrs != NULL) { + memcpy((void *)current, ivrs, ivrs->length); + ivrs = (acpi_header_t *) current; + current += ivrs->length; + acpi_add_table(rsdp, ivrs); + } else { + printk(BIOS_DEBUG, " AGESA IVRS table NULL. Skipping.\n"); + } + + /* SRAT */ + current = ALIGN(current, 8); + printk(BIOS_DEBUG, "ACPI: * SRAT at %lx\n", current); + srat = (acpi_srat_t *) agesawrapper_getlateinitptr (PICK_SRAT); + if (srat != NULL) { + memcpy((void *)current, srat, srat->header.length); + srat = (acpi_srat_t *) current; + current += srat->header.length; + acpi_add_table(rsdp, srat); + } else { + printk(BIOS_DEBUG, " AGESA SRAT table NULL. Skipping.\n"); + } + + /* SLIT */ + current = ALIGN(current, 8); + printk(BIOS_DEBUG, "ACPI: * SLIT at %lx\n", current); + slit = (acpi_slit_t *) agesawrapper_getlateinitptr (PICK_SLIT); + if (slit != NULL) { + memcpy((void *)current, slit, slit->header.length); + slit = (acpi_slit_t *) current; + current += slit->header.length; + acpi_add_table(rsdp, slit); + } else { + printk(BIOS_DEBUG, " AGESA SLIT table NULL. Skipping.\n"); + } + + /* ALIB */ + current = ALIGN(current, 16); + printk(BIOS_DEBUG, "ACPI: * AGESA ALIB SSDT at %lx\n", current); + alib = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_ALIB); + if (alib != NULL) { + memcpy((void *)current, alib, alib->length); + alib = (acpi_header_t *) current; + current += alib->length; + acpi_add_table(rsdp, (void *)alib); + } + else { + printk(BIOS_DEBUG, " AGESA ALIB SSDT table NULL. Skipping.\n"); + } + + /* this pstate ssdt may cause Blue Screen: Fixed: Keep this comment for a while. */ + /* SSDT */ + current = ALIGN(current, 16); + printk(BIOS_DEBUG, "ACPI: * SSDT at %lx\n", current); + ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE); + if (ssdt != NULL) { + memcpy((void *)current, ssdt, ssdt->length); + ssdt = (acpi_header_t *) current; + current += ssdt->length; + } + else { + printk(BIOS_DEBUG, " AGESA PState table NULL. Skipping.\n"); + } + acpi_add_table(rsdp,ssdt); + + printk(BIOS_DEBUG, "ACPI: * SSDT for PState at %lx\n", current); + + printk(BIOS_DEBUG, "ACPI: * SSDT\n"); + ssdt = (acpi_header_t *)current; + + acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR); + current += ssdt->length; + acpi_add_table(rsdp, ssdt); + + printk(BIOS_INFO, "ACPI: done.\n"); + return current; +} +#endif //FALSE diff --git a/src/mainboard/pcengines/apu2/apu2.h b/src/mainboard/pcengines/apu2/apu2.h new file mode 100644 index 0000000..847b5df --- /dev/null +++ b/src/mainboard/pcengines/apu2/apu2.h @@ -0,0 +1,42 @@ +/* + * This file is part of the coreboot project. + + * + * Copyright (C) 2015 Eltan B.V. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <northbridge/amd/pi/agesawrapper.h> + +#define APU2_SPD_STRAP0_GPIO 0x40 // GPIO49 +#define APU2_SPD_STRAP0_FUNC Function2 +#define APU2_SPD_STRAP1_GPIO 0x41 // GPIO50 +#define APU2_SPD_STRAP1_FUNC Function2 +#define APU2_PE3_RST_L_GPIO 0x42 // GPIO51 +#define APU2_PE3_RST_L_FUNC Function2 +#define APU2_PE4_RST_L_GPIO 0x43 // DEVSLP[0]/GPIO59 +#define APU2_PE4_RST_L_FUNC Function3 +#define APU2_LED1_L_GPIO 0x44 // GPIO57 +#define APU2_LED1_L_FUNC Function1 +#define APU2_LED2_L_GPIO 0x45 // GPIO58 +#define APU2_LED2_L_FUNC Function1 +#define APU2_LED3_L_GPIO 0x46 // DEVSLP[1]/GPIO59 +#define APU2_LED3_L_FUNC Function3 +#define APU2_PE3_WDIS_L_GPIO 0x47 // GPIO64 +#define APU2_PE3_WDIS_L_FUNC Function2 +#define APU2_PE4_WDIS_L_GPIO 0x48 // GPIO68 +#define APU2_PE4_WDIS_L_FUNC Function0 +#define APU2_SKR_GPIO 0x5B // SPKR/GPIO66 +#define APU2_SKR_FUNC Function0 +#define APU2_PROCHOT_GPIO 0x4D // GPIO71 +#define APU2_PROCHOT_FUNC Function0 +#define APU2_BIOS_CONSOLE_GPIO 0x59 // GENINT1_L/GPIO32 +#define APU2_BIOS_CONSOLE_FUNC Function0 diff --git a/src/mainboard/pcengines/apu2/board_info.txt b/src/mainboard/pcengines/apu2/board_info.txt new file mode 100644 index 0000000..6b676ba --- /dev/null +++ b/src/mainboard/pcengines/apu2/board_info.txt @@ -0,0 +1,6 @@ +Board name: PC Engines APU2 +Board URL: +Category: customer +ROM protocol: SPI +ROM socketed: n +Flashrom support: n diff --git a/src/mainboard/pcengines/apu2/cmos.default b/src/mainboard/pcengines/apu2/cmos.default new file mode 100644 index 0000000..82fe3d2 --- /dev/null +++ b/src/mainboard/pcengines/apu2/cmos.default @@ -0,0 +1,13 @@ +boot_option=Fallback +last_boot=Fallback +ECC_memory=Disable +hw_scrubber=Disable +interleave_chip_selects=Disable +max_mem_clock=400Mhz +multi_core=Enable +power_on_after_fail=Disable +slow_cpu=off +nmi=Disable +boot_devices='uda1' +baud_rate=115200 +debug_level=Spew diff --git a/src/mainboard/pcengines/apu2/cmos.layout b/src/mainboard/pcengines/apu2/cmos.layout new file mode 100644 index 0000000..1ab065d --- /dev/null +++ b/src/mainboard/pcengines/apu2/cmos.layout @@ -0,0 +1,126 @@ +#***************************************************************************** +# +# This file is part of the coreboot project. +# +# Copyright (C) 2012 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +#***************************************************************************** + +entries + +#start-bit length config config-ID name +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 multi_core +400 1 e 1 power_on_after_fail + +# SHOULD MATCH CONFIG_CMOS_SKIP_PXE_LOC 0x32 and MASK 0x2 :: ELTAN SEABIOS +401 1 e 11 network_boot + +412 4 e 6 debug_level + +## ETHERBOOT +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +## ETHERBOOT + +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu + +#FILO +# coreboot config options: bootloader +448 256 s 0 boot_devices +#FILO + +728 256 h 0 user_data + +984 16 h 0 check_sum +# Reserve the extended AMD configuration registers +1000 24 r 0 amd_reserved + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD +7 10 Fallback_Floppy +#7 3 ROM +8 0 400Mhz +8 1 333Mhz +8 2 266Mhz +8 3 200Mhz +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5% + +checksums + +checksum 392 983 984 diff --git a/src/mainboard/pcengines/apu2/devicetree.cb b/src/mainboard/pcengines/apu2/devicetree.cb new file mode 100644 index 0000000..d6a0d13 --- /dev/null +++ b/src/mainboard/pcengines/apu2/devicetree.cb @@ -0,0 +1,92 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2013 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +chip northbridge/amd/pi/00730F01/root_complex + device cpu_cluster 0 on + chip cpu/amd/pi/00730F01 + device lapic 0 on end + end + end + + device domain 0 on + subsystemid 0x1022 0x1410 inherit + chip northbridge/amd/pi/00730F01 # CPU side of HT root complex + + chip northbridge/amd/pi/00730F01 # PCI side of HT root complex + device pci 0.0 on end # Root Complex + device pci 0.2 off end # IOMMU + device pci 1.0 off end # Internal Graphics P2P bridge 0x9804 + device pci 1.1 off end # Internal Multimedia + device pci 2.0 on end # PCIe Host Bridge + device pci 2.1 on end # mPCIe slot 2 (on GFX lane) + device pci 2.2 on end # LAN3 + device pci 2.3 on end # LAN2 + device pci 2.4 on end # LAN1 + device pci 2.5 on end # mPCIe slot 1 + device pci 8.0 on end # Platform Security Processor + end #chip northbridge/amd/pi/00730F01 + + chip southbridge/amd/pi/hudson # it is under NB/SB Link, but on the same pci bus + device pci 10.0 on end # XHCI HC0 muxed with EHCI 2 + device pci 11.0 on end # SATA + device pci 12.0 off end # USB EHCI0 usb[0:3] not connected + device pci 13.0 on end # USB EHCI1 usb[4:7] + device pci 14.0 on end # SM +# disabled device pci 14.2 on end # HDA 0x4383 + device pci 14.3 on # LPC 0x439d + chip superio/nuvoton/nct5104d # SIO NCT5104D + register "irq_trigger_type" = "0" + device pnp 2e.0 off end + device pnp 2e.2 on + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 on + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.10 on + # UART C is conditionally turned on + io 0x60 = 0x3e8 + irq 0x70 = 4 + end + device pnp 2e.11 on + # UART D is conditionally turned on + io 0x60 = 0x2e8 + irq 0x70 = 3 + end + device pnp 2e.8 off end + device pnp 2e.f off end + # GPIO0 and GPIO1 are conditionally turned on + device pnp 2e.007 on end + device pnp 2e.107 on end + device pnp 2e.607 off end + device pnp 2e.e off end + end # SIO NCT5104D + end # LPC 0x439d + + device pci 14.7 on end # SD + device pci 16.0 on end # USB EHCI2 usb[8:7] - muxed with XHCI + end #chip southbridge/amd/pi/hudson + + device pci 18.0 on end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + device pci 18.4 on end + device pci 18.5 on end + + end #chip northbridge/amd/pi/00730F01 # CPU side of HT root complex + end #domain +end #northbridge/amd/pi/00730F01/root_complex diff --git a/src/mainboard/pcengines/apu2/dsdt.asl b/src/mainboard/pcengines/apu2/dsdt.asl new file mode 100644 index 0000000..ad8239b --- /dev/null +++ b/src/mainboard/pcengines/apu2/dsdt.asl @@ -0,0 +1,90 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Advanced Micro Devices, Inc. + * Copyright (C) 2013 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* DefinitionBlock Statement */ +DefinitionBlock ( + "DSDT.AML", /* Output filename */ + "DSDT", /* Signature */ + 0x02, /* DSDT Revision, needs to be 2 for 64bit */ + "AMD ", /* OEMID */ + "COREBOOT", /* TABLE ID */ + 0x00010001 /* OEM Revision */ + ) +{ /* Start of ASL file */ + /* #include <arch/x86/acpi/debug.asl> */ /* Include global debug methods if needed */ + + /* Globals for the platform */ + #include "acpi/mainboard.asl" + + /* Describe the USB Overcurrent pins */ + #include "acpi/usb_oc.asl" + + /* PCI IRQ mapping for the Southbridge */ + #include <southbridge/amd/pi/hudson/acpi/pcie.asl> + + /* Describe the processor tree (\_PR) */ + #include <cpu/amd/pi/00730F01/acpi/cpu.asl> + + /* Contains the supported sleep states for this chipset */ + #include <southbridge/amd/pi/hudson/acpi/sleepstates.asl> + + /* Contains the Sleep methods (WAK, PTS, GTS, etc.) */ + #include "acpi/sleep.asl" + + /* System Bus */ + Scope(\_SB) { /* Start \_SB scope */ + /* global utility methods expected within the \_SB scope */ + #include <arch/x86/acpi/globutil.asl> + + /* Describe IRQ Routing mapping for this platform (within the \_SB scope) */ + #include "acpi/routing.asl" + + Device(PWRB) { + Name(_HID, EISAID("PNP0C0C")) + Name(_UID, 0xAA) + Name(_PRW, Package () {3, 0x04}) + Name(_STA, 0x0B) + } + + Device(PCI0) { + /* Describe the AMD Northbridge */ + #include <northbridge/amd/pi/00730F01/acpi/northbridge.asl> + + /* Describe the AMD Fusion Controller Hub Southbridge */ + #include <southbridge/amd/pi/hudson/acpi/fch.asl> + } + + /* Describe PCI INT[A-H] for the Southbridge */ + #include "acpi/pci_int.asl" + + + + + } /* End \_SB scope */ + + /* Describe SMBUS for the Southbridge */ + #include <southbridge/amd/pi/hudson/acpi/smbus.asl> + + /* Define the General Purpose Events for the platform */ + #include "acpi/gpe.asl" + + /* Define the Thermal zones and methods for the platform */ + #include "acpi/thermal.asl" + + /* Define the System Indicators for the platform */ + #include "acpi/si.asl" +} +/* End of ASL file */ diff --git a/src/mainboard/pcengines/apu2/irq_tables.c b/src/mainboard/pcengines/apu2/irq_tables.c new file mode 100644 index 0000000..3a6c87e --- /dev/null +++ b/src/mainboard/pcengines/apu2/irq_tables.c @@ -0,0 +1,104 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <device/pci.h> +#include <string.h> +#include <stdint.h> +#include <arch/pirq_routing.h> +#include <cpu/amd/amdfam16.h> + +static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, + u8 link0, u16 bitmap0, u8 link1, u16 bitmap1, + u8 link2, u16 bitmap2, u8 link3, u16 bitmap3, + u8 slot, u8 rfu) +{ + pirq_info->bus = bus; + pirq_info->devfn = devfn; + pirq_info->irq[0].link = link0; + pirq_info->irq[0].bitmap = bitmap0; + pirq_info->irq[1].link = link1; + pirq_info->irq[1].bitmap = bitmap1; + pirq_info->irq[2].link = link2; + pirq_info->irq[2].bitmap = bitmap2; + pirq_info->irq[3].link = link3; + pirq_info->irq[3].bitmap = bitmap3; + pirq_info->slot = slot; + pirq_info->rfu = rfu; +} + +#define IRQ_BITMAP 0xdee8 //0xdef8 Removed IRQ 4, this is used for serial + +unsigned long write_pirq_routing_table(unsigned long addr) +{ + struct irq_routing_table *pirq; + struct irq_info *pirq_info; + u32 slot_num; + u8 *v; + + u8 sum = 0; + int i; + + /* Align the table to be 16 byte aligned. */ + addr += 15; + addr &= ~15; + + /* This table must be between 0xf0000 & 0x100000 */ + printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr); + + pirq = (void *)(addr); + v = (u8 *) (addr); + + pirq->signature = PIRQ_SIGNATURE; + pirq->version = PIRQ_VERSION; + + pirq->rtr_bus = 0; + pirq->rtr_devfn = PCI_DEVFN(0x14, 4); + + pirq->exclusive_irqs = 0; + + pirq->rtr_vendor = 0x1002; + pirq->rtr_device = 0x4384; + + pirq->miniport_data = 0; + + memset(pirq->rfu, 0, sizeof(pirq->rfu)); + + pirq_info = (void *)(&pirq->checksum + 1); + slot_num = 0; + + /* pci bridge */ + write_pirq_info(pirq_info, 0, PCI_DEVFN(0x14, 4), + 0x1, IRQ_BITMAP, 0x2, IRQ_BITMAP, 0x3, IRQ_BITMAP, 0x4, IRQ_BITMAP, 0, + 0); + pirq_info++; + + slot_num++; + + pirq->size = 32 + 16 * slot_num; + + for (i = 0; i < pirq->size; i++) + sum += v[i]; + + sum = pirq->checksum - sum; + + if (sum != pirq->checksum) { + pirq->checksum = sum; + } + + printk(BIOS_INFO, "write_pirq_routing_table done.\n"); + + return (unsigned long)pirq_info; +} diff --git a/src/mainboard/pcengines/apu2/mainboard.c b/src/mainboard/pcengines/apu2/mainboard.c new file mode 100644 index 0000000..432a643 --- /dev/null +++ b/src/mainboard/pcengines/apu2/mainboard.c @@ -0,0 +1,163 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <arch/io.h> +#include <device/pci_def.h> +#include <arch/acpi.h> +#include <northbridge/amd/pi/BiosCallOuts.h> +#include <cpu/amd/pi/s3_resume.h> +#include <southbridge/amd/pi/hudson/hudson.h> +#include <northbridge/amd/pi/agesawrapper.h> +#include <cpu/x86/msr.h> +#include <cpu/amd/mtrr.h> +#if CONFIG_USE_OPTION_TABLE +#include <pc80/mc146818rtc.h> +#endif //CONFIG_USE_OPTION_TABLE +#if CONFIG_HAVE_OPTION_TABLE +#include "option_table.h" +#endif //CONFIG_HAVE_OPTION_TABLE +#include <timestamp.h> +#include <fchgpio.h> +#include "apu2.h" +#include <superio/nuvoton/nct5104d/nct5104d.h> +#include <cbfs.h> +#include <spd_cache.h> + +/********************************************** + * enable the dedicated function in mainboard. + **********************************************/ + +static void mainboard_enable(device_t dev) +{ + struct device *sio_dev; + + setup_bsp_ramtop(); + u32 TOM1 = bsp_topmem() / (1024 *1024); // Tom1 in Mbyte + u32 TOM2 = ( bsp_topmem2() / (1024 *1024)) - 4 * 1024; // Tom2 in Mbyte + printk(BIOS_ERR, "%d MB", TOM1+TOM2); + + u8 spd_buffer[128]; + int index = 0; + + /* One SPD file contains all 4 options, determine which index to read here, then call into the standard routines*/ + + if ( ReadFchGpio(APU2_SPD_STRAP0_GPIO) ) index |= BIT0; + if ( ReadFchGpio(APU2_SPD_STRAP1_GPIO) ) index |= BIT1; + + printk(BIOS_SPEW, "Reading SPD index %d to get ECC info \n", index); + if (read_spd_from_cbfs(spd_buffer, index) < 0) + spd_buffer[3]=3; // Indicate no ECC + + if ( spd_buffer[3] == 8 ) printk(BIOS_ERR, " ECC"); + printk(BIOS_ERR, " DRAM\n\n"); + + // + // Enable the RTC output + // + pm_write16 ( 0x56, pm_read16( 0x56 ) | (1 << 11)); + + // + // Enable power on from WAKE# + // + pm_write16 ( 0xBA, pm_read16( 0xBA ) | (1 << 14)); + + if (acpi_is_wakeup_s3()) + agesawrapper_fchs3earlyrestore(); + +// +// SIO CONFIG, enable and disable UARTC and UARTD depending on the selection +// +#if CONFIG_SUPERIO_NUVOTON_NCT5104D_UARTC_ENABLE + printk(BIOS_INFO, "UARTC enabled\n"); + + sio_dev = dev_find_slot_pnp(0x2E, NCT5104D_SP3); + if ( sio_dev ) sio_dev->enabled = 1; + sio_dev = dev_find_slot_pnp(0x2E, NCT5104D_GPIO0); + if ( sio_dev ) sio_dev->enabled = 0; + +#else //CONFIG_SUPERIO_NUVOTON_NCT5104D_UARTC_ENABLE + printk(BIOS_INFO, "UARTC disabled\n"); + + sio_dev = dev_find_slot_pnp(0x2E, NCT5104D_SP3); + if ( sio_dev ) sio_dev->enabled = 0; + sio_dev = dev_find_slot_pnp(0x2E, NCT5104D_GPIO0); + if ( sio_dev ) sio_dev->enabled = 1; +#endif //CONFIG_SUPERIO_NUVOTON_NCT5104D_UARTC_ENABLE + + +#if CONFIG_SUPERIO_NUVOTON_NCT5104D_UARTD_ENABLE + printk(BIOS_INFO, "UARTD enabled\n"); + + sio_dev = dev_find_slot_pnp(0x2E, NCT5104D_SP4); + if ( sio_dev ) sio_dev->enabled = 1; + sio_dev = dev_find_slot_pnp(0x2E, NCT5104D_GPIO1); + if ( sio_dev ) sio_dev->enabled = 0; + +#else //CONFIG_SUPERIO_NUVOTON_NCT5104D_UARTD_ENABLE + printk(BIOS_INFO, "UARTD disabled\n"); + + sio_dev = dev_find_slot_pnp(0x2E, NCT5104D_SP4); + if ( sio_dev ) sio_dev->enabled = 0; + sio_dev = dev_find_slot_pnp(0x2E, NCT5104D_GPIO1); + if ( sio_dev ) sio_dev->enabled = 1; + +#endif //CONFIG_SUPERIO_NUVOTON_NCT5104D_UARTD_ENABLE +} + +static void mainboard_final(void *chip_info) { + + printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER "final\n"); + +/* Disabling LPCCLK0 which is unused according to the schematic doesn't work. The system is stuck if we do this + * So we don't do this. + + */ + +#if CONFIG_DUMP_GPIO_CONFIGURATION + //DumpGpioConfiguration( ); +#endif //CONFIG_DUMP_GPIO_CONFIGURATION + +#if CONFIG_DUMP_CLOCK_CONFIGURATION + //DumpClockConfiguration( ); +#endif //CONFIG_DUMP_GPIO_CONFIGURATION + +#if CONFIG_DUMP_LINK_CONFIGURATION + //DumpLinkConfiguration( ); +#endif //CONFIG_DUMP_LINK_CONFIGURATION + + // + // Turn off LED 2 and 3 + // + printk(BIOS_INFO, "Turn off LED 2 and 3\n"); + WriteFchGpio( APU2_LED2_L_GPIO, 1); + WriteFchGpio( APU2_LED3_L_GPIO, 1); + + printk(BIOS_INFO, "USB PORT ROUTING = 0x%08x\n", *((u8 *)(ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGEF ))); + if ( *((u8 *)(ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGEF )) & (1<<7) ) { + + printk(BIOS_INFO, "USB PORT ROUTING = XHCI PORTS ENABLED\n"); + } else { + + printk(BIOS_INFO, "USB PORT ROUTING = EHCI PORTS ENABLED\n"); + } +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, + .final = mainboard_final, +}; diff --git a/src/mainboard/pcengines/apu2/mptable.c b/src/mainboard/pcengines/apu2/mptable.c new file mode 100644 index 0000000..320e5ba --- /dev/null +++ b/src/mainboard/pcengines/apu2/mptable.c @@ -0,0 +1,198 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <arch/smp/mpspec.h> +#include <device/pci.h> +#include <arch/io.h> +#include <arch/ioapic.h> +#include <string.h> +#include <stdint.h> +#include <cpu/amd/amdfam15.h> +#include <arch/cpu.h> +#include <cpu/x86/lapic.h> +//#include <southbridge/amd/agesa/hudson/hudson.h> /* pm_ioread() */ +#include <southbridge/amd/pi/hudson/hudson.h> /* pm_ioread() */ +#include <southbridge/amd/pi/hudson/amd_pci_int_defs.h> // IRQ routing info + + +u8 picr_data[FCH_INT_TABLE_SIZE] = { + 0x03,0x03,0x05,0x07,0x0B,0x0A,0x1F,0x1F, /* 00 - 07 : INTA - INTF and 2 reserved dont map 4*/ + 0xFA,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F, /* 08 - 0F */ + 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F, /* 10 - 17 */ + 0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00, /* 18 - 1F */ + 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00, /* 20 - 27 */ + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, /* 28 - 2F */ + 0x05,0x1F,0x05,0x1F,0x04,0x1F,0x1F,0x1F, /* 30 - 37 */ + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, /* 38 - 3F */ + 0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00, /* 40 - 47 */ + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, /* 48 - 4F */ +// 0x03,0x04,0x05,0x07,0x00,0x00,0x00,0x00, /* 50 - 57 */ + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, /* 50 - 57 */ + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, /* 58 - 5F */ + 0x00,0x00,0x1F /* 60 - 62 */ +}; +u8 intr_data[FCH_INT_TABLE_SIZE] = { + 0x10,0x10,0x12,0x13,0x14,0x15,0x1F,0x1F, /* 00 - 07 : INTA - INTF and 2 reserved dont map 4*/ + 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, /* 08 - 0F */ + 0x09,0x1F,0x1F,0x1F,0x1F,0x1f,0x1F,0x10, /* 10 - 17 */ + 0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00, /* 18 - 1F */ + 0x05,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00, /* 20 - 27 */ + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, /* 28 - 2F */ + 0x12,0x1f,0x12,0x1F,0x12,0x1F,0x1F,0x00, /* 30 - 37 */ + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, /* 38 - 3F */ + 0x1f,0x13,0x00,0x00,0x00,0x00,0x00,0x00, /* 40 - 47 */ + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, /* 48 - 4F */ +// 0x10,0x11,0x12,0x13,0x00,0x00,0x00,0x00, /* 50 - 57 */ + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, /* 50 - 57 */ + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, /* 58 - 5F */ + 0x00,0x00,0x1F /* 60 - 62 */ +}; + +static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned length) +{ + mc->mpc_length += length; + mc->mpc_entry_count++; +} + +static void my_smp_write_bus(struct mp_config_table *mc, + unsigned char id, const char *bustype) +{ + struct mpc_config_bus *mpc; + mpc = smp_next_mpc_entry(mc); + memset(mpc, '\0', sizeof(*mpc)); + mpc->mpc_type = MP_BUS; + mpc->mpc_busid = id; + memcpy(mpc->mpc_bustype, bustype, sizeof(mpc->mpc_bustype)); + smp_add_mpc_entry(mc, sizeof(*mpc)); +} + +static void *smp_write_config_table(void *v) +{ + struct mp_config_table *mc; + int bus_isa; + u8 byte; + + /* + * By the time this function gets called, the IOAPIC registers + * have been written so they can be read to get the correct + * APIC ID and Version + */ + u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24); + u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF); + + mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); + + mptable_init(mc, LOCAL_APIC_ADDR); + memcpy(mc->mpc_oem, "AMD ", 8); + + smp_write_processors(mc); + + //mptable_write_buses(mc, NULL, &bus_isa); + my_smp_write_bus(mc, 0, "PCI "); + my_smp_write_bus(mc, 1, "PCI "); + bus_isa = 0x02; + my_smp_write_bus(mc, bus_isa, "ISA "); + + /* I/O APICs: APIC ID Version State Address */ + smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR); + + smp_write_ioapic(mc, ioapic_id+1, 0x21, (void *)0xFEC20000); + /* PIC IRQ routine */ + for (byte = 0x0; byte < sizeof(picr_data); byte ++) { + outb(byte, 0xC00); + outb(picr_data[byte], 0xC01); + } + + /* APIC IRQ routine */ + for (byte = 0x0; byte < sizeof(intr_data); byte ++) { + outb(byte | 0x80, 0xC00); + outb(intr_data[byte], 0xC01); + } + /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ +#define IO_LOCAL_INT(type, intr, apicid, pin) \ + smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); + mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0); + + /* PCI interrupts are level triggered, and are + * associated with a specific bus/device/function tuple. + */ +#define PCI_INT(bus, dev, int_sign, pin) \ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin)) + + /* Internal VGA */ + PCI_INT(0x0, 0x01, 0x0, intr_data[PIRQ_B]); + PCI_INT(0x0, 0x01, 0x1, intr_data[PIRQ_C]); + + /* SMBUS */ + PCI_INT(0x0, 0x14, 0x0, 0x10); + + /* HD Audio */ +// PCI_INT(0x0, 0x14, 0x0, intr_data[PIRQ_HDA]); + + /* SD card */ + PCI_INT(0x0, 0x14, 0x1, intr_data[PIRQ_SD]); + + /* USB */ + PCI_INT(0x0, 0x12, 0x0, intr_data[PIRQ_EHCI1]); + PCI_INT(0x0, 0x13, 0x0, intr_data[PIRQ_EHCI2]); + PCI_INT(0x0, 0x16, 0x0, intr_data[PIRQ_EHCI3]); + + /* sata */ + PCI_INT(0x0, 0x11, 0x0, intr_data[PIRQ_SATA]); + + /* on board NIC & Slot PCIE. */ + + + /* PCIe Lan*/ +// PCI_INT(0x0, 0x06, 0x0, 0x13); // No integrated LAN + +// /* FCH PCIe PortA */ +// PCI_INT(0x0, 0x15, 0x0, 0x10); +// /* FCH PCIe PortB */ +// PCI_INT(0x0, 0x15, 0x1, 0x11); +// /* FCH PCIe PortC */ +// PCI_INT(0x0, 0x15, 0x2, 0x12); +// /* FCH PCIe PortD */ +// PCI_INT(0x0, 0x15, 0x3, 0x13); + + /* GPP0 */ + PCI_INT(0x0, 0x2, 0x0, 0x10); // Network 3 + /* GPP1 */ + PCI_INT(0x0, 0x2, 0x1, 0x11); // Network 2 + /* GPP2 */ + PCI_INT(0x0, 0x2, 0x2, 0x12); // Network 1 + /* GPP3 */ + PCI_INT(0x0, 0x2, 0x3, 0x13); // mPCI + /* GPP4 */ + PCI_INT(0x0, 0x2, 0x4, 0x14); // mPCI + + + + /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ + IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0); + IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1); + /* There is no extension information... */ + + /* Compute the checksums */ + return mptable_finalize(mc); +} + +unsigned long write_smp_table(unsigned long addr) +{ + void *v; + v = smp_write_floating_table(addr, 0); + return (unsigned long)smp_write_config_table(v); +} diff --git a/src/mainboard/pcengines/apu2/romstage.c b/src/mainboard/pcengines/apu2/romstage.c new file mode 100644 index 0000000..2dfae0e --- /dev/null +++ b/src/mainboard/pcengines/apu2/romstage.c @@ -0,0 +1,236 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdint.h> +#include <string.h> +#include <device/pci_def.h> +#include <device/pci_ids.h> +#include <arch/acpi.h> +#include <arch/io.h> +#include <arch/stages.h> +#include <device/pnp_def.h> +#include <arch/cpu.h> +#include <cpu/x86/lapic.h> +#include <console/console.h> +#include <cpu/amd/car.h> +#include <cpu/x86/bist.h> +#include <cpu/x86/lapic.h> +#include <hudson.h> +#include <cpu/amd/pi/s3_resume.h> +#include <fchgpio.h> +#include "apu2.h" +#include <build.h> + +// +// GPIO Init Table +// +// GPIO_DEFINITION(gpio, function, outputenable, output, pullup, pulldown) +static const GPIO_CONTROL gGpioInitTable[] = { + GPIO_DEFINITION (APU2_SPD_STRAP0_GPIO, APU2_SPD_STRAP0_FUNC, 0, 0, 0, 0), + GPIO_DEFINITION (APU2_SPD_STRAP1_GPIO, APU2_SPD_STRAP1_FUNC, 0, 0, 0, 0), + GPIO_DEFINITION (APU2_PE3_RST_L_GPIO, APU2_PE3_RST_L_FUNC, 1, 1, 0, 0), + GPIO_DEFINITION (APU2_PE4_RST_L_GPIO, APU2_PE4_RST_L_FUNC, 1, 1, 0, 0), + GPIO_DEFINITION (APU2_LED1_L_GPIO, APU2_LED1_L_FUNC, 1, 0, 0, 0), // Turn on the LEDs by default + GPIO_DEFINITION (APU2_LED2_L_GPIO, APU2_LED2_L_FUNC, 1, 0, 0, 0), + GPIO_DEFINITION (APU2_LED3_L_GPIO, APU2_LED3_L_FUNC, 1, 0, 0, 0), + GPIO_DEFINITION (APU2_PE3_WDIS_L_GPIO, APU2_PE3_WDIS_L_FUNC, 1, 1, 0, 0), + GPIO_DEFINITION (APU2_PE4_WDIS_L_GPIO, APU2_PE4_WDIS_L_FUNC, 1, 1, 0, 0), +// SPKR doesn't require init, left at default + GPIO_DEFINITION (APU2_PROCHOT_GPIO, APU2_PROCHOT_FUNC, 0, 0, 0, 0), + GPIO_DEFINITION (APU2_BIOS_CONSOLE_GPIO, APU2_BIOS_CONSOLE_FUNC, 0, 0, 0, 0), + {0xFF, 0xFF, 0xFF} // Terminator + }; + + +void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +{ + u32 val; +#if CONFIG_SVI2_SLOW_SPEED + device_t d18f3_dev = PCI_DEV(0, 0x18, 3); +#endif //CONFIG_SVI2_SLOW_SPEED +#if CONFIG_SVI_WAIT_COMP_DIS + device_t d18f5_dev = PCI_DEV(0, 0x18, 5); +#endif //CONFIG_SVI_WAIT_COMP_DIS + + /* + * In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for + * LpcClk[1:0]". This following register setting has been + * replicated in every reference design since Parmer, so it is + * believed to be required even though it is not documented in + * the SoC BKDGs. Without this setting, there is no serial + * output. + */ + outb(0xD2, 0xcd6); + outb(0x00, 0xcd7); + + amd_initmmio(); + + if (!cpu_init_detectedx && boot_cpu()) { + + u32 data, *memptr; + + hudson_lpc_port80(); + // + // Configure the GPIO's + // + HandleFchGpioTbl ( (GPIO_CONTROL *) &gGpioInitTable[0] ); + + hudson_clk_output_48Mhz(); + + post_code(0x31); + console_init(); + + printk(BIOS_INFO, "14-25-48Mhz Clock settings\n"); + + memptr = (u32 *)(ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG28 ); + data = *memptr; + printk(BIOS_INFO, "FCH_MISC_REG28 is 0x%08x \n", data); + + memptr = (u32 *)(ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG40 ); + data = *memptr; + printk(BIOS_INFO, "FCH_MISC_REG40 is 0x%08x \n", data); + + // + // Configure clock request + // + data = *((u32 *)(ACPI_MMIO_BASE + MISC_BASE+FCH_MISC_REG00)); + + data &= 0xFFFF0000; + data |= (0 + 1) << (0 * 4); // CLKREQ 0 to CLK0 + data |= (1 + 1) << (1 * 4); // CLKREQ 1 to CLK1 + data |= (2 + 1) << (2 * 4); // CLKREQ 2 to CLK2 + data |= (3 + 1) << (3 * 4); // CLKREQ 3 to CLK3 + + *((u32 *)(ACPI_MMIO_BASE + MISC_BASE+FCH_MISC_REG00)) = data; + + data = *((u32 *)(ACPI_MMIO_BASE + MISC_BASE+FCH_MISC_REG04)); + + data &= 0xFFFFFF0F; + data |= 0xA << (1 * 4); // CLKREQ GFX to GFXCLK + + *((u32 *)(ACPI_MMIO_BASE + MISC_BASE+FCH_MISC_REG04)) = data; + +// // +// // Configure clock strength +// // +// data = *((u32 *)(ACPI_MMIO_BASE + MISC_BASE+FCH_MISC_REG24)); +// +// data &= ~( (3 << 18) | (3 << 6) | (3 << 4) | (3 << 2) | (3 << 0) ); +// data |= 3 << 18; // GFX CLOCK +// data |= 3 << (0 * 2); // CLK0 +// data |= 3 << (1 * 2); // CLK1 +// data |= 3 << (2 * 2); // CLK2 +// data |= 3 << (3 * 2); // CLK3 +// +// *((u32 *)(ACPI_MMIO_BASE + MISC_BASE+FCH_MISC_REG24)) = data; + } + + /* Halt if there was a built in self test failure */ + post_code(0x34); + report_bist_failure(bist); + + /* Load MPB */ + val = cpuid_eax(1); + printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val); + printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx); + + /* + * This refers to LpcClkDrvSth settling time. Without this setting, processor + * initialization is slow or incorrect, so this wait has been replicated from + * earlier development boards. + */ + { int i; for(i = 0; i < 200000; i++) inb(0xCD6); } + + post_code(0x37); + agesawrapper_amdinitreset(); + + /* TODO There is no debug output between the return from amdinitreset and amdinitearly */ + + post_code(0x38); + printk(BIOS_DEBUG, "Got past avalon_early_setup\n"); + + post_code(0x39); + agesawrapper_amdinitearly(); + + /* + // Moved here to prevent double signon message + // amdinitreset AGESA code might issue a reset when the hardware is in a wrong state. + */ + +#if CONFIG_SVI2_SLOW_SPEED + /* Force SVI2 to slow speed for APU2 */ + val = pci_read_config32( d18f3_dev, 0xA0); + if ( val & (1 << 14 ) ) { + + printk(BIOS_DEBUG, "SVI2 FREQUENCY 20 Mhz changing to 3.4\n"); + val &= ~(1 << 14 ); + pci_write_config32(d18f3_dev, 0xA0, val ); + + } else { + + printk(BIOS_DEBUG, "SVI2 FREQUENCY 3.4 Mhz\n"); + } +#endif //CONFIG_SVI2_SLOW_SPEED + +#if CONFIG_SVI_WAIT_COMP_DIS + /* Disable SVI2 controller to wait for command completion */ + val = pci_read_config32( d18f5_dev, 0x12C); + if ( val & (1 << 30 ) ) { + + printk(BIOS_DEBUG, "SVI2 Wait completion disabled\n"); + + } else { + + printk(BIOS_DEBUG, "Disabling SVI2 Wait completion\n"); + val |= (1 << 30 ); + pci_write_config32(d18f5_dev, 0x12C, val ); + } + +#endif //CONFIG_SVI_WAIT_COMP_DIS + + int s3resume = acpi_is_wakeup_s3(); + if (!s3resume) { + post_code(0x40); + agesawrapper_amdinitpost(); + + //PspMboxBiosCmdDramInfo(); + post_code(0x41); + agesawrapper_amdinitenv(); + /* + If code hangs here, please check cahaltasm.S + */ + disable_cache_as_ram(); + + } else { /* S3 detect */ + + printk(BIOS_INFO, "S3 detected\n"); + + post_code(0x60); + agesawrapper_amdinitresume(); + + agesawrapper_amds3laterestore(); + + post_code(0x61); + prepare_for_resume(); + } + + outb(0xEA, 0xCD6); + outb(0x1, 0xcd7); + + post_code(0x50); + copy_and_run(); + + post_code(0x54); /* Should never see this post code. */ +} diff --git a/src/mainboard/pcengines/apu2/spd/HYNIX-2G-1333.spd.hex b/src/mainboard/pcengines/apu2/spd/HYNIX-2G-1333.spd.hex new file mode 100644 index 0000000..7fa5757 --- /dev/null +++ b/src/mainboard/pcengines/apu2/spd/HYNIX-2G-1333.spd.hex @@ -0,0 +1,263 @@ +# PCEngines 2Gb 1333 + +# SPD contents for APU 2GB DDR3 NO ECC (1333MHz PC1333) soldered down +# 0 Number of SPD Bytes used / Total SPD Size / CRC Coverage +# bits[3:0]: 1 = 128 SPD Bytes Used +# bits[6:4]: 1 = 256 SPD Bytes Total +# bit7 : 0 = CRC covers bytes 0 ~ 128 +01 + +# 1 SPD Revision +# 0x13 = Revision 1.3 +13 + +# 2 Key Byte / DRAM Device Type +# bits[7:0]: 0x0b = DDR3 SDRAM +0B + +# 3 Key Byte / Module Type +# bits[3:0]: 3 = SO-DIMM +# bits[3:0]: 8 = 72b-SO-DIMM +# bits[7:4]: reserved +03 + +# 4 SDRAM CHIP Density and Banks +# bits[3:0]: 3 = 2 Gigabits Total SDRAM capacity per chip +# bits[3:0]: 4 = 4 Gigabits Total SDRAM capacity per chip +# bits[6:4]: 0 = 3 (8 banks) +# bit7 : reserved +03 + +# 5 SDRAM Addressing +# bits[2:0]: 1 = 10 Column Address Bits +# bits[5:3]: 4 = 16 Row Address Bits +# bits[5:3]: 3 = 15 Row Address Bits +# bits[5:3]: 2 = 14 Row Address Bits +# bits[7:6]: reserved +19 + +# 6 Module Nominal Voltage, VDD +# bit0 : 0 = 1.5 V operable +# bit1 : 0 = NOT 1.35 V operable +# bit2 : 0 = NOT 1.25 V operable +# bits[7:3]: reserved +00 + +# 7 Module Organization +# bits[2:0]: 1 = 8 bits +# bits[2:0]: 2 = 16 bits +# bits[5:3]: 0 = 1 Rank +# bits[7:6]: reserved +01 + +# 8 Module Memory Bus Width +# bits[2:0]: 3 = Primary bus width is 64 bits +# bits[4:3]: 0 = 0 bits (no bus width extension) +# bits[4:3]: 1 = 8 bits (for ECC) +# bits[7:5]: reserved +03 + +# 9 Fine Timebase (FTB) Dividend / Divisor +# bits[3:0]: 0x02 divisor +# bits[7:4]: 0x05 dividend +# 5 / 2 = 2.5ps +52 + +# 10 Medium Timebase (MTB) Dividend +# 11 Medium Timebase (MTB) Divisor +# 1 / 8 = .125 ns +01 08 + +# 12 SDRAM Minimum Cycle Time (tCKmin) +# 0x0a = tCKmin of 1.25 ns = DDR3-1600 (800 MHz clock) +# 0x0c = tCKmin of 1.5 ns = DDR3-1333 (667 MHz clock) +# 0x0c = tCKmin of 1.5 ns = in multiples of MTB +0C + +# 13 Reserved +00 + +# 14 CAS Latencies Supported, Least Significant Byte +# 15 CAS Latencies Supported, Most Significant Byte +# Cas Latencies of 11 - 5 are supported +7E 00 + +# 16 Minimum CAS Latency Time (tAAmin) +# 0x6C = 13.5ns - DDR3-1333 +# 0x69 = 13.125 ns - DDR3-1333 +69 + +# 17 Minimum Write Recovery Time (tWRmin) +# 0x78 = tWR of 15ns - All DDR3 speed grades +78 + +# 18 Minimum RAS# to CAS# Delay Time (tRCDmin) +# 0x6E = 13.5ns - DDR3-1333 +# 0x69 = 13.125 ns - DDR3-1333 +69 + +# 19 Minimum Row Active to Row Active Delay Time (tRRDmin) +# 0x30 = 6.0ns +# 0x38 = 7.0ns +# 0x3C = 7.5ns +30 + +# 20 Minimum Row Precharge Delay Time (tRPmin) +# 0x6C = 13.5ns - +# 0x69 = 13.125 ns - DDR3-1333 +69 + +# 21 Upper Nibbles for tRAS and tRC +# bits[3:0]: tRAS most significant nibble = 1 (see byte 22) +# bits[7:4]: tRC most significant nibble = 1 (see byte 23) +11 + +# 22 Minimum Active to Precharge Delay Time (tRASmin), LSB +# 0x120 = 36ns - DDR3-1333 (see byte 21) +# 0x120 = 36ns - DDR3 +20 + +# 23 Minimum Active to Active/Refresh Delay Time (tRCmin), LSB +# 0x289 = 49.125ns - DDR3-1333 +89 + +# 24 Minimum Refresh Recovery Delay Time (tRFCmin), LSB +# 25 Minimum Refresh Recovery Delay Time (tRFCmin), MSB +# 0x500 = 160ns - for 2 Gigabit chips +# 0x820 = 260ns - for 4 Gigabit chips +00 05 + +# 26 Minimum Internal Write to Read Command Delay Time (tWTRmin) +# 0x3c = 7.5 ns - All DDR3 SDRAM speed bins +3C + +# 27 Minimum Internal Read to Precharge Command Delay Time (tRTPmin) +# 0x3c = 7.5ns - All DDR3 SDRAM speed bins +3C + +# 28 Upper Nibble for tFAWmin +# 29 Minimum Four Activate Window Delay Time (tFAWmin) +# 0x00F0 = 30ns - DDR3-1333, 1 KB page size +00 F0 + +# 30 SDRAM Optional Feature +# bit0 : 1= RZQ/6 supported +# bit1 : 1 = RZQ/7 supported +# bits[6:2]: reserved +# bit7 : 1 = DLL Off mode supported +83 + +# 31 SDRAM Thermal and Refresh Options +# bit0 : 1 = Temp up to 95c supported +# bit1 : 0 = 85-95c uses 2x refresh rate +# bit2 : 1 = Auto Self Refresh supported +# bit3 : 0 = no on die thermal sensor +# bits[6:4]: reserved +# bit7 : 0 = partial self refresh supported +01 + +# 32 Module Thermal Sensor +# 0 = Thermal sensor not incorporated onto this assembly +00 + +# 33 SDRAM Device Type +# bits[1:0]: 0 = Signal Loading not specified +# bits[3:2]: reserved +# bits[6:4]: 0 = Die count not specified +# bit7 : 0 = Standard Monolithic DRAM Device +00 + +# 34 Fine Offset for SDRAM Minimum Cycle Time (tCKmin) +00 + +# 35 Fine Offset for Minimum CAS Latency Time (tAAmin) +00 + +# 36 Fine Offset for Minimum RAS# to CAS# Delay Time (tRCDmin) +00 + +# 37 Fine Offset for Minimum Row Precharge Delay Time (tRPmin) +00 + +# 38 Fine Offset for Minimum Active to Active/Refresh Delay (tRCmin) +00 + +# 39 40 (reserved) +00 00 + +# 41 tMAW, MAC +# 8K*tREFI / 200k +86 + +# 42 - 47 (reserved) +00 00 00 00 00 00 + +# 48 - 55 (reserved) +00 00 00 00 00 00 00 00 + +# 56 - 59 (reserved) +00 00 00 00 + +# 60 Raw Card Extension, Module Nominal Height +# bits[4:0]: 0 = <= 15mm tall +# bits[7:5]: 0 = raw card revision 0-3 +00 + +# 61 Module Maximum Thickness +# bits[3:0]: 0 = thickness front <= 1mm +# bits[7:4]: 0 = thinkness back <= 1mm +00 + +# 62 Reference Raw Card Used +# bits[4:0]: 0 = Reference Raw card A used +# bits[6:5]: 0 = revision 0 +# bit7 : 0 = Reference raw cards A through AL +# revision B4 +61 + +# 63 Address Mapping from Edge Connector to DRAM +# bit0 : 0 = standard mapping (not mirrored) +# bits[7:1]: reserved +00 + +# 64 - 71 (reserved) +00 00 00 00 00 00 00 00 + +# 72 - 79 (reserved) +00 00 00 00 00 00 00 00 + +# 80 - 87 (reserved) +00 00 00 00 00 00 00 00 + +# 88 - 95 (reserved) +00 00 00 00 00 00 00 00 + +# 96 - 103 (reserved) +00 00 00 00 00 00 00 00 + +# 104 - 111 (reserved) +00 00 00 00 00 00 00 00 + +# 112 - 116 (reserved) +00 00 00 00 00 + +# 117 - 118 Module ID: Module Manufacturers JEDEC ID Code +# 0x0001 = AMD +00 01 + +# 119 Module ID: Module Manufacturing Location - OEM specified +00 + +# 120 Module ID: Module Manufacture Year in BCD +# 0x15 = 2015 +15 + +# 121 Module ID: Module Manufacture week +# 0x44 = 44th week +44 + +# 122 - 125: Module Serial Number +00 00 00 00 + +# 126 - 127: Cyclical Redundancy Code +b6 73 diff --git a/src/mainboard/pcengines/apu2/spd/HYNIX-4G-1333-ECC.spd.hex b/src/mainboard/pcengines/apu2/spd/HYNIX-4G-1333-ECC.spd.hex new file mode 100644 index 0000000..b9d3983 --- /dev/null +++ b/src/mainboard/pcengines/apu2/spd/HYNIX-4G-1333-ECC.spd.hex @@ -0,0 +1,257 @@ +# HYNIX-4GBYTE-1333 The H9 N0 SPD delivered by Hynix + +# SPD contents for APU 4GB DDR3 ECC (1333MHz PC1333) soldered down +# 0 Number of SPD Bytes used / Total SPD Size / CRC Coverage +# bits[3:0]: 1 = 128 SPD Bytes Used +# bits[6:4]: 1 = 256 SPD Bytes Total +# bit7 : 0 = CRC covers bytes 0 ~ 128 +01 + +# 1 SPD Revision - +# 0x13 = Revision 1.3 +13 +# 2 Key Byte / DRAM Device Type +# bits[7:0]: 0x0b = DDR3 SDRAM +0B + +# 3 Key Byte / Module Type +# bits[3:0]: 3 = SO-DIMM +# bits[3:0]: 8 = 72b-SO-DIMM +# bits[7:4]: reserved +08 + +# 4 SDRAM CHIP Density and Banks +# bits[3:0]: 3 = 2 Gigabits Total SDRAM capacity per chip +# bits[3:0]: 4 = 4 Gigabits Total SDRAM capacity per chip +# bits[6:4]: 0 = 3 (8 banks) +# bit7 : reserved +04 + +# 5 SDRAM Addressing +# bits[2:0]: 1 = 10 Column Address Bits +# bits[5:3]: 4 = 16 Row Address Bits +# bits[5:3]: 3 = 15 Row Address Bits +# bits[5:3]: 2 = 14 Row Address Bits +# bits[7:6]: reserved +21 + +# 6 Module Nominal Voltage, VDD +# bit0 : 0 = 1.5 V operable +# bit1 : 0 = NOT 1.35 V operable +# bit2 : 0 = NOT 1.25 V operable +# bits[7:3]: reserved +00 + +# 7 Module Organization +# bits[2:0]: 1 = 8 bits +# bits[2:0]: 2 = 16 bits +# bits[5:3]: 0 = 1 Rank +# bits[7:6]: reserved +01 + +# 8 Module Memory Bus Width +# bits[2:0]: 3 = Primary bus width is 64 bits +# bits[4:3]: 0 = 0 bits (no bus width extension) +# bits[4:3]: 1 = 8 bits (for ECC) +# bits[7:5]: reserved +0B + +# 9 Fine Timebase (FTB) Dividend / Divisor +# bits[3:0]: 0x02 divisor +# bits[7:4]: 0x05 dividend +# 5 / 2 = 2.5 ps +52 + +# 10 Medium Timebase (MTB) Dividend +# 11 Medium Timebase (MTB) Divisor +# 1 / 8 = .125 ns +01 08 + +# 12 SDRAM Minimum Cycle Time (tCKmin) +# 0x0a = tCKmin of 1.25 ns = DDR3-1600 (800 MHz clock) +# 0x0c = tCKmin of 1.5 ns = DDR3-1333 (667 MHz clock) +# 0x0c = tCKmin of 1.5 ns = in multiples of MTB +0C + +# 13 Reserved +00 + +# 14 CAS Latencies Supported, Least Significant Byte +# 15 CAS Latencies Supported, Most Significant Byte +# Cas Latencies of 11 - 5 are supported +7E 00 + +# 16 Minimum CAS Latency Time (tAAmin) +# 0x6C = 13.5ns - DDR3-1333 +# 0x69 = 13.125 ns - DDR3-1333 +69 + +# 17 Minimum Write Recovery Time (tWRmin) +# 0x78 = tWR of 15ns - All DDR3 speed grades +78 + +# 18 Minimum RAS# to CAS# Delay Time (tRCDmin) +# 0x6E = 13.5ns - DDR3-1333 +# 0x69 = 13.125 ns - DDR3-1333 +69 + +# 19 Minimum Row Active to Row Active Delay Time (tRRDmin) +# 0x30 = 6ns +# 0x38 = 7.0ns +# 0x3C = 7.5ns +30 + +# 20 Minimum Row Precharge Delay Time (tRPmin) +# 0x6C = 13.5ns - +# 0x69 = 13.125 ns - DDR3-1333 +69 + +# 21 Upper Nibbles for tRAS and tRC +# bits[3:0]: tRAS most significant nibble = 1 (see byte 22) +# bits[7:4]: tRC most significant nibble = 1 (see byte 23) +11 + +# 22 Minimum Active to Precharge Delay Time (tRASmin), LSB +# 0x120 = 36ns - DDR3-1333 (see byte 21) +# 0x120 = 36ns - DDR3 +20 + +# 23 Minimum Active to Active/Refresh Delay Time (tRCmin), LSB +# 0x28C = 49.5ns - DDR3-1333 +# 0x289 = 49.125ns - DDR3-1333 +89 + +# 24 Minimum Refresh Recovery Delay Time (tRFCmin), LSB +# 25 Minimum Refresh Recovery Delay Time (tRFCmin), MSB +# 0x500 = 160ns - for 2 Gigabit chips +# 0x820 = 260ns - for 4 Gigabit chips +20 08 + +# 26 Minimum Internal Write to Read Command Delay Time (tWTRmin) +# 0x3c = 7.5 ns - All DDR3 SDRAM speed bins +3C + +# 27 Minimum Internal Read to Precharge Command Delay Time (tRTPmin) +# 0x3c = 7.5ns - All DDR3 SDRAM speed bins +3C + +# 28 Upper Nibble for tFAWmin +# 29 Minimum Four Activate Window Delay Time (tFAWmin) +# 0x00F0 = 30ns - DDR3-1333, 1 KB page size +00 F0 + +# 30 SDRAM Optional Feature +# bit0 : 1= RZQ/6 supported +# bit1 : 1 = RZQ/7 supported +# bits[6:2]: reserved +# bit7 : 1 = DLL Off mode supported +83 + +# 31 SDRAM Thermal and Refresh Options +# bit0 : 1 = Temp up to 95c supported +# bit1 : 0 = 85-95c uses 2x refresh rate +# bit2 : 1 = Auto Self Refresh supported +# bit3 : 0 = no on die thermal sensor +# bits[6:4]: reserved +# bit7 : 0 = partial self refresh supported +01 + +# 32 Module Thermal Sensor +# 0 = Thermal sensor not incorporated onto this assembly +00 + +# 33 SDRAM Device Type +# bits[1:0]: 0 = Signal Loading not specified +# bits[3:2]: reserved +# bits[6:4]: 0 = Die count not specified +# bit7 : 0 = Standard Monolithic DRAM Device +00 + +# 34 Fine Offset for SDRAM Minimum Cycle Time (tCKmin) +00 +# 35 Fine Offset for Minimum CAS Latency Time (tAAmin) +00 +# 36 Fine Offset for Minimum RAS# to CAS# Delay Time (tRCDmin) +00 +# 37 Fine Offset for Minimum Row Precharge Delay Time (tRPmin) +00 +# 38 Fine Offset for Minimum Active to Active/Refresh Delay (tRCmin) +00 + +# 39 40 (reserved) +00 00 + +# 41 tMAW, MAC +# 8K*tREFI / 200k +86 + +# 42 - 47 (reserved) +00 00 00 00 00 00 + +# 48 - 55 (reserved) +00 00 00 00 00 00 00 00 + +# 56 - 59 (reserved) +00 00 00 00 + +# 60 Raw Card Extension, Module Nominal Height +# bits[4:0]: 0 = <= 15mm tall +# bits[7:5]: 0 = raw card revision 0-3 +00 + +# 61 Module Maximum Thickness +# bits[3:0]: 0 = thickness front <= 1mm +# bits[7:4]: 0 = thinkness back <= 1mm +00 + +# 62 Reference Raw Card Used +# bits[4:0]: 0 = Reference Raw card A used +# bits[6:5]: 0 = revision 0 +# bit7 : 0 = Reference raw cards A through AL +# revision B4 +61 + +# 63 Address Mapping from Edge Connector to DRAM +# bit0 : 0 = standard mapping (not mirrored) +# bits[7:1]: reserved +00 + +# 64 - 71 (reserved) +00 00 00 00 00 00 00 00 + +# 72 - 79 (reserved) +00 00 00 00 00 00 00 00 + +# 80 - 87 (reserved) +00 00 00 00 00 00 00 00 + +# 88 - 95 (reserved) +00 00 00 00 00 00 00 00 + +# 96 - 103 (reserved) +00 00 00 00 00 00 00 00 + +# 104 - 111 (reserved) +00 00 00 00 00 00 00 00 + +# 112 - 116 (reserved) +00 00 00 00 00 + +# 117 - 118 Module ID: Module Manufacturers JEDEC ID Code +# 0x0001 = AMD +00 01 + +# 119 Module ID: Module Manufacturing Location - oem specified +00 + +# 120 Module ID: Module Manufacture Year in BCD +# 0x15 = 2015 +# 121 Module ID: Module Manufacture week +# 0x44 = 44th week +15 44 + +# 122 - 125: Module Serial Number +00 00 00 00 + +# 126 - 127: Cyclical Redundancy Code +67 94 diff --git a/src/mainboard/pcengines/apu2/spd/HYNIX-4G-1333-NOECC.spd.hex b/src/mainboard/pcengines/apu2/spd/HYNIX-4G-1333-NOECC.spd.hex new file mode 100644 index 0000000..7daa938 --- /dev/null +++ b/src/mainboard/pcengines/apu2/spd/HYNIX-4G-1333-NOECC.spd.hex @@ -0,0 +1,258 @@ +# HYNIX-4GBYTE-1333 The H9 N0 SPD delivered by Hynix + +# SPD contents for APU 4GB DDR3 NO ECC (1333MHz PC1333) soldered down +# 0 Number of SPD Bytes used / Total SPD Size / CRC Coverage +# bits[3:0]: 1 = 128 SPD Bytes Used +# bits[6:4]: 1 = 256 SPD Bytes Total +# bit7 : 0 = CRC covers bytes 0 ~ 128 +01 + +# 1 SPD Revision - +# 0x13 = Revision 1.3 +13 + +# 2 Key Byte / DRAM Device Type +# bits[7:0]: 0x0b = DDR3 SDRAM +0B + +# 3 Key Byte / Module Type +# bits[3:0]: 3 = SO-DIMM +# bits[3:0]: 8 = 72b-SO-DIMM +# bits[7:4]: reserved +03 + +# 4 SDRAM CHIP Density and Banks +# bits[3:0]: 3 = 2 Gigabits Total SDRAM capacity per chip +# bits[3:0]: 4 = 4 Gigabits Total SDRAM capacity per chip +# bits[6:4]: 0 = 3 (8 banks) +# bit7 : reserved +04 + +# 5 SDRAM Addressing +# bits[2:0]: 1 = 10 Column Address Bits +# bits[5:3]: 4 = 16 Row Address Bits +# bits[5:3]: 3 = 15 Row Address Bits +# bits[5:3]: 2 = 14 Row Address Bits +# bits[7:6]: reserved +21 + +# 6 Module Nominal Voltage, VDD +# bit0 : 0 = 1.5 V operable +# bit1 : 0 = NOT 1.35 V operable +# bit2 : 0 = NOT 1.25 V operable +# bits[7:3]: reserved +00 + +# 7 Module Organization +# bits[2:0]: 1 = 8 bits +# bits[2:0]: 2 = 16 bits +# bits[5:3]: 0 = 1 Rank +# bits[7:6]: reserved +01 + +# 8 Module Memory Bus Width +# bits[2:0]: 3 = Primary bus width is 64 bits +# bits[4:3]: 0 = 0 bits (no bus width extension) +# bits[4:3]: 1 = 8 bits (for ECC) +# bits[7:5]: reserved +03 + +# 9 Fine Timebase (FTB) Dividend / Divisor +# bits[3:0]: 0x02 divisor +# bits[7:4]: 0x05 dividend +# 5 / 2 = 2.5 ps +52 + +# 10 Medium Timebase (MTB) Dividend +# 11 Medium Timebase (MTB) Divisor +# 1 / 8 = .125 ns +01 08 + +# 12 SDRAM Minimum Cycle Time (tCKmin) +# 0x0a = tCKmin of 1.25 ns = DDR3-1600 (800 MHz clock) +# 0x0c = tCKmin of 1.5 ns = DDR3-1333 (667 MHz clock) +# 0x0c = tCKmin of 1.5 ns = in multiples of MTB +0C + +# 13 Reserved +00 + +# 14 CAS Latencies Supported, Least Significant Byte +# 15 CAS Latencies Supported, Most Significant Byte +# Cas Latencies of 11 - 5 are supported +7E 00 + +# 16 Minimum CAS Latency Time (tAAmin) +# 0x6C = 13.5ns - DDR3-1333 +# 0x69 = 13.125 ns - DDR3-1333 +69 + +# 17 Minimum Write Recovery Time (tWRmin) +# 0x78 = tWR of 15ns - All DDR3 speed grades +78 + +# 18 Minimum RAS# to CAS# Delay Time (tRCDmin) +# 0x6E = 13.5ns - DDR3-1333 +# 0x69 = 13.125 ns - DDR3-1333 +69 + +# 19 Minimum Row Active to Row Active Delay Time (tRRDmin) +# 0x30 = 6ns +# 0x38 = 7.0ns +# 0x3C = 7.5ns +30 + +# 20 Minimum Row Precharge Delay Time (tRPmin) +# 0x6C = 13.5ns - +# 0x69 = 13.125 ns - DDR3-1333 +69 + +# 21 Upper Nibbles for tRAS and tRC +# bits[3:0]: tRAS most significant nibble = 1 (see byte 22) +# bits[7:4]: tRC most significant nibble = 1 (see byte 23) +11 + +# 22 Minimum Active to Precharge Delay Time (tRASmin), LSB +# 0x120 = 36ns - DDR3-1333 (see byte 21) +# 0x120 = 36ns - DDR3 +20 + +# 23 Minimum Active to Active/Refresh Delay Time (tRCmin), LSB +# 0x28C = 49.5ns - DDR3-1333 +# 0x289 = 49.125ns - DDR3-1333 +89 + +# 24 Minimum Refresh Recovery Delay Time (tRFCmin), LSB +# 25 Minimum Refresh Recovery Delay Time (tRFCmin), MSB +# 0x500 = 160ns - for 2 Gigabit chips +# 0x820 = 260ns - for 4 Gigabit chips +20 08 + +# 26 Minimum Internal Write to Read Command Delay Time (tWTRmin) +# 0x3c = 7.5 ns - All DDR3 SDRAM speed bins +3C + +# 27 Minimum Internal Read to Precharge Command Delay Time (tRTPmin) +# 0x3c = 7.5ns - All DDR3 SDRAM speed bins +3C + +# 28 Upper Nibble for tFAWmin +# 29 Minimum Four Activate Window Delay Time (tFAWmin) +# 0x00F0 = 30ns - DDR3-1333, 1 KB page size +00 F0 + +# 30 SDRAM Optional Feature +# bit0 : 1= RZQ/6 supported +# bit1 : 1 = RZQ/7 supported +# bits[6:2]: reserved +# bit7 : 1 = DLL Off mode supported +83 + +# 31 SDRAM Thermal and Refresh Options +# bit0 : 1 = Temp up to 95c supported +# bit1 : 0 = 85-95c uses 2x refresh rate +# bit2 : 1 = Auto Self Refresh supported +# bit3 : 0 = no on die thermal sensor +# bits[6:4]: reserved +# bit7 : 0 = partial self refresh supported +01 + +# 32 Module Thermal Sensor +# 0 = Thermal sensor not incorporated onto this assembly +00 + +# 33 SDRAM Device Type +# bits[1:0]: 0 = Signal Loading not specified +# bits[3:2]: reserved +# bits[6:4]: 0 = Die count not specified +# bit7 : 0 = Standard Monolithic DRAM Device +00 + +# 34 Fine Offset for SDRAM Minimum Cycle Time (tCKmin) +00 +# 35 Fine Offset for Minimum CAS Latency Time (tAAmin) +00 +# 36 Fine Offset for Minimum RAS# to CAS# Delay Time (tRCDmin) +00 +# 37 Fine Offset for Minimum Row Precharge Delay Time (tRPmin) +00 +# 38 Fine Offset for Minimum Active to Active/Refresh Delay (tRCmin) +00 + +# 39 40 (reserved) +00 00 + +# 41 tMAW, MAC +# 8K*tREFI / 200k +86 + +# 42 - 47 (reserved) +00 00 00 00 00 00 + +# 48 - 55 (reserved) +00 00 00 00 00 00 00 00 + +# 56 - 59 (reserved) +00 00 00 00 + +# 60 Raw Card Extension, Module Nominal Height +# bits[4:0]: 0 = <= 15mm tall +# bits[7:5]: 0 = raw card revision 0-3 +00 + +# 61 Module Maximum Thickness +# bits[3:0]: 0 = thickness front <= 1mm +# bits[7:4]: 0 = thinkness back <= 1mm +00 + +# 62 Reference Raw Card Used +# bits[4:0]: 0 = Reference Raw card A used +# bits[6:5]: 0 = revision 0 +# bit7 : 0 = Reference raw cards A through AL +# revision B4 +61 + +# 63 Address Mapping from Edge Connector to DRAM +# bit0 : 0 = standard mapping (not mirrored) +# bits[7:1]: reserved +00 + +# 64 - 71 (reserved) +00 00 00 00 00 00 00 00 + +# 72 - 79 (reserved) +00 00 00 00 00 00 00 00 + +# 80 - 87 (reserved) +00 00 00 00 00 00 00 00 + +# 88 - 95 (reserved) +00 00 00 00 00 00 00 00 + +# 96 - 103 (reserved) +00 00 00 00 00 00 00 00 + +# 104 - 111 (reserved) +00 00 00 00 00 00 00 00 + +# 112 - 116 (reserved) +00 00 00 00 00 + +# 117 - 118 Module ID: Module Manufacturers JEDEC ID Code +# 0x0001 = AMD +00 01 + +# 119 Module ID: Module Manufacturing Location - oem specified +00 + +# 120 Module ID: Module Manufacture Year in BCD +# 0x15 = 2015 +# 121 Module ID: Module Manufacture week +# 0x44 = 44th week +15 44 + +# 122 - 125: Module Serial Number +00 00 00 00 + +# 126 - 127: Cyclical Redundancy Code +09 ff diff --git a/src/southbridge/amd/pi/hudson/Makefile.inc b/src/southbridge/amd/pi/hudson/Makefile.inc index 5b5c851..e845689 100644 --- a/src/southbridge/amd/pi/hudson/Makefile.inc +++ b/src/southbridge/amd/pi/hudson/Makefile.inc @@ -39,12 +39,14 @@ ramstage-y += hda.c ramstage-y += pci.c ramstage-y += pcie.c ramstage-y += sd.c +ramstage-y += fchgpio.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += fadt.c ramstage-y += reset.c romstage-$(CONFIG_USBDEBUG_IN_ROMSTAGE) += enable_usbdebug.c ramstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c romstage-y += early_setup.c +romstage-y += fchgpio.c ifeq ($(CONFIG_HUDSON_IMC_FWM), y) romstage-y += imc.c ramstage-y += imc.c diff --git a/src/southbridge/amd/pi/hudson/early_setup.c b/src/southbridge/amd/pi/hudson/early_setup.c index f4fcf8b..512ba22 100644 --- a/src/southbridge/amd/pi/hudson/early_setup.c +++ b/src/southbridge/amd/pi/hudson/early_setup.c @@ -25,12 +25,14 @@ #include <cbmem.h> #include "hudson.h" #include "pci_devs.h" +#include <Fch/Fch.h> + +#define BIT2 0x0000000000000004ull #if IS_ENABLED(CONFIG_HUDSON_UART) #include <cpu/x86/msr.h> #include <delay.h> -#include <Fch/Fch.h> void configure_hudson_uart(void) { @@ -121,6 +123,18 @@ void hudson_lpc_port80(void) pci_write_config8(dev, 0x4a, byte); } +void hudson_clk_output_48Mhz(void) +{ + u32 data, *memptr; + + // Enable the X14M_25M_48M_OSC pin and leaving it at it's default so 48Mhz will be on ball AP13 (FT3b package) + + memptr = (u32 *)(ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG40 ); + data = *memptr; + data &= (u32)~BIT2; // clear the OSCOUT1_ClkOutputEnb to enable the 48 Mhz clock + *memptr = data; +} + void hudson_lpc_decode(void) { device_t dev; diff --git a/src/southbridge/amd/pi/hudson/fchgpio.c b/src/southbridge/amd/pi/hudson/fchgpio.c new file mode 100644 index 0000000..df3a04f --- /dev/null +++ b/src/southbridge/amd/pi/hudson/fchgpio.c @@ -0,0 +1,137 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Eltan B.V. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdint.h> +#include <arch/io.h> +#include "hudson.h" +#include "fchgpio.h" + +/*----------------------------------------------------------------------------------------*/ +/** + * ProgramFchGpioTbl - FCH Gpio table (8 bits data) + * + * @param[in] pGpioTbl - Table data pointer, this table should be terminated by a 0xFF byte + * + */ +void +HandleFchGpioTbl ( + GPIO_CONTROL *pGpioTbl + ) +{ + if (pGpioTbl != NULL) { + + while (pGpioTbl->GpioPin != 0xFF) { + + ConfigureFchGpio( pGpioTbl->GpioPin, pGpioTbl->PinFunction, pGpioTbl->CfgByte ); + pGpioTbl++; + } + } +} + +/*----------------------------------------------------------------------------------------*/ +/** + * ConfigureFchGpio - FCH Gpio table (8 bits data) + * + * @param[in] pGpioTbl - Table data pointer, this table should be terminated by a 0xFF byte + * + */ +void ConfigureFchGpio(u8 gpio, u8 iomux_ftn, u8 setting) +{ + if ( gpio <= MAX_GPIO ) { // Simply ignore invalid GPIO + + u8 bdata; + u8 *memptr; + + // + // First we prepare the GPIO setting and then we switch the MUX to the correct setting to prevent glitches + // + + // The GPIO register is 4 bytes. We use bit 16 to 23 for the actual GPIO function + memptr = (u8 *)(ACPI_MMIO_BASE + GPIO_BANK0_BASE + (gpio << 2) + 2 ); + bdata = *memptr; + bdata |= (setting & FCH_GPIO_OUTPUT_VALUE); + *memptr = bdata; // First write out the data value to prevent glitches + + bdata |= (setting & FCH_GPIO_ALL_CONFIG); /* set direction and data value */ + *memptr = bdata; + + memptr = (u8 *)(ACPI_MMIO_BASE + IOMUX_BASE + gpio); + *memptr = iomux_ftn; + + } +} + +u8 ReadFchGpio(u8 gpio) +{ + if ( gpio <= MAX_GPIO ) { + + u8 *memptr = (u8 *)(ACPI_MMIO_BASE + GPIO_BANK0_BASE + (gpio << 2) + 2 ); + return (*memptr & FCH_GPIO_PIN_STS) ? 1 : 0; + + } else { + + return GPIO_INVALID; // Indicate an invalid GPIO was requested + } +} + +void WriteFchGpio( u8 gpio, u8 value) +{ + if ( gpio <= MAX_GPIO ) { // Simply ignore invalid GPIO + + u8 bdata; + u8 *memptr = (u8 *)(ACPI_MMIO_BASE + GPIO_BANK0_BASE + (gpio << 2) + 2 ); + bdata = *memptr; + bdata &= ~FCH_GPIO_OUTPUT_VALUE; + if ( value ) bdata |= FCH_GPIO_OUTPUT_VALUE; + *memptr = bdata; + } +} + +void DumpGpioConfiguration( void ) +{ + int i; + + printk(BIOS_INFO, "GPIO Bank 0 Control Registers\n"); + + for ( i = 0 ; i <= 0xf8 ; i = i + 4 ) { + + printk(BIOS_INFO, "GPIOx%03x = 0x%08x \n", i, *((u32 *)(ACPI_MMIO_BASE + GPIO_BANK0_BASE + i ))); + } + + printk(BIOS_INFO, "GPIO Bank 1 Control Registers\n"); + + for ( i = 0x100 ; i <= 0x1fc ; i = i + 4 ) { + + printk(BIOS_INFO, "GPIOx%03x = 0x%08x \n", i, *((u32 *)(ACPI_MMIO_BASE + GPIO_BANK0_BASE + i ))); + } + + printk(BIOS_INFO, "GPIO Bank 2 Control Registers\n"); + + for ( i = 0x200 ; i <= 0x2dc ; i = i + 4 ) { + + printk(BIOS_INFO, "GPIOx%03x = 0x%08x \n", i, *((u32 *)(ACPI_MMIO_BASE + GPIO_BANK0_BASE + i ))); + } + + printk(BIOS_INFO, "GPIO MUX Registers\n"); + + for ( i = 0x00 ; i <= 0x26 ; i++ ) printk(BIOS_INFO, "IOMUXx%02x = %d\n", i, *((u8 *)(ACPI_MMIO_BASE + IOMUX_BASE + i ))); + for ( i = 0x40 ; i <= 0x49 ; i++ ) printk(BIOS_INFO, "IOMUXx%02x = %d\n", i, *((u8 *)(ACPI_MMIO_BASE + IOMUX_BASE + i ))); + for ( i = 0x4C ; i <= 0x4D ; i++ ) printk(BIOS_INFO, "IOMUXx%02x = %d\n", i, *((u8 *)(ACPI_MMIO_BASE + IOMUX_BASE + i ))); + for ( i = 0x54 ; i <= 0x55 ; i++ ) printk(BIOS_INFO, "IOMUXx%02x = %d\n", i, *((u8 *)(ACPI_MMIO_BASE + IOMUX_BASE + i ))); + for ( i = 0x57 ; i <= 0x65 ; i++ ) printk(BIOS_INFO, "IOMUXx%02x = %d\n", i, *((u8 *)(ACPI_MMIO_BASE + IOMUX_BASE + i ))); + for ( i = 0x71 ; i <= 0x74 ; i++ ) printk(BIOS_INFO, "IOMUXx%02x = %d\n", i, *((u8 *)(ACPI_MMIO_BASE + IOMUX_BASE + i ))); + for ( i = 0x7E ; i <= 0x7E ; i++ ) printk(BIOS_INFO, "IOMUXx%02x = %d\n", i, *((u8 *)(ACPI_MMIO_BASE + IOMUX_BASE + i ))); + for ( i = 0x81 ; i <= 0x84 ; i++ ) printk(BIOS_INFO, "IOMUXx%02x = %d\n", i, *((u8 *)(ACPI_MMIO_BASE + IOMUX_BASE + i ))); +} diff --git a/src/southbridge/amd/pi/hudson/fchgpio.h b/src/southbridge/amd/pi/hudson/fchgpio.h new file mode 100644 index 0000000..717f5e5 --- /dev/null +++ b/src/southbridge/amd/pi/hudson/fchgpio.h @@ -0,0 +1,44 @@ +/* + * This file is part of the coreboot project. + + * + * Copyright (C) 2015 Eltan B.V. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <agesawrapper.h> +#include "FchPlatform.h" + +#define GPIO_DEFINITION(gpio, function, outputenable, output, pullup, pulldown) \ +{gpio, function, (outputenable << 7) | (output << 6) | (pullup << 4) | (pulldown << 5) } + +void HandleFchGpioTbl ( GPIO_CONTROL *pGpioTbl ); +void ConfigureFchGpio(u8 gpio, u8 iomux_ftn, u8 setting); +u8 ReadFchGpio(u8 gpio); +void WriteFchGpio(u8 gpio, u8 setting); +void DumpGpioConfiguration( void ); + +#define GPIO_DATA_LOW 0 +#define GPIO_DATA_HIGH 1 +#define GPIO_INVALID 0xFF + +#define MAX_GPIO 183 // Maximum GPIO supported + +// +// FCH MMIO Base (GPIO BANK0) +// offset : 0x1500 +// +#define FCH_GPIO_PIN_STS BIT0 // Bit 16 +#define FCH_GPIO_PULL_UP_ENABLE BIT4 // Bit 20 +#define FCH_GPIO_PULL_DOWN_ENABLE BIT5 // Bit 21 +#define FCH_GPIO_OUTPUT_VALUE BIT6 // Bit 22 +//#define FCH_GPIO_OUTPUT_ENABLE BIT7 // Bit 23 +#define FCH_GPIO_ALL_CONFIG (FCH_GPIO_PULL_UP_ENABLE | FCH_GPIO_PULL_DOWN_ENABLE |FCH_GPIO_OUTPUT_VALUE | FCH_GPIO_OUTPUT_ENABLE)

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit March 2016