coreboot-gerrit March 2016

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Patch set updated for coreboot: soc/intel/apollolake: utilize postcar phase/stage
by Aaron Durbin 19 Mar '16

19 Mar '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14141 -gerrit commit ea8a35b621181bd5d038cd9423e30a9df12dbcb6 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Mar 18 11:19:38 2016 -0500 soc/intel/apollolake: utilize postcar phase/stage The current Apollolake flow has its code executing out of cache-as-ram for the pre-DRAM stages. This is different from past platforms where they were just executing-in-place against the memory-mapped SPI flash boot media. The implication is that when cache-as-ram needs to be torn down one needs to be executing out of DRAM since the act of cache-as-ram going away means the code disappears out from under the processor. Therefore load and use the postcar infrastructure to bootstap this process for tearing down cache-as-ram and subsequently loading ramstage. Change-Id: I856f4b992dd2609b95375767bfa4fe64a267d89e Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/soc/intel/apollolake/Kconfig | 1 + src/soc/intel/apollolake/Makefile.inc | 5 +++ src/soc/intel/apollolake/bootblock/cache_as_ram.S | 7 ++-- src/soc/intel/apollolake/exit_car.S | 47 +++++++++++++++++++++++ src/soc/intel/apollolake/include/soc/cpu.h | 8 ++-- src/soc/intel/apollolake/include/soc/pci_devs.h | 2 +- src/soc/intel/apollolake/romstage.c | 7 +++- 7 files changed, 68 insertions(+), 9 deletions(-) diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index a11c5a2..efebe51 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -28,6 +28,7 @@ config CPU_SPECIFIC_OPTIONS select PCIEXP_COMMON_CLOCK select PCIEXP_CLK_PM select PCIEXP_L1_SUB_STATE + select POSTCAR_STAGE select REG_SCRIPT select RELOCATABLE_RAMSTAGE # Build fails if this is not selected select SOC_INTEL_COMMON diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index 4e05726..cac9100 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -35,6 +35,11 @@ ramstage-y += mmap_boot.c ramstage-y += uart.c ramstage-y += northbridge.c +postcar-y += exit_car.S +postcar-y += memmap.c +postcar-y += mmap_boot.c +postcar-$(CONFIG_SOC_UART_DEBUG) += uart_early.c + CPPFLAGS_common += -I$(src)/soc/intel/apollolake/include endif diff --git a/src/soc/intel/apollolake/bootblock/cache_as_ram.S b/src/soc/intel/apollolake/bootblock/cache_as_ram.S index c81fe0a..cc021dc 100644 --- a/src/soc/intel/apollolake/bootblock/cache_as_ram.S +++ b/src/soc/intel/apollolake/bootblock/cache_as_ram.S @@ -16,8 +16,7 @@ #include <cpu/x86/cache.h> #include <cpu/x86/cr.h> #include <cpu/x86/post_code.h> - -#define EVICT_CTL_MSR 0x2e0 +#include <soc/cpu.h> .global bootblock_pre_c_entry bootblock_pre_c_entry: @@ -96,7 +95,7 @@ clear_var_mtrr: mov %eax, %cr0 /* Disable cache eviction (setup stage) */ - mov $EVICT_CTL_MSR, %ecx + mov $MSR_EVICT_CTL, %ecx rdmsr or $0x1, %eax wrmsr @@ -112,7 +111,7 @@ clear_var_mtrr: post_code(0x27) /* Disable cache eviction (run stage) */ - mov $EVICT_CTL_MSR, %ecx + mov $MSR_EVICT_CTL, %ecx rdmsr or $0x2, %eax wrmsr diff --git a/src/soc/intel/apollolake/exit_car.S b/src/soc/intel/apollolake/exit_car.S new file mode 100644 index 0000000..339242b --- /dev/null +++ b/src/soc/intel/apollolake/exit_car.S @@ -0,0 +1,47 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <cpu/x86/mtrr.h> +#include <cpu/x86/cr.h> +#include <soc/cpu.h> + +.text +.global chipset_teardown_car +chipset_teardown_car: + /* + * Retrieve return address from stack as it will get trashed below if + * execution is utilizing the cache-as-ram stack. + */ + pop %ebx + + /* invalidate cache contents. */ + invd + /* Disable MTRRs. */ + mov $(MTRR_DEF_TYPE_MSR), %ecx + rdmsr + and $(~(MTRR_DEF_TYPE_EN | MTRR_DEF_TYPE_FIX_EN)), %eax + wrmsr + + /* Knock down bit 1 then bit 0 of NEM control not combining steps. */ + mov $(MSR_EVICT_CTL), %ecx + rdmsr + and $(~(1 << 1)), %eax + wrmsr + and $(~(1 << 0)), %eax + wrmsr + + /* Return to caller. */ + jmp *%ebx diff --git a/src/soc/intel/apollolake/include/soc/cpu.h b/src/soc/intel/apollolake/include/soc/cpu.h index 765be70..7c3228e 100644 --- a/src/soc/intel/apollolake/include/soc/cpu.h +++ b/src/soc/intel/apollolake/include/soc/cpu.h @@ -13,19 +13,21 @@ #ifndef _SOC_APOLLOLAKE_CPU_H_ #define _SOC_APOLLOLAKE_CPU_H_ +#ifndef __ASSEMBLER__ #include <cpu/x86/msr.h> #include <device/device.h> +void apollolake_init_cpus(struct device *dev); +#endif + #define CPUID_APOLLOLAKE_A0 0x506c8 #define CPUID_APOLLOLAKE_B0 0x506c9 #define MSR_PLATFORM_INFO 0xce #define MSR_POWER_MISC 0x120 #define MSR_CORE_THREAD_COUNT 0x35 +#define MSR_EVICT_CTL 0x2e0 #define BASE_CLOCK_MHZ 100 -void apollolake_init_cpus(struct device *dev); - - #endif /* _SOC_APOLLOLAKE_CPU_H_ */ diff --git a/src/soc/intel/apollolake/include/soc/pci_devs.h b/src/soc/intel/apollolake/include/soc/pci_devs.h index 3116389..2a65a22 100644 --- a/src/soc/intel/apollolake/include/soc/pci_devs.h +++ b/src/soc/intel/apollolake/include/soc/pci_devs.h @@ -7,7 +7,7 @@ #define _LPSS_PCI_DEVFN(slot, func) PCI_DEVFN(LPSS_DEV_SLOT_##slot, func) -#if ENV_RAMSTAGE +#if !defined(__SIMPLE_DEVICE__) #include <device/device.h> #include <device/pci_def.h> #define _NB_DEV(slot) dev_find_slot(0, _NB_DEVFN(slot)) diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c index 7c8924d..d24cdf8 100644 --- a/src/soc/intel/apollolake/romstage.c +++ b/src/soc/intel/apollolake/romstage.c @@ -11,6 +11,7 @@ * (at your option) any later version. */ +#include <arch/cpu.h> #include <arch/io.h> #include <arch/symbols.h> #include <cbfs.h> @@ -80,6 +81,7 @@ asmlinkage void car_stage_entry(void) void *hob_list_ptr; struct range_entry fsp_mem; struct range_entry reg_car; + struct postcar_frame pcf; printk(BIOS_DEBUG, "Starting romstage...\n"); @@ -109,7 +111,10 @@ asmlinkage void car_stage_entry(void) /* Now that CBMEM is up, save the list so ramstage can use it */ fsp_save_hob_list(hob_list_ptr); - run_ramstage(); + if (postcar_frame_init(&pcf, 1*KiB)) + die("Unable to initialize postcar frame.\n"); + + run_postcar_phase(&pcf); } static void fill_console_params(struct FSPM_UPD *mupd)

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Patch set updated for coreboot: arch/x86: introduce postcar stage/phase
by Aaron Durbin 19 Mar '16

19 Mar '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14140 -gerrit commit ea0ad0c70926b6e850deabe94ad142fa92badf29 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Mar 18 12:21:23 2016 -0500 arch/x86: introduce postcar stage/phase Certain chipsets don't have a memory-mapped boot media so their code execution for stages prior to DRAM initialization is backed by SRAM or cache-as-ram. The postcar stage/phase handles the cache-as-ram situation where in order to tear down cache-as-ram one needs to be executing out of a backing store that isn't transient. By current definition, cache-as-ram is volatile and tearing it down leads to its contents disappearing. Therefore provide a shim layer, postcar, that's loaded into memory and executed which does 2 things: 1. Tears down cache-as-ram with a chipset helper function. 2. Loads and runs ramstage. Because those 2 things are executed out of ram there's no issue of the code's backing store while executing the code that tears down cache-as-ram. The current implementation makes no assumption regarding cacheability of the DRAM itself. If the chipset code wishes to cache DRAM for loading of the postcar stage/phase then it's also up to the chipset to handle any coherency issues pertaining to cache-as-ram destruction. Change-Id: Ia58efdadd0b48f20cfe7de2f49ab462306c3a19b Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- Makefile.inc | 2 +- src/arch/x86/Kconfig | 5 ++ src/arch/x86/Makefile.inc | 25 +++++++ src/arch/x86/exit_car.S | 106 ++++++++++++++++++++++++++ src/arch/x86/include/arch/cpu.h | 37 ++++++++++ src/arch/x86/memlayout.ld | 2 + src/arch/x86/postcar_loader.c | 115 +++++++++++++++++++++++++++++ src/commonlib/Makefile.inc | 4 + src/commonlib/include/commonlib/cbmem_id.h | 2 + src/console/Makefile.inc | 5 ++ src/cpu/x86/lapic/Makefile.inc | 1 + src/include/console/console.h | 2 +- src/include/memlayout.h | 12 +++ src/include/rules.h | 25 ++++++- src/lib/Makefile.inc | 27 ++++++- src/lib/program.ld | 9 ++- 16 files changed, 371 insertions(+), 8 deletions(-) diff --git a/Makefile.inc b/Makefile.inc index 87dc0f7..6be9d52 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -84,7 +84,7 @@ subdirs-y += site-local ####################################################################### # Add source classes and their build options -classes-y := ramstage romstage bootblock smm smmstub cpu_microcode libverstage verstage +classes-y := ramstage romstage bootblock postcar smm smmstub cpu_microcode libverstage verstage # Add dynamic classes for rmodules $(foreach supported_arch,$(ARCH_SUPPORTED), \ diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig index 4102b68..b174c2a 100644 --- a/src/arch/x86/Kconfig +++ b/src/arch/x86/Kconfig @@ -167,3 +167,8 @@ config ROMSTAGE_ADDR config VERSTAGE_ADDR hex default 0x2000000 + +# Use the post CAR infrastructure for tearing down cache-as-ram +# from a prgoram laoded in ram and subsequently loading ramstage. +config POSTCAR_STAGE + def_bool n diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 1ba8795..5114e5f 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -331,6 +331,7 @@ endif # CONFIG_ARCH_RAMSTAGE_X86_32 / CONFIG_ARCH_RAMSTAGE_X86_64 ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32)$(CONFIG_ARCH_ROMSTAGE_X86_64),y) +romstage-y += postcar_loader.c romstage-y += cbmem.c romstage-y += boot.c @@ -390,3 +391,27 @@ rmodules_x86_64-y += memmove.c endif endif # CONFIG_ARCH_RAMSTAGE_X86_32 / CONFIG_ARCH_RAMSTAGE_X86_64 + +$(eval $(call create_class_compiler,postcar,x86_32)) +postcar-generic-ccopts += -D__POSTCAR__ + +postcar-y += boot.c +postcar-y += cbfs_and_run.c +postcar-y += exit_car.S +postcar-y += memset.c +postcar-y += memcpy.c +postcar-y += memmove.c +postcar-y += memlayout.ld +postcar-$(CONFIG_X86_TOP4G_BOOTMEDIA_MAP) += mmap_boot.c + +$(objcbfs)/postcar.debug: $$(postcar-objs) + @printf " LINK $(subst $(obj)/,,$(@))\n" + $(LD_postcar) $(LDFLAGS_postcar) -o $@ -L$(obj) $(COMPILER_RT_FLAGS_postcar) --whole-archive --start-group $(filter-out %.ld,$^) --no-whole-archive $(COMPILER_RT_postcar) --end-group -T $(call src-to-obj,postcar,src/arch/x86/memlayout.ld) + +$(objcbfs)/postcar.elf: $(objcbfs)/postcar.debug.rmod + cp $< $@ + +cbfs-files-$(CONFIG_POSTCAR_STAGE) += $(CONFIG_CBFS_PREFIX)/postcar +$(CONFIG_CBFS_PREFIX)/postcar-file := $(objcbfs)/postcar.elf +$(CONFIG_CBFS_PREFIX)/postcar-type := stage +$(CONFIG_CBFS_PREFIX)/postcar-compression := none diff --git a/src/arch/x86/exit_car.S b/src/arch/x86/exit_car.S new file mode 100644 index 0000000..e7e2866 --- /dev/null +++ b/src/arch/x86/exit_car.S @@ -0,0 +1,106 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <cpu/x86/mtrr.h> +#include <cpu/x86/cr.h> + +.section ".module_parameters", "aw", @progbits +/* stack_top indicates the stack to pull MTRR information from. */ +stack_top: +.long 0 +.long 0 + +.text +.global _start +_start: + /* chipset_teardown_car() is expected to disable cache-as-ram. */ + call chipset_teardown_car + + /* Enable caching if not already enabled. */ + mov %cr0, %eax + and $(~(CR0_CD | CR0_NW)), %eax + mov %eax, %cr0 + + /* Ensure cache is clean. */ + invd + + /* Set up new stack. */ + mov stack_top, %esp + + /* + * Honor MTRR information pushed on the stack with the following + * layout: + * + * Offset: Value + * ... + * 0x14: MTRR mask 0 63:32 + * 0x10: MTRR mask 0 31:0 + * 0x0c: MTRR base 0 63:32 + * 0x08: MTRR base 0 31:0 + * 0x04: Number of variable MTRRs to set + * 0x00: Number of variable MTRRs to clear + */ + + /* Clear variable MTRRs. */ + pop %ebx /* Number to clear */ + test %ebx, %ebx + jz 2f + xor %eax, %eax + xor %edx, %edx + mov $(MTRR_PHYS_BASE(0)), %ecx +1: + wrmsr + inc %ecx + wrmsr + inc %ecx + dec %ebx + jnz 1b +2: + + /* Set Variable MTRRs based on stack contents. */ + pop %ebx /* Number to set. */ + test %ebx, %ebx + jz 2f + mov $(MTRR_PHYS_BASE(0)), %ecx +1: + /* Write MTRR base. */ + pop %eax + pop %edx + wrmsr + inc %ecx + /* Write MTRR mask. */ + pop %eax + pop %edx + wrmsr + inc %ecx + + dec %ebx + jnz 1b +2: + + /* Enable MTRR. */ + mov $(MTRR_DEF_TYPE_MSR), %ecx + rdmsr + /* Make default type uncacheable. */ + and $(~(MTRR_DEF_TYPE_MASK)), %eax + or $(MTRR_DEF_TYPE_EN), %eax + wrmsr + + /* Load and run ramstage. */ + call copy_and_run + /* Should never return. */ +1: + jmp 1b diff --git a/src/arch/x86/include/arch/cpu.h b/src/arch/x86/include/arch/cpu.h index f50901f..87663a7 100644 --- a/src/arch/x86/include/arch/cpu.h +++ b/src/arch/x86/include/arch/cpu.h @@ -15,6 +15,7 @@ #define ARCH_CPU_H #include <stdint.h> +#include <stddef.h> #include <rules.h> /* @@ -246,6 +247,42 @@ static inline void get_fms(struct cpuinfo_x86 *c, uint32_t tfms) * cache-as-ram. */ void asmlinkage car_stage_entry(void); + +/* + * Support setting up a stack frame consisting of MTRR information + * for use in bootstrapping the caching attributes after cache-as-ram + * is torn down. + */ + +struct postcar_frame { + uintptr_t stack; + uint32_t upper_mask; + int max_var_mttrs; + int num_var_mttrs; +}; + +/* + * Initialize postcar_frame object allocating stack size in cbmem + * with the provided size. Returns 0 on success, < 0 on error. + */ +int postcar_frame_init(struct postcar_frame *pcf, size_t stack_size); + +/* + * Add variable MTRR covering the provided range with MTRR type. + */ +void postcar_frame_add_mtrr(struct postcar_frame *pcf, + uintptr_t addr, size_t size, int type); + +/* + * Load and run a program that takes control of execution that + * tears down CAR and loads ramstage. The postcar_frame object + * indicates how to set up the frame. If caching is enabled at + * the time of the call it is up to the platform code to handle + * coherency with dirty lines in the cache using some mechansim + * such as platform_prog_run() becaus run_postcar_phase() + * utilizes prog_run() internally. + */ +void run_postcar_phase(struct postcar_frame *pcf); #endif #endif /* ARCH_CPU_H */ diff --git a/src/arch/x86/memlayout.ld b/src/arch/x86/memlayout.ld index 56611041..e6db0b8 100644 --- a/src/arch/x86/memlayout.ld +++ b/src/arch/x86/memlayout.ld @@ -51,6 +51,8 @@ SECTIONS /* Pull in the cache-as-ram rules. */ #include "car.ld" +#elif ENV_POSTCAR + POSTCAR(32M, 1M) #endif } diff --git a/src/arch/x86/postcar_loader.c b/src/arch/x86/postcar_loader.c new file mode 100644 index 0000000..580cc45 --- /dev/null +++ b/src/arch/x86/postcar_loader.c @@ -0,0 +1,115 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/cpu.h> +#include <cbmem.h> +#include <console/console.h> +#include <cpu/x86/msr.h> +#include <cpu/x86/mtrr.h> +#include <program_loading.h> +#include <rmodule.h> + +static inline void stack_push(struct postcar_frame *pcf, uint32_t val) +{ + uint32_t *ptr; + + pcf->stack -= sizeof(val); + ptr = (void *)pcf->stack; + *ptr = val; +} + +int postcar_frame_init(struct postcar_frame *pcf, size_t stack_size) +{ + void *stack; + msr_t msr; + + msr = rdmsr(MTRR_CAP_MSR); + + stack = cbmem_add(CBMEM_ID_ROMSTAGE_RAM_STACK, stack_size); + if (stack == NULL) { + printk(BIOS_ERR, "Couldn't add %zd byte stack in cbmem.\n", + stack_size); + return -1; + } + + pcf->stack = (uintptr_t)stack; + pcf->stack += stack_size; + + pcf->upper_mask = (1 << (cpu_phys_address_size() - 32)) - 1; + + pcf->max_var_mttrs = msr.lo & MTRR_CAP_VCNT; + + pcf->num_var_mttrs = 0; + + return 0; +} + +void postcar_frame_add_mtrr(struct postcar_frame *pcf, + uintptr_t addr, size_t size, int type) +{ + size_t align; + + if (pcf->num_var_mttrs >= pcf->max_var_mttrs) { + printk(BIOS_ERR, "No more variable MTRRs: %d\n", + pcf->max_var_mttrs); + return; + } + + /* Determine address alignment by lowest bit set in address. */ + align = addr & (addr ^ (addr - 1)); + + if (align < size) { + printk(BIOS_ERR, "Address (%lx) alignment (%zx) < size (%zx)\n", + addr, align, size); + size = align; + } + + /* Push MTRR mask then base -- upper 32-bits then lower 32-bits. */ + stack_push(pcf, pcf->upper_mask); + stack_push(pcf, ~(size - 1) | MTRR_PHYS_MASK_VALID); + stack_push(pcf, 0); + stack_push(pcf, addr | type); + pcf->num_var_mttrs++; +} + +void run_postcar_phase(struct postcar_frame *pcf) +{ + struct prog prog = + PROG_INIT(PROG_UNKNOWN, CONFIG_CBFS_PREFIX "/postcar"); + struct rmod_stage_load rsl = { + .cbmem_id = CBMEM_ID_AFTER_CAR, + .prog = &prog, + }; + + /* + * Place the number of used variable MTRRs on stack then max number + * of variable MTRRs supported in the system. + */ + stack_push(pcf, pcf->num_var_mttrs); + stack_push(pcf, pcf->max_var_mttrs); + + if (prog_locate(&prog)) + die("Failed to locate after CAR program.\n"); + if (rmodule_stage_load(&rsl)) + die("Failed to load after CAR program.\n"); + + /* Set the stack pointer within parameters of the program loaded. */ + if (rsl.params == NULL) + die("No parameters found in after CAR program.\n"); + + *(uintptr_t *)rsl.params = pcf->stack; + + prog_run(&prog); +} diff --git a/src/commonlib/Makefile.inc b/src/commonlib/Makefile.inc index 2752922..7c14f7c 100644 --- a/src/commonlib/Makefile.inc +++ b/src/commonlib/Makefile.inc @@ -2,12 +2,14 @@ bootblock-y += mem_pool.c verstage-y += mem_pool.c romstage-y += mem_pool.c ramstage-y += mem_pool.c +postcar-y += mem_pool.c bootblock-y += region.c verstage-y += region.c romstage-y += region.c ramstage-y += region.c smm-y += region.c +postcar-y += region.c ramstage-$(CONFIG_PLATFORM_USES_FSP1_1) += fsp1_1_relocate.c @@ -16,8 +18,10 @@ verstage-y += cbfs.c romstage-y += cbfs.c ramstage-y += cbfs.c smm-y += cbfs.c +postcar-y += cbfs.c bootblock-y += lz4_wrapper.c verstage-y += lz4_wrapper.c romstage-y += lz4_wrapper.c ramstage-y += lz4_wrapper.c +postcar-y += lz4_wrapper.c diff --git a/src/commonlib/include/commonlib/cbmem_id.h b/src/commonlib/include/commonlib/cbmem_id.h index 46c5d49..adeb291 100644 --- a/src/commonlib/include/commonlib/cbmem_id.h +++ b/src/commonlib/include/commonlib/cbmem_id.h @@ -20,6 +20,7 @@ #define CBMEM_ID_ACPI 0x41435049 #define CBMEM_ID_ACPI_GNVS 0x474e5653 #define CBMEM_ID_ACPI_GNVS_PTR 0x474e5650 +#define CBMEM_ID_AFTER_CAR 0xc4787a93 #define CBMEM_ID_AGESA_RUNTIME 0x41474553 #define CBMEM_ID_AMDMCT_MEMINFO 0x494D454E #define CBMEM_ID_CAR_GLOBALS 0xcac4e6a3 @@ -71,6 +72,7 @@ { CBMEM_ID_ACPI_GNVS, "ACPI GNVS " }, \ { CBMEM_ID_ACPI_GNVS_PTR, "GNVS PTR " }, \ { CBMEM_ID_AGESA_RUNTIME, "AGESA RSVD " }, \ + { CBMEM_ID_AFTER_CAR, "AFTER CAR" }, \ { CBMEM_ID_AMDMCT_MEMINFO, "AMDMEM INFO" }, \ { CBMEM_ID_CAR_GLOBALS, "CAR GLOBALS" }, \ { CBMEM_ID_CBTABLE, "COREBOOT " }, \ diff --git a/src/console/Makefile.inc b/src/console/Makefile.inc index 94b456c..0fee12a 100644 --- a/src/console/Makefile.inc +++ b/src/console/Makefile.inc @@ -18,6 +18,11 @@ romstage-y += init.c console.c romstage-y += post.c romstage-y += die.c +postcar-y += vtxprintf.c printk.c +postcar-y += init.c console.c +postcar-y += post.c +postcar-y += die.c + bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += vtxprintf.c printk.c bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += init.c console.c bootblock-y += die.c diff --git a/src/cpu/x86/lapic/Makefile.inc b/src/cpu/x86/lapic/Makefile.inc index c0a3572..9df2c5f 100644 --- a/src/cpu/x86/lapic/Makefile.inc +++ b/src/cpu/x86/lapic/Makefile.inc @@ -7,3 +7,4 @@ bootblock-y += boot_cpu.c verstage-y += boot_cpu.c romstage-y += boot_cpu.c ramstage-y += boot_cpu.c +postcar-y += boot_cpu.c diff --git a/src/include/console/console.h b/src/include/console/console.h index 7704899..ddb5c052 100644 --- a/src/include/console/console.h +++ b/src/include/console/console.h @@ -47,7 +47,7 @@ void __attribute__ ((noreturn)) die(const char *msg); #define __CONSOLE_ENABLE__ \ ((ENV_BOOTBLOCK && CONFIG_BOOTBLOCK_CONSOLE) || \ - ENV_VERSTAGE || ENV_ROMSTAGE || ENV_RAMSTAGE || \ + ENV_VERSTAGE || ENV_ROMSTAGE || ENV_RAMSTAGE || ENV_POSTCAR || \ (ENV_SMM && CONFIG_DEBUG_SMI)) #if __CONSOLE_ENABLE__ diff --git a/src/include/memlayout.h b/src/include/memlayout.h index 49aa1cc..43a1cac 100644 --- a/src/include/memlayout.h +++ b/src/include/memlayout.h @@ -160,6 +160,18 @@ #define OVERLAP_VERSTAGE_ROMSTAGE(addr, size) ROMSTAGE(addr, size) #endif +#if ENV_POSTCAR + #define POSTCAR(addr, sz) \ + SYMBOL(postcar, addr) \ + _epostcar = _postcar + sz; \ + _ = ASSERT(_eprogram - _program <= sz, \ + STR(Aftercar exceeded its allotted size! (sz))); \ + INCLUDE "postcar/lib/program.ld" +#else + #define POSTCAR(addr, sz) \ + REGION(postcar, addr, sz, 1) +#endif + #define WATCHDOG_TOMBSTONE(addr, size) \ REGION(watchdog_tombstone, addr, size, 4) \ _ = ASSERT(size == 4, "watchdog tombstones should be exactly 4 byte!"); diff --git a/src/include/rules.h b/src/include/rules.h index 6a05ae9..89fdd21 100644 --- a/src/include/rules.h +++ b/src/include/rules.h @@ -26,6 +26,7 @@ #define ENV_SMM 0 #define ENV_VERSTAGE 0 #define ENV_RMODULE 0 +#define ENV_POSTCAR 0 #define ENV_STRING "bootblock" #elif defined(__ROMSTAGE__) @@ -35,6 +36,7 @@ #define ENV_SMM 0 #define ENV_VERSTAGE 0 #define ENV_RMODULE 0 +#define ENV_POSTCAR 0 #define ENV_STRING "romstage" #elif defined(__SMM__) @@ -44,6 +46,7 @@ #define ENV_SMM 1 #define ENV_VERSTAGE 0 #define ENV_RMODULE 0 +#define ENV_POSTCAR 0 #define ENV_STRING "smm" #elif defined(__VERSTAGE__) @@ -53,6 +56,7 @@ #define ENV_SMM 0 #define ENV_VERSTAGE 1 #define ENV_RMODULE 0 +#define ENV_POSTCAR 0 #define ENV_STRING "verstage" #elif defined(__RAMSTAGE__) @@ -62,6 +66,7 @@ #define ENV_SMM 0 #define ENV_VERSTAGE 0 #define ENV_RMODULE 0 +#define ENV_POSTCAR 0 #define ENV_STRING "ramstage" #elif defined(__RMODULE__) @@ -71,8 +76,19 @@ #define ENV_SMM 0 #define ENV_VERSTAGE 0 #define ENV_RMODULE 1 +#define ENV_POSTCAR 0 #define ENV_STRING "rmodule" +#elif defined(__POSTCAR__) +#define ENV_BOOTBLOCK 0 +#define ENV_ROMSTAGE 0 +#define ENV_RAMSTAGE 0 +#define ENV_SMM 0 +#define ENV_VERSTAGE 0 +#define ENV_RMODULE 0 +#define ENV_POSTCAR 1 +#define ENV_STRING "postcar" + #else /* * Default case of nothing set for random blob generation using @@ -86,18 +102,21 @@ #define ENV_SMM 0 #define ENV_VERSTAGE 0 #define ENV_RMODULE 0 +#define ENV_POSTCAR 0 #define ENV_STRING "UNKNOWN" #endif -/* For romstage and ramstage always build with simple device model, ie. - * PCI, PNP and CPU functions operate without use of devicetree. +/* For pre-DRAM stages and post-CAR always build with simple device model, ie. + * PCI, PNP and CPU functions operate without use of devicetree. The reason + * post-CAR utilizes __SIMPLE_DEVICE__ is for simplicity. Currently there's + * no known requirement that devicetree would be needed during that stage. * * For ramstage individual source file may define __SIMPLE_DEVICE__ * before including any header files to force that particular source * be built with simple device model. */ -#if defined(__PRE_RAM__) || defined(__SMM__) +#if defined(__PRE_RAM__) || ENV_SMM || ENV_POSTCAR #define __SIMPLE_DEVICE__ #endif diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 646fefa..3352a30 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -131,13 +131,16 @@ ramstage-$(CONFIG_ACPI_NHLT) += nhlt.c romstage-y += cbmem_common.c romstage-y += imd_cbmem.c +romstage-y += imd.c ramstage-y += cbmem_common.c ramstage-y += imd_cbmem.c - -romstage-y += imd.c ramstage-y += imd.c +postcar-y += cbmem_common.c +postcar-y += imd_cbmem.c +postcar-y += imd.c + bootblock-y += hexdump.c ramstage-y += hexdump.c romstage-y += hexdump.c @@ -167,12 +170,14 @@ romstage-y += version.c ramstage-y += version.c smm-y += version.c verstage-y += version.c +postcar-y += version.c $(call src-to-obj,bootblock,$(dir)/version.c) : $(obj)/build.h $(call src-to-obj,romstage,$(dir)/version.c) : $(obj)/build.h $(call src-to-obj,ramstage,$(dir)/version.c) : $(obj)/build.h $(call src-to-obj,smm,$(dir)/version.c) : $(obj)/build.h $(call src-to-obj,verstage,$(dir)/version.c) : $(obj)/build.h +$(call src-to-obj,postcar,$(dir)/version.c) : $(obj)/build.h romstage-y += bootmode.c ramstage-y += bootmode.c @@ -183,9 +188,27 @@ romstage-y += halt.c ramstage-y += halt.c smm-y += halt.c +postcar-y += bootmode.c +postcar-y += boot_device.c +postcar-y += cbfs.c +postcar-$(CONFIG_COMMON_CBFS_SPI_WRAPPER) += cbfs_spi.c +postcar-y += delay.c +postcar-y += fmap.c +postcar-y += gcc.c +postcar-y += halt.c +postcar-y += libgcc.c +postcar-$(CONFIG_COMPRESS_RAMSTAGE) += lzma.c lzmadecode.c +postcar-y += memchr.c +postcar-y += memcmp.c +postcar-y += prog_loaders.c +postcar-y += prog_ops.c +postcar-y += rmodule.c +postcar-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c + # Use program.ld for all the platforms which use C fo the bootblock. bootblock-$(CONFIG_C_ENVIRONMENT_BOOTBLOCK) += program.ld +postcar-y += program.ld romstage-y += program.ld ramstage-y += program.ld verstage-y += program.ld diff --git a/src/lib/program.ld b/src/lib/program.ld index 9b8c7c9..99afe5d 100644 --- a/src/lib/program.ld +++ b/src/lib/program.ld @@ -80,7 +80,14 @@ . = ALIGN(ARCH_CACHELINE_ALIGN_SIZE); _data = .; -#if ENV_RMODULE +/* + * The postcar phase uses a stack value that is located in the relocatable + * module section. While the postcar stage could be linked like smm and + * other rmodules the postcar stage needs similar semantics of the more + * traditional stages in the coreboot infrastructure. Therefore it's easier + * to specialize this case. + */ +#if ENV_RMODULE || ENV_POSTCAR _rmodule_params = .; KEEP(*(.module_parameters)); _ermodule_params = .;

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Patch set updated for coreboot: arch/x86: honor CONFIG_X86_TOP4G_BOOTMEDIA_MAP for verstage
by Aaron Durbin 19 Mar '16

19 Mar '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14142 -gerrit commit cd50a36730849d0f433d1eb7f7606319fe81ab29 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Mar 18 13:12:41 2016 -0500 arch/x86: honor CONFIG_X86_TOP4G_BOOTMEDIA_MAP for verstage When CONFIG_X86_TOP4G_BOOTMEDIA_MAP was introduced verstage was not updated. Correct this oversight. Change-Id: I2775c08798906ba0ba55a361407d7d2b52313229 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/arch/x86/Makefile.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 249cdd1..1ba8795 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -184,7 +184,7 @@ verstage-$(CONFIG_ARCH_RAMSTAGE_X86_32) += cpu_common.c verstage-y += memset.c verstage-y += memcpy.c verstage-y += memmove.c -verstage-y += mmap_boot.c +verstage-$(CONFIG_X86_TOP4G_BOOTMEDIA_MAP) += mmap_boot.c verstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c

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Patch set updated for coreboot: soc/intel/apollolake: Fill ACPI FADT table
by Andrey Petrov 19 Mar '16

19 Mar '16

Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13352 -gerrit commit 09858a82da95156cabb5abafe53c5b29129941dc Author: Lance Zhao <lijian.zhao(a)intel.com> Date: Tue Nov 10 19:00:18 2015 -0800 soc/intel/apollolake: Fill ACPI FADT table Fill the ACPI FADT table base on apollolake SOC definition. Change-Id: Ib7226a3b130f14810dc2af5ca484cef58f477063 Signed-off-by: Lance Zhao <lijian.zhao(a)intel.com> --- src/soc/intel/apollolake/acpi.c | 88 +++++++++++++++++++++++++++++ src/soc/intel/apollolake/include/soc/acpi.h | 20 +++++++ src/soc/intel/apollolake/include/soc/pm.h | 31 ++++++++++ 3 files changed, 139 insertions(+) diff --git a/src/soc/intel/apollolake/acpi.c b/src/soc/intel/apollolake/acpi.c new file mode 100644 index 0000000..5fd2b74 --- /dev/null +++ b/src/soc/intel/apollolake/acpi.c @@ -0,0 +1,88 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corp. + * (Written by Lance Zhao <lijian.zhao(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include <arch/acpi.h> +#include <cpu/x86/smm.h> +#include <soc/acpi.h> +#include <soc/iomap.h> +#include <soc/pm.h> + +unsigned long acpi_fill_mcfg(unsigned long current) +{ + return current; +} + +unsigned long acpi_fill_madt(unsigned long current) +{ + return current; +} + +static int acpi_sci_irq(void) +{ + int sci_irq = 9; + return sci_irq; +} + +void soc_fill_common_fadt(acpi_fadt_t * fadt) +{ + const uint16_t pmbase = ACPI_PMIO_BASE; + + fadt->sci_int = acpi_sci_irq(); + fadt->smi_cmd = 0; /* No Smi Handler as SMI_CMD is 0*/ + + fadt->pm1a_evt_blk = pmbase + PM1_STS; + fadt->pm1a_cnt_blk = pmbase + PM1_CNT; + fadt->pm_tmr_blk = pmbase + PM1_TMR; + fadt->gpe0_blk = pmbase + GPE0_STS(0); + + fadt->pm1_evt_len = 4; + fadt->pm1_cnt_len = 2; + fadt->pm_tmr_len = 4; + /* There are 4 GPE0 STS/EN pairs each 32 bits wide. */ + fadt->gpe0_blk_len = 2 * GPE0_REG_MAX * sizeof(uint32_t); + fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED; + fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED; + fadt->flush_size = 0x400; /* twice of cache size*/ + fadt->flush_stride = 0x10; /* Cache line width */ + fadt->duty_offset = 1; + fadt->duty_width = 3; + fadt->day_alrm = 0xd; + fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042; + + fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED | + ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON | + ACPI_FADT_RESET_REGISTER | ACPI_FADT_SEALED_CASE | + ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_PLATFORM_CLOCK; + + fadt->reset_reg.space_id = 1; + fadt->reset_reg.bit_width = 8; + fadt->reset_reg.addrl = 0xcf9; + fadt->reset_value = 6; + + fadt->x_pm1a_evt_blk.space_id = 1; + fadt->x_pm1a_evt_blk.bit_width = fadt->pm1_evt_len * 8; + fadt->x_pm1a_evt_blk.addrl = pmbase + PM1_STS; + + fadt->x_pm1b_evt_blk.space_id = 1; + + fadt->x_pm1a_cnt_blk.space_id = 1; + fadt->x_pm1a_cnt_blk.bit_width = fadt->pm1_cnt_len * 8; + fadt->x_pm1a_cnt_blk.addrl = pmbase + PM1_CNT; + + fadt->x_pm1b_cnt_blk.space_id = 1; + + fadt->x_pm_tmr_blk.space_id = 1; + fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8; + fadt->x_pm_tmr_blk.addrl = pmbase + PM1_TMR; + + fadt->x_gpe1_blk.space_id = 1; +} diff --git a/src/soc/intel/apollolake/include/soc/acpi.h b/src/soc/intel/apollolake/include/soc/acpi.h new file mode 100644 index 0000000..a01ac1e --- /dev/null +++ b/src/soc/intel/apollolake/include/soc/acpi.h @@ -0,0 +1,20 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Lance Zhao <lijian.zhao(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef _SOC_APOLLOLAKE_ACPI_H_ +#define _SOC_APOLLOLAKE_ACPI_H_ + +#include <arch/acpi.h> + +void soc_fill_common_fadt(acpi_fadt_t * fadt); + +#endif /* _SOC_APOLLOLAKE_ACPI_H_ */ diff --git a/src/soc/intel/apollolake/include/soc/pm.h b/src/soc/intel/apollolake/include/soc/pm.h new file mode 100644 index 0000000..77b5902 --- /dev/null +++ b/src/soc/intel/apollolake/include/soc/pm.h @@ -0,0 +1,31 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Lance Zhao <lijian.zhao(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef _SOC_APOLLOLAKE_PM_H_ +#define _SOC_APOLLOLAKE_PM_H_ + +/* ACPI_BASE_ADDRESS / PMBASE */ + +#define PM1_STS 0x00 +#define PM1_EN 0x02 +#define PM1_CNT 0x04 +#define PM1_TMR 0x08 +#define SMI_EN 0x40 +#define SMI_STS 0x44 +#define GPE_CNTL 0x50 +#define DEVACT_STS 0x4c + +#define GPE0_REG_MAX 4 +#define GPE0_STS(x) (0x20 + (x * 4)) +#define GPE0_EN(x) (0x30 + (x * 4)) + +#endif

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Patch set updated for coreboot: soc/intel/apollolake: Fill ACPI FADT table
by Lijian Zhao 19 Mar '16

19 Mar '16

Lijian Zhao (lijian.zhao(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13352 -gerrit commit 15340befa47314cfbeabecb92ea816af4b9ca9e2 Author: Lance Zhao <lijian.zhao(a)intel.com> Date: Tue Nov 10 19:00:18 2015 -0800 soc/intel/apollolake: Fill ACPI FADT table Fill the ACPI FADT table base on apollolake SOC definition. Change-Id: Ib7226a3b130f14810dc2af5ca484cef58f477063 Signed-off-by: Lance Zhao <lijian.zhao(a)intel.com> --- src/soc/intel/apollolake/acpi.c | 88 +++++++++++++++++++++++++++++ src/soc/intel/apollolake/include/soc/acpi.h | 20 +++++++ src/soc/intel/apollolake/include/soc/pm.h | 31 ++++++++++ 3 files changed, 139 insertions(+) diff --git a/src/soc/intel/apollolake/acpi.c b/src/soc/intel/apollolake/acpi.c new file mode 100644 index 0000000..d2b2305 --- /dev/null +++ b/src/soc/intel/apollolake/acpi.c @@ -0,0 +1,88 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corp. + * (Written by Lance Zhao <lijian.zhao(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include <arch/acpi.h> +#include <cpu/x86/smm.h> +#include <soc/acpi.h> +#include <soc/iomap.h> +#include <soc/pm.h> + +unsigned long acpi_fill_mcfg(unsigned long current) +{ + return current; +} + +unsigned long acpi_fill_madt(unsigned long current) +{ + return current; +} + +static int acpi_sci_irq(void) +{ + int sci_irq = 9; + return sci_irq; +} + +void soc_fill_common_fadt(acpi_fadt_t * fadt) +{ + const uint16_t pmbase = ACPI_PMIO_BASE; + + fadt->sci_int = acpi_sci_irq(); + fadt->smi_cmd = 0; /* No Smi Handler as SMI_CMD is 0*/ + + fadt->pm1a_evt_blk = pmbase + PM1_STS; + fadt->pm1a_cnt_blk = pmbase + PM1_CNT; + fadt->pm_tmr_blk = pmbase + PM1_TMR; + fadt->gpe0_blk = pmbase + GPE0_STS(0); + + fadt->pm1_evt_len = 4; + fadt->pm1_cnt_len = 2; + fadt->pm_tmr_len = 4; + /* There are 4 GPE0 STS/EN pairs each 32 bits wide. */ + fadt->gpe0_blk_len = 2 * GPE0_REG_MAX * sizeof(uint32_t); + fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED; + fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED; + fadt->flush_size = 0x400; /* twice of cache size*/ + fadt->flush_stride = 0x10; /* Cache line width */ + fadt->duty_offset = 1; + fadt->duty_width = 3; + fadt->day_alrm = 0xd; + fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042; + + fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED | + ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON | + ACPI_FADT_RESET_REGISTER | ACPI_FADT_SEALED_CASE | + ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_PLATFORM_CLOCK; + + fadt->reset_reg.space_id = 1; + fadt->reset_reg.bit_width = 8; + fadt->reset_reg.addrl = 0xcf9; + fadt->reset_value = 6; + + fadt->x_pm1a_evt_blk.space_id = 1; + fadt->x_pm1a_evt_blk.bit_width = fadt->pm1_evt_len * 8; + fadt->x_pm1a_evt_blk.addrl = pmbase + PM1_STS; + + fadt->x_pm1b_evt_blk.space_id = 1; + + fadt->x_pm1a_cnt_blk.space_id = 1; + fadt->x_pm1a_cnt_blk.bit_width = fadt->pm1_cnt_len * 8; + fadt->x_pm1a_cnt_blk.addrl = pmbase + PM1_CNT; + + fadt->x_pm1b_cnt_blk.space_id = 1; + + fadt->x_pm_tmr_blk.space_id = 1; + fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8; + fadt->x_pm_tmr_blk.addrl = pmbase + PM1_TMR; + + fadt->x_gpe1_blk.space_id = 1; +} diff --git a/src/soc/intel/apollolake/include/soc/acpi.h b/src/soc/intel/apollolake/include/soc/acpi.h new file mode 100644 index 0000000..a01ac1e --- /dev/null +++ b/src/soc/intel/apollolake/include/soc/acpi.h @@ -0,0 +1,20 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Lance Zhao <lijian.zhao(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef _SOC_APOLLOLAKE_ACPI_H_ +#define _SOC_APOLLOLAKE_ACPI_H_ + +#include <arch/acpi.h> + +void soc_fill_common_fadt(acpi_fadt_t * fadt); + +#endif /* _SOC_APOLLOLAKE_ACPI_H_ */ diff --git a/src/soc/intel/apollolake/include/soc/pm.h b/src/soc/intel/apollolake/include/soc/pm.h new file mode 100644 index 0000000..77b5902 --- /dev/null +++ b/src/soc/intel/apollolake/include/soc/pm.h @@ -0,0 +1,31 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Lance Zhao <lijian.zhao(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef _SOC_APOLLOLAKE_PM_H_ +#define _SOC_APOLLOLAKE_PM_H_ + +/* ACPI_BASE_ADDRESS / PMBASE */ + +#define PM1_STS 0x00 +#define PM1_EN 0x02 +#define PM1_CNT 0x04 +#define PM1_TMR 0x08 +#define SMI_EN 0x40 +#define SMI_STS 0x44 +#define GPE_CNTL 0x50 +#define DEVACT_STS 0x4c + +#define GPE0_REG_MAX 4 +#define GPE0_STS(x) (0x20 + (x * 4)) +#define GPE0_EN(x) (0x30 + (x * 4)) + +#endif

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Patch set updated for coreboot: soc/intel/apollolake: Fill ACPI FADT table
by Lijian Zhao 19 Mar '16

19 Mar '16

Lijian Zhao (lijian.zhao(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13352 -gerrit commit 561685e6d0d5c87d55a7290c641cd9a0f11fe738 Author: Lance Zhao <lijian.zhao(a)intel.com> Date: Tue Nov 10 19:00:18 2015 -0800 soc/intel/apollolake: Fill ACPI FADT table Fill the ACPI FADT table base on apollolake SOC definition. Change-Id: Ib7226a3b130f14810dc2af5ca484cef58f477063 Signed-off-by: Lance Zhao <lijian.zhao(a)intel.com> --- src/soc/intel/apollolake/acpi.c | 90 +++++++++++++++++++++++++++++ src/soc/intel/apollolake/include/soc/acpi.h | 20 +++++++ src/soc/intel/apollolake/include/soc/pm.h | 31 ++++++++++ 3 files changed, 141 insertions(+) diff --git a/src/soc/intel/apollolake/acpi.c b/src/soc/intel/apollolake/acpi.c new file mode 100644 index 0000000..ed260f9 --- /dev/null +++ b/src/soc/intel/apollolake/acpi.c @@ -0,0 +1,90 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corp. + * (Written by Lance Zhao <lijian.zhao(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include <arch/acpi.h> +#include <cpu/x86/smm.h> +#include <soc/acpi.h> +#include <soc/iomap.h> +#include <soc/pm.h> + +unsigned long acpi_fill_mcfg(unsigned long current) +{ + return current; +} + +unsigned long acpi_fill_madt(unsigned long current) +{ + return current; +} + +static int acpi_sci_irq(void) +{ + int sci_irq = 9; + return sci_irq; +} + +void soc_fill_common_fadt(acpi_fadt_t * fadt) +{ + const uint16_t pmbase = ACPI_PMIO_BASE; + + fadt->sci_int = acpi_sci_irq(); + fadt->smi_cmd = APM_CNT; + fadt->acpi_enable = APM_CNT_ACPI_ENABLE; + fadt->acpi_disable = APM_CNT_ACPI_DISABLE; + + fadt->pm1a_evt_blk = pmbase + PM1_STS; + fadt->pm1a_cnt_blk = pmbase + PM1_CNT; + fadt->pm_tmr_blk = pmbase + PM1_TMR; + fadt->gpe0_blk = pmbase + GPE0_STS(0); + + fadt->pm1_evt_len = 4; + fadt->pm1_cnt_len = 2; + fadt->pm_tmr_len = 4; + /* There are 4 GPE0 STS/EN pairs each 32 bits wide. */ + fadt->gpe0_blk_len = 2 * GPE0_REG_MAX * sizeof(uint32_t); + fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED; + fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED; + fadt->flush_size = 0x400; /* twice of cache size*/ + fadt->flush_stride = 0x10; /* Cache line width */ + fadt->duty_offset = 1; + fadt->duty_width = 3; + fadt->day_alrm = 0xd; + fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042; + + fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED | + ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON | + ACPI_FADT_RESET_REGISTER | ACPI_FADT_SEALED_CASE | + ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_PLATFORM_CLOCK; + + fadt->reset_reg.space_id = 1; + fadt->reset_reg.bit_width = 8; + fadt->reset_reg.addrl = 0xcf9; + fadt->reset_value = 6; + + fadt->x_pm1a_evt_blk.space_id = 1; + fadt->x_pm1a_evt_blk.bit_width = fadt->pm1_evt_len * 8; + fadt->x_pm1a_evt_blk.addrl = pmbase + PM1_STS; + + fadt->x_pm1b_evt_blk.space_id = 1; + + fadt->x_pm1a_cnt_blk.space_id = 1; + fadt->x_pm1a_cnt_blk.bit_width = fadt->pm1_cnt_len * 8; + fadt->x_pm1a_cnt_blk.addrl = pmbase + PM1_CNT; + + fadt->x_pm1b_cnt_blk.space_id = 1; + + fadt->x_pm_tmr_blk.space_id = 1; + fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8; + fadt->x_pm_tmr_blk.addrl = pmbase + PM1_TMR; + + fadt->x_gpe1_blk.space_id = 1; +} diff --git a/src/soc/intel/apollolake/include/soc/acpi.h b/src/soc/intel/apollolake/include/soc/acpi.h new file mode 100644 index 0000000..a01ac1e --- /dev/null +++ b/src/soc/intel/apollolake/include/soc/acpi.h @@ -0,0 +1,20 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Lance Zhao <lijian.zhao(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef _SOC_APOLLOLAKE_ACPI_H_ +#define _SOC_APOLLOLAKE_ACPI_H_ + +#include <arch/acpi.h> + +void soc_fill_common_fadt(acpi_fadt_t * fadt); + +#endif /* _SOC_APOLLOLAKE_ACPI_H_ */ diff --git a/src/soc/intel/apollolake/include/soc/pm.h b/src/soc/intel/apollolake/include/soc/pm.h new file mode 100644 index 0000000..77b5902 --- /dev/null +++ b/src/soc/intel/apollolake/include/soc/pm.h @@ -0,0 +1,31 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Lance Zhao <lijian.zhao(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef _SOC_APOLLOLAKE_PM_H_ +#define _SOC_APOLLOLAKE_PM_H_ + +/* ACPI_BASE_ADDRESS / PMBASE */ + +#define PM1_STS 0x00 +#define PM1_EN 0x02 +#define PM1_CNT 0x04 +#define PM1_TMR 0x08 +#define SMI_EN 0x40 +#define SMI_STS 0x44 +#define GPE_CNTL 0x50 +#define DEVACT_STS 0x4c + +#define GPE0_REG_MAX 4 +#define GPE0_STS(x) (0x20 + (x * 4)) +#define GPE0_EN(x) (0x30 + (x * 4)) + +#endif

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Patch merged into coreboot/master: coreinfo: Allow numbers in addition to F keys
by gerrit＠coreboot.org 18 Mar '16

18 Mar '16

the following patch was just integrated into master: commit c2b50ace1b04c90c27dae8d5999c14f925b93c65 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Fri Mar 11 23:17:28 2016 -0800 coreinfo: Allow numbers in addition to F keys When using coreinfo on a serial console (at least with gtkterm, picocom and minicom on Ubuntu 15.10) you can't send F keys to the payload. Allow 1..9 for F1..F9 Change-Id: Ie3a11fa1de57c7345737a1ccaff177f407cd5e48 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Reviewed-on: https://review.coreboot.org/14065 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/14065 for details. -gerrit

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Patch merged into coreboot/master: src/arch/x86/acpi.c: Use correct host address width in DMAR ACPI table
by gerrit＠coreboot.org 18 Mar '16

18 Mar '16

the following patch was just integrated into master: commit f3f654ddb90fedfb72eab99db6f9893e898ffbff Author: Jacob Laska <jlaska(a)xes-inc.com> Date: Tue Mar 15 21:53:27 2016 -0500 src/arch/x86/acpi.c: Use correct host address width in DMAR ACPI table The previous implementation assumed the CPU physical address size to be 40 which is not true of all platforms. Use an existing function to obtain the correct CPU physical address to report in the DMAR ACPI table. Change-Id: Ia79e9dadecc3f5f6a86ce3789b213222bef482b3 Signed-off-by: Jacob Laska <jlaska91(a)gmail.com> Reviewed-on: https://review.coreboot.org/14102 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> Reviewed-by: Nico Huber <nico.h(a)gmx.de> See https://review.coreboot.org/14102 for details. -gerrit

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Patch merged into coreboot/master: mtrr: Define a function for obtaining free var mtrr
by gerrit＠coreboot.org 18 Mar '16

18 Mar '16

the following patch was just integrated into master: commit 331ac1b07896140a14dbb079b3cb907762cec218 Author: Furquan Shaikh <furquan(a)google.com> Date: Wed Mar 16 16:12:06 2016 -0700 mtrr: Define a function for obtaining free var mtrr Instead of hard-coding var mtrr numbers in code, use this function to identify the first available variable mtrr. If no such mtrr is available, the function will return -1. Change-Id: I2a1e02cdb45c0ab7e30609641977471eaa2431fd Signed-off-by: Furquan Shaikh <furquan(a)google.com> Reviewed-on: https://review.coreboot.org/14115 Tested-by: build bot (Jenkins) Reviewed-by: Andrey Petrov <andrey.petrov(a)intel.com> See https://review.coreboot.org/14115 for details. -gerrit

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New patch to review for coreboot: arch/x86: honor CONFIG_X86_TOP4G_BOOTMEDIA_MAP for verstage
by Aaron Durbin 18 Mar '16

18 Mar '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14142 -gerrit commit dc30023b0d4f48fcc32acf91b63428abc5b0575c Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Mar 18 13:12:41 2016 -0500 arch/x86: honor CONFIG_X86_TOP4G_BOOTMEDIA_MAP for verstage When CONFIG_X86_TOP4G_BOOTMEDIA_MAP was introduced verstage was not updated. Correct this oversight. Change-Id: I2775c08798906ba0ba55a361407d7d2b52313229 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/arch/x86/Makefile.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 6980555..5114e5f 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -184,7 +184,7 @@ verstage-$(CONFIG_ARCH_RAMSTAGE_X86_32) += cpu_common.c verstage-y += memset.c verstage-y += memcpy.c verstage-y += memmove.c -verstage-y += mmap_boot.c +verstage-$(CONFIG_X86_TOP4G_BOOTMEDIA_MAP) += mmap_boot.c verstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c

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coreboot-gerrit March 2016