coreboot-gerrit March 2016

coreboot-gerrit@coreboot.org

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1119 discussions

Patch merged into coreboot/master: skylake mainboards: Configure gpio PADRSTCFG to PLTRST
by gerrit＠coreboot.org 16 Mar '16

16 Mar '16

the following patch was just integrated into master: commit 1a1515b949ef759729a217faf5e8274ec3f3cb5f Author: Naresh G Solanki <naresh.solanki(a)intel.com> Date: Mon Feb 29 13:20:44 2016 +0530 skylake mainboards: Configure gpio PADRSTCFG to PLTRST With gpio PADRSTCFG set to DEEP & GPIROUTIOXAPIC=1 & PADRSTCFG, causes IRQ storm after S3 resume. GPIOs that fire IRQs via IOAPIC need to get their logic reset over pltrst and hence configuring PADRSTCFG to PLTRST to prevent IRQ strom after S3 resume. BRANCH=glados BUG=chrome-os-partner:50536 TEST=Build for kunimitsu and Boot on FAB4, no irq storm observed after S3 resume. Change-Id: I7f1ae90aed03778e7d6cb2d79de0efe9a6d9e20d Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: aff91da4feaf8f7e42cfeee756cf468288cbfd68 Original-Change-Id: I7cac60fb0144e090b8decb05d948b2d8d2f8deac Original-Signed-off-by: Naresh G Solanki <naresh.solanki(a)intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/329453 Original-Commit-Ready: Naresh Solanki <naresh.solanki(a)intel.com> Original-Tested-by: Naresh Solanki <naresh.solanki(a)intel.com> Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/331174 Original-Commit-Ready: Patrick Georgi <pgeorgi(a)chromium.org> Original-Tested-by: Patrick Georgi <pgeorgi(a)chromium.org> Reviewed-on: https://review.coreboot.org/13992 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See https://review.coreboot.org/13992 for details. -gerrit

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Patch merged into coreboot/master: util/nvidia/cbootimage: update to latest master
by gerrit＠coreboot.org 16 Mar '16

16 Mar '16

the following patch was just integrated into master: commit d7f6bd586098b2e3a3811f23e596d8c46a66182a Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Mon Mar 14 17:16:33 2016 +0100 util/nvidia/cbootimage: update to latest master This includes a fix that allows using cbootimage with paths containing the "@" sign, which happens sometimes in jenkins configurations. Change-Id: I83154afa35b6d24449e713e57031b1a93d7ac748 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Reviewed-on: https://review.coreboot.org/14090 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See https://review.coreboot.org/14090 for details. -gerrit

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Patch merged into coreboot/master: parade/ps8640: Clean up
by gerrit＠coreboot.org 16 Mar '16

16 Mar '16

the following patch was just integrated into master: commit db2815ecf41bb76e39e27264466dc871a9d046a5 Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Sat Mar 12 09:28:59 2016 +0100 parade/ps8640: Clean up Sort out some style issues that were identified by Paul. Change-Id: I9ed946ae613c87234f8c9824eb14b8d28909dfcf Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Reviewed-on: https://review.coreboot.org/14064 Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See https://review.coreboot.org/14064 for details. -gerrit

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Patch set updated for coreboot: device/dram/ddr3: fix debug output
by Patrick Rudolph 16 Mar '16

16 Mar '16

Patrick Rudolph (siro(a)das-labor.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14083 -gerrit commit ffd3e38581eb4f43e025fb6170bb8486494af9ef Author: Patrick Rudolph <siro(a)das-labor.org> Date: Sun Mar 13 13:02:16 2016 +0100 device/dram/ddr3: fix debug output Add missing punctuation and align output. No functionality is changed. Old logging output: Revision: 11 Type : b Key : 2 Banks : 8 Capacity: 4 Gb Supported voltages: 1.5V SDRAM width : 8 Bus extension : 0 bits Bus width : 64 Optional features : DLL-Off_mode RZQ/7 RZQ/6 Thermal features : ASR ext_temp_range Thermal sensor : no Standard SDRAM : yes DIMM Rank1 Address bits mirrored!!! DIMM Reference card B DIMM Manufacturer ID cd04 DIMM Part number F3-1866C9-8GSR XMP Profile 1 Max DIMMs per channel: 4 XMP Revision: 1.3 Requested voltage: 1500 mV New logging output: Revision : 11 Type : b Key : 2 Banks : 8 Capacity : 4 Gb Supported voltages : 1.5V SDRAM width : 8 Bus extension : 0 bits Bus width : 64 Optional features : DLL-Off_mode RZQ/7 RZQ/6 Thermal features : ASR ext_temp_range Thermal sensor : no Standard SDRAM : yes Rank1 Address bits : mirrored DIMM Reference card: B Manufacturer ID : cd04 Part number : F3-1866C9-8GSR XMP Profile : 1 Max DIMMs/channel : 4 XMP Revision : 1.3 Requested voltage : 1500 mV Change-Id: Iee4d7a7c0e1070706fb60d7316fad49813963b51 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- src/device/dram/ddr3.c | 50 +++++++++++++++++++++++++++----------------------- 1 file changed, 27 insertions(+), 23 deletions(-) diff --git a/src/device/dram/ddr3.c b/src/device/dram/ddr3.c index b5658ef..cb5b685 100644 --- a/src/device/dram/ddr3.c +++ b/src/device/dram/ddr3.c @@ -137,9 +137,9 @@ int spd_decode_ddr3(dimm_attr * dimm, spd_raw_data spd) ret = SPD_STATUS_CRC_ERROR; }; - printram(" Revision: %x\n", spd[1]); - printram(" Type : %x\n", spd[2]); - printram(" Key : %x\n", spd[3]); + printram(" Revision : %x\n", spd[1]); + printram(" Type : %x\n", spd[2]); + printram(" Key : %x\n", spd[3]); reg8 = spd[4]; /* Number of memory banks */ @@ -149,7 +149,7 @@ int spd_decode_ddr3(dimm_attr * dimm, spd_raw_data spd) ret = SPD_STATUS_INVALID_FIELD; } param = 1 << (val + 3); - printram(" Banks : %u\n", param); + printram(" Banks : %u\n", param); /* SDRAM capacity */ capacity_shift = reg8 & 0x0f; if (capacity_shift > 0x06) { @@ -157,9 +157,9 @@ int spd_decode_ddr3(dimm_attr * dimm, spd_raw_data spd) ret = SPD_STATUS_INVALID_FIELD; } if (capacity_shift < 0x02) { - printram(" Capacity: %u Mb\n", 256 << capacity_shift); + printram(" Capacity : %u Mb\n", 256 << capacity_shift); } else { - printram(" Capacity: %u Gb\n", 1 << (capacity_shift - 2)); + printram(" Capacity : %u Gb\n", 1 << (capacity_shift - 2)); } reg8 = spd[5]; @@ -180,7 +180,7 @@ int spd_decode_ddr3(dimm_attr * dimm, spd_raw_data spd) /* Module nominal voltage */ reg8 = spd[6]; - printram(" Supported voltages:"); + printram(" Supported voltages :"); if (reg8 & (1 << 2)) { dimm->flags.operable_1_25V = 1; dimm->voltage = 1250; @@ -214,7 +214,7 @@ int spd_decode_ddr3(dimm_attr * dimm, spd_raw_data spd) ret = SPD_STATUS_INVALID_FIELD; } dimm->width = (4 << val); - printram(" SDRAM width : %u\n", dimm->width); + printram(" SDRAM width : %u\n", dimm->width); /* Memory bus width */ reg8 = spd[8]; @@ -225,7 +225,7 @@ int spd_decode_ddr3(dimm_attr * dimm, spd_raw_data spd) ret = SPD_STATUS_INVALID_FIELD; } dimm->flags.is_ecc = val ? 1 : 0; - printram(" Bus extension : %u bits\n", val ? 8 : 0); + printram(" Bus extension : %u bits\n", val ? 8 : 0); /* Bus width */ val = reg8 & 0x07; if (val > 3) { @@ -233,7 +233,7 @@ int spd_decode_ddr3(dimm_attr * dimm, spd_raw_data spd) ret = SPD_STATUS_INVALID_FIELD; } bus_width = 8 << val; - printram(" Bus width : %u\n", bus_width); + printram(" Bus width : %u\n", bus_width); /* We have all the info we need to compute the dimm size */ /* Capacity is 256Mbit multiplied by the power of 2 specified in @@ -282,7 +282,7 @@ int spd_decode_ddr3(dimm_attr * dimm, spd_raw_data spd) /* SDRAM Optional Features */ reg8 = spd[30]; - printram(" Optional features :"); + printram(" Optional features :"); if (reg8 & 0x80) { dimm->flags.dll_off_mode = 1; printram(" DLL-Off_mode"); @@ -299,7 +299,7 @@ int spd_decode_ddr3(dimm_attr * dimm, spd_raw_data spd) /* SDRAM Thermal and Refresh Options */ reg8 = spd[31]; - printram(" Thermal features :"); + printram(" Thermal features :"); if (reg8 & 0x80) { dimm->flags.pasr = 1; printram(" PASR"); @@ -326,27 +326,28 @@ int spd_decode_ddr3(dimm_attr * dimm, spd_raw_data spd) reg8 = spd[32]; if (reg8 & 0x80) dimm->flags.therm_sensor = 1; - printram(" Thermal sensor : %s\n", + printram(" Thermal sensor : %s\n", dimm->flags.therm_sensor ? "yes" : "no"); /* SDRAM Device Type */ reg8 = spd[33]; - printram(" Standard SDRAM : %s\n", (reg8 & 0x80) ? "no" : "yes"); + printram(" Standard SDRAM : %s\n", (reg8 & 0x80) ? "no" : "yes"); if (spd[63] & 0x01) { dimm->flags.pins_mirrored = 1; - printram(" DIMM Rank1 Address bits mirrored!!!\n"); } + printram(" Rank1 Address bits : %s\n", + (spd[63] & 0x01) ? "mirrored" : "normal"); dimm->reference_card = spd[62] & 0x1f; - printram(" DIMM Reference card %c\n", 'A' + dimm->reference_card); + printram(" DIMM Reference card: %c\n", 'A' + dimm->reference_card); dimm->manufacturer_id = (spd[118] << 8) | spd[117]; - printram(" DIMM Manufacturer ID %x\n", dimm->manufacturer_id); + printram(" Manufacturer ID : %x\n", dimm->manufacturer_id); dimm->part_number[16] = 0; memcpy(dimm->part_number, &spd[128], 16); - printram(" DIMM Part number %s\n", dimm->part_number); + printram(" Part number : %s\n", dimm->part_number); return ret; } @@ -397,7 +398,8 @@ int spd_xmp_decode_ddr3(dimm_attr *dimm, dimm->dram_type = SPD_MEMORY_TYPE_UNDEFINED; return SPD_STATUS_INVALID; } - printram(" XMP Profile 1\n"); + + printram(" XMP Profile : 1\n"); xmp = &spd[185]; /* Medium Timebase = @@ -412,7 +414,7 @@ int spd_xmp_decode_ddr3(dimm_attr *dimm, dimm->dram_type = SPD_MEMORY_TYPE_UNDEFINED; return SPD_STATUS_INVALID; } - printram(" XMP Profile 2\n"); + printram(" XMP Profile : 2\n"); xmp = &spd[220]; /* Medium Timebase = @@ -422,16 +424,18 @@ int spd_xmp_decode_ddr3(dimm_attr *dimm, dimm->dimms_per_channel = ((spd[178] >> 4) & 0x3) + 1; } - printram(" Max DIMMs per channel: %u\n", + + printram(" Max DIMMs/channel : %u\n", dimm->dimms_per_channel); - printram(" XMP Revision: %u.%u\n", spd[179] >> 4, spd[179] & 0xf); + printram(" XMP Revision : %u.%u\n", spd[179] >> 4, spd[179] & 0xf); /* calculate voltage in mV */ dimm->voltage = (xmp[0] & 1) * 50; dimm->voltage += ((xmp[0] >> 1) & 0xf) * 100; dimm->voltage += ((xmp[0] >> 5) & 0x3) * 1000; - printram(" Requested voltage: %u mV\n", dimm->voltage); + + printram(" Requested voltage : %u mV\n", dimm->voltage); /* SDRAM Minimum Cycle Time (tCKmin) */ dimm->tCK = xmp[1] * mtb;

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New patch to review for coreboot: src/arch/x86/acpi.c: Use correct host address width in DMAR ACPI table.
by Jacob Laska 16 Mar '16

16 Mar '16

Jacob Laska (jlaska91(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14102 -gerrit commit 1ddb643718f4045fa9b1f9b4f5f5008dcd76fbe3 Author: Jacob Laska <jlaska(a)xes-inc.com> Date: Tue Mar 15 21:53:27 2016 -0500 src/arch/x86/acpi.c: Use correct host address width in DMAR ACPI table. The previous implementation assumed the CPU physical address size to be 40 which is not true of all platforms. Use an existing function to obtain the correct CPU physical address to report in the DMAR ACPI table. Change-Id: Ia79e9dadecc3f5f6a86ce3789b213222bef482b3 Signed-off-by: Jacob Laska <jlaska91(a)gmail.com> --- src/arch/x86/acpi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/arch/x86/acpi.c b/src/arch/x86/acpi.c index 9a031ad..1550be59 100644 --- a/src/arch/x86/acpi.c +++ b/src/arch/x86/acpi.c @@ -411,7 +411,7 @@ void acpi_create_dmar(acpi_dmar_t *dmar, enum dmar_flags flags, header->length = sizeof(acpi_dmar_t); header->revision = 1; - dmar->host_address_width = 40 - 1; /* FIXME: == MTRR size? */ + dmar->host_address_width = cpu_phys_address_size() - 1; dmar->flags = flags; current = acpi_fill_dmar(current);

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New patch to review for coreboot: build system: Allow overriding the path to the futility binary
by Patrick Georgi 15 Mar '16

15 Mar '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14100 -gerrit commit f0d6f89594dcd733dfc6a7138443c4aa6860569b Author: Patrick Georgi <pgeorgi(a)google.com> Date: Tue Mar 15 23:14:08 2016 +0100 build system: Allow overriding the path to the futility binary Change-Id: I84e68e8407149780769c3e6a1148c175e42d1025 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- Makefile.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile.inc b/Makefile.inc index a70ff5c..87dc0f7 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -423,7 +423,7 @@ $(AMDFWTOOL): $(top)/util/amdfwtool/amdfwtool.c CBOOTIMAGE:=$(objutil)/cbootimage/cbootimage -FUTILITY:=$(objutil)/futility/futility +FUTILITY?=$(objutil)/futility/futility subdirs-y += util/nvidia

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Patch set updated for coreboot: soc/apollolake: Tear down cache-as-ram very early in ramstage
by Andrey Petrov 15 Mar '16

15 Mar '16

Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13364 -gerrit commit 5a31de57916221e0ac85b8ea241e205e74c62252 Author: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> Date: Thu Mar 10 15:02:02 2016 -0800 soc/apollolake: Tear down cache-as-ram very early in ramstage Because of the reasons explained in the file, teardown of CAR needs to be done in ramstage. This patch addresses that issue in a way designed to minimize boot time. Change-Id: I6a0cb07f5b35ad42537da688e376ac96612990a6 Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- src/soc/intel/apollolake/Makefile.inc | 1 + src/soc/intel/apollolake/bootblock/cache_as_ram.S | 7 +- src/soc/intel/apollolake/car_teardown.c | 135 ++++++++++++++++++++++ src/soc/intel/apollolake/include/soc/cpu.h | 7 +- 4 files changed, 144 insertions(+), 6 deletions(-) diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index 4e05726..6bbfe57 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -25,6 +25,7 @@ romstage-y += memmap.c romstage-y += mmap_boot.c smm-y += placeholders.c +ramstage-y += car_teardown.c ramstage-y += cpu.c ramstage-y += chip.c ramstage-y += placeholders.c diff --git a/src/soc/intel/apollolake/bootblock/cache_as_ram.S b/src/soc/intel/apollolake/bootblock/cache_as_ram.S index c81fe0a..cc021dc 100644 --- a/src/soc/intel/apollolake/bootblock/cache_as_ram.S +++ b/src/soc/intel/apollolake/bootblock/cache_as_ram.S @@ -16,8 +16,7 @@ #include <cpu/x86/cache.h> #include <cpu/x86/cr.h> #include <cpu/x86/post_code.h> - -#define EVICT_CTL_MSR 0x2e0 +#include <soc/cpu.h> .global bootblock_pre_c_entry bootblock_pre_c_entry: @@ -96,7 +95,7 @@ clear_var_mtrr: mov %eax, %cr0 /* Disable cache eviction (setup stage) */ - mov $EVICT_CTL_MSR, %ecx + mov $MSR_EVICT_CTL, %ecx rdmsr or $0x1, %eax wrmsr @@ -112,7 +111,7 @@ clear_var_mtrr: post_code(0x27) /* Disable cache eviction (run stage) */ - mov $EVICT_CTL_MSR, %ecx + mov $MSR_EVICT_CTL, %ecx rdmsr or $0x2, %eax wrmsr diff --git a/src/soc/intel/apollolake/car_teardown.c b/src/soc/intel/apollolake/car_teardown.c new file mode 100644 index 0000000..77d0dd4 --- /dev/null +++ b/src/soc/intel/apollolake/car_teardown.c @@ -0,0 +1,135 @@ +/* + * Cache-as-ram teardown for apollolake SOC. See detailed explanation below. + * + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> for Intel Corp.) + * (Written by Andrey Petrov <andrey.petrov(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include <bootstate.h> +#include <console/console.h> +#include <cpu/cpu.h> +#include <cpu/x86/cache.h> +#include <cpu/x86/mtrr.h> +#include <cpu/x86/msr.h> +#include <cpu/x86/tsc.h> +#include <cbmem.h> +#include <memrange.h> +#include <soc/cpu.h> +#include <symbols.h> + +#define CACHELINE_SIZE 64 +/* + * The CAR teardown on apollolake is more complicated than the standard x86 + * teardown paths because romstage executes in CAR. That means romstage cannot + * do the teardown. For performance reasons, the cache is also used as a backing + * store for RAM after raminit. + * + * This results in a cache with both a CAR region, and memory-backed regions: + * - Invalidating the entire cache will evict stack and code that has not yet + * been commited, to RAM, resulting in a crash. + * - A 'wbinvd' will result in a crash during the write-back phase because + * the CAR region has no backing store. + * + * This teardown path resolves these problems by first flushing important data + * out of cache, to memory. After this operation, it is safe to invalidate the + * entire cache, which is then followed by standard MTRR housekeeping. + * + * For performance reasons, only the memory regions which may have been written + * to are flushed. This includes ramstage code and cbmem. A complete flush of + * all RAM ranges would take several seconds. + */ + +static void clflush(uintptr_t addr) +{ + __asm__ volatile ("clflush (%0)"::"r" (addr)); +} + +static void clflush_mem_range(uintptr_t start, uintptr_t end) +{ + end = ALIGN_UP(end, CACHELINE_SIZE); + + for (start = ALIGN_DOWN(start, CACHELINE_SIZE); start < end; + start += CACHELINE_SIZE) + clflush(start); +} + +static void flush_ram_cache_and_invalidate(void) +{ + uintptr_t cbmem_base; + size_t cbmem_size; + struct memranges ctx; + struct range_entry entries[3]; + const struct range_entry *r; + const struct cbmem_entry *fsp_rsvd_mem; + + memranges_init_empty(&ctx, entries, ARRAY_SIZE(entries)); + + /* Figure out where ramstage resides; this is inclusive of the stack */ + memranges_insert(&ctx, (uintptr_t)&_program, _program_size, 0); + + /* It's okay if CBMEM and ramstage overlap. */ + cbmem_region_used(&cbmem_base, &cbmem_size); + memranges_insert(&ctx, cbmem_base, cbmem_size, 0); + + /* + * FSP reserved memory was written before caching was enabled. Thus it + * does not need to be flushed. This saves about 10ms of boot time. + */ + fsp_rsvd_mem = cbmem_entry_find(CBMEM_ID_FSP_RESERVED_MEMORY); + if (fsp_rsvd_mem) { + memranges_create_hole(&ctx, + (uintptr_t)cbmem_entry_start(fsp_rsvd_mem), + cbmem_entry_size(fsp_rsvd_mem) + ); + } + + /* Flush ramstage code and stack */ + memranges_each_entry(r, &ctx) + clflush_mem_range(range_entry_base(r), range_entry_end(r)); + + /* Now that important data is flushed, invalidate all caches */ + invd(); +} + +static void disable_car_region_and_no_evict_mode(void) +{ + msr_t msr; + + /* Disable variable and fixed MTRRs */ + msr.lo = msr.hi = 0; + wrmsr(MTRR_DEF_TYPE_MSR, msr); + /* Disable CAR MTRR */ + wrmsr(MTRR_PHYS_BASE(0), msr); + wrmsr(MTRR_PHYS_MASK(0), msr); + + /* Switch out of "no evict" mode */ + msr = rdmsr(MSR_EVICT_CTL); + msr.lo &= ~2; + wrmsr(MSR_EVICT_CTL, msr); + + msr.lo &= ~1; + wrmsr(MSR_EVICT_CTL, msr); + + /* Re-enable remaining MTRRs */ + msr.lo = MTRR_DEF_TYPE_EN; + msr.hi = 0; + wrmsr(MTRR_DEF_TYPE_MSR, msr); +} + +static void tear_down_car(void *unused_arg) +{ + (void) unused_arg; + + flush_ram_cache_and_invalidate(); + disable_car_region_and_no_evict_mode(); +} + +BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_ENTRY, tear_down_car, NULL); diff --git a/src/soc/intel/apollolake/include/soc/cpu.h b/src/soc/intel/apollolake/include/soc/cpu.h index 765be70..b7b2fcc 100644 --- a/src/soc/intel/apollolake/include/soc/cpu.h +++ b/src/soc/intel/apollolake/include/soc/cpu.h @@ -13,19 +13,22 @@ #ifndef _SOC_APOLLOLAKE_CPU_H_ #define _SOC_APOLLOLAKE_CPU_H_ +#ifndef __ASSEMBLER__ #include <cpu/x86/msr.h> #include <device/device.h> +void apollolake_init_cpus(struct device *dev); +#endif + #define CPUID_APOLLOLAKE_A0 0x506c8 #define CPUID_APOLLOLAKE_B0 0x506c9 #define MSR_PLATFORM_INFO 0xce #define MSR_POWER_MISC 0x120 #define MSR_CORE_THREAD_COUNT 0x35 +#define MSR_EVICT_CTL 0x2e0 #define BASE_CLOCK_MHZ 100 -void apollolake_init_cpus(struct device *dev); - #endif /* _SOC_APOLLOLAKE_CPU_H_ */

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Patch set updated for coreboot: soc/intel/apollolake: enable RAM cache for cbmem region in ramstage
by Andrey Petrov 15 Mar '16

15 Mar '16

Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14095 -gerrit commit c9bb41f2e23f4f937c02581b45af776647ab000c Author: Andrey Petrov <andrey.petrov(a)intel.com> Date: Sun Mar 13 16:01:55 2016 -0700 soc/intel/apollolake: enable RAM cache for cbmem region in ramstage Since ramstage code as well as FSP code is run in cbmem that is placed in DRAM, it is important to have that region cached for performance reasons. This patch enables WB cache for 16MiB below cbmem top which is a safe bet ramstage is covered. Change-Id: I3f2f6e82f3b9060c7350ddff754cd3dbcf457671 Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- src/soc/intel/apollolake/romstage.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c index 7c8924d..1d5365c 100644 --- a/src/soc/intel/apollolake/romstage.c +++ b/src/soc/intel/apollolake/romstage.c @@ -15,6 +15,7 @@ #include <arch/symbols.h> #include <cbfs.h> #include <cbmem.h> +#include <cpu/x86/mtrr.h> #include <console/console.h> #include <device/pci_def.h> #include <fsp/api.h> @@ -80,6 +81,7 @@ asmlinkage void car_stage_entry(void) void *hob_list_ptr; struct range_entry fsp_mem; struct range_entry reg_car; + uintptr_t top_of_ram; printk(BIOS_DEBUG, "Starting romstage...\n"); @@ -95,6 +97,24 @@ asmlinkage void car_stage_entry(void) die("FSP memory init failed. Giving up."); } + /* + * Cache 16 MiB area right below cbmem, so that ramstage and FSP + * reserved memory run cached. This assumes cbmem top is at least + * 16 MiB aligned. + * + * After this call we get: + * - Non-evict mode (NEM) is enabled + * - Write-back cache is active for small window in DRAM + * + * Since NEM mode blocks cache fills, memory operations do not make + * it into L2 cache. L1D cache however works in normal mode. Since + * L1 size is smaller than the actual working set, we are slower than + * fully fledged L2. However it is still about 10x faster than non- + * cached memory. + */ + top_of_ram = (uintptr_t) cbmem_top(); + set_var_mtrr(1, top_of_ram - 16 * MiB, 16 * MiB, MTRR_TYPE_WRBACK); + fsp_find_reserved_memory(&fsp_mem, hob_list_ptr); /* initialize cbmem by adding FSP reserved memory first thing */

1 0

Patch set updated for coreboot: libpayload: recreate config files
by Stefan Reinauer 15 Mar '16

15 Mar '16

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14077 -gerrit commit 02e44b2c5d40d909f6b683e886263f9190f4ba5c Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Sat Mar 12 16:51:30 2016 -0800 libpayload: recreate config files Add all the default options with: for i in configs/* do cp $i .config make savedefconfig mv defconfig $i done This also switches to minimal config files instead of the full configuration files that were previously checked in. Change-Id: If18a32eca4df9e1dfeb0e212b652d972cea8e4b8 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- payloads/libpayload/configs/config.arm64-generic | 64 +----------------- payloads/libpayload/configs/config.purin | 68 -------------------- payloads/libpayload/configs/config.veyron | 70 -------------------- payloads/libpayload/configs/defconfig | 82 ------------------------ payloads/libpayload/configs/defconfig-arm | 76 ---------------------- payloads/libpayload/configs/defconfig-mips | 73 --------------------- payloads/libpayload/configs/defconfig-tinycurses | 81 ----------------------- 7 files changed, 1 insertion(+), 513 deletions(-) diff --git a/payloads/libpayload/configs/config.arm64-generic b/payloads/libpayload/configs/config.arm64-generic index a2d596c..569f262 100644 --- a/payloads/libpayload/configs/config.arm64-generic +++ b/payloads/libpayload/configs/config.arm64-generic @@ -1,72 +1,10 @@ -# -# Automatically generated file; DO NOT EDIT. -# Libpayload Configuration -# - -# -# Generic Options -# -# CONFIG_LP_GPL is not set -# CONFIG_LP_EXPERIMENTAL is not set -# CONFIG_LP_DEVELOPER is not set -CONFIG_LP_COMPILER_GCC=y -# CONFIG_LP_COMPILER_LLVM_CLANG is not set - -# -# Architecture Options -# -# CONFIG_LP_ARCH_ARM is not set -# CONFIG_LP_ARCH_X86 is not set CONFIG_LP_ARCH_ARM64=y -# CONFIG_LP_ARCH_MIPS is not set -# CONFIG_LP_MEMMAP_RAM_ONLY is not set - -# -# Standard Libraries -# -CONFIG_LP_LIBC=y # CONFIG_LP_CURSES is not set -CONFIG_LP_CBFS=y -CONFIG_LP_LZMA=y - -# -# Console Options -# CONFIG_LP_SKIP_CONSOLE_INIT=y -CONFIG_LP_CBMEM_CONSOLE=y # CONFIG_LP_SERIAL_CONSOLE is not set -CONFIG_LP_VIDEO_CONSOLE=y CONFIG_LP_COREBOOT_VIDEO_CONSOLE=y -# CONFIG_LP_PC_KEYBOARD is not set - -# -# Drivers -# -# CONFIG_LP_RTC_PORT_EXTENDED_VIA is not set # CONFIG_LP_STORAGE is not set -CONFIG_LP_TIMER_NONE=y -# CONFIG_LP_TIMER_MCT is not set -# CONFIG_LP_TIMER_TEGRA_1US is not set -# CONFIG_LP_TIMER_IPQ806X is not set -# CONFIG_LP_TIMER_RK is not set -# CONFIG_LP_TIMER_BG4CD is not set -# CONFIG_LP_TIMER_CYGNUS is not set -# CONFIG_LP_TIMER_IMG_PISTACHIO is not set -# CONFIG_LP_TIMER_MTK is not set CONFIG_LP_USB=y -# CONFIG_LP_USB_OHCI is not set CONFIG_LP_USB_EHCI=y CONFIG_LP_USB_XHCI=y -# CONFIG_LP_USB_XHCI_MTK_QUIRK is not set -CONFIG_LP_USB_HID=y -CONFIG_LP_USB_HUB=y -# CONFIG_LP_USB_EHCI_HOSTPC_ROOT_HUB_TT is not set -CONFIG_LP_USB_MSC=y -CONFIG_LP_USB_GEN_HUB=y -# CONFIG_LP_USB_PCI is not set -# CONFIG_LP_UDC is not set -# CONFIG_LP_BIG_ENDIAN is not set -CONFIG_LP_LITTLE_ENDIAN=y -# CONFIG_LP_IO_ADDRESS_SPACE is not set -CONFIG_LP_ARCH_SPECIFIC_OPTIONS=y -CONFIG_LP_DMA_LIM_EXCL=0x1000 +CONFIG_LP_ARM64_A53_ERRATUM_843419=y diff --git a/payloads/libpayload/configs/config.purin b/payloads/libpayload/configs/config.purin index c4f225b..afcc199 100644 --- a/payloads/libpayload/configs/config.purin +++ b/payloads/libpayload/configs/config.purin @@ -1,79 +1,11 @@ -# -# Automatically generated file; DO NOT EDIT. -# Libpayload Configuration -# - -# -# Generic Options -# CONFIG_LP_GPL=y -# CONFIG_LP_EXPERIMENTAL is not set -# CONFIG_LP_DEVELOPER is not set -CONFIG_LP_COMPILER_GCC=y -# CONFIG_LP_COMPILER_LLVM_CLANG is not set -# CONFIG_LP_REMOTEGDB is not set - -# -# Architecture Options -# CONFIG_LP_ARCH_ARM=y -# CONFIG_LP_ARCH_X86 is not set -# CONFIG_LP_ARCH_ARM64 is not set -# CONFIG_LP_ARCH_MIPS is not set -# CONFIG_LP_MEMMAP_RAM_ONLY is not set - -# -# Standard Libraries -# -CONFIG_LP_LIBC=y # CONFIG_LP_CURSES is not set -CONFIG_LP_CBFS=y -CONFIG_LP_LZMA=y -CONFIG_LP_LZ4=y - -# -# Console Options -# CONFIG_LP_SKIP_CONSOLE_INIT=y -CONFIG_LP_CBMEM_CONSOLE=y -CONFIG_LP_SERIAL_CONSOLE=y -CONFIG_LP_8250_SERIAL_CONSOLE=y -# CONFIG_LP_S5P_SERIAL_CONSOLE is not set -# CONFIG_LP_IPQ806X_SERIAL_CONSOLE is not set -# CONFIG_LP_BG4CD_SERIAL_CONSOLE is not set -# CONFIG_LP_PL011_SERIAL_CONSOLE is not set -# CONFIG_LP_SERIAL_SET_SPEED is not set -# CONFIG_LP_SERIAL_ACS_FALLBACK is not set # CONFIG_LP_VIDEO_CONSOLE is not set -# CONFIG_LP_PC_KEYBOARD is not set - -# -# Drivers -# -# CONFIG_LP_RTC_PORT_EXTENDED_VIA is not set # CONFIG_LP_STORAGE is not set -# CONFIG_LP_TIMER_NONE is not set -# CONFIG_LP_TIMER_MCT is not set -# CONFIG_LP_TIMER_TEGRA_1US is not set -# CONFIG_LP_TIMER_IPQ806X is not set -# CONFIG_LP_TIMER_RK is not set -# CONFIG_LP_TIMER_BG4CD is not set CONFIG_LP_TIMER_CYGNUS=y -# CONFIG_LP_TIMER_IMG_PISTACHIO is not set -# CONFIG_LP_TIMER_MTK is not set -CONFIG_LP_IPROC_PERIPH_GLB_TIM_REG_BASE=0x19020200 CONFIG_LP_USB=y -# CONFIG_LP_USB_OHCI is not set -# CONFIG_LP_USB_EHCI is not set -# CONFIG_LP_USB_XHCI is not set -# CONFIG_LP_USB_DWC2 is not set # CONFIG_LP_USB_HID is not set # CONFIG_LP_USB_HUB is not set # CONFIG_LP_USB_MSC is not set -# CONFIG_LP_USB_GEN_HUB is not set -# CONFIG_LP_USB_PCI is not set -# CONFIG_LP_UDC is not set -# CONFIG_LP_BIG_ENDIAN is not set -CONFIG_LP_LITTLE_ENDIAN=y -# CONFIG_LP_IO_ADDRESS_SPACE is not set -CONFIG_LP_ARCH_SPECIFIC_OPTIONS=y diff --git a/payloads/libpayload/configs/config.veyron b/payloads/libpayload/configs/config.veyron index 47d54ea..793907f 100644 --- a/payloads/libpayload/configs/config.veyron +++ b/payloads/libpayload/configs/config.veyron @@ -1,81 +1,11 @@ -# -# Automatically generated file; DO NOT EDIT. -# Libpayload Configuration -# - -# -# Generic Options -# CONFIG_LP_GPL=y -# CONFIG_LP_EXPERIMENTAL is not set -# CONFIG_LP_DEVELOPER is not set -CONFIG_LP_COMPILER_GCC=y -# CONFIG_LP_COMPILER_LLVM_CLANG is not set -# CONFIG_LP_REMOTEGDB is not set - -# -# Architecture Options -# CONFIG_LP_ARCH_ARM=y -# CONFIG_LP_ARCH_X86 is not set -# CONFIG_LP_ARCH_ARM64 is not set -# CONFIG_LP_ARCH_MIPS is not set -# CONFIG_LP_MEMMAP_RAM_ONLY is not set - -# -# Standard Libraries -# -CONFIG_LP_LIBC=y # CONFIG_LP_CURSES is not set -CONFIG_LP_CBFS=y -CONFIG_LP_LZMA=y -CONFIG_LP_LZ4=y - -# -# Console Options -# CONFIG_LP_SKIP_CONSOLE_INIT=y -CONFIG_LP_CBMEM_CONSOLE=y -CONFIG_LP_SERIAL_CONSOLE=y -CONFIG_LP_8250_SERIAL_CONSOLE=y -# CONFIG_LP_S5P_SERIAL_CONSOLE is not set -# CONFIG_LP_IPQ806X_SERIAL_CONSOLE is not set -# CONFIG_LP_BG4CD_SERIAL_CONSOLE is not set -# CONFIG_LP_PL011_SERIAL_CONSOLE is not set -# CONFIG_LP_SERIAL_SET_SPEED is not set -# CONFIG_LP_SERIAL_ACS_FALLBACK is not set -CONFIG_LP_VIDEO_CONSOLE=y CONFIG_LP_COREBOOT_VIDEO_CONSOLE=y -# CONFIG_LP_PC_KEYBOARD is not set - -# -# Drivers -# -# CONFIG_LP_RTC_PORT_EXTENDED_VIA is not set # CONFIG_LP_STORAGE is not set -# CONFIG_LP_TIMER_NONE is not set -# CONFIG_LP_TIMER_MCT is not set -# CONFIG_LP_TIMER_TEGRA_1US is not set -# CONFIG_LP_TIMER_IPQ806X is not set CONFIG_LP_TIMER_RK=y -# CONFIG_LP_TIMER_BG4CD is not set -# CONFIG_LP_TIMER_CYGNUS is not set -# CONFIG_LP_TIMER_IMG_PISTACHIO is not set -# CONFIG_LP_TIMER_MTK is not set -CONFIG_LP_TIMER_RK_ADDRESS=0xff810020 CONFIG_LP_USB=y -# CONFIG_LP_USB_OHCI is not set CONFIG_LP_USB_EHCI=y -# CONFIG_LP_USB_XHCI is not set CONFIG_LP_USB_DWC2=y # CONFIG_LP_USB_HID is not set -CONFIG_LP_USB_HUB=y -# CONFIG_LP_USB_EHCI_HOSTPC_ROOT_HUB_TT is not set -CONFIG_LP_USB_MSC=y -CONFIG_LP_USB_GEN_HUB=y -# CONFIG_LP_USB_PCI is not set -# CONFIG_LP_UDC is not set -# CONFIG_LP_BIG_ENDIAN is not set -CONFIG_LP_LITTLE_ENDIAN=y -# CONFIG_LP_IO_ADDRESS_SPACE is not set -CONFIG_LP_ARCH_SPECIFIC_OPTIONS=y diff --git a/payloads/libpayload/configs/defconfig b/payloads/libpayload/configs/defconfig index 53320e7..ef1982f 100644 --- a/payloads/libpayload/configs/defconfig +++ b/payloads/libpayload/configs/defconfig @@ -1,89 +1,7 @@ -# -# Automatically generated file; DO NOT EDIT. -# Libpayload Configuration -# - -# -# Generic Options -# -# CONFIG_LP_GPL is not set -# CONFIG_LP_EXPERIMENTAL is not set -# CONFIG_LP_DEVELOPER is not set -CONFIG_LP_COMPILER_GCC=y -# CONFIG_LP_COMPILER_LLVM_CLANG is not set - -# -# Architecture Options -# -# CONFIG_LP_ARCH_ARM is not set -CONFIG_LP_ARCH_X86=y -# CONFIG_LP_ARCH_ARM64 is not set -# CONFIG_LP_ARCH_MIPS is not set -# CONFIG_LP_MEMMAP_RAM_ONLY is not set # CONFIG_LP_MULTIBOOT is not set - -# -# Standard Libraries -# -CONFIG_LP_LIBC=y -CONFIG_LP_CURSES=y -# CONFIG_LP_TINYCURSES is not set -CONFIG_LP_PDCURSES=y -CONFIG_LP_CBFS=y -CONFIG_LP_LZMA=y -CONFIG_LP_LZ4=y - -# -# Console Options -# -# CONFIG_LP_SKIP_CONSOLE_INIT is not set -CONFIG_LP_CBMEM_CONSOLE=y -CONFIG_LP_SERIAL_CONSOLE=y -CONFIG_LP_8250_SERIAL_CONSOLE=y -# CONFIG_LP_S5P_SERIAL_CONSOLE is not set -# CONFIG_LP_8250_MMIO32_SERIAL_CONSOLE is not set -# CONFIG_LP_IPQ806X_SERIAL_CONSOLE is not set -# CONFIG_LP_BG4CD_SERIAL_CONSOLE is not set -# CONFIG_LP_PL011_SERIAL_CONSOLE is not set -CONFIG_LP_SERIAL_IOBASE=0x3f8 -# CONFIG_LP_SERIAL_SET_SPEED is not set -# CONFIG_LP_SERIAL_ACS_FALLBACK is not set -CONFIG_LP_VIDEO_CONSOLE=y -CONFIG_LP_VGA_VIDEO_CONSOLE=y -# CONFIG_LP_GEODELX_VIDEO_CONSOLE is not set CONFIG_LP_COREBOOT_VIDEO_CONSOLE=y -CONFIG_LP_PC_KEYBOARD=y -CONFIG_LP_PC_KEYBOARD_LAYOUT_US=y -# CONFIG_LP_PC_KEYBOARD_LAYOUT_DE is not set - -# -# Drivers -# -CONFIG_LP_PCI=y -CONFIG_LP_NVRAM=y -# CONFIG_LP_RTC_PORT_EXTENDED_VIA is not set -CONFIG_LP_SPEAKER=y -CONFIG_LP_STORAGE=y -# CONFIG_LP_STORAGE_64BIT_LBA is not set -CONFIG_LP_STORAGE_ATA=y -CONFIG_LP_STORAGE_ATAPI=y -CONFIG_LP_STORAGE_AHCI=y -CONFIG_LP_STORAGE_AHCI_ONLY_TESTED=y -CONFIG_LP_TIMER_RDTSC=y CONFIG_LP_USB=y CONFIG_LP_USB_UHCI=y CONFIG_LP_USB_OHCI=y CONFIG_LP_USB_EHCI=y CONFIG_LP_USB_XHCI=y -# CONFIG_LP_USB_XHCI_MTK_QUIRK is not set -CONFIG_LP_USB_HID=y -CONFIG_LP_USB_HUB=y -# CONFIG_LP_USB_EHCI_HOSTPC_ROOT_HUB_TT is not set -CONFIG_LP_USB_MSC=y -CONFIG_LP_USB_GEN_HUB=y -CONFIG_LP_USB_PCI=y -# CONFIG_LP_UDC is not set -# CONFIG_LP_BIG_ENDIAN is not set -CONFIG_LP_LITTLE_ENDIAN=y -CONFIG_LP_IO_ADDRESS_SPACE=y -CONFIG_LP_ARCH_SPECIFIC_OPTIONS=y diff --git a/payloads/libpayload/configs/defconfig-arm b/payloads/libpayload/configs/defconfig-arm index 5b0ebe6..a72fa67 100644 --- a/payloads/libpayload/configs/defconfig-arm +++ b/payloads/libpayload/configs/defconfig-arm @@ -1,83 +1,7 @@ -# -# Automatically generated file; DO NOT EDIT. -# Libpayload Configuration -# - -# -# Generic Options -# -# CONFIG_LP_GPL is not set -# CONFIG_LP_EXPERIMENTAL is not set -# CONFIG_LP_DEVELOPER is not set -CONFIG_LP_COMPILER_GCC=y -# CONFIG_LP_COMPILER_LLVM_CLANG is not set - -# -# Architecture Options -# CONFIG_LP_ARCH_ARM=y -# CONFIG_LP_ARCH_X86 is not set -# CONFIG_LP_ARCH_ARM64 is not set -# CONFIG_LP_ARCH_MIPS is not set -# CONFIG_LP_MEMMAP_RAM_ONLY is not set - -# -# Standard Libraries -# -CONFIG_LP_LIBC=y -CONFIG_LP_CURSES=y CONFIG_LP_TINYCURSES=y -# CONFIG_LP_PDCURSES is not set -CONFIG_LP_CBFS=y -CONFIG_LP_LZMA=y - -# -# Console Options -# -# CONFIG_LP_SKIP_CONSOLE_INIT is not set -CONFIG_LP_CBMEM_CONSOLE=y -CONFIG_LP_SERIAL_CONSOLE=y # CONFIG_LP_8250_SERIAL_CONSOLE is not set -# CONFIG_LP_S5P_SERIAL_CONSOLE is not set -# CONFIG_LP_8250_MMIO32_SERIAL_CONSOLE is not set -# CONFIG_LP_IPQ806X_SERIAL_CONSOLE is not set -# CONFIG_LP_BG4CD_SERIAL_CONSOLE is not set -# CONFIG_LP_SERIAL_SET_SPEED is not set -# CONFIG_LP_SERIAL_ACS_FALLBACK is not set -CONFIG_LP_VIDEO_CONSOLE=y -# CONFIG_LP_COREBOOT_VIDEO_CONSOLE is not set -# CONFIG_LP_PC_KEYBOARD is not set - -# -# Drivers -# -# CONFIG_LP_RTC_PORT_EXTENDED_VIA is not set -CONFIG_LP_STORAGE=y -# CONFIG_LP_STORAGE_64BIT_LBA is not set -CONFIG_LP_STORAGE_ATA=y -CONFIG_LP_STORAGE_ATAPI=y -CONFIG_LP_TIMER_NONE=y -# CONFIG_LP_TIMER_MCT is not set -# CONFIG_LP_TIMER_TEGRA_1US is not set -# CONFIG_LP_TIMER_IPQ806X is not set -# CONFIG_LP_TIMER_RK is not set -# CONFIG_LP_TIMER_BG4CD is not set -# CONFIG_LP_TIMER_CYGNUS is not set -# CONFIG_LP_TIMER_IMG_PISTACHIO is not set -# CONFIG_LP_TIMER_MTK is not set CONFIG_LP_USB=y CONFIG_LP_USB_OHCI=y CONFIG_LP_USB_EHCI=y CONFIG_LP_USB_XHCI=y -# CONFIG_LP_USB_XHCI_MTK_QUIRK is not set -CONFIG_LP_USB_HID=y -CONFIG_LP_USB_HUB=y -# CONFIG_LP_USB_EHCI_HOSTPC_ROOT_HUB_TT is not set -CONFIG_LP_USB_MSC=y -CONFIG_LP_USB_GEN_HUB=y -# CONFIG_LP_USB_PCI is not set -# CONFIG_LP_UDC is not set -# CONFIG_LP_BIG_ENDIAN is not set -CONFIG_LP_LITTLE_ENDIAN=y -# CONFIG_LP_IO_ADDRESS_SPACE is not set -CONFIG_LP_ARCH_SPECIFIC_OPTIONS=y diff --git a/payloads/libpayload/configs/defconfig-mips b/payloads/libpayload/configs/defconfig-mips index 5b78777..7e31478 100644 --- a/payloads/libpayload/configs/defconfig-mips +++ b/payloads/libpayload/configs/defconfig-mips @@ -1,77 +1,4 @@ -# -# Automatically generated file; DO NOT EDIT. -# Libpayload Configuration -# - -# -# Generic Options -# -# CONFIG_LP_GPL is not set -# CONFIG_LP_EXPERIMENTAL is not set -# CONFIG_LP_DEVELOPER is not set -CONFIG_LP_COMPILER_GCC=y -# CONFIG_LP_COMPILER_LLVM_CLANG is not set - -# -# Architecture Options -# -# CONFIG_LP_ARCH_ARM is not set -# CONFIG_LP_ARCH_X86 is not set -# CONFIG_LP_ARCH_ARM64 is not set CONFIG_LP_ARCH_MIPS=y -# CONFIG_LP_MEMMAP_RAM_ONLY is not set - -# -# Standard Libraries -# -CONFIG_LP_LIBC=y -CONFIG_LP_CURSES=y -# CONFIG_LP_TINYCURSES is not set -CONFIG_LP_PDCURSES=y -CONFIG_LP_CBFS=y -CONFIG_LP_LZMA=y - -# -# Console Options -# -# CONFIG_LP_SKIP_CONSOLE_INIT is not set -CONFIG_LP_CBMEM_CONSOLE=y -CONFIG_LP_SERIAL_CONSOLE=y -CONFIG_LP_8250_SERIAL_CONSOLE=y -# CONFIG_LP_S5P_SERIAL_CONSOLE is not set -# CONFIG_LP_8250_MMIO32_SERIAL_CONSOLE is not set -# CONFIG_LP_IPQ806X_SERIAL_CONSOLE is not set -# CONFIG_LP_BG4CD_SERIAL_CONSOLE is not set -# CONFIG_LP_PL011_SERIAL_CONSOLE is not set -# CONFIG_LP_SERIAL_SET_SPEED is not set -# CONFIG_LP_SERIAL_ACS_FALLBACK is not set -CONFIG_LP_VIDEO_CONSOLE=y CONFIG_LP_COREBOOT_VIDEO_CONSOLE=y CONFIG_LP_PC_KEYBOARD=y -CONFIG_LP_PC_KEYBOARD_LAYOUT_US=y -# CONFIG_LP_PC_KEYBOARD_LAYOUT_DE is not set - -# -# Drivers -# -# CONFIG_LP_RTC_PORT_EXTENDED_VIA is not set -CONFIG_LP_STORAGE=y -# CONFIG_LP_STORAGE_64BIT_LBA is not set -CONFIG_LP_STORAGE_ATA=y -CONFIG_LP_STORAGE_ATAPI=y -# CONFIG_LP_TIMER_NONE is not set -# CONFIG_LP_TIMER_MCT is not set -# CONFIG_LP_TIMER_TEGRA_1US is not set -# CONFIG_LP_TIMER_IPQ806X is not set -# CONFIG_LP_TIMER_RK is not set -# CONFIG_LP_TIMER_BG4CD is not set -# CONFIG_LP_TIMER_CYGNUS is not set CONFIG_LP_TIMER_IMG_PISTACHIO=y -# CONFIG_LP_TIMER_MTK is not set -# CONFIG_LP_USB is not set -# CONFIG_LP_USB_GEN_HUB is not set -# CONFIG_LP_UDC is not set -# CONFIG_LP_BIG_ENDIAN is not set -CONFIG_LP_LITTLE_ENDIAN=y -# CONFIG_LP_IO_ADDRESS_SPACE is not set -CONFIG_LP_ARCH_SPECIFIC_OPTIONS=y diff --git a/payloads/libpayload/configs/defconfig-tinycurses b/payloads/libpayload/configs/defconfig-tinycurses index ad0a8cf..be49420 100644 --- a/payloads/libpayload/configs/defconfig-tinycurses +++ b/payloads/libpayload/configs/defconfig-tinycurses @@ -1,89 +1,8 @@ -# -# Automatically generated file; DO NOT EDIT. -# Libpayload Configuration -# - -# -# Generic Options -# -# CONFIG_LP_GPL is not set -# CONFIG_LP_EXPERIMENTAL is not set -# CONFIG_LP_DEVELOPER is not set -CONFIG_LP_COMPILER_GCC=y -# CONFIG_LP_COMPILER_LLVM_CLANG is not set - -# -# Architecture Options -# -# CONFIG_LP_ARCH_ARM is not set -CONFIG_LP_ARCH_X86=y -# CONFIG_LP_ARCH_ARM64 is not set -# CONFIG_LP_ARCH_MIPS is not set -# CONFIG_LP_MEMMAP_RAM_ONLY is not set # CONFIG_LP_MULTIBOOT is not set - -# -# Standard Libraries -# -CONFIG_LP_LIBC=y -CONFIG_LP_CURSES=y CONFIG_LP_TINYCURSES=y -# CONFIG_LP_PDCURSES is not set -CONFIG_LP_CBFS=y -CONFIG_LP_LZMA=y -CONFIG_LP_LZ4=y - -# -# Console Options -# -# CONFIG_LP_SKIP_CONSOLE_INIT is not set -CONFIG_LP_CBMEM_CONSOLE=y -CONFIG_LP_SERIAL_CONSOLE=y -CONFIG_LP_8250_SERIAL_CONSOLE=y -# CONFIG_LP_S5P_SERIAL_CONSOLE is not set -# CONFIG_LP_8250_MMIO32_SERIAL_CONSOLE is not set -# CONFIG_LP_IPQ806X_SERIAL_CONSOLE is not set -# CONFIG_LP_BG4CD_SERIAL_CONSOLE is not set -# CONFIG_LP_PL011_SERIAL_CONSOLE is not set -CONFIG_LP_SERIAL_IOBASE=0x3f8 -# CONFIG_LP_SERIAL_SET_SPEED is not set -# CONFIG_LP_SERIAL_ACS_FALLBACK is not set -CONFIG_LP_VIDEO_CONSOLE=y -CONFIG_LP_VGA_VIDEO_CONSOLE=y -# CONFIG_LP_GEODELX_VIDEO_CONSOLE is not set CONFIG_LP_COREBOOT_VIDEO_CONSOLE=y -CONFIG_LP_PC_KEYBOARD=y -CONFIG_LP_PC_KEYBOARD_LAYOUT_US=y -# CONFIG_LP_PC_KEYBOARD_LAYOUT_DE is not set - -# -# Drivers -# -CONFIG_LP_PCI=y -CONFIG_LP_NVRAM=y -# CONFIG_LP_RTC_PORT_EXTENDED_VIA is not set -CONFIG_LP_SPEAKER=y -CONFIG_LP_STORAGE=y -# CONFIG_LP_STORAGE_64BIT_LBA is not set -CONFIG_LP_STORAGE_ATA=y -CONFIG_LP_STORAGE_ATAPI=y -CONFIG_LP_STORAGE_AHCI=y -CONFIG_LP_STORAGE_AHCI_ONLY_TESTED=y -CONFIG_LP_TIMER_RDTSC=y CONFIG_LP_USB=y CONFIG_LP_USB_UHCI=y CONFIG_LP_USB_OHCI=y CONFIG_LP_USB_EHCI=y CONFIG_LP_USB_XHCI=y -# CONFIG_LP_USB_XHCI_MTK_QUIRK is not set -CONFIG_LP_USB_HID=y -CONFIG_LP_USB_HUB=y -# CONFIG_LP_USB_EHCI_HOSTPC_ROOT_HUB_TT is not set -CONFIG_LP_USB_MSC=y -CONFIG_LP_USB_GEN_HUB=y -CONFIG_LP_USB_PCI=y -# CONFIG_LP_UDC is not set -# CONFIG_LP_BIG_ENDIAN is not set -CONFIG_LP_LITTLE_ENDIAN=y -CONFIG_LP_IO_ADDRESS_SPACE=y -CONFIG_LP_ARCH_SPECIFIC_OPTIONS=y

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Patch merged into coreboot/master: coreinfo: Use tinycurses
by gerrit＠coreboot.org 15 Mar '16

15 Mar '16

the following patch was just integrated into master: commit 80547369eaedc8ff7d3d987f4bd0a5614258f1d6 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Sat Mar 12 11:47:00 2016 -0800 coreinfo: Use tinycurses When using PDcurses over a serial line, the background of coreinfo is not properly cleared. Hence use tinycurses, which was the only option when coreinfo was developed. Change-Id: I15bb6eb552cf924de98d09ef63be33ecf336c526 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Reviewed-on: https://review.coreboot.org/14067 Reviewed-by: Martin Roth <martinroth(a)google.com> Tested-by: build bot (Jenkins) See https://review.coreboot.org/14067 for details. -gerrit

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coreboot-gerrit March 2016